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algebrato/eldig | contatore_4_cifre/contatore_4_cifre.vhd | 1 | 2,748 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:04:21 05/02/2016
-- Design Name:
-- Module Name: contatore_4_cifre - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity contatore_4_cifre is
end contatore_4_cifre;
architecture Behavioral of contatore_4_cifre is
component Contatore_1_cifra is
port(Clock, Enable_in, UpDown, Reset, Preset : in std_logic;
N_preset : in std_logic_vector(3 downto 0);
N : out std_logic_vector(3 downto 0);
Enable_out : out std_logic);
end Contatore_1_cifra;
begin
C0:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale,
Enable_in => enable,
UpDown => updown,
Reset => reset,
Preset => preset,
N_preset => npreset,
N => N0,
Enable_out => enable_0_to_1);
C1:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale,
Enable_in => enable_0_to_1,
UpDown => updown,
Reset => reset,
Preset => preset,
N_preset => npreset,
N => N1,
Enable_out => enable_1_to_2);
C2:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale,
Enable_in => enable_1_to_2,
UpDown => updown,
Reset => reset,
Preset => preset,
N_preset => npreset,
N => N2,
Enable_out => enable_2_to_3);
C3:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale,
Enable_in => enable_2_to_3,
UpDown => updown,
Reset => reset,
Preset => preset,
N_preset => npreset,
N => N3,
Enable_out => open);
--C1:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale,
-- enable_in => enable_0_to_1, N_OUT => N1,
-- enable_out => enable_1_to_2);
--C2:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, -
-- enable_in => enable_1_to_2, N_OUT => N2,
-- enable_out => enable_2_to_3);
--C3:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale,
-- enable_in => enable_2_to_3, N_OUT => N3,
-- enable_out => open);
end Behavioral;
| gpl-3.0 | 1251487a541f67dc0cab08ccecbe81a5 | 0.553493 | 3.229142 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/sync.vhd | 13 | 3,382 | ----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Synchronizes la_input with clock on rising or falling edge and does some
-- optional preprocessing. (Noise filter and demux.)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync is
port(
la_input : in std_logic_vector (31 downto 0);
clock : in std_logic;
enableFilter : in std_logic;
enableDemux : in std_logic;
falling : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end sync;
architecture behavioral of sync is
component demux
port(
la_input : in std_logic_vector(15 downto 0);
la_input180 : in std_logic_vector(15 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
component filter
port(
la_input : in std_logic_vector(31 downto 0);
la_input180 : in std_logic_vector(31 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
attribute equivalent_register_removal : string;
signal filteredla_input, demuxedla_input, synchronizedla_input, synchronizedla_input180: std_logic_vector (31 downto 0);
attribute equivalent_register_removal of demuxedla_input : signal is "no";
begin
Inst_demux: demux
port map(
la_input => synchronizedla_input(15 downto 0),
la_input180 => synchronizedla_input180(15 downto 0),
clock => clock,
output => demuxedla_input
);
Inst_filter: filter
port map(
la_input => synchronizedla_input,
la_input180 => synchronizedla_input180,
clock => clock,
output => filteredla_input
);
-- synch la_input guarantees use of iob ff on spartan 3 (as filter and demux do)
process (clock)
begin
if rising_edge(clock) then
synchronizedla_input <= la_input;
end if;
if falling_edge(clock) then
synchronizedla_input180 <= la_input;
end if;
end process;
-- add another pipeline step for la_input selector to not decrease maximum clock rate
process (clock)
begin
if rising_edge(clock) then
if enableDemux = '1' then
output <= demuxedla_input;
else
if enableFilter = '1' then
output <= filteredla_input;
else
if falling = '1' then
output <= synchronizedla_input180;
else
output <= synchronizedla_input;
end if;
end if;
end if;
end if;
end process;
end behavioral;
| mit | 2379050d0415a0e11e583062ce40488d | 0.654938 | 3.624866 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_i2c.vhd | 1 | 3,855 | --
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use Work.I2C_Master.all;
entity zpuino_i2c is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity zpuino_i2c;
architecture behave of zpuino_i2c is
signal scl_padi : std_logic; -- i2c clock line input
signal scl_pado : std_logic; -- i2c clock line output
signal scl_padoen : std_logic; -- i2c clock line output enable, active low
signal sda_padi : std_logic; -- i2c data line input
signal sda_pado : std_logic; -- i2c data line output
signal sda_padoen : std_logic; -- i2c data line output enable, active low
signal SCL : std_logic; -- i2c clock line
signal SDA : std_logic; -- i2c data line
begin
i2c_inst : I2C_MasterTop
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => wb_dat_o( 7 downto 0),
wb_dat_i => wb_dat_i( 7 downto 0),
wb_adr_i => wb_adr_i( 2 downto 0),
wb_we_i => wb_we_i,
wb_cyc_i => wb_cyc_i,
wb_stb_i => wb_stb_i,
wb_ack_o => wb_ack_o,
wb_inta_o => wb_inta_o,
-- i2c lines
scl_pad_i => scl_pad_i,
scl_pad_o => scl_pad_o,
scl_padoen_o => scl_padoen_o,
sda_pad_i => sda_pad_i,
sda_pad_o => sda_pad_o,
sda_padoen_o => sda_padoen_o
);
end behave;
| mit | cbfdc4144e633b876573063339f0b572 | 0.625162 | 3.225941 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/shifter.vhd | 14 | 3,771 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lshifter is
generic (
stages: integer := 3
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end lshifter;
architecture behave of lshifter is
subtype word is signed(63 downto 0);
type mregtype is array(0 to stages-1) of word;
signal rq: mregtype;
signal d: std_logic_vector(0 to stages -1);
begin
process(clk,inputA,inputB)
variable r: signed(63 downto 0);
variable idx: signed(31 downto 0);
begin
if rising_edge(clk) then
if rst='1' then
done <= '0';
else
d <= (others =>'0');
if enable='1' then
if multorshift='1' then
idx := signed(inputB);
else
case inputB(4 downto 0) is
when "00000" => idx := "00000000000000000000000000000001";
when "00001" => idx := "00000000000000000000000000000010";
when "00010" => idx := "00000000000000000000000000000100";
when "00011" => idx := "00000000000000000000000000001000";
when "00100" => idx := "00000000000000000000000000010000";
when "00101" => idx := "00000000000000000000000000100000";
when "00110" => idx := "00000000000000000000000001000000";
when "00111" => idx := "00000000000000000000000010000000";
when "01000" => idx := "00000000000000000000000100000000";
when "01001" => idx := "00000000000000000000001000000000";
when "01010" => idx := "00000000000000000000010000000000";
when "01011" => idx := "00000000000000000000100000000000";
when "01100" => idx := "00000000000000000001000000000000";
when "01101" => idx := "00000000000000000010000000000000";
when "01110" => idx := "00000000000000000100000000000000";
when "01111" => idx := "00000000000000001000000000000000";
when "10000" => idx := "00000000000000010000000000000000";
when "10001" => idx := "00000000000000100000000000000000";
when "10010" => idx := "00000000000001000000000000000000";
when "10011" => idx := "00000000000010000000000000000000";
when "10100" => idx := "00000000000100000000000000000000";
when "10101" => idx := "00000000001000000000000000000000";
when "10110" => idx := "00000000010000000000000000000000";
when "10111" => idx := "00000000100000000000000000000000";
when "11000" => idx := "00000001000000000000000000000000";
when "11001" => idx := "00000010000000000000000000000000";
when "11010" => idx := "00000100000000000000000000000000";
when "11011" => idx := "00001000000000000000000000000000";
when "11100" => idx := "00010000000000000000000000000000";
when "11101" => idx := "00100000000000000000000000000000";
when "11110" => idx := "01000000000000000000000000000000";
when "11111" => idx := "10000000000000000000000000000000";
when others =>
end case;
end if;
r := signed(inputA) * idx;
rq(0) <= r(63 downto 0);
d(0) <= '1';
for i in 1 to stages-1 loop
rq(i) <= rq(i-1);
d(i) <= d(i-1);
end loop;
done <= d(stages-1);
output <= std_logic_vector(rq(stages-1));
else
done <= '0';
end if;
end if;
end if;
end process;
end behave; | mit | ffed6a1a9058d23475fc8097b8c0709b | 0.5834 | 4.834615 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_rp/bg_rp_sim_netlist.vhdl | 1 | 41,919 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_rp/bg_rp_sim_netlist.vhdl
-- Design : bg_rp
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_rp_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_rp_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_rp_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0305060700020301000203010402010704020107030506070002030100030305",
INIT_01 => X"0001060700000107030506070000010700020301030506070402010704020107",
INIT_02 => X"0402010702050205020100070001060700000107000001070305060704020107",
INIT_03 => X"0000010703050607000203010001070500020301030506070402010700010205",
INIT_04 => X"0305070503050607000203010406030103050607000203010305060700020301",
INIT_05 => X"0402010704020107000001070406030100020301000001070406030100010607",
INIT_06 => X"0305060700020301040201070305060703050607000001070305060700000107",
INIT_07 => X"0003030503050607040201070002060000010607030506070305060703050705",
INIT_08 => X"0406030100000107000001070305060700020703030506070002030103050607",
INIT_09 => X"0305060703050607000207030205020502050205040603010305060700020703",
INIT_0A => X"0002030100020301000001070305060700010607040603010305060703050705",
INIT_0B => X"0002070304020107040201070002030104020107040201070305060700020301",
INIT_0C => X"0205020502050205000203010000010703050705030506070001060704020107",
INIT_0D => X"0001060700020703030506070402010704020107020502050001030103050607",
INIT_0E => X"0205020500020301030506070402010700020703000203010402010704060301",
INIT_0F => X"0002030100020703040201070305060700000107030506070402010703050607",
INIT_10 => X"0402010700020301040201070002070300020703030506070305060700000107",
INIT_11 => X"0402010700020301000203010402010700020301000203010402010700020301",
INIT_12 => X"0305060704020107020502050305060700010607040201070305060703050607",
INIT_13 => X"0000000000000000000000000000000002050205040201070305060700010607",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => addra(7 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
ADDRBWRADDR(4 downto 0) => B"10000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 11) => B"00000",
DIADI(10 downto 8) => dina(5 downto 3),
DIADI(7 downto 3) => B"00000",
DIADI(2 downto 0) => dina(2 downto 0),
DIBDI(15 downto 11) => B"00000",
DIBDI(10 downto 8) => dina(11 downto 9),
DIBDI(7 downto 3) => B"00000",
DIBDI(2 downto 0) => dina(8 downto 6),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
DOADO(10 downto 8) => douta(5 downto 3),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
DOADO(2 downto 0) => douta(2 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
DOBDO(10 downto 8) => douta(11 downto 9),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
DOBDO(2 downto 0) => douta(8 downto 6),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
ENARDEN => '1',
ENBWREN => '1',
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_rp_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_rp_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_rp_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_rp_blk_mem_gen_prim_wrapper_init
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_rp_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_rp_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_rp_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bg_rp_blk_mem_gen_prim_width
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_rp_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_rp_blk_mem_gen_top;
architecture STRUCTURE of bg_rp_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_rp_blk_mem_gen_generic_cstr
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_rp_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_rp_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_rp_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_rp_blk_mem_gen_top
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_rp_blk_mem_gen_v8_3_5 : entity is 8;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_rp_blk_mem_gen_v8_3_5 : entity is 8;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_rp_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_rp_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_rp_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_rp_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_rp_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_rp_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_rp_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_rp_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.70645 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_rp_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_rp_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_rp_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_rp_blk_mem_gen_v8_3_5 : entity is "bg_rp.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_rp_blk_mem_gen_v8_3_5 : entity is "bg_rp.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 156;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 156;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_rp_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_rp_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_rp_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_rp_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_rp_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 156;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 156;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_rp_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_rp_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_rp_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_rp_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_rp_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_rp_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_rp_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_rp_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_rp_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_rp_blk_mem_gen_v8_3_5_synth
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_rp is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_rp : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_rp : entity is "bg_rp,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_rp : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_rp : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_rp;
architecture STRUCTURE of bg_rp is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 8;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 8;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.70645 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_rp.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_rp.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 156;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 156;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 156;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 156;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_rp_blk_mem_gen_v8_3_5
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => B"00000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 72b2cf1efa09a68574a2ac0ae2c48755 | 0.679215 | 3.109257 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/zpuino_uart_rx.vhd | 13 | 4,937 | --
-- UART for ZPUINO - Receiver unit
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end entity zpuino_uart_rx;
architecture behave of zpuino_uart_rx is
component zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end component zpuino_uart_mv_filter;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
signal rxf: std_logic;
signal baudtick: std_logic;
signal rxd: std_logic_vector(7 downto 0);
signal datacount: unsigned(2 downto 0);
signal baudreset: std_logic;
signal filterreset: std_logic;
signal datao: std_logic_vector(7 downto 0);
signal dataready: std_logic;
signal start: std_logic;
signal debug_synctick_q: std_logic;
signal debug_baudreset_q: std_logic;
-- State
type uartrxstate is (
rx_idle,
rx_start,
rx_data,
rx_end
);
signal state: uartrxstate;
begin
data <= datao;
data_av <= dataready;
rxmvfilter: zpuino_uart_mv_filter
generic map (
bits => 4,
threshold => 10
)
port map (
clk => clk,
rst => rst,
sin => rx,
sout => rxf,
clear => filterreset,
enable => rxclk
);
filterreset <= baudreset or baudtick;
--istart <= start;
baudgen: uart_brgen
port map (
clk => clk,
rst => baudreset,
en => rxclk,
count => x"000f",
clkout => baudtick
);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
state <= rx_idle;
dataready <= '0';
baudreset <= '0';
start<='0';
else
baudreset <= '0';
start<='0';
if read='1' then
dataready <= '0';
end if;
case state is
when rx_idle =>
if rx='0' then -- Start bit
state <= rx_start;
baudreset <= '1';
start <='1';
end if;
when rx_start =>
if baudtick='1' then
-- Check filtered output.
if rxf='0' then
datacount <= b"111";
state <= rx_data; -- Valid start bit.
else
state <= rx_idle;
end if;
end if;
when rx_data =>
if baudtick='1' then
rxd(7) <= rxf;
rxd(6 downto 0) <= rxd(7 downto 1);
datacount <= datacount - 1;
if datacount=0 then
state <= rx_end;
end if;
end if;
when rx_end =>
-- Check for framing errors ?
-- Do fast recovery here.
if rxf='1' then
dataready<='1';
datao <= rxd;
state <= rx_idle;
end if;
if baudtick='1' then
-- Framing error.
state <= rx_idle;
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
| mit | 091a21ffd4972f04ff93245052f944f6 | 0.588819 | 3.657037 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_uart.vhd | 13 | 6,945 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 3b283e7f5acf0edfc86f47462614e6c7 | 0.585169 | 3.112954 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/group_selector.vhd | 13 | 2,904 | ----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- multiplexes valid groups, output is registered
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity group_selector is
port(
clock : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_input_ready : in std_logic;
output : out std_logic_vector(31 downto 0);
output_ready : out std_logic;
disabledGroups : in std_logic_vector(3 downto 0)
);
end group_selector;
architecture behavioral of group_selector is
signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0);
signal tmp : std_logic_vector(31 downto 0);
begin
ib0 <= la_input(7 downto 0);
ib1 <= la_input(15 downto 8);
ib2 <= la_input(23 downto 16);
ib3 <= la_input(31 downto 24);
tmp <= -- select 8-bit enabled group
x"000000" & ib0 when disabledGroups = "1110" else
x"000000" & ib1 when disabledGroups = "1101" else
x"000000" & ib2 when disabledGroups = "1011" else
x"000000" & ib3 when disabledGroups = "0111" else
-- select 2 8-bit enabled groups
x"0000" & ib1 & ib0 when disabledGroups = "1100" else
x"0000" & ib2 & ib0 when disabledGroups = "1010" else
x"0000" & ib3 & ib0 when disabledGroups = "0110" else
x"0000" & ib2 & ib1 when disabledGroups = "1001" else
x"0000" & ib3 & ib1 when disabledGroups = "0101" else
x"0000" & ib3 & ib2 when disabledGroups = "0011" else
-- clear unused group
ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else
ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else
ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else
x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else
-- full
la_input when disabledGroups = "0000" else
(others => 'X');
process (clock)
begin
if rising_edge(clock) then
output <= tmp;
output_ready <= la_input_ready;
end if;
end process;
end behavioral; | mit | 253831436046481b5c51d862aff300ea | 0.634986 | 3.365006 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_250k/zpu_config.vhd | 13 | 2,676 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
constant Undefined: std_logic := '0';
end zpu_config;
| mit | 77e4ddf9807bc6dfe2f730276359d738 | 0.737668 | 3.732218 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_char_ram_8x8_sp.vhd | 13 | 16,221 | --
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
| mit | be213828cad4cc51343931dd5cedbed2 | 0.539794 | 1.618539 | false | false | false | false |
ordepmalo/matrizled | rtl/vhdl/clk_divider/sim/clk_divider_tb.vhd | 1 | 2,400 | -------------------------------------------------------------------------------
-- Title : Testbench for design "clk_divider"
-- Project :
-------------------------------------------------------------------------------
-- File : clk_divider_tb.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created : 2015-04-21
-- Last update : 2015-04-21
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-21 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity clk_divider_tb is
end entity clk_divider_tb;
-------------------------------------------------------------------------------
architecture clk_divider_tb_rtl of clk_divider_tb is
-- component generics
constant MAX_VALUE : natural := 20;
-- component ports
signal sysclk : std_logic := '0';
signal reset_n : std_logic := '0';
signal clk_divider_o : std_logic;
begin -- architecture clk_divider_tb_rtl
-- component instantiation
DUT: entity work.clk_divider
generic map (
MAX_VALUE => MAX_VALUE)
port map (
sysclk => sysclk,
reset_n => reset_n,
clk_divider_o => clk_divider_o);
-- clock generation
sysclk <= not sysclk after 5 ns;
-- reset generation
reset_proc: process
begin
reset_n <= '0';
wait for 50 us;
reset_n <= '1';
wait;
end process reset_proc;
-- Stimulus generation
stimulus_proc : process
begin
-- Add stimulus here
wait;
end process stimulus_proc;
end architecture clk_divider_tb_rtl;
-------------------------------------------------------------------------------
configuration clk_divider_tb_clk_divider_tb_rtl_cfg of clk_divider_tb is
for clk_divider_tb_rtl
end for;
end clk_divider_tb_clk_divider_tb_rtl_cfg;
-------------------------------------------------------------------------------
| mit | 0c2d752670792d1e879b78c13bbbd221 | 0.41375 | 4.878049 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/title3/synth/title3.vhd | 1 | 14,282 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY title3 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END title3;
ARCHITECTURE title3_arch OF title3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF title3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF title3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF title3_arch : ARCHITECTURE IS "title3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF title3_arch: ARCHITECTURE IS "title3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=title3.mif,C" &
"_INIT_FILE=title3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=3725,C_READ_DEPTH_A=3725,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=37" &
"25,C_READ_DEPTH_B=3725,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BH" &
"V_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.822999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "title3.mif",
C_INIT_FILE => "title3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 3725,
C_READ_DEPTH_A => 3725,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 3725,
C_READ_DEPTH_B => 3725,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.822999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END title3_arch;
| gpl-3.0 | 3527a886bc52b7d19fe818699a9c4362 | 0.625123 | 3.008003 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/ball_pixel_1/ball_pixel_sim_netlist.vhdl | 1 | 58,811 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_pixel_1/ball_pixel_sim_netlist.vhdl
-- Design : ball_pixel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end ball_pixel_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of ball_pixel_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000001950000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000042000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000045300000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000129B92000000000000000000000",
INIT_06 => X"00000000000000000000000000000000000000007AAABB940000000000000000",
INIT_07 => X"00000000000000000000000000000000000000000025ACB9ABB4000000000000",
INIT_08 => X"00000000000000000000000000000000000000000000006BBA9A99A400000000",
INIT_09 => X"40000000000000000000000000000000000000000000000007BBA9ABAAC50000",
INIT_0A => X"ABAA91000000000000000000000000000000000000000000000359BBAA9ABBB8",
INIT_0B => X"9BBA9ABB810000000000000000000000000000000000000000000005BA9ABB99",
INIT_0C => X"BBA9ABA9AABB800000000000000000000000000000000000000000000004ABA9",
INIT_0D => X"029BB99ABA99BB9A920000000000000000000000000000000000000000000038",
INIT_0E => X"000049BB99ABA9ABB99BB9300000000000000000000000000000000000000000",
INIT_0F => X"000000147ABBA9ABAA9ABA9ABC50000000000000000000000000000000000000",
INIT_10 => X"000000000019AA9ABA9ABB99ABA9AC5000000000000000000000000000000000",
INIT_11 => X"0000000000000018BBA9ABA99BBA9ABA9A400000000000000000000000000000",
INIT_12 => X"0000000000000000B209BA9AABA9ABA9AABAAB84000000000000000000000000",
INIT_13 => X"00000000000000000000941AB99BB99ABA99BB99AAA810000000000000000000",
INIT_14 => X"000000000000000000000000149A9ABB99ABA9ABB99BA2110000000000000000",
INIT_15 => X"000000000000000000000000000005CAABBA9ABA9ABBA9AB9000000000000000",
INIT_16 => X"0000000000000000000000000000000006CAABA9ABB99ABA9ABB810000000000",
INIT_17 => X"00068888600000000000000000000000000005AA9ABA99BBA9ABA99A91000000",
INIT_18 => X"0000003FFEEFF30000000000000000000000000005BAAABA9ABA9AABA9B84000",
INIT_19 => X"ABB4000007EF8119FE6000000000000000000000000006CAAB99ABA99BB99AC5",
INIT_1A => X"ABA9AA52000009F866669F8000000000000000000000000005AAAA9ABA9ABB99",
INIT_1B => X"ABB99ABAA810000009E07FF60E8000000000000000000000000005BAAA9ABAA9",
INIT_1C => X"9ABA99BBA9A9AB93000009E07FF60E8000000000000000000000000006CAABA9",
INIT_1D => X"05BAAABA9ABA999ABBB4000009F867768F8000000000000000000000000005AA",
INIT_1E => X"000006CAAB99ABA9A9ABBAA4000007EF8119FE60000000000000000000000000",
INIT_1F => X"0000000005AAAA9ABA9ABA9ABBA40000013FFEEFF30000000000000000000000",
INIT_20 => X"00000000000005BAAA9ABAA9ABA9ABB840000007899870000000000000000000",
INIT_21 => X"000000000000000006CAABA9ABB99ABA9ABB9100000000000000000000000000",
INIT_22 => X"0000000000000000000005B99ABA9ABB99ABA9AA800000000000000000000000",
INIT_23 => X"000000000000000000000000036AA9ABA9ABBA9ABA9AA5100000000000000000",
INIT_24 => X"0000000000000000000000000000000AB99BBA9ABA99BBAABB51100000000000",
INIT_25 => X"240000000000000000000000000000000018AABB99ABA9ABB999ABA893000000",
INIT_26 => X"AA916A200000000000000000000000000000001AB9ABA9ABAA9ABA999ABBA730",
INIT_27 => X"ABB99BB8AB9400000000000000000000000000000019BA9ABA9ABB99ABA999BB",
INIT_28 => X"AABA9AA9ABBAABB4000000000000000000000000000000017CA9ABA99BBA9ABA",
INIT_29 => X"BA99BB99A99ABA9A99A4000000000000000000000000000000005B9AABA9ABA9",
INIT_2A => X"99ABA9ABB99ABAABA9ABAAC5000000000000000000000000000000005AABB99A",
INIT_2B => X"36ABA9ABAA9ABA9AA9ABAA9ABBB8400000000000000000000000000000005BBA",
INIT_2C => X"0000007BBA9ABB99ABA99A9ABB99ABAA91000000000000000000000000000000",
INIT_2D => X"000000000006BBA9ABB99ABA9BA99BBA9ABB8100000000000000000000000000",
INIT_2E => X"00000000000000026ABA9ABBA9ABBBA9ABA9AABB800000000000000000000000",
INIT_2F => X"0000000000000000000007BBA9ABA99BB99ABA99BB9A92000000000000000000",
INIT_30 => X"000000000000000000000000006BABBA9ABB99ABA9ABB99BB930000000000000",
INIT_31 => X"0000000000000000000000000000002558BBA9ABA9ABAA9ABA9ABC5000000000",
INIT_32 => X"000000000000000000000000000000000000049BBA9ABA9ABB99ABA9AC500000",
INIT_33 => X"9B840000000000000000000000000000000000000029CCA9ABA99BBA9ABA9A40",
INIT_34 => X"BBA9ABB91000000000000000000000000000000000000004669BBBA9ABA9AABA",
INIT_35 => X"AAACBAABCAB90000000000000000000000000000000000000000007AA99ABA9A",
INIT_36 => X"04665456545565554200000000000000000000000000000000000000001129CC",
INIT_37 => X"0000000000000000000079000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end ball_pixel_blk_mem_gen_prim_width;
architecture STRUCTURE of ball_pixel_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.ball_pixel_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ball_pixel_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ball_pixel_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \ball_pixel_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \ball_pixel_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end ball_pixel_blk_mem_gen_generic_cstr;
architecture STRUCTURE of ball_pixel_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.ball_pixel_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\ball_pixel_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
douta(7 downto 0) => douta(11 downto 4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_top : entity is "blk_mem_gen_top";
end ball_pixel_blk_mem_gen_top;
architecture STRUCTURE of ball_pixel_blk_mem_gen_top is
begin
\valid.cstr\: entity work.ball_pixel_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end ball_pixel_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of ball_pixel_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.ball_pixel_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of ball_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of ball_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of ball_pixel_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of ball_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of ball_pixel_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of ball_pixel_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of ball_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of ball_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of ball_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of ball_pixel_blk_mem_gen_v8_3_5 : entity is "ball_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of ball_pixel_blk_mem_gen_v8_3_5 : entity is "ball_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of ball_pixel_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of ball_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_pixel_blk_mem_gen_v8_3_5 : entity is "yes";
end ball_pixel_blk_mem_gen_v8_3_5;
architecture STRUCTURE of ball_pixel_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.ball_pixel_blk_mem_gen_v8_3_5_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ball_pixel : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ball_pixel : entity is "ball_pixel,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_pixel : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ball_pixel : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end ball_pixel;
architecture STRUCTURE of ball_pixel is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "ball_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "ball_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 3600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 3600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 3600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 3600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.ball_pixel_blk_mem_gen_v8_3_5
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => B"000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 9e2e198a5725abc8cebe6d1c68c690d5 | 0.711993 | 2.901381 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpu_core_extreme_icache.vhd | 1 | 47,548 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
cache_flush: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_icache;
architecture behave of zpu_core_extreme_icache is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
component zpuino_icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(wordSize-1 downto 0);
address: in std_logic_vector(maxAddrBit downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end component;
signal cache_valid: std_logic;
signal cache_data: std_logic_vector(wordSize-1 downto 0);
signal cache_address: std_logic_vector(maxAddrBit downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_LoadStack,
State_Loadb,
State_Loadh,
State_Resync2,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Loadh,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := stackSize_bits-1;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_LSU,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
-- LSU
signal lsu_req: std_logic;
signal lsu_we: std_logic;
signal lsu_busy: std_logic;
signal lsu_data_read: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_write: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_sel: std_logic_vector(3 downto 0);
signal lsu_address: std_logic_vector(maxAddrBitIncIO downto 0);
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
--dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
--dbg_out.stacka <= std_logic_vector(exr.tos);
--dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
-- synopsys translate_off
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
-- synopsys translate_on
cache: zpuino_icache
generic map (
ADDRESS_HIGH => maxAddrBitBRAM
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => cache_flush,
-- Master wishbone interface
m_wb_ack_i => rom_wb_ack_i,
m_wb_dat_i => rom_wb_dat_i,
m_wb_adr_o => rom_wb_adr_o,
m_wb_cyc_o => rom_wb_cyc_o,
m_wb_stb_o => rom_wb_stb_o,
m_wb_stall_i => rom_wb_stall_i
);
lsu: zpuino_lsu
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_ack_i => wb_ack_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_adr_o => wb_adr_o(maxAddrBitIncIO downto 2),
wb_cyc_o => wb_cyc_o,
wb_stb_o => wb_stb_o,
wb_sel_o => wb_sel_o,
wb_we_o => wb_we_o,
req => lsu_req,
we => lsu_we,
busy => lsu_busy,
data_read => lsu_data_read,
data_write => lsu_data_write,
data_sel => lsu_data_sel,
address => lsu_address
);
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(cache_data, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(cache_data(31 downto 24));
when 1 => tOpcode := std_logic_vector(cache_data(23 downto 16));
when 2 => tOpcode := std_logic_vector(cache_data(15 downto 8));
when 3 => tOpcode := std_logic_vector(cache_data(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Loadh) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadh;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_StoreH) then
sampledDecodedOpcode<=Decoded_StoreH;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
--sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_LSU;
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
cache_enable <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, cache_valid, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, cache_stall
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
cache_address(maxAddrBit downto 0) <= std_logic_vector(decr.fetchpc(maxAddrBit downto 0));
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
cache_strobe <= DontCareValue;
else
cache_strobe <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and cache_stall='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cyc_o<='0';
cache_strobe<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
--rom_wb_cyc_o <='0';
cache_strobe <= '0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
--if exu_busy='0' then
w.valid := cache_valid;
--end if;
end if;
if cache_valid='1' then
--if exu_busy='0' then
w.im := sampledOpcode(7);
--end if;
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and cache_stall='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
--if cache_stall='0' then
if exu_busy='0' then
w.opcode := sampledOpcode;
end if;
--end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
if cache_stall='0' then
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
end if;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
--rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
if exu_busy='0' then
w.valid := decr.valid;
end if;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
--| Decoded_Load
| Decoded_LoadH
| Decoded_Store
| Decoded_StoreH
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(spMaxBit downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(spMaxBit downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
lsu_address <= std_logic_vector(exr.tos(maxAddrBitIncIO downto 0));
--wb_cyc_o <= exr.wb_cyc;
--wb_stb_o <= exr.wb_stb;
--wb_we_o <= exr.wb_we;
--lsu_data_write <= std_logic_vector( nos );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output,
lsu_busy, lsu_data_read
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
variable datawrite: std_logic_vector(wordSize-1 downto 0);
variable sel: std_logic_vector(3 downto 0);
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= (others => '0');
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= (others => '0');
wroteback := wroteback_q;
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
lsu_req <= '0';
lsu_we <= DontCareValue;
lsu_data_sel <= (others => DontCareValue);
lsu_data_write <= (others => DontCareValue);
case exr.state is
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(spMaxBit downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when Tos_Source_LSU =>
if lsu_busy='0' then
w.tos := unsigned(lsu_data_read);
end if;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<=(others =>'1');
wroteback:='1';
stack_b_enable<= '0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= (others => '1');
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= (others =>'1');
when Decoded_StoreSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<=(others =>'1');
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store | Decoded_StoreB | Decoded_StoreH =>
if prefr.decodedOpcode=Decoded_Store then
datawrite := std_logic_vector(nos);
sel := "1111";
elsif prefr.decodedOpcode=Decoded_StoreH then
datawrite := (others => DontCareValue);
if exr.tos(1)='1' then
datawrite(15 downto 0) := std_logic_vector(nos(15 downto 0)) ;
sel := "0011";
else
datawrite(31 downto 16) := std_logic_vector(nos(15 downto 0)) ;
sel := "1100";
end if;
else
datawrite := (others => DontCareValue);
case exr.tos(1 downto 0) is
when "11" =>
datawrite(7 downto 0) := std_logic_vector(nos(7 downto 0)) ;
sel := "0001";
when "10" =>
datawrite(15 downto 8) := std_logic_vector(nos(7 downto 0)) ;
sel := "0010";
when "01" =>
datawrite(23 downto 16) := std_logic_vector(nos(7 downto 0)) ;
sel := "0100";
when "00" =>
datawrite(31 downto 24) := std_logic_vector(nos(7 downto 0)) ;
sel := "1000";
when others =>
end case;
end if;
stack_a_writeenable <=sel;
lsu_data_sel <= sel;
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_write <= datawrite;
stack_a_writeenable <= sel;
w.state := State_ResyncFromStoreStack;
else
--w.wb_we := '1';
--w.wb_cyc := '1';
--w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
-- stack_a_enable<='0';
stack_a_enable<=not lsu_busy;
stack_a_writeenable <= (others => '0');
-- stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_b_enable<= not lsu_busy;
lsu_data_write <= datawrite;
instruction_executed := '0';
exu_busy <= '1';
lsu_req <= '1';
lsu_we <= '1';
if lsu_busy='0' then
wroteback := '0';
w.state := State_Resync2;
end if;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_Loadh =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_enable<='1';
exu_busy <= '1';
w.state := State_LoadStack;
else
exu_busy <= lsu_busy;
lsu_req <= '1';
lsu_we <= '0';
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable <= not lsu_busy;
if lsu_busy='0' then
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
end if;
else
wroteback := '0';
end if;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadh =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1) is
when '1' =>
w.tos(15 downto 0) := unsigned(exr.tos(15 downto 0));
when '0' =>
w.tos(15 downto 0) := unsigned(exr.tos(31 downto 16));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
wroteback_q <= '0';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
| mit | c08fd2d675d6860f9494fb91c574d5f3 | 0.552831 | 3.593953 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8.vhd | 13 | 6,645 | ----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8 is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic;
rx : in std_logic;
tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic;
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8 is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
reset => '0',
speed => SPEED,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
-- Inst_spi_slave: spi_slave
-- port map(
-- clock => clock,
-- data => output,
-- send => send,
-- mosi => mosi,
-- sclk => sclk,
-- cs => cs,
-- miso => miso,
-- cmd => cmd,
-- execute => execute,
-- busy => busy,
-- dataReady => dataReady,
-- tx_bytes => tx_bytes
-- );
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
| mit | 68be8e865e1a122d9588765a5a2eea56 | 0.629797 | 3.092136 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/select1/select1_sim_netlist.vhdl | 1 | 58,422 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/select1/select1_sim_netlist.vhdl
-- Design : select1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of select1_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end select1_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of select1_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"FF00000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000FFFFFF000000000FFFFFF00FFFFFFF0000000000000000000000000FFFF",
INIT_03 => X"000000000000000F0000F0000000000000000000000000000000000000000000",
INIT_04 => X"000000000000000000000000F0000FF00000000F0000FFFF00000FFFFFFFFF00",
INIT_05 => X"FF0000000FF00000FFFFFFFFFF00000000F0000FF000000FFFFFF00000000000",
INIT_06 => X"00F0000FF000000000000000000000FFFFFF00000FFF00000F000FFFFFF00000",
INIT_07 => X"0000FFFFF00000000000F00000000F00000000000000FFFFFFFF0F00000F0000",
INIT_08 => X"000000F0F00000FF00000F00000FFF0000000000000000000F0000FFFFFFF000",
INIT_09 => X"000FF0000FF0000F00000000000F00000000000000000000F000000000000000",
INIT_0A => X"000FF00000000000000000000F0FF00000F00000F0000000F000000000000000",
INIT_0B => X"000F000000000FFFFFFFFFF00000000000F00000000000F00000000000000000",
INIT_0C => X"0000000000000000FF00000F00000000000000000000F00F00000FF0000F0000",
INIT_0D => X"00F000000F0000FF000000F00FFFFFFFF000000FF0000000000000FF00000000",
INIT_0E => X"0000000000000000000F00000000000000FFF00000FF0000000000000000FFFF",
INIT_0F => X"000000000000000FF0000F000000FF0000F00000FF00F00000000000000F0000",
INIT_10 => X"00000000000000000000000000000000000000F000000000000000F0000000FF",
INIT_11 => X"000000000F0000000FFF00000000FF00000F000FF0000000FFF00F00000F000F",
INIT_12 => X"00000FF0FF0000FF00F000000000000000000000000000000000000000000000",
INIT_13 => X"00000F000000000000F000000000000000000FF00000FFFFF00000F00FF00000",
INIT_14 => X"0FFF00000F0FF000000000000FFFF00000F00FF0000000000000000000000000",
INIT_15 => X"00FF0000F0000000000000000FF000000FFFFF000000000000000000FFF0000F",
INIT_16 => X"00000F000000FF0000FFF0000000F0F0000000000000000F00000F000FFF0000",
INIT_17 => X"00FF0000F00000FFFFFFFFFFFFFFF0000000000000000FFF0000F000F0000000",
INIT_18 => X"00000FFF000FF00000000000FF00000000000F000000000F0F0000000F000000",
INIT_19 => X"0FF0F000000FFFF000000FF0000F0000000000000000000FF000000000000000",
INIT_1A => X"000FFFF00000FFF000000000F000000FF0000000000FFF0000000000F0000000",
INIT_1B => X"FF00000000FF0000000FF00FF0000FF00FFFFFFFFFFFFFF00000000000000000",
INIT_1C => X"0000000000000000000000000FF0000F0FF00000000F0000000FFFFFFFFFFFF0",
INIT_1D => X"00000000000000000000FFFFFFFFFFFFFFFFFFF0000FFFFFF000000000000000",
INIT_1E => X"000000000000000000000000000000000000000000000FFFFFF00FFFFFFFFFF0",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \select1_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \select1_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \select1_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \select1_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"4F4F4F4F4F4F4F4F500000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_01 => X"4F0000000000004F4F000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_02 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000000000004F4F4F4F4F4F4F4F",
INIT_03 => X"FFFF004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_04 => X"FFFFFF00000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00FFFFFFFF",
INIT_05 => X"4F4F4F1000FFFFFFFFFFFF004F4F4F4F4F4F4F00FFFFFFFFFFFF0000FFFFFFFF",
INIT_06 => X"00004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_07 => X"000000000000004F4F4F4F4F4F4F00FFF0F0F0F0FF004F4F4F4F4F4F00000000",
INIT_08 => X"4F4F0000000000FFF0F0F0F0FFFFFFFFF0F0F0F0F0FFFFFFFFFFFFFFFFFF0000",
INIT_09 => X"4F4F4F4F4F4F4F4F4F4F4F0000000000004F4F4F4F4F0000FFF0F0F0F0FFFF00",
INIT_0A => X"0000FFF0FFFFF0FFFF004F4F4F4F00FFFFFFFFFFFF004F4F4F4F4F4F4F4F4F4F",
INIT_0B => X"FFFFF0F0FFFFFFF0F0FFFFF0F0F0F0F0FFFFFFFFFFFFFFFFFFFF000000000000",
INIT_0C => X"FFFFFFFF0000000000FFFFFFF0FFFFF0F0FF000000FFFFFFFFFFFFF0FFFFF0F0",
INIT_0D => X"4F00FFF0F0F0F0FFFF0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00FFFF",
INIT_0E => X"FFFFF0F0F0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF00FFF0FFFFF0F0FF004F4F4F",
INIT_0F => X"F0FFFFF0FFFFFFFFFFF0F0F0F0F0F0F0FFFFF0F0FFF0FFFFF0FFFFF0F0FFF0FF",
INIT_10 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000FFF0F0F0F0FFFFFFFFFFFFFFF0F0F0",
INIT_11 => X"F0F0F0F0F0F0FF00FFF0F0FFFFF0FFFF004F4F4F00FFF0FFFFF0F0FFFFFF004F",
INIT_12 => X"F0F0F0FFFFFFF0F0F0F0FFFFFFFFFFF0FFF0F0FFFFFFFFFFF0FFFFFFFFFFF0F0",
INIT_13 => X"000000FFFFF0FFFFF0FFFFF0F0F0F0FFF0FFFFFFFFFFF0F0F0F0F0FFF0FFFFFF",
INIT_14 => X"F0F0FF004F4F4F00FFF0FFFFFFF0F0F0FF004F4F4F4F4F4F4F4F000000000000",
INIT_15 => X"FFFFF0FFFFF0FFFFFFF0F0F0F0F0F0FFFFFFFFFFFFFFFFFFF0FF00FFFFF0FFFF",
INIT_16 => X"FFF0FFF0F0F0FFFFFFFFFFFFFFF0FFF0FFFFF0F0FFFFFFFFFFFFFFFFF0F0F0F0",
INIT_17 => X"FFFFF0FF004F00000000000000FFFFFFFFFFFFFFFFFFFFF0F0FFFFF0F0F0F0FF",
INIT_18 => X"FFF0F0F0FFFFF0F0F0F0F0F0FF0000FFF0FFFFFFF0FFFF004F4F00FFF0F0FFFF",
INIT_19 => X"F0F0F0FFFFF0F0FFFFF0F0FFFFF0F0F0FFFFF0FFFFF0F0FFF0F0FFFFFFF0F0FF",
INIT_1A => X"FFF0F0F0F0F0F0FFFFF0F0FFFFFFFFFFF0FFFFFFF0F0FFFFF0F0F0F0FFFFF0F0",
INIT_1B => X"0000FFF0FFFFFFF0F0FF004F4F00FFFFF0FFFFF0F0F0FF0000FFFFFFFFFFFFFF",
INIT_1C => X"F0F0FFFFFFF0FFFFFFF0FFFFF0F0FFFFF0F0FFF0FFFFF0F0FFFFF0F0FFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFF0F0F0F0F0F0F0FFFFF0F0FFF0FFFFFFF0F0FFFFF0F0FFFF",
INIT_1E => X"4F00FFF0FFFFF0F0FFFF0000FFF0F0F0F0F0F0F0F0FFFFFFFFF0F0FFF0FFFFF0",
INIT_1F => X"F0F0FFFFF0F0FFFFF0F0F0F0FFFFF0FFFF00000000FFF0FFFFFFFFF0FFFF0000",
INIT_20 => X"FFFFFFFFFFF0FFF0FFFFFFF0F0FFFFF0F0F0FFFFF0F0FFF0F0FFFFFFF0F0FFFF",
INIT_21 => X"F0FFFFFFF0F0FFFFFFFFFFFFFFF0F0F0FFFFF0FFFFF0F0FFFFFFFFF0F0FFFFFF",
INIT_22 => X"FFF0F0FF004F00FFFFF0FFFFFFFFF0F0FFFFFF0000FFF0F0FFFFF0FF000000FF",
INIT_23 => X"F0FFFFF0F0FFFFFFF0FFF0FFFFFFFFFFF0FFFFFFF0FFFFF0F0F0F0F0FFFFF0FF",
INIT_24 => X"FFF0F0FFFFF0FFFFFFF0F0FFFFFFFFF0FFF0F0F0FFFFFFFFF0F0F0FFFFFFF0F0",
INIT_25 => X"FFFFF0F0F0FFFF00FFFFF0FFFFF0FFFF0000FFF0F0FFFFFFFFFFFFFFFFF0FFFF",
INIT_26 => X"FFFFFFF0F0FFFFF0F0FFFFF0FFFFFFFFFFF0F0FFFFF0FF0000FFFFF0F0FFFFF0",
INIT_27 => X"FFFFF0FFF0FFF0F0F0FFFFFFF0F0F0F0F0F0FFF0FFFFF0F0F0FFFFF0F0F0FFFF",
INIT_28 => X"F0F0FF0000FFFFF0F0F0FFFFFFFFF0F0F0F0FFFFF0F0F0FFFFF0FFFFFFFFF0FF",
INIT_29 => X"4FFFFFFFF0F0FFFFF0FF00FFFFF0F0FFFFFFF0F0FFFFFFF0F0FFFFFFFFF0FFFF",
INIT_2A => X"F0FFFFFFFFFFF0FFFFF0F0F0F0FFFFF0F0F0F0F0FFFFFFF0FFFFFFF0FFFFF0FF",
INIT_2B => X"F0F0FFFFF0F0F0F0FFF0F0FFFFFFFFFFFFFFF0FFFFF0FFF0F0FFFFF0F0F0FFFF",
INIT_2C => X"F0FFFFFFFFF0F0F0FFFFFFF0F0F0F0FFF0F0FFFFF0FF004F00FFFFFFF0F0F0F0",
INIT_2D => X"F0FFFFF0F0FFF0F0FFFFF0F0FFFFF0FFFFF0FFFFFFF0F0F0FFFFFFF0FF00FFF0",
INIT_2E => X"FFFFFFFFF0F0F0FFFFF0FFF0F0FFFFFFF0F0F0F0FF000000FFF0F0FFFFFFFFF0",
INIT_2F => X"FFF0FFFFF0FFFFF0FF004F4F0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F0FF",
INIT_30 => X"F0F0FFFFF0FFF0F0F0FFFFFFFFF0F0FF00FFF0FFFFFFFFF0F0FFF0F0F0FFFFFF",
INIT_31 => X"F0F0F0F0F0FFFFFF004F00FFFFF0F0FFFFFFF0F0FFFFFFF0FFFFF0F0FFFFF0F0",
INIT_32 => X"4F0000000000000000000000000000FFFFF0F0F0F0FFFFF0F0F0F0F0F0FFFFF0",
INIT_33 => X"F0FFFF00FFF0F0FFFFF0F0FFFFFFFFF0F0F0F0F0F0FFFFF0F0F0F0FF004F4F4F",
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INIT_39 => X"0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000FFFFF0F0F0F0FF",
INIT_3A => X"FFFFFFFFFFFFFF004F4F00FFFFFFFFFFFF004F4F000000000000000000000000",
INIT_3B => X"4F4F4F4F4F4F0000000000000000000000004F00FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"4F4F4F4F4F4F4F4F4F4F4F4F00FFFFFFFFFFFF0000FFFFFFFFFFFFFFFFFFFF00",
INIT_3D => X"000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_3E => X"4F4F4F4F4F4F4F000000000000000000000000000000000000004F4F4F4F0000",
INIT_3F => X"0000000000004F00000000000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of select1_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end select1_blk_mem_gen_prim_width;
architecture STRUCTURE of select1_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.select1_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \select1_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \select1_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \select1_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \select1_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\select1_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of select1_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end select1_blk_mem_gen_generic_cstr;
architecture STRUCTURE of select1_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.select1_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\select1_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
douta(7 downto 0) => douta(11 downto 4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of select1_blk_mem_gen_top : entity is "blk_mem_gen_top";
end select1_blk_mem_gen_top;
architecture STRUCTURE of select1_blk_mem_gen_top is
begin
\valid.cstr\: entity work.select1_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of select1_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end select1_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of select1_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.select1_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of select1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of select1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of select1_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of select1_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of select1_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of select1_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of select1_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of select1_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of select1_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of select1_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of select1_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of select1_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of select1_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of select1_blk_mem_gen_v8_3_5 : entity is "select1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of select1_blk_mem_gen_v8_3_5 : entity is "select1.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of select1_blk_mem_gen_v8_3_5 : entity is 2071;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of select1_blk_mem_gen_v8_3_5 : entity is 2071;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of select1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of select1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of select1_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of select1_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of select1_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of select1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of select1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of select1_blk_mem_gen_v8_3_5 : entity is 2071;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of select1_blk_mem_gen_v8_3_5 : entity is 2071;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of select1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of select1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of select1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of select1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of select1_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of select1_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of select1_blk_mem_gen_v8_3_5 : entity is "yes";
end select1_blk_mem_gen_v8_3_5;
architecture STRUCTURE of select1_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.select1_blk_mem_gen_v8_3_5_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity select1 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of select1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of select1 : entity is "select1,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of select1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of select1 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end select1;
architecture STRUCTURE of select1 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "select1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "select1.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2071;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2071;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2071;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2071;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.select1_blk_mem_gen_v8_3_5
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => B"000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 4a45f79bc85a9b0d8038366bc0aa7e2a | 0.7123 | 3.326046 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_gpio.vhd | 1 | 9,885 | --
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
entity zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end entity zpuino_gpio;
architecture behave of zpuino_gpio is
signal gpio_q: std_logic_vector(127 downto 0); -- GPIO output data FFs
signal gpio_tris_q: std_logic_vector(127 downto 0); -- Tristate FFs
signal ppspin_q: std_logic_vector(127 downto 0); -- SPP pin mode FFs
subtype input_number is integer range 0 to 127;
type mapper_q_type is array(0 to 127) of input_number;
signal input_mapper_q: mapper_q_type; -- Mapper for output pins (input data)
signal output_mapper_q: mapper_q_type; -- Mapper for input pins (output data)
signal gpio_r_i: std_logic_vector(127 downto 0);
signal gpio_tris_r_i: std_logic_vector(127 downto 0);
signal gpio_i_q: std_logic_vector(127 downto 0);
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
gpio_t <= gpio_tris_q(gpio_count-1 downto 0);
-- Generate muxers for output.
tgen: for i in 0 to gpio_count-1 generate
process( wb_clk_i )
begin
if rising_edge(wb_clk_i) then -- synchronous output
-- Enforce RST on gpio_o
if wb_rst_i='1' then
gpio_o(i)<='1';
else
if ppspin_q(i)='1' and spp_cap_out(i)='1' then
gpio_o(i) <= spp_data( input_mapper_q(i));
else
gpio_o(i) <= gpio_q(i);
end if;
end if;
end if;
end process;
end generate;
-- Generate muxers for input
spprgen: for i in 0 to gpio_count-1 generate
gpio_i_q(i) <= gpio_i(i) when spp_cap_in(i)='1' else DontCareValue;
process( gpio_i_q(i), output_mapper_q(i) )
begin
spp_read(i) <= gpio_i_q( output_mapper_q(i) );
end process;
end generate;
ilink1: for i in 0 to gpio_count-1 generate
gpio_r_i(i) <= gpio_i(i);
gpio_tris_r_i(i) <= gpio_tris_q(i);
end generate;
ilink2: for i in gpio_count to 127 generate
gpio_r_i(i) <= DontCareValue;
gpio_tris_r_i(i) <= DontCareValue;
end generate;
process(wb_adr_i,gpio_r_i,gpio_tris_r_i,ppspin_q)
begin
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_r_i(127 downto 96);
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_tris_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_tris_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_tris_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_tris_r_i(127 downto 96);
when others =>
end case;
when "10" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= ppspin_q(31 downto 0);
when "01" =>
wb_dat_o <= ppspin_q(63 downto 32);
when "10" =>
wb_dat_o <= ppspin_q(95 downto 64);
when "11" =>
wb_dat_o <= ppspin_q(127 downto 96);
when others =>
end case;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
gpio_tris_q <= (others => '1');
ppspin_q <= (others => '0');
gpio_q <= (others => DontCareValue);
-- Default values for input/output mapper
--for i in 0 to 127 loop
-- input_mapper_q(i) <= 0;
-- output_mapper_q(i) <= 0;
--end loop;
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(10 downto 9) is
when "00" =>
case wb_adr_i(6 downto 4) is
when "000" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "001" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_tris_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_tris_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_tris_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_tris_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "010" =>
if zpuino_pps_enabled then
case wb_adr_i(3 downto 2) is
when "00" =>
ppspin_q(31 downto 0) <= wb_dat_i;
when "01" =>
ppspin_q(63 downto 32) <= wb_dat_i;
when "10" =>
ppspin_q(95 downto 64) <= wb_dat_i;
when "11" =>
ppspin_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
end if;
when "100" => -- set bits
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= gpio_q(31 downto 0) or wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= gpio_q(63 downto 32) or wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= gpio_q(95 downto 64) or wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= gpio_q(127 downto 96) or wb_dat_i;
when others =>
end case;
when "101" => -- clear bits
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= gpio_q(31 downto 0) and not wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= gpio_q(63 downto 32) and not wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= gpio_q(95 downto 64) and not wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= gpio_q(127 downto 96) and not wb_dat_i;
when others =>
end case;
when "110" => -- toggle bits
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= gpio_q(31 downto 0) xor wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= gpio_q(63 downto 32) xor wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= gpio_q(95 downto 64) xor wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= gpio_q(127 downto 96) xor wb_dat_i;
when others =>
end case;
when others =>
end case;
when "01" =>
if zpuino_pps_enabled then
input_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when "10" =>
if zpuino_pps_enabled then
output_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
| mit | 060dbf13886df93f169db0edf3fb1545 | 0.541528 | 3.226175 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a-DLX.vhd | 1 | 6,252 | ------------------------------------------------------------------------------------------------
-- DLX. It contains both Datapath and Control Unit
-- NOTE: Synthesizable version, thus without IRAM and DRAM
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
entity DLX is
port (
-- INPUTS
clk : in std_logic;
rst : in std_logic;
iram_data : in std_logic_vector(31 downto 0);
-- from external DRAM
Data_out_fromRAM : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- OUTPUTS
addr_to_iram : out std_logic_vector(31 downto 0);
-- to external DRAM
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end DLX;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
architecture dlx_rtl of DLX is
--------------------------------------------------------------------
-- Components Declaration
--------------------------------------------------------------------
component cu is
port (
-- INPUTS
opcode : in std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : in std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
-- OUTPUTS
cw : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- Control Word + ALU operation for the current instruction decoded
);
end component;
component DataPath is
port(
-- INPUTS
clk : in std_logic;
rst : in std_logic;
fromIRAM : in std_logic_vector(31 downto 0); -- data coming from IRAM
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- Control Word + ALU operation for the current instruction decoded
-- from external DRAM
Data_out_fromRAM : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- OUTPUTS
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
Addr : out std_logic_vector(31 downto 0); -- address coming from PC (goes to IRAM)
-- to external DRAM
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end component;
----------------------------------------------------------------
-- Signals Declaration
----------------------------------------------------------------
signal opcode_i : std_logic_vector(OPCODE_SIZE - 1 downto 0);
signal func_i : std_logic_vector(FUNC_SIZE - 1 downto 0);
signal cw_i : std_logic_vector(CW_SIZE + ALUOP_SIZE - 1 downto 0);
begin -- DLX
-- component instantiations
u_cu: cu port map(
-- INPUTS
opcode => opcode_i, -- opcode field in instruction register
func => func_i, -- func field in instruction register
-- OUTPUTS
cw => cw_i
);
u_DataPath: DataPath port map(
-- INPUTS
clk => clk,
rst => rst,
fromIRAM => iram_data, -- data coming from IRAM
cw => cw_i,
-- from external DRAM
Data_out_fromRAM => Data_out_fromRAM, -- data to be read from the DRAM (load op)
--
-- OUTPUTS
opcode => opcode_i, -- opcode field in instruction register
func => func_i, -- func field in instruction register
Addr => addr_to_iram,
-- to external DRAM
read_op => read_op, -- ctrl sig for read operation
write_op => write_op, -- ctrl sig for write operation
nibble => nibble, -- specifies which byte of the 32-bit word to access
write_byte => write_byte, -- if '1' write operation on a single byte
Address_toRAM => Address_toRAM, -- address
Data_in => Data_in -- data to be written into the DRAM (store op)
--
);
end dlx_rtl;
| mit | 9503755e84d49c6f4f5ab16c77604ced | 0.424344 | 5.192691 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/simulation/frame_buffer_synth.vhd | 1 | 8,915 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: frame_buffer_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY frame_buffer_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE frame_buffer_synth_ARCH OF frame_buffer_synth IS
COMPONENT frame_buffer_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: frame_buffer_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| mit | 85c7694097840ad30e229330a631df32 | 0.569714 | 3.600565 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/i2c_master_byte_ctrl.vhd | 15 | 12,630 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $
--
-- $Date: 2004-02-18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
| mit | 8ec2d39832674485e97b9d617b2e9cac | 0.460174 | 3.8683 | false | false | false | false |
johnmurrayvi/misc-scripts-files | vhdl/others/simpleALU.vhdl | 1 | 2,581 | --
-- VERY simplistic ALU implementation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU is
Port ( enableF, Go, clk : in std_logic;
F : in std_logic_vector (3 downto 0);
BUSin : in std_logic_vector (15 downto 0);
R0,R1 : out std_logic_vector (15 downto 0);
ex : out std_logic -- exit is a keyword, so use ex instead
);
end ALU;
architecture behav of ALU is
type state_type is (S0,S1,S2,S3);
signal s_cur : state_type := S0;
signal F1 : std_logic_vector (3 downto 0);
signal REG0,REG1,A,C : std_logic_vector (15 downto 0);
signal T0,T1,T2,T3,I0,I1,I2,I3,ExtData,AddSub : std_logic;
signal R0in,R0out,R1in,R1out,Ain,Cin,Cout : std_logic;
begin
process (enableF,Go,clk)
begin
if (clk'event and clk = '1') then
if (enableF = '1') then
-- load instruction vector
F1 <= F;
-- reset instruction register
I0 <= '0';
I1 <= '0';
I2 <= '0';
I3 <= '0';
elsif (Go = '1') then
-- start fsm cycle
s_cur <= S1;
-- op code decode
-- note: I* must be reset to '0' at end of cycle
case F1(3)F1(2) is
when "00" => -- load
I0 <= '1';
when "01" => -- copy
I1 <= '1';
when "10" => -- add
I2 <= '1';
when "11" => -- subtract
I3 <= '1';
end case;
elsif
case s_cur is
when S2 =>
s_cur <= S3;
when S3 =>
s_cur <= S0;
end case;
end if;
end if;
-- internal signals
-- timing decode
T0 <= '1' when s_curr = S0 else '0';
T1 <= '1' when s_curr = S1 else '0';
T2 <= '1' when s_curr = S2 else '0';
T3 <= '1' when s_curr = S3 else '0';
-- Reg decode
Ain <= '1' when (T1 and (I2 or I3)) else '0';
Cin <= '1' when (T2 and (I2 or I3)) else '0';
Cout <= '1' when (T3 and (I2 or I3)) else '0';
R0in <= '1' when (
(T1 and ((I0 and not F1(1)) or (I1 and F1(0))) or
(T3 and ((I2 and not F1(1)) or (I3 and not F1(1)))
) else '0';
R0out <= '1' when (
(T1 and not F1(1) and (I1 or I2 or I3)) or
(T2 and not F1(0) and (I2 or I3))
) else '0';
R1in <= '1' when (
(T1 and ((I0 and F1(1)) or (I1 and F1(0))) or
(T3 and ((I2 and F1(1)) or (I3 and F1(1)))
) else '0';
R1out <= '1' when (
(T1 and F1(1) and (I1 or I2 or I3)) or
(T2 and F1(0) and (I2 or I3))
) else '0';
-- other signals
AddSub <= '1' when (T2 and I3) else '0';
-- external signals
ExtData <= '1' when (T1 and I0) else '0';
ex <= '1' when T3 else '0';
end process;
end behav;
| gpl-3.0 | 184c3b27ca3d9a3e82eea271373a0f52 | 0.531577 | 2.385397 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.d-memory.core/a.b.d.a-DRAM_block.vhd | 1 | 5,054 | ---------------------------------------------------------------------------
-- DRAM Block
-- This unit is the top-level entity containing the DRAM and the two MMU:
-- - MMU in
-- - MMU out
-- *** NB. reset has been removed in this synthesizable version
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
entity dram_block is
port (
-- INPUTS
address : in std_logic_vector(31 downto 0); -- address to the memory
data_write : in std_logic_vector(31 downto 0); -- data to be written in memory
mem_op : in std_logic_vector(5 downto 0); -- control signals for mem operations (sb, sw, lbu, lw, lhu, lb)
-- for protocol: external DRAM communication
Data_out : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- OUTPUTS
unaligned : out std_logic; -- control signal asserted in case of unaligned access
data_read : out std_logic_vector(31 downto 0); -- data read from memory
-- for protocol: external DRAM communication
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end dram_block;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture structural of dram_block is
-- Component declarations
component mmu_in_dram is
port (
--INPUTS
mem_op : in std_logic_vector(5 downto 0); -- control signal which groups the control signals directed to the memory (sb, sw, lbu, lw, lhu, lb)
aligned_address : in std_logic_vector(31 downto 0); -- aligned access to be translated
data : in std_logic_vector(31 downto 0); -- data to be written at the address specified in aligned address
--OUTPUTS
unaligned : out std_logic; -- signal directed to the PSW, asserted in case of unaligned access to the memory
nibble : out std_logic_vector(1 downto 0); -- last two bit of the incoming address in case of lb, sb, lbu, lhu
write_op : out std_logic; -- write signal to the memory
read_op : out std_logic; -- read signal to the memory
mem_address : out std_logic_vector(31 downto 0); -- physical address to memory
mem_data : out std_logic_vector(31 downto 0); -- data to written in the right format
write_byte : out std_logic -- Inform DRAM that we want to write a byte
);
end component;
component mmu_out_dram is
port (
-- INPUTS
data_ram : in std_logic_vector(31 downto 0); -- data coming from the dram
mem_op : in std_logic_vector(5 downto 0); -- control signals grouped in the following order (sb, sw, lbu, lw, lhu, lb)
nibble : in std_logic_vector(1 downto 0); -- which byte should be selected
unaligned : in std_logic; -- in case of unaligned access set the output to zero
-- OUTPUTS
data_read : out std_logic_vector(31 downto 0) -- data in the correct format
);
end component;
-- Internal Signals
signal nibble_i : std_logic_vector(1 downto 0);
signal unaligned_i : std_logic;
begin
-- components instatiation
mmu_in0: mmu_in_dram port map (
mem_op => mem_op,
aligned_address => address,
data => data_write,
unaligned => unaligned_i,
nibble => nibble_i,
write_op => write_op,
read_op => read_op,
mem_address => Address_toRAM,
mem_data => Data_in,
write_byte => write_byte
);
mmu_out0: mmu_out_dram port map (
data_ram => Data_out,
mem_op => mem_op,
nibble => nibble_i,
unaligned => unaligned_i,
data_read => data_read
);
-- Output assignment
unaligned <= unaligned_i;
nibble <= nibble_i;
end structural;
| mit | 97c7620d3f37e111b702713490f6a568 | 0.499011 | 4.468612 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Papilio_Default_Wing_Pinout.vhd | 13 | 13,006 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
| mit | d4f900aadea1be6fdc491f87637db329 | 0.604875 | 2.505973 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config_hyperion.vhd | 13 | 2,695 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config_hyperion is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
constant Undefined: std_logic := '0';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
end zpu_config_hyperion;
| mit | 2aee25165121a88394e3012221c41298 | 0.738404 | 3.712121 | false | false | false | false |
ordepmalo/matrizled | rtl/vhdl/edit_msg/sim/edit_msg_tb.vhd | 1 | 2,390 | -------------------------------------------------------------------------------
-- Title : Testbench for design "edit_msg"
-- Project :
-------------------------------------------------------------------------------
-- File : edit_msg_tb.vhd
-- Author : Pedro Bastos
-- Company :
-- Created : 2015-05-19
-- Last update : 2015-05-19
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-05-19 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity edit_msg_tb is
end entity edit_msg_tb;
-------------------------------------------------------------------------------
architecture edit_msg_tb_rtl of edit_msg_tb is
-- component ports
signal data_o : std_logic_vector (31 downto 0);
signal stb_i : std_logic := '0';
signal sysclk : std_logic := '0';
signal reset_n : std_logic := '0';
begin -- architecture edit_msg_tb_rtl
-- component instantiation
DUT : entity work.edit_msg
port map (
data_o => data_o,
stb_i => stb_i,
sysclk => sysclk,
reset_n => reset_n);
-- clock generation
sysclk <= not sysclk after 5 NS;
-- reset generation
reset_proc : process
begin
reset_n <= '0';
wait for 50 US;
reset_n <= '1';
wait;
end process reset_proc;
-- Stimulus generation
stimulus_proc : process
begin
-- Add stimulus here
wait for 100 US;
loop
stb_i <= '1';
wait for 10 NS;
stb_i <= '0';
wait for 100 US;
end loop;
wait;
end process stimulus_proc;
end architecture edit_msg_tb_rtl;
-------------------------------------------------------------------------------
configuration edit_msg_tb_edit_msg_tb_rtl_cfg of edit_msg_tb is
for edit_msg_tb_rtl
end for;
end edit_msg_tb_edit_msg_tb_rtl_cfg;
-------------------------------------------------------------------------------
| mit | 42ace67ca42adc07bae18fcdbb44c985 | 0.394142 | 4.587332 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/IO/timer.vhd | 1 | 2,253 | library ieee;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity timer is
generic(
speed: natural := 500
);
port(
clk : in std_logic;
clock_50 : in std_logic; --Use 50MHz for time keeping standard
rst : in std_logic;
tin : in std_logic_vector(31 downto 0);
tout : out std_logic_vector(31 downto 0);
wr : in std_logic;
INT : out std_logic;
IACK : in std_logic
);
end;
architecture repeat of timer is
signal data_reg : std_logic_vector(31 downto 0);
signal done : std_logic;
begin
tout(0) <= done;
---------------------------------------------------------
--Generating internal clock according to speed parameter
--Must run on the 50MHz clock so the time is correct
---------------------------------------------------------
slow_clock_generator: process(clock_50, data_reg(0))
variable loopcount : integer range 0 to 50000000;
begin
if(data_reg(0) = '0') then
loopcount := 0;
done <= '0';
elsif(clock_50'event AND clock_50 = '1') then
if(loopcount = 49999999) then --50,000,000 cycles of 50MHz clock = 1 second
done <= '1';
else
loopcount := loopcount + 1;
end if;
end if;
end process;
------------------------------------------------
--CPU write 32-bit unsigned to data register
--This number will not be destroyed for
--repeating time keeping function
--Timer stops counting when data_reg=0
--Write 0 to data_reg to stop timer
------------------------------------------------
timer_write: process(rst, clk) is
begin
if(rst='1') then
data_reg <= x"00000000";
elsif(clk'event and clk='1') then
if(wr='1') then
data_reg <= tin;
end if; --CPU write handle
end if;
end process timer_write;
-----------------------------------------------
-- INT Handshaking signal handling;
-- When count is DONE, set INT
-- When IACK is received, reset INT
-----------------------------------------------
INT_handshaking : process(rst, iack, done) is
begin
if(rst='1' or iack = '1') then
int <= '0';
elsif(done'event and done = '1') then
int <= '1';
end if;
end process;
end repeat;
| gpl-3.0 | 8939cc0af6761209ac8e49bfec04b25c | 0.524634 | 3.514821 | false | false | false | false |
feddischson/soc_maker | spec/test_soc_lib/cores/core_C_v1/core_C.vhd | 1 | 923 | library ieee;
library std;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity core_c is
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
wr_i : in std_logic;
bidir_io : inout std_logic_vector( 7 downto 0 )
);
end entity;
architecture IMP of core_c is
signal cnt : unsigned( 7 downto 0 );
begin
p : process( clk, rst )
begin
if clk'event and clk='1' then
if rst = '1' then
cnt <= ( others => '0' );
bidir <= ( others => 'Z' );
else
-- default case: we increase the counter
cnt <= cnt+1;
if en = '0' then
if wr = '1' then
cnt <= unsigned( bidir );
end if;
bidir <= ( others => 'Z' );
else
bidir <= std_logic_vector( cnt );
end if;
end if;
end if;
end process;
end architecture IMP;
| gpl-3.0 | 55241ff0ccd64cc79df491c2e7f66f77 | 0.503792 | 3.431227 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/platform/tta-accel.vhdl | 2 | 28,539 | -- Copyright (c) 2016-2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-----------------------------------------------------------------------------
-- Title : AXI interface for AlmaIF wrapper
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : tta-accel-rtl.vhdl
-- Author : Viitanen Timo (Tampere University) <[email protected]>
-- Company :
-- Created : 2016-01-27
-- Last update: 2017-03-27
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-01-27 1.0 viitanet Created
-- 2016-11-18 1.1 tervoa Added full AXI4 interface
-- 2017-03-27 1.2 tervoa Change to axislave interface
-- 2017-04-25 1.3 tervoa Merge entity and architecture, use generics
-- instead of consts from packages
-- 2017-06-01 1.4 tervoa Convert to memory buses with handshaking
-- 2018-07-30 1.5 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.tce_util.all;
entity tta_accel is
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer;
bus_count_g : integer;
local_mem_addrw_g : integer;
axi_offset_g : integer := 0;
full_debugger_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(4-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_awid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector (8-1 downto 0);
s_axi_awsize : in std_logic_vector (3-1 downto 0);
s_axi_awburst : in std_logic_vector (2-1 downto 0);
s_axi_bid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector (8-1 downto 0);
s_axi_arsize : in std_logic_vector (3-1 downto 0);
s_axi_arburst : in std_logic_vector (2-1 downto 0);
s_axi_rid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_rlast : out std_logic;
-- AXI4-Lite Master for global mem
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(32-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(dmem_data_width_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(dmem_data_width_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(32-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(dmem_data_width_g-1 downto 0);
aql_read_idx_in : in std_logic_vector(64-1 downto 0);
aql_read_idx_clear_out : out std_logic_vector(0 downto 0);
core_dmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_aaddr_in : in std_logic_vector(core_count_g*dmem_addr_width_g-1
downto 0);
core_dmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_astrb_in : in std_logic_vector((dmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_dmem_adata_in : in std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
core_dmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_rdata_out : out std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
data_a_avalid_out : out std_logic_vector(1-1 downto 0);
data_a_aready_in : in std_logic_vector(1-1 downto 0);
data_a_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_a_awren_out : out std_logic_vector(1-1 downto 0);
data_a_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_a_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_a_rvalid_in : in std_logic_vector(1-1 downto 0);
data_a_rready_out : out std_logic_vector(1-1 downto 0);
data_a_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_avalid_out : out std_logic_vector(1-1 downto 0);
data_b_aready_in : in std_logic_vector(1-1 downto 0);
data_b_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_b_awren_out : out std_logic_vector(1-1 downto 0);
data_b_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_b_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_rvalid_in : in std_logic_vector(1-1 downto 0);
data_b_rready_out : out std_logic_vector(1-1 downto 0);
data_b_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
core_pmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_aaddr_in : in std_logic_vector(core_count_g*pmem_addr_width_g-1
downto 0);
core_pmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_astrb_in : in std_logic_vector((pmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_pmem_adata_in : in std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
core_pmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_rdata_out : out std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
param_a_avalid_out : out std_logic_vector(1-1 downto 0);
param_a_aready_in : in std_logic_vector(1-1 downto 0);
param_a_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_a_awren_out : out std_logic_vector(1-1 downto 0);
param_a_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_a_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_a_rvalid_in : in std_logic_vector(1-1 downto 0);
param_a_rready_out : out std_logic_vector(1-1 downto 0);
param_a_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_avalid_out : out std_logic_vector(1-1 downto 0);
param_b_aready_in : in std_logic_vector(1-1 downto 0);
param_b_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_b_awren_out : out std_logic_vector(1-1 downto 0);
param_b_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_b_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_rvalid_in : in std_logic_vector(1-1 downto 0);
param_b_rready_out : out std_logic_vector(1-1 downto 0);
param_b_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
-- Debug ports
core_db_tta_nreset : out std_logic_vector(core_count_g-1 downto 0);
core_db_lockrq : out std_logic_vector(core_count_g-1 downto 0);
core_db_pc : in std_logic_vector(core_count_g*imem_addr_width_g-1
downto 0);
core_db_lockcnt : in std_logic_vector(core_count_g*64-1 downto 0);
core_db_cyclecnt : in std_logic_vector(core_count_g*64-1 downto 0)
);
end entity tta_accel;
architecture rtl of tta_accel is
constant dataw_c : integer := 32;
constant ctrl_addr_width_c : integer := 8;
constant dbg_core_sel_width_c : integer := bit_width(core_count_g);
constant imem_byte_sel_width_c : integer := bit_width(imem_data_width_g/8);
constant dmem_byte_sel_width_c : integer := bit_width(dmem_data_width_g/8);
constant pmem_byte_sel_width_c : integer := bit_width(pmem_data_width_g/8);
constant pmem_offset_c : integer := axi_offset_g + 2**(axi_addr_width_g-2)*3;
constant enable_dmem : boolean := dmem_data_width_g > 0;
constant enable_pmem : boolean := pmem_data_width_g > 0;
-- AXI slave memory bus
signal axi_avalid : std_logic;
signal axi_aready : std_logic;
signal axi_aaddr : std_logic_vector(axi_addr_width_g-2-1 downto 0);
signal axi_awren : std_logic;
signal axi_astrb : std_logic_vector(dataw_c/8-1 downto 0);
signal axi_adata : std_logic_vector(dataw_c-1 downto 0);
signal axi_rvalid : std_logic;
signal axi_rready : std_logic;
signal axi_rdata : std_logic_vector(dataw_c-1 downto 0);
signal dmem_avalid : std_logic;
signal dmem_aready : std_logic;
signal dmem_rvalid : std_logic;
signal dmem_rready : std_logic;
signal dmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_avalid : std_logic;
signal ctrl_aready : std_logic;
signal ctrl_rvalid : std_logic;
signal ctrl_rready : std_logic;
signal ctrl_rdata : std_logic_vector(core_count_g*dataw_c-1 downto 0);
signal pmem_avalid : std_logic;
signal pmem_aready : std_logic;
signal pmem_rvalid : std_logic;
signal pmem_rready : std_logic;
signal pmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal imem_avalid : std_logic;
signal imem_aready : std_logic;
signal imem_rvalid : std_logic;
signal imem_rready : std_logic;
signal imem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal core_busy : std_logic_vector(core_count_g-1 downto 0);
signal tta_sync_nreset : std_logic_vector(core_count_g-1 downto 0);
signal ctrl_en : std_logic;
signal ctrl_data : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_core_sel : std_logic_vector(bit_width(core_count_g)-1 downto 0);
signal mc_arb_pmem_avalid : std_logic;
signal mc_arb_pmem_aready : std_logic;
signal mc_arb_pmem_aaddr : std_logic_vector(pmem_addr_width_g-1 downto 0);
signal mc_arb_pmem_awren : std_logic;
signal mc_arb_pmem_astrb : std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
signal mc_arb_pmem_adata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal mc_arb_pmem_rvalid : std_logic;
signal mc_arb_pmem_rready : std_logic;
signal mc_arb_pmem_rdata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal axi_imem_avalid_out : std_logic;
signal axi_imem_aready_in : std_logic;
signal axi_imem_aaddr_out : std_logic_vector(imem_addr_width_g-1 downto 0);
signal axi_imem_awren_out : std_logic;
signal axi_imem_astrb_out : std_logic_vector((imem_data_width_g+7)/8-1 downto 0);
signal axi_imem_adata_out : std_logic_vector(imem_data_width_g-1 downto 0);
signal axi_imem_rvalid_in : std_logic;
signal axi_imem_rready_out : std_logic;
signal axi_imem_rdata_in : std_logic_vector(imem_data_width_g-1 downto 0);
signal tta_aready : std_logic_vector(core_count_g-1 downto 0);
signal tta_rvalid : std_logic_vector(core_count_g-1 downto 0);
signal aql_read_idx, aql_write_idx : std_logic_vector(64-1 downto 0);
signal aql_read_idx_clear : std_logic_vector(0 downto 0);
signal core_db_pc_start : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_instr : std_logic_vector(core_count_g*imem_data_width_g-1 downto 0);
signal core_db_pc_next : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_bustraces : std_logic_vector(core_count_g*32*bus_count_g-1 downto 0);
begin
-----------------------------------------------------------------------------
-- AXI Controller
-----------------------------------------------------------------------------
tta_axislave_1 : entity work.tta_axislave
generic map (
axi_addrw_g => axi_addr_width_g,
axi_idw_g => axi_id_width_g,
axi_dataw_g => dataw_c,
sync_reset_g => sync_reset_g
)
port map (
clk => clk,
rstx => rstx,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
avalid_out => axi_avalid,
aready_in => axi_aready,
aaddr_out => axi_aaddr,
awren_out => axi_awren,
astrb_out => axi_astrb,
adata_out => axi_adata,
rvalid_in => axi_rvalid,
rready_out => axi_rready,
rdata_in => axi_rdata
);
bus_splitter : entity work.membus_splitter
generic map (
core_count_g => core_count_g,
axi_addr_width_g => axi_addr_width_g,
axi_data_width_g => dataw_c,
ctrl_addr_width_g => ctrl_addr_width_c,
imem_addr_width_g => imem_addr_width_g + imem_byte_sel_width_c,
dmem_addr_width_g => dmem_addr_width_g + dmem_byte_sel_width_c,
pmem_addr_width_g => pmem_addr_width_g + pmem_byte_sel_width_c
) port map (
-- AXI slave
avalid_in => axi_avalid,
aready_out => axi_aready,
aaddr_in => axi_aaddr,
rvalid_out => axi_rvalid,
rready_in => axi_rready,
rdata_out => axi_rdata,
-- Control signals to arbiters
dmem_avalid_out => dmem_avalid,
dmem_aready_in => dmem_aready,
dmem_rvalid_in => dmem_rvalid,
dmem_rready_out => dmem_rready,
dmem_rdata_in => dmem_rdata,
pmem_avalid_out => pmem_avalid,
pmem_aready_in => pmem_aready,
pmem_rvalid_in => pmem_rvalid,
pmem_rready_out => pmem_rready,
pmem_rdata_in => pmem_rdata,
imem_avalid_out => imem_avalid,
imem_aready_in => imem_aready,
imem_rvalid_in => imem_rvalid,
imem_rready_out => imem_rready,
imem_rdata_in => imem_rdata,
-- Signals to debugger(s)
ctrl_avalid_out => ctrl_avalid,
ctrl_aready_in => ctrl_aready,
ctrl_rvalid_in => ctrl_rvalid,
ctrl_rready_out => ctrl_rready,
ctrl_rdata_in => ctrl_rdata,
ctrl_core_sel_out => ctrl_core_sel
);
------------------------------------------------------------------------------
-- Debugger
------------------------------------------------------------------------------
minidebug : entity work.minidebugger
generic map (
data_width_g => 32,
axi_addr_width_g => axi_addr_width_g,
core_count_g => core_count_g,
core_id_width_g => dbg_core_sel_width_c,
imem_data_width_g => imem_data_width_g,
imem_addr_width_g => imem_addr_width_g,
dmem_data_width_g => dmem_data_width_g,
dmem_addr_width_g => dmem_addr_width_g,
pmem_data_width_g => pmem_data_width_g,
pmem_addr_width_g => local_mem_addrw_g
) port map (
clk => clk,
rstx => rstx,
avalid_in => ctrl_avalid,
aready_out => ctrl_aready,
aaddr_in => axi_aaddr,
awren_in => axi_awren,
astrb_in => axi_astrb,
adata_in => axi_adata,
rvalid_out => ctrl_rvalid,
rready_in => ctrl_rready,
rdata_out => ctrl_rdata(dataw_c-1 downto 0),
core_sel_in => ctrl_core_sel,
tta_locked_in => core_busy,
tta_lockrq_out => core_db_lockrq,
tta_nreset_out => core_db_tta_nreset,
tta_pc_in => core_db_pc,
tta_lockcnt_in => core_db_lockcnt,
tta_cyclecnt_in => core_db_cyclecnt,
tta_read_idx_in => aql_read_idx,
tta_read_idx_clear_out => aql_read_idx_clear,
tta_write_idx_out => aql_write_idx
);
rdata_broadcast : for I in 1 to core_count_g-1 generate
ctrl_rdata((I+1)*dataw_c-1 downto I*dataw_c)
<= ctrl_rdata(dataw_c-1 downto 0);
end generate rdata_broadcast;
aql_read_idx <= aql_read_idx_in;
aql_read_idx_clear_out <= aql_read_idx_clear;
------------------------------------------------------------------------------
-- Memory arbitration between IO and TTA
------------------------------------------------------------------------------
mc_arbiters : if core_count_g > 1 generate
gen_dmem_arbiter : if enable_dmem generate
mc_arbiter_dmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_dmem_avalid_in,
tta_aready_out => core_dmem_aready_out,
tta_aaddr_in => core_dmem_aaddr_in,
tta_awren_in => core_dmem_awren_in,
tta_astrb_in => core_dmem_astrb_in,
tta_adata_in => core_dmem_adata_in,
tta_rvalid_out => core_dmem_rvalid_out,
tta_rready_in => core_dmem_rready_in,
tta_rdata_out => core_dmem_rdata_out,
-- Bus to memory
mem_avalid_out => data_a_avalid_out(0),
mem_aready_in => data_a_aready_in(0),
mem_aaddr_out => data_a_aaddr_out,
mem_awren_out => data_a_awren_out(0),
mem_astrb_out => data_a_astrb_out,
mem_adata_out => data_a_adata_out,
mem_rvalid_in => data_a_rvalid_in(0),
mem_rready_out => data_a_rready_out(0),
mem_rdata_in => data_a_rdata_in
);
end generate;
gen_pmem_arbiter : if enable_pmem generate
mc_arbiter_pmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => pmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_pmem_avalid_in,
tta_aready_out => core_pmem_aready_out,
tta_aaddr_in => core_pmem_aaddr_in,
tta_awren_in => core_pmem_awren_in,
tta_astrb_in => core_pmem_astrb_in,
tta_adata_in => core_pmem_adata_in,
tta_rvalid_out => core_pmem_rvalid_out,
tta_rready_in => core_pmem_rready_in,
tta_rdata_out => core_pmem_rdata_out,
-- Bus to memory
mem_avalid_out => mc_arb_pmem_avalid,
mem_aready_in => mc_arb_pmem_aready,
mem_aaddr_out => mc_arb_pmem_aaddr,
mem_awren_out => mc_arb_pmem_awren,
mem_astrb_out => mc_arb_pmem_astrb,
mem_adata_out => mc_arb_pmem_adata,
mem_rvalid_in => mc_arb_pmem_rvalid,
mem_rready_out => mc_arb_pmem_rready,
mem_rdata_in => mc_arb_pmem_rdata
);
end generate;
end generate;
no_mc_arbiters : if core_count_g <= 1 generate
data_a_avalid_out <= core_dmem_avalid_in;
core_dmem_aready_out <= data_a_aready_in;
data_a_aaddr_out <= core_dmem_aaddr_in;
data_a_awren_out <= core_dmem_awren_in;
data_a_astrb_out <= core_dmem_astrb_in;
data_a_adata_out <= core_dmem_adata_in;
core_dmem_rvalid_out <= data_a_rvalid_in;
data_a_rready_out <= core_dmem_rready_in;
core_dmem_rdata_out <= data_a_rdata_in;
mc_arb_pmem_avalid <= core_pmem_avalid_in(0);
core_pmem_aready_out(0) <= mc_arb_pmem_aready;
mc_arb_pmem_aaddr <= core_pmem_aaddr_in;
mc_arb_pmem_awren <= core_pmem_awren_in(0);
mc_arb_pmem_astrb <= core_pmem_astrb_in;
mc_arb_pmem_adata <= core_pmem_adata_in;
core_pmem_rvalid_out(0) <= mc_arb_pmem_rvalid;
mc_arb_pmem_rready <= core_pmem_rready_in(0);
core_pmem_rdata_out <= mc_arb_pmem_rdata;
end generate;
gen_decoder : if axi_offset_g /= 0 generate
decoder_pmem : entity work.almaif_decoder
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_addrw_g => 32,
mem_offset_g => pmem_offset_c,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
-- Bus from arbiter
arb_avalid_in => mc_arb_pmem_avalid,
arb_aready_out => mc_arb_pmem_aready,
arb_aaddr_in => mc_arb_pmem_aaddr,
arb_awren_in => mc_arb_pmem_awren,
arb_astrb_in => mc_arb_pmem_astrb,
arb_adata_in => mc_arb_pmem_adata,
--
arb_rvalid_out => mc_arb_pmem_rvalid,
arb_rready_in => mc_arb_pmem_rready,
arb_rdata_out => mc_arb_pmem_rdata,
-- Bus to local memory
mem_avalid_out => param_a_avalid_out(0),
mem_aready_in => param_a_aready_in(0),
mem_aaddr_out => param_a_aaddr_out,
mem_awren_out => param_a_awren_out(0),
mem_astrb_out => param_a_astrb_out,
mem_adata_out => param_a_adata_out,
--
mem_rvalid_in => param_a_rvalid_in(0),
mem_rready_out => param_a_rready_out(0),
mem_rdata_in => param_a_rdata_in,
-- AXI lite master
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awprot => m_axi_awprot,
--
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
--
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
--
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
--
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
m_axi_rdata => m_axi_rdata
);
end generate;
no_decoder : if axi_offset_g = 0 generate
param_a_avalid_out(0) <= mc_arb_pmem_avalid;
mc_arb_pmem_aready <= param_a_aready_in(0);
param_a_aaddr_out <= mc_arb_pmem_aaddr;
param_a_awren_out(0) <= mc_arb_pmem_awren;
param_a_astrb_out <= mc_arb_pmem_astrb;
param_a_adata_out <= mc_arb_pmem_adata;
mc_arb_pmem_rvalid <= param_a_rvalid_in(0);
param_a_rready_out(0) <= mc_arb_pmem_rready;
mc_arb_pmem_rdata <= param_a_rdata_in;
end generate;
gen_dmem_expander : if enable_dmem generate
dmem_expander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => dmem_avalid,
axi_aready_out => dmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => dmem_rvalid,
axi_rready_in => dmem_rready,
axi_rdata_out => dmem_rdata,
-- Bus to memory
mem_avalid_out => data_b_avalid_out(0),
mem_aready_in => data_b_aready_in(0),
mem_aaddr_out => data_b_aaddr_out,
mem_awren_out => data_b_awren_out(0),
mem_astrb_out => data_b_astrb_out,
mem_adata_out => data_b_adata_out,
mem_rvalid_in => data_b_rvalid_in(0),
mem_rready_out => data_b_rready_out(0),
mem_rdata_in => data_b_rdata_in
);
end generate;
no_dmem_expander : if not enable_dmem generate
dmem_aready <= '1';
dmem_rvalid <= '1';
dmem_rdata <= (others => '0');
end generate;
gen_pmem_expander : if enable_pmem generate
pmem_epander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => pmem_avalid,
axi_aready_out => pmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => pmem_rvalid,
axi_rready_in => pmem_rready,
axi_rdata_out => pmem_rdata,
-- Bus to memory
mem_avalid_out => param_b_avalid_out(0),
mem_aready_in => param_b_aready_in(0),
mem_aaddr_out => param_b_aaddr_out,
mem_awren_out => param_b_awren_out(0),
mem_astrb_out => param_b_astrb_out,
mem_adata_out => param_b_adata_out,
mem_rvalid_in => param_b_rvalid_in(0),
mem_rready_out => param_b_rready_out(0),
mem_rdata_in => param_b_rdata_in
);
end generate;
no_pmem_expander : if not enable_pmem generate
pmem_aready <= '1';
pmem_rvalid <= '1';
pmem_rdata <= (others => '0');
end generate;
end architecture rtl;
| mit | 6533a2639fbb962d08237e1a41755b01 | 0.576825 | 3.038003 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_basic.vhd | 1 | 9,280 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_no_int is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Behaviour of Rhody_CPU_no_int is
-- state machine: CPU_state
type State_type is (S1, S2, S3, S4, S5, S6, S7);
signal CPU_state: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, IR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
--Rhody Instruction Format
alias Opcode: std_logic_vector(5 downto 0) is IR(31 downto 26);
alias RX : std_logic_vector(2 downto 0) is IR(25 downto 23);
alias RY : std_logic_vector(2 downto 0) is IR(22 downto 20);
alias I : std_logic_vector(15 downto 0) is IR(15 downto 0);
alias M : std_logic_vector(19 downto 0) is IR(19 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when (CPU_state=S2) else
'1' when ((Opcode=LDM or Opcode=LDR) and CPU_state=S4) else
'1' when ((Opcode=POP or Opcode=RET) and CPU_state=S4) else
'1' when (Opcode=RETI and (CPU_state=S4 or CPU_state=S6)) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode=STM or Opcode=STR) and CPU_state=S1) else
'1' when ((Opcode=PUSH or Opcode=CALL) and CPU_state=S1) else
'1' when (Opcode=SYS and (CPU_state=S6 or CPU_state=S1)) else
'0'; --Memory write control signal
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
CPU_state <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
elsif clk'event and clk = '1' then
case CPU_state is
when S1 =>
MAR <= std_logic_vector(PC);
CPU_state <= S2;
when S2 =>
IR <= MEM_IN;
PC <= PC + 1;
CPU_state <= S3;
when S3 =>
if (Opcode=LDM) then
MAR <= x"000" & M; CPU_state <= S4;
elsif (Opcode=LDR) then
MAR <= register_file(to_integer(unsigned(RY))); CPU_state <= S4;
elsif (Opcode=LDI) then
register_file(to_integer(unsigned(RX)))<=(31 downto 16=>I(15)) & I; CPU_state <= S1;
elsif (Opcode=LDH) then
register_file(to_integer(unsigned(RX)))(31 downto 16)<= I; CPU_state <= S1;
elsif (Opcode=LDL) then
register_file(to_integer(unsigned(RX)))(15 downto 0)<= I; CPU_state <= S1;
elsif (Opcode=STM) then
MAR <= x"000" & M; MDR_out <= register_file(to_integer(unsigned(RX)));
CPU_state <= S4;
elsif (Opcode=STR) then
MAR <= register_file(to_integer(unsigned(RX)));
MDR_out <= register_file(to_integer(unsigned(RY))); CPU_state <= S4;
elsif (Opcode=MOV) then
register_file(to_integer(unsigned(RX)))<=register_file(to_integer(unsigned(RY)));
CPU_state <= S1;
elsif (Opcode=ADD or Opcode=SUB or Opcode=MUL or Opcode=CMP or
Opcode=IAND or Opcode=IOR or Opcode=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY))); CPU_state <= S4;
elsif (Opcode=IROR) then
CPU_state <= S4;
elsif (Opcode=ADI or Opcode=CMPI) then
operand1 <= (31 downto 16=>I(15)) & I; CPU_state <= S4;
elsif (Opcode=JMP or
(Opcode=JNZ and Z='0') or (Opcode=JZ and Z='1') or
(Opcode=JNS and S='0') or (Opcode=JS and S='1') or
(Opcode=JNV and V='0') or (Opcode=JV and V='1') or
(Opcode=JNC and C='0') or (Opcode=JC and C='1') ) then
PC <= x"000" & unsigned(M); CPU_state <= S1;
elsif (Opcode=CALL or Opcode=PUSH or Opcode=SYS) then
SP <= SP + 1; CPU_state <= S4;
elsif (Opcode=RET or Opcode=RETI or Opcode=POP) then
MAR <= std_logic_vector(SP); CPU_state <= S4;
else CPU_state <= S1;
end if;
when S4 =>
if (Opcode=LDM or Opcode=LDR) then
MDR_in <= MEM_in; CPU_state <= S5;
elsif (Opcode=STM or Opcode=STR) then
CPU_state <= S1;
elsif (Opcode=ADD or Opcode=SUB or Opcode=IROR or Opcode=IAND or
Opcode=MUL or Opcode=IOR or Opcode=IXOR or Opcode=ADI) then
register_file(to_integer(unsigned(RX))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
CPU_state <= S1;
elsif (Opcode=CMP or Opcode=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
CPU_state <= S1;
elsif (Opcode=CALL or Opcode=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
CPU_state <= S5;
elsif (Opcode=RET or Opcode=RETI or Opcode=POP) then
MDR_in <= MEM_IN; SP <= SP - 1; CPU_state <= S5;
elsif (Opcode=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX)));
CPU_state <= S5;
else CPU_state <= S1;
end if;
when S5 =>
if (Opcode=LDM or Opcode=LDR or Opcode=POP) then
register_file(to_integer(unsigned(RX))) <= MDR_in;
CPU_state <= S1;
elsif (Opcode=CALL) then
PC <= x"000" & unsigned(M); CPU_state <= S1;
elsif (Opcode=RET) then
PC <= unsigned(MDR_in); CPU_state <= S1;
elsif (Opcode=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
CPU_state <= S6;
elsif (Opcode=PUSH) then
CPU_state <= S1;
elsif (Opcode=SYS) then
SP <= SP + 1; CPU_state <= S6;
else CPU_state <= S1;
end if;
when S6 =>
if (Opcode=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1; CPU_state <= S7;
elsif (Opcode=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW; CPU_state <= S7;
else CPU_state <= S1;
end if;
when S7 =>
if (Opcode=RETI) then
PC <= unsigned(MDR_in); CPU_state <= S1;
elsif (Opcode=SYS) then
PC <= X"000FFC0"&unsigned(IR(3 downto 0)); CPU_state <= S1;
else CPU_state <= S1;
end if;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX)));
-----------------------------------------------------
end Behaviour;
| gpl-3.0 | 8c754d8b0e4a2ce0be89bc4125de7577 | 0.619181 | 2.823243 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/addr_gen_tb.vhd | 1 | 4,287 | -- addr_gen_tb.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity addr_gen_tb is
end entity;
architecture behavioral of addr_gen_tb is
-- Component Declaration for the Unit Under Test (UUT)
component addr_gen
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
lvl: in std_logic_vector(FFTEXP-2 downto 0); -- iteration level of butterflies
bfno: in std_logic_vector(FFTEXP-2 downto 0); -- butterfly number in current level
addra1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank A
addra2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank A
en_wrta: out std_logic; -- write enable for membank A, high active
addrb1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank B
addrb2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank B
en_wrtb: out std_logic; -- write enable for membank B, high active
addrtf: out std_logic_vector(FFTEXP-2 downto 0)); -- twiddle factor address
end component;
-- Clock period definitions
constant clk_period: time := 10 ns;
-- Generics
constant RSTDEF: std_logic := '0';
constant FFTEXP: natural := 3; -- 8-point FFT
-- Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal swrst: std_logic := '0';
signal en: std_logic := '0';
signal lvl: std_logic_vector(FFTEXP-2 downto 0) := (others => '0');
signal bfno: std_logic_vector(FFTEXP-2 downto 0) := (others => '0');
-- Outputs
signal addra1: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal addra2: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal en_wrta: std_logic := '0';
signal addrb1: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal addrb2: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal en_wrtb: std_logic := '0';
signal addrtf: std_logic_vector(FFTEXP-2 downto 0) := (others => '0');
begin
-- Instantiate the Unit Under Test (UUT)
uut: addr_gen
generic map(RSTDEF => RSTDEF,
FFTEXP => FFTEXP)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
lvl => lvl,
bfno => bfno,
addra1 => addra1,
addra2 => addra2,
en_wrta => en_wrta,
addrb1 => addrb1,
addrb2 => addrb2,
en_wrtb => en_wrtb,
addrtf => addrtf);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure inc_step is
variable tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
begin
tmp := std_logic_vector(unsigned('0' & bfno) + 1);
bfno <= tmp(FFTEXP-2 downto 0);
-- check if butterflies had overflow
-- then we reach next level of FFT
-- remark: bfno is always one bit too long
if tmp(FFTEXP-1) = '1' then
lvl <= std_logic_vector(unsigned(lvl) + 1);
end if;
wait for clk_period;
end procedure;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
swrst <= '1';
en <= '1';
wait for clk_period;
-- do 11 steps after initial for full 8-point FFT
for i in 0 to 10 loop
inc_step;
end loop;
wait;
end process;
end;
| mit | 57cdac02c25147f0981284f38d65dd37 | 0.522277 | 3.737576 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/delay_bit.vhd | 1 | 1,222 | -- delay_bit.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
--
-- Component that delays an input bit by
-- a given amount of cycles.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delay_bit is
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din: in std_logic; -- data in
dout: out std_logic); -- data out
end entity;
architecture behavioral of delay_bit is
-- vector through which signal is chained
signal dvec: std_logic_vector(DELAYLEN-1 downto 0) := (others => '0');
begin
dout <= dvec(DELAYLEN-1);
process(rst, clk)
begin
if rst = RSTDEF then
dvec <= (others => '0');
elsif rising_edge(clk) then
if swrst = RSTDEF then
dvec <= (others => '0');
elsif en = '1' then
dvec <= dvec(DELAYLEN-2 downto 0) & din;
end if;
end if;
end process;
end architecture;
| mit | 6122233f38f559dfbde942540a594be4 | 0.563011 | 3.573099 | false | false | false | false |
DomBlack/mal | vhdl/printer.vhdl | 17 | 3,030 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package printer is
procedure pr_str(ast: inout mal_val_ptr; readable: in boolean; result: out line);
procedure pr_seq(start_ch: in string; end_ch: in string; delim: in string; a_seq: inout mal_seq_ptr; readable: in boolean; result: out line);
end package printer;
package body printer is
procedure pr_string(val: inout line; readable: in boolean; result: out line) is
variable s: line;
variable src_i, dst_i: integer;
begin
if readable then
s := new string(1 to val'length * 2);
dst_i := 0;
for src_i in val'range loop
dst_i := dst_i + 1;
case val(src_i) is
when LF =>
s(dst_i) := '\';
dst_i := dst_i + 1;
s(dst_i) := 'n';
when '"' =>
s(dst_i) := '\';
dst_i := dst_i + 1;
s(dst_i) := '"';
when '\' =>
s(dst_i) := '\';
dst_i := dst_i + 1;
s(dst_i) := '\';
when others =>
s(dst_i) := val(src_i);
end case;
end loop;
result := new string'("" & '"' & s(1 to dst_i) & '"');
deallocate(s);
else
result := val;
end if;
end;
procedure pr_str(ast: inout mal_val_ptr; readable: in boolean; result: out line) is
variable l: line;
begin
case ast.val_type is
when mal_nil =>
result := new string'("nil");
when mal_true =>
result := new string'("true");
when mal_false =>
result := new string'("false");
when mal_number =>
write(l, ast.number_val);
result := l;
when mal_symbol =>
result := ast.string_val;
when mal_string =>
pr_string(ast.string_val, readable, result);
when mal_keyword =>
result := new string'(":" & ast.string_val.all);
when mal_list =>
pr_seq("(", ")", " ", ast.seq_val, readable, result);
when mal_vector =>
pr_seq("[", "]", " ", ast.seq_val, readable, result);
when mal_hashmap =>
pr_seq("{", "}", " ", ast.seq_val, readable, result);
when mal_atom =>
pr_str(ast.seq_val(0), true, l);
result := new string'("(atom " & l.all & ")");
when mal_nativefn =>
result := new string'("#<NativeFunction:" & ast.string_val.all & ">");
when mal_fn =>
result := new string'("#<MalFunction>");
end case;
end procedure pr_str;
procedure pr_seq(start_ch: in string; end_ch: in string; delim: in string; a_seq: inout mal_seq_ptr; readable: in boolean; result: out line) is
variable s, element_s: line;
begin
s := new string'(start_ch);
for i in a_seq'range loop
pr_str(a_seq(i), readable, element_s);
if i = 0 then
s := new string'(s.all & element_s.all);
else
s := new string'(s.all & delim & element_s.all);
end if;
end loop;
s := new string'(s.all & end_ch);
result := s;
end procedure pr_seq;
end package body printer;
| mpl-2.0 | c2a162ec5a66007678610a4f385c6c7b | 0.526403 | 3.400673 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/addr_gen.vhd | 1 | 4,801 | -- addr_gen.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- Address generation component for pipelined FFT.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity addr_gen is
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
lvl: in std_logic_vector(FFTEXP-2 downto 0); -- iteration level of butterflies
bfno: in std_logic_vector(FFTEXP-2 downto 0); -- butterfly number in current level
addra1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank A
addra2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank A
en_wrta: out std_logic; -- write enable for membank A, high active
addrb1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank B
addrb2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank B
en_wrtb: out std_logic; -- write enable for membank B, high active
addrtf: out std_logic_vector(FFTEXP-2 downto 0)); -- twiddle factor address
end addr_gen;
architecture behavioral of addr_gen is
signal en_wrta_tmp: std_logic := '0';
signal addrtf_tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal bfno_tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal lvl_tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
begin
-- if lvl is even then en_wrtb is active
-- if lvl is odd then en_wrta is active
en_wrta_tmp <= lvl(0);
bfno_tmp <= '0' & bfno;
lvl_tmp <= '0' & lvl;
addrtf <= addrtf_tmp(FFTEXP-2 downto 0);
process(rst, clk) is
-- reset this component
procedure reset is
begin
addra1 <= (others => '0');
addra2 <= (others => '0');
en_wrta <= '0';
addrb1 <= (others => '0');
addrb2 <= (others => '0');
en_wrtb <= '0';
addrtf_tmp <= (others => '0');
end;
-- calculates the read address
function read_addr(x: std_logic_vector(FFTEXP-1 downto 0);
y: std_logic_vector(FFTEXP-1 downto 0))
return std_logic_vector is
begin
-- rotate left y times
return std_logic_vector(rotate_left(unsigned(x), to_integer(unsigned(y))));
end function;
variable tfidx: natural := 0;
variable j: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
variable j_inc: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
begin
if rst = RSTDEF then
reset;
elsif rising_edge(clk) then
if swrst = RSTDEF then
-- software reset to reinitialize component
-- if needed
reset;
elsif en = '1' then
-- make sure only one write enable is set at a time
en_wrta <= en_wrta_tmp;
en_wrtb <= not en_wrta_tmp;
-- calc twiddle factor address
tfidx := FFTEXP-1-to_integer(unsigned(lvl_tmp));
addrtf_tmp <= (others => '0');
addrtf_tmp(FFTEXP-1 downto tfidx) <= bfno_tmp(FFTEXP-1 downto tfidx);
-- pre compute j for address generation
j := std_logic_vector(shift_left(unsigned(bfno_tmp), 1));
j_inc := std_logic_vector(unsigned(j) + 1);
if en_wrta_tmp = '1' then
-- a is the one to write
-- target write address is simply in order
-- addr1: current bfno * 2
-- addr2: (current bfno * 2) + 1
addra1 <= j;
addra2 <= j_inc;
addrb1 <= read_addr(j, lvl_tmp);
addrb2 <= read_addr(j_inc, lvl_tmp);
else
-- b is the one to write
-- target write address is simply in order
-- addr1: current bfno * 2
-- addr2: (current bfno * 2) + 1
addrb1 <= j;
addrb2 <= j_inc;
addra1 <= read_addr(j, lvl_tmp);
addra2 <= read_addr(j_inc, lvl_tmp);
end if;
end if;
end if;
end process;
end behavioral;
| mit | ee3cb67504320083668baba37d707caf | 0.49823 | 3.881164 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MC6847/CharRam.vhd | 1 | 16,744 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CharRam is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(10 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(10 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end CharRam;
architecture BEHAVIORAL of CharRam is
-- Shared memory
type ram_type is array (0 to 2047) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type := (
x"00", x"00", x"00", x"1c", x"22", x"02", x"1a", x"26", x"26", x"1c", x"00", x"00", x"00", x"1C", x"22", x"02",
x"00", x"00", x"00", x"08", x"14", x"22", x"22", x"3e", x"22", x"22", x"00", x"00", x"1A", x"2A", x"2A", x"1C",
x"00", x"00", x"00", x"3c", x"12", x"12", x"1c", x"12", x"12", x"3c", x"00", x"00", x"00", x"08", x"14", x"22",
x"00", x"00", x"00", x"1c", x"22", x"20", x"20", x"20", x"22", x"1c", x"00", x"00", x"22", x"3E", x"22", x"22",
x"00", x"00", x"00", x"3c", x"12", x"12", x"12", x"12", x"12", x"3c", x"00", x"00", x"00", x"3C", x"12", x"12",
x"00", x"00", x"00", x"3e", x"20", x"20", x"38", x"20", x"20", x"3e", x"00", x"00", x"1C", x"12", x"12", x"3C",
x"00", x"00", x"00", x"3e", x"20", x"20", x"38", x"20", x"20", x"20", x"00", x"00", x"00", x"1C", x"22", x"20",
x"00", x"00", x"00", x"1c", x"22", x"20", x"20", x"26", x"22", x"1c", x"00", x"00", x"20", x"20", x"22", x"1C",
x"00", x"00", x"00", x"22", x"22", x"22", x"3e", x"22", x"22", x"22", x"00", x"00", x"00", x"3C", x"12", x"12",
x"00", x"00", x"00", x"1c", x"08", x"08", x"08", x"08", x"08", x"1c", x"00", x"00", x"12", x"12", x"12", x"3C",
x"00", x"00", x"00", x"02", x"02", x"02", x"02", x"02", x"22", x"1c", x"00", x"00", x"00", x"3E", x"20", x"20",
x"00", x"00", x"00", x"22", x"24", x"28", x"30", x"28", x"24", x"22", x"00", x"00", x"38", x"20", x"20", x"3E",
x"00", x"00", x"00", x"20", x"20", x"20", x"20", x"20", x"20", x"3e", x"00", x"00", x"00", x"3E", x"20", x"20",
x"00", x"00", x"00", x"22", x"36", x"2a", x"2a", x"22", x"22", x"22", x"00", x"00", x"38", x"20", x"20", x"20",
x"00", x"00", x"00", x"22", x"22", x"32", x"2a", x"26", x"22", x"22", x"00", x"00", x"00", x"1E", x"20", x"20",
x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"22", x"22", x"1c", x"00", x"00", x"26", x"22", x"22", x"1E",
x"00", x"00", x"00", x"3c", x"22", x"22", x"3c", x"20", x"20", x"20", x"00", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"2a", x"24", x"1a", x"00", x"00", x"3E", x"22", x"22", x"22",
x"00", x"00", x"00", x"3c", x"22", x"22", x"3c", x"28", x"24", x"22", x"00", x"00", x"00", x"1C", x"08", x"08",
x"00", x"00", x"00", x"1c", x"22", x"20", x"1c", x"02", x"22", x"1c", x"00", x"00", x"08", x"08", x"08", x"1C",
x"00", x"00", x"00", x"3e", x"08", x"08", x"08", x"08", x"08", x"08", x"00", x"00", x"00", x"02", x"02", x"02",
x"00", x"00", x"00", x"22", x"22", x"22", x"22", x"22", x"22", x"1c", x"00", x"00", x"02", x"22", x"22", x"1C",
x"00", x"00", x"00", x"22", x"22", x"22", x"14", x"14", x"08", x"08", x"00", x"00", x"00", x"22", x"24", x"28",
x"00", x"00", x"00", x"22", x"22", x"22", x"22", x"2a", x"36", x"22", x"00", x"00", x"30", x"28", x"24", x"22",
x"00", x"00", x"00", x"22", x"22", x"14", x"08", x"14", x"22", x"22", x"00", x"00", x"00", x"20", x"20", x"20",
x"00", x"00", x"00", x"22", x"22", x"14", x"08", x"08", x"08", x"08", x"00", x"00", x"20", x"20", x"20", x"3E",
x"00", x"00", x"00", x"3e", x"02", x"04", x"08", x"10", x"20", x"3e", x"00", x"00", x"00", x"22", x"36", x"2A",
x"00", x"00", x"00", x"1c", x"10", x"10", x"10", x"10", x"10", x"1c", x"00", x"00", x"2A", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"20", x"10", x"08", x"04", x"02", x"00", x"00", x"00", x"00", x"22", x"32", x"2A",
x"00", x"00", x"00", x"1c", x"04", x"04", x"04", x"04", x"04", x"1c", x"00", x"00", x"26", x"22", x"22", x"22",
x"00", x"00", x"00", x"08", x"1c", x"2a", x"08", x"08", x"08", x"08", x"00", x"00", x"00", x"3E", x"22", x"22",
x"00", x"00", x"00", x"00", x"08", x"10", x"3e", x"10", x"08", x"00", x"00", x"00", x"22", x"22", x"22", x"3E",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3C", x"22", x"22",
x"00", x"00", x"00", x"08", x"08", x"08", x"08", x"08", x"00", x"08", x"00", x"00", x"3C", x"20", x"20", x"20",
x"00", x"00", x"00", x"14", x"14", x"14", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1C", x"22", x"22",
x"00", x"00", x"00", x"14", x"14", x"3e", x"14", x"3e", x"14", x"14", x"00", x"00", x"22", x"2A", x"24", x"1A",
x"00", x"00", x"00", x"08", x"1e", x"28", x"1c", x"0a", x"3c", x"08", x"00", x"00", x"00", x"3C", x"22", x"22",
x"00", x"00", x"00", x"30", x"32", x"04", x"08", x"10", x"26", x"06", x"00", x"00", x"3C", x"28", x"24", x"22",
x"00", x"00", x"00", x"10", x"28", x"28", x"10", x"2a", x"24", x"1a", x"00", x"00", x"00", x"1C", x"22", x"10",
x"00", x"00", x"00", x"08", x"08", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"04", x"22", x"1C",
x"00", x"00", x"00", x"04", x"08", x"10", x"10", x"10", x"08", x"04", x"00", x"00", x"00", x"3E", x"08", x"08",
x"00", x"00", x"00", x"10", x"08", x"04", x"04", x"04", x"08", x"10", x"00", x"00", x"08", x"08", x"08", x"08",
x"00", x"00", x"00", x"00", x"08", x"2a", x"1c", x"1c", x"2a", x"08", x"00", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"08", x"08", x"3e", x"08", x"08", x"00", x"00", x"00", x"22", x"22", x"22", x"1C",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"10", x"20", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"00", x"00", x"00", x"14", x"14", x"08", x"08",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"02", x"04", x"08", x"10", x"20", x"00", x"00", x"00", x"2A", x"2A", x"36", x"22",
x"00", x"00", x"00", x"1c", x"22", x"26", x"2a", x"32", x"22", x"1c", x"00", x"00", x"00", x"22", x"22", x"14",
x"00", x"00", x"00", x"08", x"18", x"08", x"08", x"08", x"08", x"1c", x"00", x"00", x"08", x"14", x"22", x"22",
x"00", x"00", x"00", x"1c", x"22", x"02", x"1c", x"20", x"20", x"3e", x"00", x"00", x"00", x"22", x"22", x"14",
x"00", x"00", x"00", x"1c", x"22", x"02", x"04", x"02", x"22", x"1c", x"00", x"00", x"08", x"08", x"08", x"08",
x"00", x"00", x"00", x"04", x"0c", x"14", x"24", x"3e", x"04", x"04", x"00", x"00", x"00", x"3E", x"02", x"04",
x"00", x"00", x"00", x"3e", x"20", x"3c", x"02", x"02", x"22", x"1c", x"00", x"00", x"08", x"10", x"20", x"3E",
x"00", x"00", x"00", x"1c", x"20", x"20", x"3c", x"22", x"22", x"1c", x"00", x"00", x"00", x"38", x"20", x"20",
x"00", x"00", x"00", x"3e", x"02", x"04", x"08", x"10", x"20", x"20", x"00", x"00", x"20", x"20", x"20", x"38",
x"00", x"00", x"00", x"1c", x"22", x"22", x"1c", x"22", x"22", x"1c", x"00", x"00", x"00", x"20", x"20", x"10",
x"00", x"00", x"00", x"1c", x"22", x"22", x"1e", x"02", x"02", x"1c", x"00", x"00", x"08", x"04", x"02", x"02",
x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"00", x"08", x"00", x"00", x"00", x"00", x"0E", x"02", x"02",
x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"00", x"08", x"08", x"10", x"00", x"02", x"02", x"02", x"0E",
x"00", x"00", x"00", x"04", x"08", x"10", x"20", x"10", x"08", x"04", x"00", x"00", x"00", x"08", x"1C", x"2A",
x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"3e", x"00", x"00", x"00", x"00", x"08", x"08", x"08", x"08",
x"00", x"00", x"00", x"10", x"08", x"04", x"02", x"04", x"08", x"10", x"00", x"00", x"00", x"00", x"08", x"10",
x"00", x"00", x"00", x"1c", x"22", x"02", x"04", x"08", x"00", x"08", x"00", x"00", x"3E", x"10", x"08", x"00",
x"00", x"00", x"00", x"08", x"14", x"22", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"1c", x"02", x"1e", x"22", x"1e", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"20", x"20", x"2c", x"32", x"22", x"32", x"2c", x"00", x"00", x"00", x"08", x"08", x"08",
x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"20", x"22", x"1c", x"00", x"00", x"08", x"08", x"00", x"08",
x"00", x"00", x"00", x"02", x"02", x"1a", x"26", x"22", x"26", x"1a", x"00", x"00", x"00", x"14", x"14", x"14",
x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"3e", x"20", x"1c", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"04", x"0a", x"08", x"1c", x"08", x"08", x"08", x"00", x"00", x"00", x"14", x"14", x"36",
x"00", x"00", x"00", x"00", x"00", x"1a", x"26", x"22", x"26", x"1a", x"02", x"1c", x"00", x"36", x"14", x"14",
x"00", x"00", x"00", x"20", x"20", x"2c", x"32", x"22", x"22", x"22", x"00", x"00", x"00", x"08", x"1E", x"20",
x"00", x"00", x"00", x"08", x"00", x"18", x"08", x"08", x"08", x"1c", x"00", x"00", x"1C", x"02", x"3C", x"08",
x"00", x"00", x"00", x"02", x"00", x"02", x"02", x"02", x"02", x"22", x"1c", x"00", x"00", x"32", x"32", x"04",
x"00", x"00", x"00", x"20", x"20", x"24", x"28", x"30", x"28", x"24", x"00", x"00", x"08", x"10", x"26", x"26",
x"00", x"00", x"00", x"18", x"08", x"08", x"08", x"08", x"08", x"1c", x"00", x"00", x"00", x"10", x"28", x"28",
x"00", x"00", x"00", x"00", x"00", x"3c", x"2a", x"2a", x"2a", x"2a", x"00", x"00", x"10", x"2A", x"24", x"1A",
x"00", x"00", x"00", x"00", x"00", x"2c", x"32", x"22", x"22", x"22", x"00", x"00", x"00", x"18", x"18", x"18",
x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"1c", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"3c", x"22", x"22", x"22", x"3c", x"20", x"20", x"00", x"08", x"10", x"20",
x"00", x"00", x"00", x"00", x"00", x"1e", x"22", x"22", x"22", x"1e", x"02", x"02", x"20", x"20", x"10", x"08",
x"00", x"00", x"00", x"00", x"00", x"2c", x"32", x"20", x"20", x"20", x"00", x"00", x"00", x"08", x"04", x"02",
x"00", x"00", x"00", x"00", x"00", x"1e", x"20", x"1c", x"02", x"3c", x"00", x"00", x"02", x"02", x"04", x"08",
x"00", x"00", x"00", x"10", x"10", x"38", x"10", x"10", x"12", x"0c", x"00", x"00", x"00", x"00", x"08", x"1C",
x"00", x"00", x"00", x"00", x"00", x"22", x"22", x"22", x"26", x"1a", x"00", x"00", x"3E", x"1C", x"08", x"00",
x"00", x"00", x"00", x"00", x"00", x"22", x"22", x"22", x"14", x"08", x"00", x"00", x"00", x"00", x"08", x"08",
x"00", x"00", x"00", x"00", x"00", x"22", x"2a", x"2a", x"14", x"14", x"00", x"00", x"3E", x"08", x"08", x"00",
x"00", x"00", x"00", x"00", x"00", x"22", x"14", x"08", x"14", x"22", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"22", x"22", x"22", x"1e", x"02", x"1c", x"00", x"30", x"30", x"10", x"20",
x"00", x"00", x"00", x"00", x"00", x"3e", x"04", x"08", x"10", x"3e", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"04", x"08", x"08", x"10", x"08", x"08", x"04", x"00", x"00", x"3E", x"00", x"00", x"00",
x"00", x"00", x"00", x"08", x"08", x"08", x"00", x"08", x"08", x"08", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"10", x"08", x"08", x"04", x"08", x"08", x"10", x"00", x"00", x"00", x"00", x"30", x"30",
x"00", x"00", x"00", x"10", x"2a", x"04", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"02", x"02", x"04",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"08", x"10", x"20", x"20",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"24", x"24",
x"00", x"00", x"00", x"08", x"00", x"08", x"08", x"08", x"08", x"08", x"00", x"00", x"24", x"24", x"24", x"18",
x"00", x"00", x"00", x"00", x"08", x"1c", x"20", x"20", x"20", x"1c", x"08", x"00", x"00", x"08", x"18", x"08",
x"00", x"00", x"00", x"0c", x"12", x"10", x"38", x"10", x"10", x"3e", x"00", x"00", x"08", x"08", x"08", x"1C",
x"00", x"00", x"00", x"00", x"00", x"22", x"1c", x"14", x"1c", x"22", x"00", x"00", x"00", x"1C", x"22", x"02",
x"00", x"00", x"00", x"22", x"14", x"08", x"3e", x"08", x"3e", x"08", x"00", x"00", x"1C", x"20", x"20", x"3E",
x"00", x"00", x"00", x"08", x"08", x"08", x"00", x"08", x"08", x"08", x"00", x"00", x"00", x"1C", x"22", x"02",
x"00", x"00", x"00", x"1c", x"20", x"1c", x"22", x"1c", x"02", x"1c", x"00", x"00", x"04", x"02", x"22", x"1C",
x"14", x"14", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"0C", x"14",
x"00", x"00", x"3e", x"41", x"5d", x"51", x"51", x"5d", x"41", x"3e", x"00", x"00", x"3E", x"04", x"04", x"04",
x"00", x"00", x"00", x"1c", x"02", x"1e", x"22", x"1e", x"00", x"00", x"00", x"00", x"00", x"3E", x"20", x"3C",
x"00", x"00", x"00", x"00", x"0a", x"14", x"28", x"14", x"0a", x"00", x"00", x"00", x"02", x"02", x"22", x"1C",
x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"02", x"02", x"00", x"00", x"00", x"00", x"1C", x"20", x"20",
x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"00", x"00", x"00", x"3C", x"22", x"22", x"1C",
x"00", x"00", x"3e", x"41", x"5d", x"55", x"59", x"55", x"41", x"3e", x"00", x"00", x"00", x"3E", x"02", x"04",
x"00", x"00", x"00", x"7e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"10", x"20", x"20",
x"00", x"00", x"00", x"10", x"28", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1C", x"22", x"22",
x"00", x"00", x"08", x"08", x"3e", x"08", x"08", x"00", x"3e", x"00", x"00", x"00", x"1C", x"22", x"22", x"1C",
x"00", x"00", x"00", x"18", x"04", x"08", x"10", x"1c", x"00", x"00", x"00", x"00", x"00", x"1C", x"22", x"22",
x"00", x"00", x"00", x"18", x"04", x"18", x"04", x"18", x"00", x"00", x"00", x"00", x"1E", x"02", x"02", x"1C",
x"04", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"18",
x"00", x"00", x"00", x"00", x"00", x"12", x"12", x"12", x"12", x"1c", x"10", x"20", x"00", x"18", x"18", x"00",
x"00", x"00", x"00", x"1a", x"2a", x"2a", x"1a", x"0a", x"0a", x"0a", x"00", x"00", x"00", x"18", x"18", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"18", x"00", x"00", x"00", x"00", x"18", x"18", x"08", x"10",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"18", x"00", x"04", x"08", x"10",
x"00", x"00", x"00", x"08", x"18", x"08", x"08", x"1c", x"00", x"00", x"00", x"00", x"20", x"10", x"08", x"04",
x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"1c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3E",
x"00", x"00", x"00", x"00", x"28", x"14", x"0a", x"14", x"28", x"00", x"00", x"00", x"00", x"3E", x"00", x"00",
x"00", x"00", x"00", x"20", x"20", x"20", x"22", x"06", x"0e", x"02", x"00", x"00", x"00", x"10", x"08", x"04",
x"00", x"00", x"00", x"20", x"20", x"20", x"2e", x"02", x"04", x"0e", x"00", x"00", x"02", x"04", x"08", x"10",
x"00", x"00", x"00", x"70", x"10", x"70", x"12", x"76", x"0e", x"02", x"00", x"00", x"00", x"18", x"24", x"04",
x"00", x"00", x"00", x"08", x"00", x"08", x"08", x"10", x"12", x"0c", x"00", x"00", x"08", x"08", x"00", x"08"
);
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra(10 downto 0))) := dina;
end if;
douta <= RAM(conv_integer(addra(10 downto 0)));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb(10 downto 0))) := dinb;
end if;
doutb <= RAM(conv_integer(addrb(10 downto 0)));
end if;
end process;
end BEHAVIORAL;
| apache-2.0 | cada735532859319ead6e38b9978618e | 0.413163 | 1.865835 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/lutFileRtl.vhd | 2 | 3,300 | -------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity lutFile is
generic (
gLutCount : natural := 4;
gLutWidth : natural := 32;
gLutInitValue : std_logic_vector :=
x"1111_1111" & x"2222_2222" & x"3333_3333" & x"4444_4444"
);
port (
iAddrRead : in std_logic_vector(LogDualis(gLutCount)-1 downto 0);
oData : out std_logic_vector
);
end lutFile;
architecture Rtl of lutFile is
constant cLutFile : std_logic_vector(gLutCount*gLutWidth-1 downto 0) :=
gLutInitValue;
signal lutOutput : std_logic_vector(gLutWidth-1 downto 0);
begin
--Lut File is a bitstream that is blockwise (gLutWidth) read with
--respect to iAddrRead.
bitSelect : process(iAddrRead)
begin
--default
lutOutput <= (others => '0');
for i in gLutWidth-1 downto 0 loop
--assign selected bits in Lut File to output
lutOutput(i) <= cLutFile
( (gLutCount-1-to_integer(unsigned(iAddrRead)))*gLutWidth + i );
end loop;
end process;
--! downscale lut width to output
oData <= lutOutput(oData'range);
end Rtl;
| gpl-2.0 | 23f5c803f395e3a092f211bb81b9375a | 0.628788 | 4.347826 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_combined/control_unit.vhd | 1 | 3,606 | library IEEE;
use IEEE.std_logic_1164.all;
entity control_unit is
port ( Clk: in STD_LOGIC; rst: in STD_LOGIC;
X: in STD_LOGIC_vector(10 downto 0);
Y: out STD_LOGIC_vector(25 downto 1));
end control_unit;
architecture control_unit of control_unit is
-- Òèï, èñïîëüçóþùèé ñèìâîëüíîå êîäèðîâàíèå ñîñòîÿíèé àâòîìàòà
type State_type is (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16);
signal State, NextState: State_type;
begin
-- NextState logic (combinatorial)
Sreg0_NextState: process (State, x)
begin
-- èíèöèàëèçàöèÿ çíà÷åíèé âûõîäîâ
y <= (others => '0');
case State is
when a0 =>
if x(0) = '1' then
NextState <= a1;
y(1) <= '1';
y(2) <= '1';
y(3) <= '1';
y(4) <= '1';
else
NextState <= a6;
y(1) <= '1';
y(14) <= '1';
end if;
when a1 =>
NextState <= a2;
if x(1) = '1' then
y(5) <= '1';
end if;
when a2 =>
NextState <= a3;
y(6) <= '1';
y(7) <= '1';
y(8) <= '1';
when a3 =>
NextState <= a4;
if x(2) = '1' then
y(9) <= '1';
else
y(10) <= '1';
end if;
when a4 =>
if x(3) = '0' then
NextState <= a1;
elsif x(4) = '1' then
NextState <= a5;
y(11) <= '1';
else
NextState <= a5;
end if;
when a5 =>
NextState <= a0;
y(12) <= '1';
y(13) <= '1';
when a6 =>
if x(5) = '1' then
NextState <= a0;
y(24) <= '1';
else
NextState <= a7;
y(15) <= '1';
y(16) <= '1';
end if;
when a7 =>
if x(6) = '0' then
NextState <= a8;
y(17) <= '1';
else
NextState <= a9;
y(18) <= '1';
end if;
when a8 =>
if x(6) = '0' then
NextState <= a0;
y(25) <= '1';
else
NextState <= a10;
y(3) <= '1';
y(4) <= '1';
end if;
when a9 =>
if x(6) = '1' then
NextState <= a0;
y(25) <= '1';
else
NextState <= a10;
y(3) <= '1';
y(4) <= '1';
end if;
when a10 =>
if x(6) = '0' then
NextState <= a11;
y(19) <= '1';
else
NextState <= a11;
y(20) <= '1';
end if;
when a11 =>
NextState <= a12;
y(8) <= '1';
when a12 =>
if x(3) = '0' then
if x(6) = '0' then
NextState <= a13;
y(21) <= '1';
else
NextState <= a14;
y(21) <= '1';
end if;
else
if x(7) = '1' then
NextState <= a15;
elsif x(8) = '0' then
NextState <= a15;
y(18) <= '1';
else
NextState <= a15;
y(17) <= '1';
end if;
end if;
when a13 =>
NextState <= a10;
y(17) <= '1';
when a14 =>
NextState <= a10;
y(18) <= '1';
when a15 =>
NextState <= a16;
if x(9) = '0' then
if x(4) = '1' and x(10) = '1' then
y(22) <= '1';
end if;
else
if x(4) = '1' then
y(22) <= '1';
elsif x(10) = '0' then
y(22) <= '1';
end if;
end if;
when a16 =>
NextState <= a0;
y(23) <= '1';
when others => NextState <= a0;
-- ïðèñâîåíèå çíà÷åíèé âûõîäàì äëÿ ñîñòîÿíèÿ ïî óìîë÷àíèþ
--Óñòàíîâêà àâòîìàòà â íà÷àëüíîå ñîñòîÿíèå
end case;
end process;
Sreg0_CurrentState: process (Clk, rst)
begin
if rst='0' then
State <= a0; -- íà÷àëüíîå ñîñòîÿíèå
elsif rising_edge(clk) then
State <= NextState;
end if;
end process;
end control_unit; | mit | 9ab84c09ab4224e4176653af8a361942 | 0.43594 | 2.449728 | false | false | false | false |
hoglet67/AtomGodilVideo | src/DCM/DCM0.vhd | 2 | 2,059 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 25.368 =49.152 * 16 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | 7556d87d3f3498e0544ccda40d459105 | 0.405051 | 4.26294 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_wci.vhd | 1 | 7,167 | -- This package defines constants relating to the WCI interface
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; use ocpi.ocp;
package wci is
TYPE control_op_t IS (INITIALIZE_e,
START_e,
STOP_e,
RELEASE_e,
BEFORE_QUERY_e,
AFTER_CONFIG_e,
TEST_e,
NO_OP_e);
subtype control_op_mask_t is std_logic_vector(control_op_t'pos(no_op_e) downto 0);
--subtype control_op_t is unsigned(2 downto 0); -- natural range 0 to 7;
--constant INITIALIZE_e : control_op_t := to_unsigned(0,3);
--constant START_e : control_op_t := to_unsigned(1,3);
--constant STOP_e : control_op_t := to_unsigned(2,3);
--constant RELEASE_e : control_op_t := to_unsigned(3,3);
--constant BEFORE_QUERY_e : control_op_t := to_unsigned(4,3);
--constant AFTER_CONFIG_e : control_op_t := to_unsigned(5,3);
--constant TEST_e : control_op_t := to_unsigned(6,3);
--constant NO_OP_e : control_op_t := to_unsigned(7,3);
--subtype control_op_mask_t is std_logic_vector(to_integer(NO_OP_e) downto 0);
type worker_t is record
decode_width : natural;
allowed_ops : control_op_mask_t;
end record worker_t;
type property_t is record
data_width, -- data width of datum in bits, but 32 for strings
offset, -- offset in property space in bytes
bytes_1, -- total bytes in this property minus 1
string_length, -- bytes (excluding null) for string values
nitems -- nitems array
: natural; -- with of a single item
writable, readable, volatile, parameter : boolean;
end record property_t;
-- Address Space Selection
CONSTANT CONFIG : std_logic := '1';
CONSTANT CONTROL : std_logic := '0';
-- Worker State
-- These are not normative to the WCI interface, but are useful for bookkeepping
-- Note we track the state where we have accepted a control operation but
-- have not yet responded to it.
--TYPE State_t IS (EXISTS_e, -- 0
-- INITIALIZED_e, -- 1
-- OPERATING_e, -- 2
-- SUSPENDED_e, -- 3
-- UNUSABLE_e); -- 4
subtype State_t is natural range 0 to 4;
constant EXISTS_e : State_t := 0;
constant INITIALIZED_e : State_t := 1;
constant OPERATING_e : State_t := 2;
constant SUSPENDED_e : State_t := 3;
constant UNUSABLE_e : State_t := 4;
type control_op_masks_t is array (natural range <>) of control_op_mask_t;
-- constant masks for what control op is allowed in each state
constant next_ops : control_op_masks_t :=
("00000010", -- EXISTS_e
"10010100", -- INITIALIZED_e
"01111000", -- OPERATING_e
"01110100", -- SUSPENDED_e
"00000000" -- UNUSABLE_e: nothing to do but reset
);
--SUBTYPE State_t IS std_logic_vector(2 DOWNTO 0);
--CONSTANT EXISTS : State_t := "000";
--CONSTANT INITIALIZED : State_t := "001";
--CONSTANT OPERATING : State_t := "010";
--CONSTANT SUSPENDED : State_t := "011";
--CONSTANT UNUSABLE : State_t := "100";
---- Worker Control Operations
--SUBTYPE ControlOp_t IS std_logic_vector(2 DOWNTO 0);
--CONSTANT INITIALIZE : ControlOp_t := "000";
--CONSTANT START : ControlOp_t := "001";
--CONSTANT STOP : ControlOp_t := "010";
--CONSTANT RELEASE : ControlOp_t := "011";
--CONSTANT TEST : ControlOp_t := "100";
--CONSTANT BEFORE_QUERY : ControlOp_t := "101";
--CONSTANT AFTER_CONFIG : ControlOp_t := "110";
--CONSTANT RESERVED : ControlOp_t := "111";
type in_t is record
Clk : std_logic;
MAddr : std_logic_vector(31 downto 0);
MAddrSpace : std_logic_vector(0 downto 0);
MByteEn : std_logic_vector(3 downto 0);
MCmd : ocp.MCmd_t;
MData : std_logic_vector(31 downto 0);
MFlag : std_logic_vector(1 downto 0);
MReset_n : std_logic;
end record in_t;
type out_t is record
SData : std_logic_vector(31 downto 0);
SFlag : std_logic_vector(1 downto 0);
SResp : ocp.SResp_t;
SThreadBusy : std_logic_vector(0 downto 0);
end record out_t;
-- This is the type of access to the property, or none
type Access_t IS (None_e, Error_e, Read_e, Write_e, Control_e);
-- Return the currently decoded access
function decode_access(input : in_t) return Access_t;
-- Return the byte offset from the byte enables
--subtype byte_offset_t is unsigned(1 downto 0);
-- function be2offset(input: in_t) return byte_offset_t;
-- pull the value from the data bus, shifted and sized
function get_value(input : in_t; boffset : unsigned; width : natural) return std_logic_vector;
function to_control_op(bits : std_logic_vector(2 downto 0)) return control_op_t;
function resize(bits : std_logic_vector; n : natural) return std_logic_vector;
subtype hword_t is std_logic_vector(15 downto 0);
subtype byte_t is std_logic_vector(7 downto 0);
type properties_t is array (natural range <>) of property_t;
type data_a_t is array (natural range <>) of word_t;
type offset_a_t is array (natural range <>) of unsigned(31 downto 0);
type boolean_array_t is array (natural range <>) of boolean;
function data_out_top (property : property_t) return natural;
-- the wci convenience IP that makes it simple to implement a WCI interface
component decoder
generic(worker : worker_t; properties : properties_t);
port(
ocp_in : in in_t;
done : in bool_t := btrue;
resp : out ocp.SResp_t;
write_enables : out bool_array_t(properties'range);
read_enables : out bool_array_t(properties'range);
offsets : out offset_a_t(properties'range);
indices : out offset_a_t(properties'range);
hi32 : out bool_t;
nbytes_1 : out byte_offset_t;
data_outputs : out data_a_t(properties'range);
control_op : out control_op_t;
state : out state_t;
is_operating : out bool_t; -- just a convenience for state = operating_e
abort_control_op : out bool_t;
is_big_endian : out bool_t -- for runtime dynamic endian
);
end Component;
component readback
generic(properties : properties_t);
port(
read_enables : in bool_array_t(properties'range);
data_inputs : in data_a_t(properties'range);
data_output : out std_logic_vector(31 downto 0)
);
end component readback;
end package wci;
| lgpl-3.0 | f7429dea81bcdc850925b4e7d1dcb005 | 0.568857 | 3.599699 | false | false | false | false |
matbur95/ucisw-pro | pro3/vga_init.vhd | 1 | 4,708 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:38:12 03/08/2017
-- Design Name:
-- Module Name: vga_init - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_init is
Port ( CLK : in STD_LOGIC;
VGA_COLOR : in STD_LOGIC_VECTOR(2 downto 0);
POS : out STD_LOGIC_VECTOR(18 downto 0);
-- ADC_DOA : in STD_LOGIC_VECTOR(13 downto 0);
-- ADC_DOB : in STD_LOGIC_VECTOR(13 downto 0);
-- ADC_Busy : in STD_LOGIC;
VGA_R : out STD_LOGIC;
VGA_G : out STD_LOGIC;
VGA_B : out STD_LOGIC;
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC
-- AMP_WE : out STD_LOGIC;
-- AMP_DI : out STD_LOGIC_VECTOR(7 downto 0);
-- ADC_Start : out STD_LOGIC;
--
-- Line : out STD_LOGIC_VECTOR(63 downto 0);
-- Blank : out STD_LOGIC_VECTOR(15 downto 0)
);
end vga_init;
architecture Behavioral of vga_init is
-- x = HPOS, y = VPOS
constant HPOS_MAX : integer := 1039;
constant VPOS_MAX : integer := 665;
-- constant HT_S : integer := 1040;
constant HT_DISP : integer := 800;
constant HT_PW : integer := 120;
constant HT_FP : integer := 64;
constant HT_BP : integer := 56;
-- constant VT_S : integer := 666;
constant VT_DISP : integer := 600;
constant VT_PW : integer := 6;
constant VT_FP : integer := 37;
constant VT_BP : integer := 23;
signal HPOS : integer range 0 to HPOS_MAX := 0;
signal VPOS : integer range 0 to VPOS_MAX := 0;
-- constant BLUE : STD_LOGIC_VECTOR(0 to 2) := "001";
-- constant YELLOW : STD_LOGIC_VECTOR(0 to 2) := "110";
-- constant SIDE : integer := 50;
-- signal BOX_HPOS : integer range -100 to HT_DISP := 400;
-- signal BOX_VPOS : integer range -100 to VT_DISP := 300;
-- signal BOX_HPOS_INT : integer range -100 to HT_DISP := 400;
-- signal BOX_VPOS_INT : integer range -100 to VT_DISP := 300;
begin
HPOS_CNT: process (CLK)
begin
if rising_edge(CLK) then
if HPOS = HPOS_MAX then
HPOS <= 0;
else
HPOS <= HPOS + 1;
end if;
end if;
end process HPOS_CNT;
VPOS_CNT: process (CLK)
begin
if rising_edge(CLK) and HPOS = HPOS_MAX then
if VPOS = VPOS_MAX then
VPOS <= 0;
else
VPOS <= VPOS + 1;
end if;
end if;
end process VPOS_CNT;
VGA_HS <= '1' when HPOS >= HT_DISP + HT_FP and HPOS < HPOS_MAX - HT_BP else '0';
VGA_VS <= '1' when VPOS >= VT_DISP + VT_FP and VPOS < VPOS_MAX - VT_BP else '0';
POS <= STD_LOGIC_VECTOR(to_unsigned(HPOS + VPOS * HPOS_MAX, 19));
-- VGA_R <= '1' when HPOS < HT_DISP and VPOS < VT_DISP else '0';
-- VGA_G <= '1' when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else '0';
-- AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
-- AMP_DI <= X"11";
-- ADC_Start <= '1' when HPOS = HT_DISP and VPOS = VT_DISP else '0';
--
-- Blank <= X"0F0F";
-- Line <= "00" & ADC_DOA & X"0000" & "00" & ADC_DOB & X"0000";
--
-- BOX: process (CLK, HPOS, VPOS)
-- begin
-- if rising_edge(CLK) then
-- if HPOS = 0 and VPOS = 0 then
-- BOX_HPOS_INT <= BOX_HPOS - to_integer(signed(ADC_DOA(13 downto 11)));
-- BOX_VPOS_INT <= BOX_VPOS + to_integer(signed(ADC_DOB(13 downto 11)));
-- end if;
--
-- if BOX_HPOS_INT < 0 then
-- BOX_HPOS_INT <= 0;
-- elsif BOX_HPOS_INT > HT_DISP - SIDE then
-- BOX_HPOS_INT <= HT_DISP - SIDE;
-- end if;
--
-- if BOX_VPOS_INT < 0 then
-- BOX_VPOS_INT <= 0;
-- elsif BOX_VPOS_INT > VT_DISP - SIDE then
-- BOX_VPOS_INT <= VT_DISP - SIDE;
-- end if;
--
-- BOX_HPOS <= BOX_HPOS_INT;
-- BOX_VPOS <= BOX_VPOS_INT;
-- end if;
-- end process BOX;
---- BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 12)));
end Behavioral;
| mit | dc16242c999776602b2ff310ad2b08b7 | 0.533135 | 3.255878 | false | false | false | false |
fgr1986/ddr_MIG_ctrl_interface | src/hdl/ram_ddr_wrapper.vhd | 1 | 22,959 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Fernando García Redondo, [email protected]
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Create Date: 26/07/2017
-- Design Name: Nexys4 DDR RAM/DDR2/DDR3 Interface
-- Module Name: ram_ddr_wrapper - behavioral
-- Project Name: ram_ddr_wrapper
-- Target Devices: Nexys4 DDR Development Board, containing a XC7a100t-1 csg324 device
-- Tool versions:
-- Description:
--
-- IMPORTANT: This ddr_xadc module includes already an xadc instance. Do not instantiate outside.
-- IMPORTANT: If xadc is instantiated outside, use ddr IP (not ddr_xadc) and drive to ddr instance
-- IMPORTANT: the xadc sensed temperature.
--
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Project library
library work;
use work.ram_ddr_MIG7_interface_pkg.ALL;
entity ram_ddr_wrapper is
port (
-- Common
clk_200MHz_i : in std_logic;
rst_i : in std_logic;
-- ram control interface
ram_rnw_i : in std_logic; -- operation to be done : 0->READ, 1->WRITE
ram_addr_i : in std_logic_vector(c_DATA_ADDRESS_WIDTH-1 downto 0);
ram_new_instr_i : in std_logic; -- cs, '1' starts operation
ram_new_ack_o : out std_logic; -- ack between clk domains
ram_end_op_i : in std_logic; -- '1' ends the current write or read operation
-- for high performance consecutive writes or reads
ram_rd_ack_o : out std_logic;
ram_rd_valid_o : out std_logic;
ram_wr_ack_o : out std_logic;
ram_data_to_i : in std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
ram_data_from_o : out std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
ram_available_o : out std_logic; -- when available for a different command
-- write to read, read to write
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface
ddr2_addr : out std_logic_vector(c_DDR_ADDRESS_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0)
);
end ram_ddr_wrapper;
architecture behavioral of ram_ddr_wrapper is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component ddr_xadc
port (
-- Inouts
ddr2_dq : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(c_DDR_ADDRESS_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(c_APP_DATA_ADDRESS_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(c_DDR_CMD_WIDTH-1 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
-- device_temp_i : in ...,
init_calib_complete : out std_logic );
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (st_IDLE, st_PREP_OP, st_SEND_WRITE,
st_SEND_READ, st_WAIT_NEXT_WRITE, st_WAIT_NEXT_READ);
------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------
constant c_MASK_DIFF : positive := c_DDR_WDF_MASK_WIDTH - (c_APP_DATA_WIDTH-c_DATA_2_MEM_WIDTH)/8;
--report "The value of 'c_MASK_DIFF' is " & integer'image(c_MASK_DIFF);
constant c_MASK : std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0)
:= (c_DDR_WDF_MASK_WIDTH-1 downto c_MASK_DIFF => '1')
& (c_MASK_DIFF-1 downto 0 => '0');
--------------------------------------
-- Signals
--------------------------------------
-- state machine
signal st_state, st_next_state : state_type;
-- active-low reset for the MIG component
signal s_rstn : std_logic;
signal s_rst_d2 : std_logic_vector(1 downto 0);
-- double registered imputs
signal s_ram_rnw_pre : std_logic;
signal s_ram_rnw : std_logic;
signal s_ram_new_instr : std_logic;
signal s_ram_new_instr_pre : std_logic;
signal s_ram_end_op_pre : std_logic;
signal s_ram_end_op : std_logic;
signal s_ram_data_to_pre : std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
signal s_ram_data_to : std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
signal s_ram_addr_pre : std_logic_vector(c_APP_DATA_ADDRESS_WIDTH-1 downto 0);
----------------------------------------
-- We will use 'mem_ui_' for UI with ddr
-- ddr user interface signals
--------------------------------------
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal mem_ui_addr : std_logic_vector(c_APP_DATA_ADDRESS_WIDTH-1 downto 0); -- address for current request
signal mem_ui_cmd : std_logic_vector(c_DDR_CMD_WIDTH-1 downto 0); -- command for current request
signal mem_ui_wdf_rdy : std_logic; -- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_ui_wdf_data : std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
signal mem_ui_wdf_end : std_logic; -- active-high last 'wdf_data'
signal mem_ui_wdf_mask : std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0);
signal mem_ui_wdf_wren : std_logic;
signal mem_ui_rd_data : std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
signal mem_ui_rd_data_end : std_logic; -- active-high last 'rd_data'
signal mem_ui_rd_data_valid : std_logic; -- active-high 'rd_data' valid
signal s_calib_complete : std_logic; -- active-high calibration complete
-- enables the sending of CMD to the ddr (1 pulse per command)
signal mem_ui_en : std_logic; -- active-high strobe for 'cmd' and 'addr'
-- if HIGH, the CMD sent when mem_ui_en is HIGH has been accepted
signal mem_ui_rdy : std_logic;
-- registered ack 1 clk pulses
signal s_ram_rd_ack : std_logic;
signal s_ram_wr_ack : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering the active-low reset for the MIG component
-- delay because of FSM
------------------------------------------------------------------------
p_rst_sync: process(clk_200MHz_i)
begin
if rising_edge(clk_200MHz_i) then
s_rst_d2 <= s_rst_d2(0) & rst_i;
s_rstn <= not s_rst_d2(1);
end if;
end process p_rst_sync;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
inst_ddr_xadc: ddr_xadc
port map (
-- IOB outputs [Physical Interface]
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => s_rstn,
-- user interface signals
app_addr => mem_ui_addr,
app_cmd => mem_ui_cmd,
app_en => mem_ui_en,
app_wdf_data => mem_ui_wdf_data,
app_wdf_end => mem_ui_wdf_end,
app_wdf_mask => mem_ui_wdf_mask,
app_wdf_wren => mem_ui_wdf_wren,
app_rd_data => mem_ui_rd_data,
app_rd_data_end => mem_ui_rd_data_end,
app_rd_data_valid => mem_ui_rd_data_valid,
app_rdy => mem_ui_rdy,
app_wdf_rdy => mem_ui_wdf_rdy,
app_sr_req => '0', -- see UG586
app_sr_active => open,
app_ref_req => '0', -- see UG586
app_ref_ack => open,
app_zq_req => '0', -- see UG586
app_zq_ack => open,
ui_clk => mem_ui_clk, -- 1/2 or 1/4 of 200Mhz clk, see UG586
ui_clk_sync_rst => mem_ui_rst,
-- device_temp_i => device_temp_i,
init_calib_complete => s_calib_complete
);
------------------------------------------------------------------------
-- Registering handshake ack
------------------------------------------------------------------------
p_new_instr_ack: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' or s_calib_complete='0' then
ram_new_ack_o <= '0';
else
ram_new_ack_o <= ram_new_instr_i;
end if;
end if;
end process p_new_instr_ack;
------------------------------------------------------------------------
-- Double Registering all ctrl inputs to 'mem_ui_clk' domain
------------------------------------------------------------------------
p_reg_in_ctrl: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' then
-- pre-signals
s_ram_rnw_pre <= '0';
s_ram_new_instr_pre <= '0';
s_ram_end_op_pre <= '0';
-- valid signals (faster domain)
s_ram_rnw <= '0';
s_ram_new_instr <= '0';
s_ram_end_op <= '0';
else
-- pre-signals
s_ram_rnw_pre <= ram_rnw_i;
s_ram_new_instr_pre <= ram_new_instr_i;
s_ram_end_op_pre <= ram_end_op_i;
-- valid signals (faster domain)
if s_ram_new_instr = '0' then
s_ram_new_instr <= s_ram_new_instr_pre;
else
s_ram_new_instr <= '0';
end if;
if s_ram_end_op = '0' then
s_ram_end_op <= s_ram_end_op_pre;
else
s_ram_end_op <= '0';
end if;
-- valid signals with no pulse control
s_ram_rnw <= s_ram_rnw_pre;
end if;
end if;
end process p_reg_in_ctrl;
------------------------------------------------------------------------
-- Double Registering all data inputs to 'mem_ui_clk' domain
------------------------------------------------------------------------
p_reg_in_data: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' then
-- pre-signals
s_ram_addr_pre <= (others => '0');
s_ram_data_to_pre <= (others => '0');
-- valid signals (faster domain)
mem_ui_addr <= (others => '0');
s_ram_data_to <= (others => '0');
else
-- pre-signals
s_ram_addr_pre <= '0' & ram_addr_i; -- rank in DDR2 MT47H64M16HR-25 is '0'
s_ram_data_to_pre <= ram_data_to_i;
-- valid signals (faster domain)
-- with control
if s_ram_new_instr_pre='1' then
mem_ui_addr <= s_ram_addr_pre;
s_ram_data_to <= s_ram_data_to_pre;
end if;
end if;
end if;
end process p_reg_in_data;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
p_sync_FSM: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst = '1' then
st_state <= st_IDLE;
else
st_state <= st_next_state;
end if;
end if;
end process p_sync_FSM;
-- Next state logic
p_next_state: process(st_state, s_calib_complete, s_ram_new_instr,
s_ram_rnw, mem_ui_rdy, mem_ui_wdf_rdy, s_ram_end_op)
begin
st_next_state <= st_state;
case(st_state) is
-- If calibration is done successfully
when st_IDLE =>
-- comment for simulation
if s_calib_complete = '1' then
st_next_state <= st_PREP_OP;
end if;
-- In st_PREP_OP We store address (for write/read) and data (for write)
-- operates if conditions are met
when st_PREP_OP =>
if s_ram_new_instr = '1' then
if s_ram_rnw = '1' then
st_next_state <= st_SEND_WRITE;
elsif s_ram_rnw = '0' then
st_next_state <= st_SEND_READ;
end if;
end if;
-- We send write the command until accepted (mem_ui_rdy = '1')
when st_SEND_WRITE =>
-- end operation if s_ram_new_instr (registered for delay) is deaserted
if mem_ui_rdy = '1' and mem_ui_wdf_rdy='1' then
st_next_state <= st_WAIT_NEXT_WRITE;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
when st_WAIT_NEXT_WRITE =>
if s_ram_new_instr = '1' then
st_next_state <= st_SEND_WRITE;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
-- We send write the command until accepted (mem_ui_rdy = '1')
when st_SEND_READ =>
-- end operation if s_ram_new_instr (registered for delay) is deaserted
if mem_ui_rdy = '1' then
st_next_state <= st_WAIT_NEXT_READ;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
when st_WAIT_NEXT_READ =>
if s_ram_new_instr = '1' then
st_next_state <= st_SEND_READ;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
when others => st_next_state <= st_IDLE;
end case;
end process;
---------------------------------------------------------------
-- Memory control
-- Creates mem_ui_en pulse
---------------------------------------------------------------
p_mem_ctrl: process(st_state, mem_ui_wdf_rdy)
begin
if st_state = st_SEND_WRITE then
mem_ui_en <= mem_ui_wdf_rdy; -- send control command only if wdf_data can be loaded in fifo
-- until mem_ui_rdy
elsif st_state = st_SEND_READ then
mem_ui_en <= '1';
else
mem_ui_en <= '0';
end if;
end process p_mem_ctrl;
---------------------------------------------------------------
-- Memory control 2
-- Controls CMD Message
---------------------------------------------------------------
p_mem_ctrl_2: process(st_state)
begin
-- select command
if st_state = st_SEND_WRITE then
mem_ui_cmd <= c_CMD_WRITE;
elsif st_state = st_SEND_READ then
mem_ui_cmd <= c_CMD_READ;
else
mem_ui_cmd <= c_CMD_READ;
end if;
end process p_mem_ctrl_2;
------------------------------------------------------------------------
-- Generating the FIFO control and command signals according to the
-- current state of the FSM
------------------------------------------------------------------------
p_mem_ctrl_3: process(st_state, mem_ui_wdf_rdy, s_ram_data_to )
begin
if st_state = st_SEND_WRITE and mem_ui_wdf_rdy='1' then
mem_ui_wdf_data <= (c_APP_DATA_WIDTH-1 downto s_ram_data_to'length => '0') & s_ram_data_to;
mem_ui_wdf_end <= '1';
mem_ui_wdf_mask <= c_MASK;
mem_ui_wdf_wren <= '1';
elsif st_state = st_SEND_READ then
mem_ui_wdf_data <= (others => '0');
mem_ui_wdf_end <= '0';
mem_ui_wdf_mask <= (others => '1');
mem_ui_wdf_wren <= '0';
else
mem_ui_wdf_data <= (others => '0');
mem_ui_wdf_end <= '0';
mem_ui_wdf_mask <= (others => '1');
mem_ui_wdf_wren <= '0';
end if;
end process p_mem_ctrl_3;
------------------------------------------
-- ACK signals if registered at outputs
------------------------------------------
p_ack_ctrl: process(st_state, mem_ui_en, mem_ui_rdy)
begin
s_ram_wr_ack <= '0';
s_ram_rd_ack <= '0';
case(st_state) is
when st_SEND_WRITE =>
if mem_ui_en='1' and mem_ui_rdy='1' then
s_ram_wr_ack <= '1';
else
s_ram_wr_ack <= '0';
end if;
s_ram_rd_ack <= '0';
when st_SEND_READ =>
if mem_ui_en='1' and mem_ui_rdy='1' then
s_ram_rd_ack <= '1';
else
s_ram_rd_ack <= '0';
end if;
s_ram_wr_ack <= '0';
when others =>
s_ram_wr_ack <= '0';
s_ram_rd_ack <= '0';
end case;
end process p_ack_ctrl;
------------------------------------------------------------------------
-- Registering all outputs of the state machine to 'mem_ui_clk' domain
------------------------------------------------------------------------
p_reg_out: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' or s_calib_complete='0' then
ram_rd_ack_o <= '0';
ram_wr_ack_o <= '0';
ram_data_from_o <= (others => '0');
ram_available_o <= '0';
init_calib_complete_o <= '0';
else
ram_rd_ack_o <= s_ram_rd_ack;
ram_wr_ack_o <= s_ram_wr_ack;
-- if mem_ui_rd_data_end='0' then -- mem_ui_rd_data_end high erases contents on mem_ui_rd_data
ram_rd_valid_o <= mem_ui_rd_data_valid;
ram_data_from_o <= mem_ui_rd_data(ram_data_from_o'length-1 downto 0);
-- end if;
if st_state = st_PREP_OP then
ram_available_o <= '1';
else
ram_available_o <= '0';
end if;
init_calib_complete_o <= s_calib_complete;
end if;
end if;
end process p_reg_out;
end behavioral;
| gpl-3.0 | addd2c7258069279a4b1e099ce911010 | 0.428522 | 3.818696 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/whole_design.vhd | 1 | 11,275 | -- whole_design.vhd
--
-- Created on: 17 Jul 2017
-- Author: Fabian Meyer
--
-- Whole integration of 16-point FFT communicating over I2C.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity whole_design is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end whole_design;
architecture behavioral of whole_design is
-- import i2c slave
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic := '0'; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0) := (others => '0'); -- rx, data received
rx_recv: out std_logic := '0'; -- rx received, high active
busy: out std_logic := '0'; -- busy, high active
sda: inout std_logic := 'Z'; -- serial data of I2C
scl: inout std_logic := 'Z'); -- serial clock of I2C
end component;
-- import fft16 component
component fft16
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
start: in std_logic; -- start FFT, high active
set: in std_logic; -- load FFT with values, high active
get: in std_logic; -- read FFT results, high active
din: in complex; -- datain for loading FFT
done: out std_logic; -- FFT is done, active high
dout: out complex); -- data out for reading results
end component;
constant FFTEXP: natural := 4;
-- OP codes for I2C
constant OPSET: std_logic_vector(7 downto 0) := "00000001";
constant OPRUN: std_logic_vector(7 downto 0) := "00000010";
constant OPGET: std_logic_vector(7 downto 0) := "00000011";
-- INTERNALS
-- =========
-- define states for FSM of whole design
type TState is (SIDLE, SRECV1, SRECV2, SRUN1, SRUN2, SSEND1, SSEND2, SSEND3);
signal state: TState := SIDLE;
-- INPUTS
-- ======
signal byte_cnt: unsigned(1 downto 0) := (others => '0');
signal sample_cnt: unsigned(FFTEXP-1 downto 0) := (others => '0');
-- send buffer for I2C
signal tx_data_i2c: std_logic_vector(7 downto 0) := (others => '0');
signal en_i2c: std_logic := '0';
signal en_fft: std_logic := '1';
signal start_fft: std_logic := '0';
signal set_fft: std_logic := '0';
signal get_fft: std_logic := '0';
signal din_fft: complex := COMPZERO;
-- OUTPUTS
-- =======
-- receive buffer for I2C
signal rx_data_i2c: std_logic_vector(7 downto 0);
signal rx_recv_i2c: std_logic;
signal tx_sent_i2c: std_logic;
signal busy_i2c: std_logic;
signal done_fft: std_logic;
signal dout_fft: complex;
begin
process(rst, clk) is
procedure reset is
begin
state <= SIDLE;
-- reset counters
byte_cnt <= (others => '0');
sample_cnt <= (others => '0');
-- reset I2C
tx_data_i2c <= (others => '0');
en_i2c <= '0';
-- reset fft
en_fft <= '1';
set_fft <= '0';
get_fft <= '0';
din_fft <= (COMPZERO);
start_fft <= '0';
end procedure;
variable byte_cnt_shift: unsigned(4 downto 0) := (others => '0');
variable byte_start: natural := 0;
variable byte_end: natural := 0;
begin
if rst = RSTDEF then
reset;
elsif rising_edge(clk) then
-- only stay high for one cycle
start_fft <= '0';
get_fft <= '0';
set_fft <= '0';
-- divide frequency, only enable I2C every second cycle
en_i2c <= not en_i2c;
case state is
when SIDLE =>
-- we have received something
if rx_recv_i2c = '1' and en_i2c = '1' then
case rx_data_i2c is
when OPSET =>
-- receive data from master
state <= SRECV1;
when OPGET =>
-- send results to master
state <= SSEND1;
get_fft <= '1';
when OPRUN =>
-- run FFT on data we have
state <= SRUN1;
when others =>
-- do nothing, ignore
end case;
end if;
when SRECV1 =>
-- disable fft until we get next number
en_fft <= '0';
if rx_recv_i2c = '1' and en_i2c = '1' then
-- received a byte
byte_cnt <= byte_cnt + 1;
-- multiply byte count by 8
byte_cnt_shift := shift_left(resize(byte_cnt, 5), 3);
byte_start := FIXLEN-to_integer(byte_cnt_shift)-1;
byte_end := FIXLEN-to_integer(byte_cnt_shift)-8;
-- write rx of I2C to din of FFT
din_fft.r(byte_start downto byte_end) <= signed(rx_data_i2c);
if byte_cnt = "10" then
-- we have received 3 bytes
-- now enable fft for 1 cycle to read this value
set_fft <= '1';
en_fft <= '1';
-- reset byte_cnt
byte_cnt <= (others => '0');
-- inc sample counter
sample_cnt <= sample_cnt + 1;
if sample_cnt = "1111" then
-- we have received all samples
state <= SRECV2;
-- reset sample counter
sample_cnt <= (others => '0');
end if;
end if;
end if;
when SRECV2 =>
-- wait until fft module is done
if done_fft = '1' then
state <= SIDLE;
end if;
when SRUN1 =>
if done_fft = '1' then
-- wait until fft is done and has finished writing data to memory
-- the start computing FFT
start_fft <= '1';
state <= SRUN2;
end if;
when SRUN2 =>
if start_fft = '0' and done_fft = '1' then
-- go back to idle mode, fft is done
state <= SIDLE;
end if;
when SSEND1 =>
-- wait for 2 cycles in this state such that FFT module
-- is ready to read data
byte_cnt <= byte_cnt + 1;
if byte_cnt = "10" then
byte_cnt <= "01";
en_fft <= '0';
tx_data_i2c <= std_logic_vector(dout_fft.r(FIXLEN-1 downto FIXLEN-8));
state <= SSEND2;
end if;
when SSEND2 =>
en_fft <= '0';
if tx_sent_i2c = '1' and en_i2c = '1' then
-- if we have sent the byte process next one
byte_cnt <= byte_cnt + 1;
-- multiply byte count by 8
byte_cnt_shift := shift_left(resize(byte_cnt, 5), 3);
byte_start := FIXLEN-to_integer(byte_cnt_shift)-1;
byte_end := FIXLEN-to_integer(byte_cnt_shift)-8;
-- apply current result data to I2C component
tx_data_i2c <= std_logic_vector(dout_fft.r(byte_start downto byte_end));
-- if we have sent 3 bytes then go to next result
if byte_cnt = "10" then
-- enable FFT for one cycle to get next result
en_fft <= '1';
-- reset byte_cnt
byte_cnt <= (others => '0');
-- inc sample counter
sample_cnt <= sample_cnt + 1;
-- if sample counter overflows we just sent last result
if sample_cnt = "1111" then
sample_cnt <= (others => '0');
state <= SSEND3;
end if;
end if;
end if;
when SSEND3 =>
-- wait until also last byte was sent
if tx_sent_i2c = '1' and en_i2c = '1' then
state <= SIDLE;
end if;
end case;
end if;
end process;
i2c: i2c_slave
generic map(RSTDEF => RSTDEF,
ADDRDEF => "0100000")
port map(rst => rst,
clk => clk,
swrst => not RSTDEF,
en => en_i2c,
tx_data => tx_data_i2c,
tx_sent => tx_sent_i2c,
rx_data => rx_data_i2c,
rx_recv => rx_recv_i2c,
busy => busy_i2c,
sda => sda,
scl => scl);
fft: fft16
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
swrst => not RSTDEF,
en => en_fft,
start => start_fft,
set => set_fft,
get => get_fft,
din => din_fft,
done => done_fft,
dout => dout_fft);
end architecture;
| mit | 272f5818af833fb3e1e9529dc4e15a7a | 0.413925 | 4.453002 | false | false | false | false |
kristofferkoch/ethersound | rxdecode.vhd | 1 | 6,123 | -----------------------------------------------------------------------------
-- Module for decoding received frames.
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity rxdecode is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_dv : in STD_LOGIC;
data_end : in STD_LOGIC;
data_err : in STD_LOGIC;
audio : out STD_LOGIC_VECTOR (23 downto 0);
audio_dv : out STD_LOGIC;
cmd:out unsigned(15 downto 0);
cmd_len:out unsigned(7 downto 0);
cmd_d:out std_logic_vector(7 downto 0);
cmd_dv:out std_logic;
debug: out std_logic_vector(7 downto 0)
);
end rxdecode;
architecture Behavioral of rxdecode is
type state_t is (Idle, rxDest, rxSource, rxType, rxMagic, rxCmd, rxCmdLen, rxCmdParam, rxAudio, Drop);
signal state:state_t;
signal counter:integer range 0 to 255;
type byte_ary is array (0 to 6) of std_logic_vector(7 downto 0); --7 bytes = 3 bytes audio + 4 bytes CRC
signal inbuf:byte_ary;
signal cmd_s:unsigned(7 downto 0);
begin
audio <= inbuf(0) & inbuf(1) & inbuf(2);
process(sysclk) is
variable audio_dv_v:std_logic;
begin
if rising_edge(sysclk) then
if reset = '1' then
state <= Idle;
debug <= (OTHERS => '1');
audio_dv <= '0';
inbuf <= (OTHERS => (OTHERS => '0'));
else
audio_dv_v := '0';
case state is
when rxDest =>
debug(0) <= '0';
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
if data = x"ff" then
if counter = 0 then
state <= rxSource;
counter <= 5;
else
counter <= counter - 1;
end if;
else
state <= Drop;
end if;
end if;
when rxSource =>
debug(1) <= '0';
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
if counter = 0 then
state <= rxType;
counter <= 1;
else
counter <= counter - 1;
end if;
end if;
when rxType =>
debug(2) <= '0';
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
if counter = 0 then
if data = x"b5" then
state <= rxMagic;
counter <= 1;
else
state <= Drop;
end if;
else --counter = 1
if data /= x"88" then
state <= Drop;
end if;
counter <= counter - 1;
end if;
end if;
when RxMagic =>
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
if counter = 0 then
if data = x"0d" then
state <= rxCmd;
counter <= 1;
else
state <= Drop;
end if;
else --counter = 1
if data /= x"f0" then
state <= Drop;
end if;
counter <= counter - 1;
end if;
end if;
when rxCmd =>
debug(3) <= '0';
cmd_dv <= '0';
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
if counter = 0 then
if cmd_s = x"00" and data = x"00" then
state <= rxAudio;
counter <= 8;
else
cmd(15 downto 8) <= cmd_s;
cmd(7 downto 0) <= unsigned(data);
state <= rxCmdLen;
end if;
else --counter = 1
cmd_s(7 downto 0) <= unsigned(data);
end if;
end if;
when rxCmdLen =>
debug(5) <= '0';
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
cmd_len <= unsigned(data);
counter <= to_integer(unsigned(data));
state <= rxCmdParam;
end if;
when rxCmdParam =>
debug(6) <= '0';
if data_end = '1' then
state <= Idle;
elsif data_dv = '1' then
cmd_dv <= '1';
cmd_d <= data;
if counter = 0 then
state <= rxCmd;
else
counter <= counter - 1;
end if;
else
cmd_dv <= '0';
end if;
when rxAudio =>
debug(4) <= '0';
if data_end = '1' and data_err = '0' then
--Last 4 bytes was crc. Discard them.
-- that is, counter should be 1 (1 crc-byte in framebuf)
-- and 3 crc-bytes in framebuf2
state <= Idle;
elsif data_end = '1' and data_err = '1' then
--Premature data-end. Discard current frame
state <= Idle;
elsif data_dv = '1' then
inbuf(6) <= data;
for i in 5 downto 0 loop
inbuf(i) <= inbuf(i+1);
end loop;
if counter = 0 then
counter <= 2;
else
counter <= counter - 1;
if counter = 2 then
audio_dv_v := '1';
end if;
end if;
end if;
when Drop =>
debug(7) <= '0';
if data_end = '1' then
state <= Idle;
end if;
when others => --Idle
if data_dv = '1' then
debug <= (OTHERS => '1');
if data = x"ff" then
state <= rxDest;
counter <= 4;
else
state <= Drop;
end if;
end if;
end case;
audio_dv <= audio_dv_v;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 087887c1f56a2a826141b1ae78c34587 | 0.498938 | 3.324104 | false | false | false | false |
kristofferkoch/ethersound | crc.vhd | 1 | 2,917 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package crc is
function CRC32_4
( Data: std_logic_vector(3 downto 0);
CRC: std_logic_vector(31 downto 0);
Enable:std_logic)
return std_logic_vector;
end crc;
package body crc is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 4
-- convention: the first serial data bit is D(3)
function CRC32_4
( Data: std_logic_vector(3 downto 0);
CRC: std_logic_vector(31 downto 0);
Enable:std_logic)
return std_logic_vector is
variable D: std_logic_vector(3 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NewCRC: std_logic_vector(31 downto 0);
variable E:std_logic;
begin
for i in 0 to 3 loop
D(i) := Data(3-i);
end loop;
C := CRC;
E := Enable;
NewCRC(0) := E and (D(0) xor C(28));
NewCRC(1) := E and (D(1) xor D(0) xor C(28) xor C(29));
NewCRC(2) := E and (D(2) xor D(1) xor D(0) xor C(28) xor C(29) xor C(30));
NewCRC(3) := E and (D(3) xor D(2) xor D(1) xor C(29) xor C(30) xor C(31));
NewCRC(4) := (E and (D(3) xor D(2) xor D(0) xor C(28) xor C(30) xor C(31))) xor C(0);
NewCRC(5) := (E and (D(3) xor D(1) xor D(0) xor C(28) xor C(29) xor C(31))) xor C(1);
NewCRC(6) := (E and (D(2) xor D(1) xor C(29) xor C(30))) xor C(2);
NewCRC(7) := (E and (D(3) xor D(2) xor D(0) xor C(28) xor C(30) xor C(31))) xor C(3);
NewCRC(8) := (E and (D(3) xor D(1) xor D(0) xor C(28) xor C(29) xor C(31))) xor C(4);
NewCRC(9) := (E and (D(2) xor D(1) xor C(29) xor C(30))) xor C(5);
NewCRC(10) := (E and (D(3) xor D(2) xor D(0) xor C(28) xor C(30) xor C(31))) xor C(6);
NewCRC(11) := (E and (D(3) xor D(1) xor D(0) xor C(28) xor C(29) xor C(31))) xor C(7);
NewCRC(12) := (E and (D(2) xor D(1) xor D(0) xor C(28) xor C(29) xor C(30))) xor C(8);
NewCRC(13) := (E and (D(3) xor D(2) xor D(1) xor C(29) xor C(30) xor C(31))) xor C(9);
NewCRC(14) := (E and (D(3) xor D(2) xor C(30) xor C(31))) xor C(10);
NewCRC(15) := (E and (D(3) xor C(31))) xor C(11);
NewCRC(16) := (E and (D(0) xor C(28))) xor C(12);
NewCRC(17) := (E and (D(1) xor C(29))) xor C(13);
NewCRC(18) := (E and (D(2) xor C(30))) xor C(14);
NewCRC(19) := (E and (D(3) xor C(31))) xor C(15);
NewCRC(20) := C(16);
NewCRC(21) := C(17);
NewCRC(22) := (E and (D(0) xor C(28))) xor C(18);
NewCRC(23) := (E and (D(1) xor D(0) xor C(28) xor C(29))) xor C(19);
NewCRC(24) := (E and (D(2) xor D(1) xor C(29) xor C(30))) xor C(20);
NewCRC(25) := (E and (D(3) xor D(2) xor C(30) xor C(31))) xor C(21);
NewCRC(26) := (E and (D(3) xor D(0) xor C(28) xor C(31))) xor C(22);
NewCRC(27) := (E and (D(1) xor C(29))) xor C(23);
NewCRC(28) := (E and (D(2) xor C(30))) xor C(24);
NewCRC(29) := (E and (D(3) xor C(31))) xor C(25);
NewCRC(30) := C(26);
NewCRC(31) := C(27);
return NewCRC;
end CRC32_4;
end crc;
| gpl-3.0 | f67b9174ebc6cd3df32cbce7c1eeedb8 | 0.53891 | 2.339214 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/fifo/src/asyncFifo-e.vhd | 2 | 3,669 | -------------------------------------------------------------------------------
--! @file asyncFifo-e.vhd
--
--! @brief The asynchronous FIFO entity.
--!
--! @details This is the asynchronous FIFO interface description, for a dual
--! clocked FIFO component.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity asyncFifo is
generic (
--! Data width of write and read port
gDataWidth : natural := 8;
--! Number of words stored in fifo
gWordSize : natural := 64;
--! Number of synchronizer stages
gSyncStages : natural := 2;
--! Select memory resource ("ON" = memory / "OFF" = registers)
gMemRes : string := "ON"
);
port (
--! Asynchronous clear (FIXME: Convert this to reset, and add wr-/rd-clear inputs)
iAclr : in std_logic;
--! Write Clk
iWrClk : in std_logic;
--! Write Request
iWrReq : in std_logic;
--! Write Data
iWrData : in std_logic_vector(gDataWidth-1 downto 0);
--! Write Empty Flag
oWrEmpty : out std_logic;
--! Write Full Flag
oWrFull : out std_logic;
--! Write used words
oWrUsedw : out std_logic_vector(logDualis(gWordSize)-1 downto 0);
--! Read clk
iRdClk : in std_logic;
--! Read Request
iRdReq : in std_logic;
--! Read Data
oRdData : out std_logic_vector(gDataWidth-1 downto 0);
--! Read Empty Flag
oRdEmpty : out std_logic;
--! Read Full Flag
oRdFull : out std_logic;
--! Read used words
oRdUsedw : out std_logic_vector(logDualis(gWordSize)-1 downto 0)
);
end entity asyncFifo;
| gpl-2.0 | 9c18c12f5ddbf5938ffaa3400dd7fbe4 | 0.599073 | 4.662008 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/naChans.vhdl | 1 | 22,143 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity naChans is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_in : in sfixed (-22 downto -53);
param_none_na_m_instances : in sfixed (18 downto -13);
exposure_none_na_m_fcond : out sfixed (18 downto -13);
exposure_none_na_m_q : out sfixed (18 downto -13);
statevariable_none_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_na_h_instances : in sfixed (18 downto -13);
exposure_none_na_h_fcond : out sfixed (18 downto -13);
exposure_none_na_h_q : out sfixed (18 downto -13);
statevariable_none_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end naChans;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of naChans is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_conductance_channelg : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_channelg_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component na
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
param_none_m_instances : in sfixed (18 downto -13);
exposure_none_m_fcond : out sfixed (18 downto -13);
exposure_none_m_q : out sfixed (18 downto -13);
statevariable_none_m_q_out : out sfixed (18 downto -13);
statevariable_none_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_m_fcond_in : in sfixed (18 downto -13);
param_per_time_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_h_instances : in sfixed (18 downto -13);
exposure_none_h_fcond : out sfixed (18 downto -13);
exposure_none_h_q : out sfixed (18 downto -13);
statevariable_none_h_q_out : out sfixed (18 downto -13);
statevariable_none_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_h_fcond_in : in sfixed (18 downto -13);
param_per_time_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal na_Component_done : STD_LOGIC ; signal Exposure_conductance_na_g_internal : sfixed (-22 downto -53);
signal Exposure_none_na_m_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_na_m_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_na_m_forwardRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_na_m_reverseRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_none_na_h_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_na_h_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_na_h_forwardRateh1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_na_h_reverseRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
na_uut : na
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => na_Component_done,
param_conductance_conductance => param_conductance_na_conductance,
requirement_voltage_v => requirement_voltage_v,
Exposure_conductance_g => Exposure_conductance_na_g_internal,
derivedvariable_conductance_g_out => derivedvariable_conductance_na_g_out,
derivedvariable_conductance_g_in => derivedvariable_conductance_na_g_in,
param_none_m_instances => param_none_na_m_instances,
Exposure_none_m_fcond => Exposure_none_na_m_fcond_internal,
Exposure_none_m_q => Exposure_none_na_m_q_internal,
statevariable_none_m_q_out => statevariable_none_na_m_q_out,
statevariable_none_m_q_in => statevariable_none_na_m_q_in,
derivedvariable_none_m_fcond_out => derivedvariable_none_na_m_fcond_out,
derivedvariable_none_m_fcond_in => derivedvariable_none_na_m_fcond_in,
param_per_time_m_forwardRatem1_rate => param_per_time_na_m_forwardRatem1_rate,
param_voltage_m_forwardRatem1_midpoint => param_voltage_na_m_forwardRatem1_midpoint,
param_voltage_m_forwardRatem1_scale => param_voltage_na_m_forwardRatem1_scale,
param_voltage_inv_m_forwardRatem1_scale_inv => param_voltage_inv_na_m_forwardRatem1_scale_inv,
Exposure_per_time_m_forwardRatem1_r => Exposure_per_time_na_m_forwardRatem1_r_internal,
derivedvariable_per_time_m_forwardRatem1_r_out => derivedvariable_per_time_na_m_forwardRatem1_r_out,
derivedvariable_per_time_m_forwardRatem1_r_in => derivedvariable_per_time_na_m_forwardRatem1_r_in,
param_per_time_m_reverseRatem1_rate => param_per_time_na_m_reverseRatem1_rate,
param_voltage_m_reverseRatem1_midpoint => param_voltage_na_m_reverseRatem1_midpoint,
param_voltage_m_reverseRatem1_scale => param_voltage_na_m_reverseRatem1_scale,
param_voltage_inv_m_reverseRatem1_scale_inv => param_voltage_inv_na_m_reverseRatem1_scale_inv,
Exposure_per_time_m_reverseRatem1_r => Exposure_per_time_na_m_reverseRatem1_r_internal,
derivedvariable_per_time_m_reverseRatem1_r_out => derivedvariable_per_time_na_m_reverseRatem1_r_out,
derivedvariable_per_time_m_reverseRatem1_r_in => derivedvariable_per_time_na_m_reverseRatem1_r_in,
param_none_h_instances => param_none_na_h_instances,
Exposure_none_h_fcond => Exposure_none_na_h_fcond_internal,
Exposure_none_h_q => Exposure_none_na_h_q_internal,
statevariable_none_h_q_out => statevariable_none_na_h_q_out,
statevariable_none_h_q_in => statevariable_none_na_h_q_in,
derivedvariable_none_h_fcond_out => derivedvariable_none_na_h_fcond_out,
derivedvariable_none_h_fcond_in => derivedvariable_none_na_h_fcond_in,
param_per_time_h_forwardRateh1_rate => param_per_time_na_h_forwardRateh1_rate,
param_voltage_h_forwardRateh1_midpoint => param_voltage_na_h_forwardRateh1_midpoint,
param_voltage_h_forwardRateh1_scale => param_voltage_na_h_forwardRateh1_scale,
param_voltage_inv_h_forwardRateh1_scale_inv => param_voltage_inv_na_h_forwardRateh1_scale_inv,
Exposure_per_time_h_forwardRateh1_r => Exposure_per_time_na_h_forwardRateh1_r_internal,
derivedvariable_per_time_h_forwardRateh1_r_out => derivedvariable_per_time_na_h_forwardRateh1_r_out,
derivedvariable_per_time_h_forwardRateh1_r_in => derivedvariable_per_time_na_h_forwardRateh1_r_in,
param_per_time_h_reverseRateh1_rate => param_per_time_na_h_reverseRateh1_rate,
param_voltage_h_reverseRateh1_midpoint => param_voltage_na_h_reverseRateh1_midpoint,
param_voltage_h_reverseRateh1_scale => param_voltage_na_h_reverseRateh1_scale,
param_voltage_inv_h_reverseRateh1_scale_inv => param_voltage_inv_na_h_reverseRateh1_scale_inv,
Exposure_per_time_h_reverseRateh1_r => Exposure_per_time_na_h_reverseRateh1_r_internal,
derivedvariable_per_time_h_reverseRateh1_r_out => derivedvariable_per_time_na_h_reverseRateh1_r_out,
derivedvariable_per_time_h_reverseRateh1_r_in => derivedvariable_per_time_na_h_reverseRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_conductance_na_g <= Exposure_conductance_na_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_conductance_na_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_conductance_na_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
derivedvariable_conductance_channelg_next <= resize(( exposure_conductance_na_g_internal ),-22,-53);
derivedvariable_conductance_geff_next <= resize(( derivedvariable_conductance_channelg_next * param_none_number ),-22,-53);
derivedvariable_current_i_next <= resize(( derivedvariable_conductance_geff_next * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_conductance_channelg <= derivedvariable_conductance_channelg_next;
derivedvariable_conductance_geff <= derivedvariable_conductance_geff_next;
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(na_component_done,CLK)
begin
if (na_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | a27b95c8396c7edd8f78751573a92dd4 | 0.630854 | 3.338812 | false | false | false | false |
riverever/verilogTestSuit | ivltests/br986.vhd | 1 | 859 | -- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
clk1_i : in std_logic_vector;
clk1_ib : in std_logic;
clk1_o : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
component IBUFDS generic (
DIFF_TERM : boolean := FALSE
); port(
O : out std_logic;
I : in std_logic;
IB : in std_logic
); end component;
begin
ibufds1 : ibufds
generic map (
DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy
)
port map (
i => clk1_i,
ib => clk1_ib,
o => clk1_o
);
end bug3_syn;
entity ibufds is
generic (
DIFF_TERM : boolean := FALSE
);
port (
i : in std_logic_vector;
ib : in std_logic;
o : out std_logic
);
end ibufds;
architecture ibufds_sim of ibufds is
begin
o <= i;
end ibufds_sim;
| gpl-2.0 | bac7c40173870dec11b97e721d749596 | 0.615832 | 2.863333 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/irqGenRtl.vhd | 2 | 7,158 | -------------------------------------------------------------------------------
--! @file irqGenRtl.vhd
--
--! @brief irq generator with sync latch feature
--
--! @details The irq generator is similar to a ordinary interrupt controller,
--! however, it is extended with a "sync-latch" feature. This enables to
--! throttle the interrupt requests and assert the general irq with the sync
--! input signal. Hence, any irq source is deferred to the sync assertion.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity irqGen is
generic (
--! number of interrupt sources
gIrqSourceCount : natural := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- Irq
--! sync source
iSync : in std_logic;
--! interrupt source vector (pulse)
iIrqSource : in std_logic_vector(gIrqSourceCount downto 1);
--! interrupt signal
oIrq : out std_logic;
-- Control
--! master enable
iIrqMasterEnable : in std_logic;
--! interrupt source enable vector ('right is sync)
iIrqSourceEnable : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
iIrqAcknowledge : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source pending
oIrgPending : out std_logic_vector(gIrqSourceCount downto 0)
);
end irqGen;
architecture Rtl of irqGen is
--! sync rising edge
signal syncRising : std_logic;
--! interrupt register latch
signal irqRegLatch, irqRegLatch_next : std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source store
signal irqSourceStore, irqSourceStore_next : std_logic_vector(gIrqSourceCount downto 1);
--! unregistered irq out signal
signal unregIrq, irq_reg : std_logic;
begin
--! generate pulse for rising edge of sync
syncEdgeDet : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iSync,
oRising => syncRising,
oFalling => open,
oAny => open
);
--! irq registers
clkdReg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
irqRegLatch <= (others => cInactivated);
irqSourceStore <= (others => cInactivated);
irq_reg <= cInactivated;
else
irqRegLatch <= irqRegLatch_next;
irqSourceStore <= irqSourceStore_next;
irq_reg <= unregIrq;
end if;
end if;
end process;
oIrq <= irq_reg;
--! irq register control
combIrqRegCont : process (
iIrqSource,
iIrqAcknowledge,
irqRegLatch,
irqSourceStore,
syncRising,
iIrqSourceEnable(iIrqSourceEnable'right)
)
begin
--default
irqRegLatch_next <= irqRegLatch;
irqSourceStore_next <= irqSourceStore;
-- do acknowledge with latched and source register
for i in gIrqSourceCount downto 1 loop
if iIrqAcknowledge(i) = cActivated then
irqRegLatch_next(i) <= cInactivated;
irqSourceStore_next(i) <= cInactivated;
end if;
end loop;
if iIrqAcknowledge(irqRegLatch'right) = cActivated then
irqRegLatch_next(irqRegLatch'right) <= cInactivated;
end if;
for i in gIrqSourceCount downto 1 loop
if iIrqSource(i) = cActivated then
irqSourceStore_next(i) <= cActivated;
end if;
end loop;
-- trigger irq with sync
if syncRising = cActivated then
-- loop through all irq sources
for i in gIrqSourceCount downto 1 loop
irqRegLatch_next(i) <= irqSourceStore(i);
end loop;
-- activate sync irq if it is enabled
-- (sync irqs in the past are not of interest!)
irqRegLatch_next(irqRegLatch'right) <= iIrqSourceEnable(iIrqSourceEnable'right);
end if;
end process;
--! output irq register
oIrgPending <= irqRegLatch;
--! irq signal generation
combIrqGen : process (
irqRegLatch,
iIrqMasterEnable,
iIrqSourceEnable
)
variable vTmp : std_logic;
begin
--default
unregIrq <= cInactivated;
-- the master enable overrules everything
if iIrqMasterEnable = cActivated then
-- check individual irqs
vTmp := cInactivated;
for i in gIrqSourceCount downto 0 loop
vTmp := vTmp or (iIrqSourceEnable(i) and irqRegLatch(i));
end loop;
-- variable holds irq state
unregIrq <= vTmp;
end if;
end process;
end Rtl;
| gpl-2.0 | 9ec159f21b236694b9628f183d823335 | 0.589131 | 5.019635 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/clk.vhd | 1 | 1,082 | LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
ival : in std_logic_vector(31 downto 0)
);
end clk;
architecture rtl of clk is
signal foo : std_logic_vector(10+3 downto 0);
signal baz : std_logic_vector(2 downto 0);
signal egg : std_logic_vector(4 to 7-1);
begin
pfoo: process(reset, sysclk)
begin
if( reset /= '0' ) then
foo <= (others => '1');
elsif( sysclk'event and sysclk = '1' ) then
foo <= ival(31 downto 31-(10+3));
end if;
end process;
pbaz: process(preset, dsysclk)
begin
if( preset /= '1' ) then
baz <= (others => '0');
elsif( dsysclk'event and dsysclk = '0' ) then
baz <= ival(2 downto 0);
end if;
end process;
pegg: process(qreset, esysclk)
begin
if( qreset /= '1' ) then
egg <= (others => '0');
elsif( esysclk'event and esysclk = '0' ) then
egg <= ival(6 downto 4);
end if;
end process;
end rtl;
| apache-2.0 | f6c4fae9dbebe9813f4dcdca9d6a7615 | 0.591497 | 3.136232 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_props.vhd | 1 | 20,131 | library ieee; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
--library std;
--use std.all;
library ocpi; use ocpi.types.all; use ocpi.wci.all;
package props is
--
-- Property storage entities to attach to a wci.decoder
--
-- Declarations for various property implementationss
--
-- registered bool property value, with write pulse
--
component bool_property
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(0 downto 0);
value : out bool_t;
written : out bool_t);
end component;
--
-- registered bool property array value, with write pulse
--
component bool_array_property
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out bool_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_bool_property
generic (worker : worker_t; property : property_t);
port (value : in bool_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_bool_array_property
generic (worker : worker_t; property : property_t);
port (value : in bool_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered char property value, with write pulse
--
component char_property
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(char_t'range);
value : out char_t;
written : out bool_t);
end component;
--
-- registered char property array value, with write pulse
--
component char_array_property
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out char_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_char_property
generic (worker : worker_t; property : property_t);
port (value : in char_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_char_array_property
generic (worker : worker_t; property : property_t);
port (value : in char_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered double property value, with write pulse
--
component double_property
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_t;
written : out bool_t;
hi32 : in bool_t);
end component;
--
-- registered double property array value, with write pulse
--
component double_array_property
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property
--
component read_double_property
generic (worker : worker_t; property : property_t);
port (value : in double_t;
data_out : out std_logic_vector(31 downto 0);
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property array
--
component read_double_array_property
generic (worker : worker_t; property : property_t);
port (value : in double_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end component;
--
-- registered float property value, with write pulse
--
component float_property
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(float_t'range);
value : out float_t;
written : out bool_t);
end component;
--
-- registered float property array value, with write pulse
--
component float_array_property
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out float_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_float_property
generic (worker : worker_t; property : property_t);
port (value : in float_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_float_array_property
generic (worker : worker_t; property : property_t);
port (value : in float_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered short property value, with write pulse
--
component short_property
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(short_t'range);
value : out short_t;
written : out bool_t);
end component;
--
-- registered short property array value, with write pulse
--
component short_array_property
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out short_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_short_property
generic (worker : worker_t; property : property_t);
port (value : in short_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_short_array_property
generic (worker : worker_t; property : property_t);
port (value : in short_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered long property value, with write pulse
--
component long_property
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(long_t'range);
value : out long_t;
written : out bool_t);
end component;
--
-- registered long property array value, with write pulse
--
component long_array_property
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out long_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_long_property
generic (worker : worker_t; property : property_t);
port (value : in long_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_long_array_property
generic (worker : worker_t; property : property_t);
port (value : in long_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered uchar property value, with write pulse
--
component uchar_property
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(uchar_t'range);
value : out uchar_t;
written : out bool_t);
end component;
--
-- registered uchar property array value, with write pulse
--
component uchar_array_property
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out uchar_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_uchar_property
generic (worker : worker_t; property : property_t);
port (value : in uchar_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_uchar_array_property
generic (worker : worker_t; property : property_t);
port (value : in uchar_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered ulong property value, with write pulse
--
component ulong_property
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ulong_t'range);
value : out ulong_t;
written : out bool_t);
end component;
--
-- registered ulong property array value, with write pulse
--
component ulong_array_property
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_ulong_property
generic (worker : worker_t; property : property_t);
port (value : in ulong_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_ulong_array_property
generic (worker : worker_t; property : property_t);
port (value : in ulong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered ushort property value, with write pulse
--
component ushort_property
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ushort_t'range);
value : out ushort_t;
written : out bool_t);
end component;
--
-- registered ushort property array value, with write pulse
--
component ushort_array_property
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ushort_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_ushort_property
generic (worker : worker_t; property : property_t);
port (value : in ushort_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_ushort_array_property
generic (worker : worker_t; property : property_t);
port (value : in ushort_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered longlong property value, with write pulse
--
component longlong_property
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_t;
written : out bool_t;
hi32 : in bool_t);
end component;
--
-- registered longlong property array value, with write pulse
--
component longlong_array_property
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property
--
component read_longlong_property
generic (worker : worker_t; property : property_t);
port (value : in longlong_t;
data_out : out std_logic_vector(31 downto 0);
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property array
--
component read_longlong_array_property
generic (worker : worker_t; property : property_t);
port (value : in longlong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end component;
--
-- registered ulonglong property value, with write pulse
--
component ulonglong_property
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_t;
written : out bool_t;
hi32 : in bool_t);
end component;
--
-- registered ulonglong property array value, with write pulse
--
component ulonglong_array_property
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property
--
component read_ulonglong_property
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_t;
data_out : out std_logic_vector(31 downto 0);
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property array
--
component read_ulonglong_array_property
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end component;
--
-- registered string property value, with write pulse
--
component string_property
generic(worker : worker_t; property : property_t; default : string_t := ("00000000","00000000"));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_t(0 to property.string_length);
written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
--
-- registered string property array value, with write pulse
--
component string_array_property
generic(worker : worker_t; property : property_t; default : string_array_t := (("00000000","00000000"),("00000000","00000000")));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
--
-- readback scalar <=32 property
--
component read_string_property
generic (worker : worker_t; property : property_t);
port (value : in string_t;
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
--
-- readback string property array
--
component read_string_array_property
generic (worker : worker_t; property : property_t);
port (value : in string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
end package props;
| lgpl-3.0 | 58ddc243933e87f6c30e194b03706b00 | 0.609508 | 3.401656 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_B/CPLD Firmware/VGAtonic_Firmware.vhd | 2 | 3,154 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
--SPI (no MISO)
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD: in STD_LOGIC; -- Active low
-- VGA
PIXEL : inout STD_LOGIC_VECTOR(7 downto 0);
HSYNC : inout STD_LOGIC;
VSYNC : inout STD_LOGIC;
--CPLD_GPIO : out STD_LOGIC_VECTOR(16 downto 16) := "0";
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SCK : IN std_logic;
SEL : IN std_logic;
MOSI : IN std_logic;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
MISO : OUT std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code
-- Just VGA for now
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
PIXEL : INOUT std_logic_vector(7 downto 0);
HSYNC : INOUT std_logic;
VSYNC : INOUT std_logic;
--CPLD_GPIO : OUT std_logic_vector(16 to 16);
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and VGA output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SCK => EXT_SCK,
SEL => EXT_SEL_CPLD,
MOSI => EXT_MOSI,
MISO => EXT_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
PIXEL => PIXEL,
HSYNC => HSYNC,
VSYNC => VSYNC,
--CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
| mit | aafdf003d8069d17bbecab1165da27c0 | 0.647749 | 2.766667 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/dpRamSplx-e.vhd | 2 | 3,747 | -------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity dpRamSplx is
generic (
--! Word width port A [bit]
gWordWidthA : natural := 16;
--! Byteenable width port A [bit]
gByteenableWidthA : natural := 2;
--! Number of words (reference is port A)
gNumberOfWordsA : natural := 1024;
--! Word width port B [bit]
gWordWidthB : natural := 32;
--! Number of words (reference is port B)
gNumberOfWordsB : natural := 512;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWordsA)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gByteenableWidthA-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidthA-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWordsB)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidthB-1 downto 0)
);
end dpRamSplx;
| gpl-2.0 | 2cc3c7470dfe54e11d567042dfab6b9b | 0.595943 | 4.541818 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/testbench.vhdl | 1 | 28,055 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity tb_simulation is
end tb_simulation;
architecture tb of tb_simulation is
FILE test_out_data: TEXT open WRITE_MODE is "VHDLoutput.csv";component top_synth
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_param_voltage_v0 : in sfixed (2 downto -22);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_capacitance_C : in sfixed (-33 downto -47);
neuron_model_param_capacitance_inv_C_inv : in sfixed (47 downto 33);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_none_spiking : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_spiking : in sfixed (18 downto -13);
neuron_model_param_none_leak_number : in sfixed (18 downto -13);
neuron_model_param_voltage_leak_erev : in sfixed (2 downto -22);
neuron_model_exposure_current_leak_i : out sfixed (-28 downto -53);
neuron_model_stateCURRENT_current_leak_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_leak_i : in sfixed (-28 downto -53);
neuron_model_param_conductance_leak_passive_conductance : in sfixed (-22 downto -53);
neuron_model_exposure_conductance_leak_passive_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_leak_passive_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_leak_passive_g : in sfixed (-22 downto -53);
neuron_model_param_none_naChans_number : in sfixed (18 downto -13);
neuron_model_param_voltage_naChans_erev : in sfixed (2 downto -22);
neuron_model_exposure_current_naChans_i : out sfixed (-28 downto -53);
neuron_model_stateCURRENT_current_naChans_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_naChans_i : in sfixed (-28 downto -53);
neuron_model_param_conductance_naChans_na_conductance : in sfixed (-22 downto -53);
neuron_model_exposure_conductance_naChans_na_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_naChans_na_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_naChans_na_g : in sfixed (-22 downto -53);
neuron_model_param_none_naChans_na_m_instances : in sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_m_fcond : out sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_m_q : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_m_q : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_m_q : in sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_m_fcond : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_m_fcond : in sfixed (18 downto -13);
neuron_model_param_per_time_naChans_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_m_forwardRatem1_r : in sfixed (18 downto -2);
neuron_model_param_per_time_naChans_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_m_reverseRatem1_r : in sfixed (18 downto -2);
neuron_model_param_none_naChans_na_h_instances : in sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_h_fcond : out sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_h_q : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_h_q : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_h_q : in sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_h_fcond : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_h_fcond : in sfixed (18 downto -13);
neuron_model_param_per_time_naChans_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_h_forwardRateh1_r : in sfixed (18 downto -2);
neuron_model_param_per_time_naChans_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_h_reverseRateh1_r : in sfixed (18 downto -2);
neuron_model_param_none_kChans_number : in sfixed (18 downto -13);
neuron_model_param_voltage_kChans_erev : in sfixed (2 downto -22);
neuron_model_exposure_current_kChans_i : out sfixed (-28 downto -53);
neuron_model_stateCURRENT_current_kChans_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_kChans_i : in sfixed (-28 downto -53);
neuron_model_param_conductance_kChans_k_conductance : in sfixed (-22 downto -53);
neuron_model_exposure_conductance_kChans_k_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_kChans_k_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_kChans_k_g : in sfixed (-22 downto -53);
neuron_model_param_none_kChans_k_n_instances : in sfixed (18 downto -13);
neuron_model_exposure_none_kChans_k_n_fcond : out sfixed (18 downto -13);
neuron_model_exposure_none_kChans_k_n_q : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_kChans_k_n_q : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_kChans_k_n_q : in sfixed (18 downto -13);
neuron_model_stateCURRENT_none_kChans_k_n_fcond : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_kChans_k_n_fcond : in sfixed (18 downto -13);
neuron_model_param_per_time_kChans_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_kChans_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_kChans_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_kChans_k_n_forwardRaten1_r : in sfixed (18 downto -2);
neuron_model_param_per_time_kChans_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_kChans_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_kChans_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_kChans_k_n_reverseRaten1_r : in sfixed (18 downto -2);
neuron_model_param_time_synapsemodel_tauDecay : in sfixed (6 downto -18);
neuron_model_param_conductance_synapsemodel_gbase : in sfixed (-22 downto -53);
neuron_model_param_voltage_synapsemodel_erev : in sfixed (2 downto -22);
neuron_model_param_time_inv_synapsemodel_tauDecay_inv : in sfixed (18 downto -6);
neuron_model_exposure_current_synapsemodel_i : out sfixed (-28 downto -53);
neuron_model_exposure_conductance_synapsemodel_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_synapsemodel_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_synapsemodel_g : in sfixed (-22 downto -53);
neuron_model_stateCURRENT_current_synapsemodel_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_synapsemodel_i : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal clk : std_logic := '0';
signal eog : std_logic := '0';
signal init_model : std_logic := '1';
signal step_once_go : std_logic := '0';
signal step_once_complete : std_logic := '0';
signal eventport_in_spike_aggregate : STD_LOGIC_VECTOR(511 downto 0);
signal sysparam_time_simtime : sfixed ( 6 downto -22) := to_sfixed (0.0,6 , -22);
signal Errors : integer;
signal sysparam_time_timestep : sfixed (-6 downto -22) := to_sfixed( 5.0E-5 ,-6,-22);
signal neuron_model_stateCURRENT_voltage_v_int : sfixed (2 downto -22);signal neuron_model_stateCURRENT_none_spiking_int : sfixed (18 downto -13);signal neuron_model_eventport_out_spike_internal : std_logic; signal neuron_model_stateCURRENT_current_leak_i_int : sfixed (-28 downto -53);signal neuron_model_stateCURRENT_conductance_leak_passive_g_int : sfixed (-22 downto -53);signal neuron_model_stateCURRENT_current_naChans_i_int : sfixed (-28 downto -53);signal neuron_model_stateCURRENT_conductance_naChans_na_g_int : sfixed (-22 downto -53);signal neuron_model_stateCURRENT_none_naChans_na_m_q_int : sfixed (18 downto -13);signal neuron_model_stateCURRENT_none_naChans_na_m_fcond_int : sfixed (18 downto -13);signal neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r_int : sfixed (18 downto -2);signal neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r_int : sfixed (18 downto -2);signal neuron_model_stateCURRENT_none_naChans_na_h_q_int : sfixed (18 downto -13);signal neuron_model_stateCURRENT_none_naChans_na_h_fcond_int : sfixed (18 downto -13);signal neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r_int : sfixed (18 downto -2);signal neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r_int : sfixed (18 downto -2);signal neuron_model_stateCURRENT_current_kChans_i_int : sfixed (-28 downto -53);signal neuron_model_stateCURRENT_conductance_kChans_k_g_int : sfixed (-22 downto -53);signal neuron_model_stateCURRENT_none_kChans_k_n_q_int : sfixed (18 downto -13);signal neuron_model_stateCURRENT_none_kChans_k_n_fcond_int : sfixed (18 downto -13);signal neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r_int : sfixed (18 downto -2);signal neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r_int : sfixed (18 downto -2);signal neuron_model_stateCURRENT_conductance_synapsemodel_g_int : sfixed (-22 downto -53);signal neuron_model_stateCURRENT_current_synapsemodel_i_int : sfixed (-28 downto -53);signal neuron_model_eventport_in_synapsemodel_in_internal : std_logic;
file stimulus: TEXT open read_mode is "stimulus.csv";
begin
top_synth_uut : top_synth
port map ( clk => clk,
init_model => init_model,
step_once_go => step_once_go,
step_once_complete => step_once_complete,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
neuron_model_eventport_out_spike => neuron_model_eventport_out_spike_internal ,
neuron_model_param_voltage_v0 => to_sfixed (-0.065,2 , -22),
neuron_model_param_voltage_thresh => to_sfixed (0.02,2 , -22),
neuron_model_param_capacitance_C => to_sfixed (1.0E-11,-33 , -47),
neuron_model_param_capacitance_inv_C_inv => to_sfixed (9.9999998E10,47 , 33),
neuron_model_stateCURRENT_voltage_v => neuron_model_stateCURRENT_voltage_v_int,
neuron_model_stateRESTORE_voltage_v => to_sfixed (-0.065,2 , -22),
neuron_model_stateCURRENT_none_spiking => neuron_model_stateCURRENT_none_spiking_int,
neuron_model_stateRESTORE_none_spiking => to_sfixed (0.0,18 , -13),
neuron_model_param_none_leak_number => to_sfixed (300.0,18 , -13),
neuron_model_param_voltage_leak_erev => to_sfixed (-0.0543,2 , -22),
neuron_model_stateCURRENT_current_leak_i => neuron_model_stateCURRENT_current_leak_i_int,
neuron_model_stateRESTORE_current_leak_i => to_sfixed (3.21E-11,-28 , -53),
neuron_model_param_conductance_leak_passive_conductance => to_sfixed (1.0E-11,-22 , -53),
neuron_model_stateCURRENT_conductance_leak_passive_g => neuron_model_stateCURRENT_conductance_leak_passive_g_int,
neuron_model_stateRESTORE_conductance_leak_passive_g => to_sfixed (1.0E-11,-22 , -53),
neuron_model_param_none_naChans_number => to_sfixed (120000.0,18 , -13),
neuron_model_param_voltage_naChans_erev => to_sfixed (0.05,2 , -22),
neuron_model_stateCURRENT_current_naChans_i => neuron_model_stateCURRENT_current_naChans_i_int,
neuron_model_stateRESTORE_current_naChans_i => to_sfixed (1.2200572E-11,-28 , -53),
neuron_model_param_conductance_naChans_na_conductance => to_sfixed (1.0E-11,-22 , -53),
neuron_model_stateCURRENT_conductance_naChans_na_g => neuron_model_stateCURRENT_conductance_naChans_na_g_int,
neuron_model_stateRESTORE_conductance_naChans_na_g => to_sfixed (8.8409943E-16,-22 , -53),
neuron_model_param_none_naChans_na_m_instances => to_sfixed (3.0,18 , -13),
neuron_model_stateCURRENT_none_naChans_na_m_q => neuron_model_stateCURRENT_none_naChans_na_m_q_int,
neuron_model_stateRESTORE_none_naChans_na_m_q => to_sfixed (0.052932486,18 , -13),
neuron_model_stateCURRENT_none_naChans_na_m_fcond => neuron_model_stateCURRENT_none_naChans_na_m_fcond_int,
neuron_model_stateRESTORE_none_naChans_na_m_fcond => to_sfixed (1.4830878E-4,18 , -13),
neuron_model_param_per_time_naChans_na_m_forwardRatem1_rate => to_sfixed (1000.0,18 , -2),
neuron_model_param_voltage_naChans_na_m_forwardRatem1_midpoint => to_sfixed (-0.04,2 , -22),
neuron_model_param_voltage_naChans_na_m_forwardRatem1_scale => to_sfixed (0.01,2 , -22),
neuron_model_param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv => to_sfixed (100.0,22 , -2),
neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r => neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r_int,
neuron_model_stateRESTORE_per_time_naChans_na_m_forwardRatem1_r => to_sfixed (223.56372,18 , -2),
neuron_model_param_per_time_naChans_na_m_reverseRatem1_rate => to_sfixed (4000.0,18 , -2),
neuron_model_param_voltage_naChans_na_m_reverseRatem1_midpoint => to_sfixed (-0.065,2 , -22),
neuron_model_param_voltage_naChans_na_m_reverseRatem1_scale => to_sfixed (-0.018,2 , -22),
neuron_model_param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv => to_sfixed (-55.555557,22 , -2),
neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r => neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r_int,
neuron_model_stateRESTORE_per_time_naChans_na_m_reverseRatem1_r => to_sfixed (4000.0,18 , -2),
neuron_model_param_none_naChans_na_h_instances => to_sfixed (1.0,18 , -13),
neuron_model_stateCURRENT_none_naChans_na_h_q => neuron_model_stateCURRENT_none_naChans_na_h_q_int,
neuron_model_stateRESTORE_none_naChans_na_h_q => to_sfixed (0.5961208,18 , -13),
neuron_model_stateCURRENT_none_naChans_na_h_fcond => neuron_model_stateCURRENT_none_naChans_na_h_fcond_int,
neuron_model_stateRESTORE_none_naChans_na_h_fcond => to_sfixed (0.5961208,18 , -13),
neuron_model_param_per_time_naChans_na_h_forwardRateh1_rate => to_sfixed (70.0,18 , -2),
neuron_model_param_voltage_naChans_na_h_forwardRateh1_midpoint => to_sfixed (-0.065,2 , -22),
neuron_model_param_voltage_naChans_na_h_forwardRateh1_scale => to_sfixed (-0.02,2 , -22),
neuron_model_param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv => to_sfixed (-50.0,22 , -2),
neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r => neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r_int,
neuron_model_stateRESTORE_per_time_naChans_na_h_forwardRateh1_r => to_sfixed (70.0,18 , -2),
neuron_model_param_per_time_naChans_na_h_reverseRateh1_rate => to_sfixed (1000.0,18 , -2),
neuron_model_param_voltage_naChans_na_h_reverseRateh1_midpoint => to_sfixed (-0.035,2 , -22),
neuron_model_param_voltage_naChans_na_h_reverseRateh1_scale => to_sfixed (0.01,2 , -22),
neuron_model_param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv => to_sfixed (100.0,22 , -2),
neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r => neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r_int,
neuron_model_stateRESTORE_per_time_naChans_na_h_reverseRateh1_r => to_sfixed (47.425873,18 , -2),
neuron_model_param_none_kChans_number => to_sfixed (36000.0,18 , -13),
neuron_model_param_voltage_kChans_erev => to_sfixed (-0.077,2 , -22),
neuron_model_stateCURRENT_current_kChans_i => neuron_model_stateCURRENT_current_kChans_i_int,
neuron_model_stateRESTORE_current_kChans_i => to_sfixed (-4.3997334E-11,-28 , -53),
neuron_model_param_conductance_kChans_k_conductance => to_sfixed (1.0E-11,-22 , -53),
neuron_model_stateCURRENT_conductance_kChans_k_g => neuron_model_stateCURRENT_conductance_kChans_k_g_int,
neuron_model_stateRESTORE_conductance_kChans_k_g => to_sfixed (1.0184568E-13,-22 , -53),
neuron_model_param_none_kChans_k_n_instances => to_sfixed (4.0,18 , -13),
neuron_model_stateCURRENT_none_kChans_k_n_q => neuron_model_stateCURRENT_none_kChans_k_n_q_int,
neuron_model_stateRESTORE_none_kChans_k_n_q => to_sfixed (0.3176769,18 , -13),
neuron_model_stateCURRENT_none_kChans_k_n_fcond => neuron_model_stateCURRENT_none_kChans_k_n_fcond_int,
neuron_model_stateRESTORE_none_kChans_k_n_fcond => to_sfixed (0.010184568,18 , -13),
neuron_model_param_per_time_kChans_k_n_forwardRaten1_rate => to_sfixed (100.0,18 , -2),
neuron_model_param_voltage_kChans_k_n_forwardRaten1_midpoint => to_sfixed (-0.055,2 , -22),
neuron_model_param_voltage_kChans_k_n_forwardRaten1_scale => to_sfixed (0.01,2 , -22),
neuron_model_param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv => to_sfixed (100.0,22 , -2),
neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r => neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r_int,
neuron_model_stateRESTORE_per_time_kChans_k_n_forwardRaten1_r => to_sfixed (58.19767,18 , -2),
neuron_model_param_per_time_kChans_k_n_reverseRaten1_rate => to_sfixed (125.0,18 , -2),
neuron_model_param_voltage_kChans_k_n_reverseRaten1_midpoint => to_sfixed (-0.065,2 , -22),
neuron_model_param_voltage_kChans_k_n_reverseRaten1_scale => to_sfixed (-0.08,2 , -22),
neuron_model_param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv => to_sfixed (-12.5,22 , -2),
neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r => neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r_int,
neuron_model_stateRESTORE_per_time_kChans_k_n_reverseRaten1_r => to_sfixed (125.0,18 , -2),
neuron_model_param_time_synapsemodel_tauDecay => to_sfixed (0.003,6 , -18),
neuron_model_param_conductance_synapsemodel_gbase => to_sfixed (1.0E-9,-22 , -53),
neuron_model_param_voltage_synapsemodel_erev => to_sfixed (0.0,2 , -22),
neuron_model_param_time_inv_synapsemodel_tauDecay_inv => to_sfixed (333.33334,18 , -6),
neuron_model_stateCURRENT_conductance_synapsemodel_g => neuron_model_stateCURRENT_conductance_synapsemodel_g_int,
neuron_model_stateRESTORE_conductance_synapsemodel_g => to_sfixed (0.0,-22 , -53),
neuron_model_stateCURRENT_current_synapsemodel_i => neuron_model_stateCURRENT_current_synapsemodel_i_int,
neuron_model_stateRESTORE_current_synapsemodel_i => to_sfixed (0.0,-28 , -53),
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
receive_data: process
variable l: line;
variable char : character;
variable s : STD_LOGIC_VECTOR(0 downto 0);
begin
-- wait for Reset to complete
-- wait until init_model='1';
wait until init_model='0';
while not endfile(stimulus) loop
-- read digital data from input file
readline(stimulus, l);
read(l, s);
eventport_in_spike_aggregate(0) <= s(0);
wait until step_once_go = '1';
end loop;
assert false report "end of simulation" severity failure;
end process receive_data;
process
variable L1 : LINE;
begin
write(L1, "SimulationTime " );
write(L1, "neuron_model_spike " );
write(L1, "neuron_model_stateCURRENT_voltage_v" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_spiking" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_current_leak_i" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_conductance_leak_passive_g" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_current_naChans_i" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_conductance_naChans_na_g" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_naChans_na_m_q" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_naChans_na_m_fcond" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_naChans_na_h_q" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_naChans_na_h_fcond" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_current_kChans_i" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_conductance_kChans_k_g" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_kChans_k_n_q" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_kChans_k_n_fcond" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_conductance_synapsemodel_g" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_current_synapsemodel_i" );
write(L1, " ");
writeline(test_out_data, L1); -- write row to output file
Wait;
end process;
clk <= not(clk) after 10 ns;
step_once_go_proc: process
begin
-- wait for Reset to complete
-- wait until init_model='1';
wait until init_model='0';
wait for 180 ns;
while 1 = 1 loop
step_once_go <= '1';
wait for 20 ns;
step_once_go <= '0';
wait until step_once_complete = '1';
wait until step_once_complete = '0';
end loop;
end process step_once_go_proc;
process
begin
wait for 20 ns;
init_model <= '1';
wait for 20 ns;
init_model <= '0';
wait;
end process ;
--
-- Print the results at each clock tick.
--
process(step_once_complete)
variable L1 : LINE;
begin
if (init_model = '1') then
sysparam_time_simtime <= to_sfixed (0.0,6, -22);
else
if (step_once_complete'event and step_once_complete = '1' and init_model = '0') then
sysparam_time_simtime <= resize(sysparam_time_simtime + sysparam_time_timestep,6, -22);
write(L1, real'image(to_real( sysparam_time_simtime ))); -- nth value in row
write(L1, " ");
if ( neuron_model_eventport_out_spike_internal = '1') then
write(L1, "1 " );
else
write(L1, "0 " );
end if;
write(L1, real'image(to_real(neuron_model_stateCURRENT_voltage_v_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_spiking_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_current_leak_i_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_conductance_leak_passive_g_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_current_naChans_i_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_conductance_naChans_na_g_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_naChans_na_m_q_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_naChans_na_m_fcond_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_naChans_na_h_q_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_naChans_na_h_fcond_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_current_kChans_i_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_conductance_kChans_k_g_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_kChans_k_n_q_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_kChans_k_n_fcond_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_conductance_synapsemodel_g_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_current_synapsemodel_i_int)) );
write(L1, " ");
writeline(test_out_data, L1); -- write row to output file
end if;
end if;
end process;
end tb;
| lgpl-3.0 | 83189aed144fbc2246a1decd5e6bde01 | 0.708359 | 2.735739 | false | false | false | false |
riverever/verilogTestSuit | ivltests/vhdl_case_multi.vhd | 1 | 1,387 | -- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for multiple choices in case alternative statements.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_case_multi is
port ( inp: in std_logic_vector (0 to 2);
parity: out std_logic );
end vhdl_case_multi;
architecture vhdl_case_multi_rtl of vhdl_case_multi is
begin
process (inp)
begin
case inp is
when "000"|"011"|"101"|"110" => parity <= "0";
when "001"|"010"|"100"|"111" => parity <= "1";
when others => parity <= "Z";
end case;
end process;
end vhdl_case_multi_rtl;
| gpl-2.0 | 88a792ffbc01f4db158d988b765039a4 | 0.700072 | 3.779292 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/altera/openmac/src/alteraOpenmacTop-rtl-ea.vhd | 2 | 20,879 | -------------------------------------------------------------------------------
--! @file alteraOpenmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Altera
--
--! @details This is the openMAC toplevel for Altera platform.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity alteraOpenmacTop is
generic (
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
csi_mainClk_clock : in std_logic;
--! Main reset used for openMAC, openHUB and openFILTER
rsi_mainRst_reset : in std_logic;
--! DMA master clock
csi_dmaClk_clock : in std_logic;
--! DMA master reset
rsi_dmaRst_reset : in std_logic;
--! Packet buffer clock
csi_pktClk_clock : in std_logic;
--! Packet buffer reset
rsi_pktRst_reset : in std_logic;
--! Twice main clock used for Rmii Tx path
csi_mainClkx2_clock : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC REGISTER chipselect
avs_macReg_chipselect : in std_logic;
--! MM slave MAC REGISTER write
avs_macReg_write : in std_logic;
--! MM slave MAC REGISTER read
avs_macReg_read : in std_logic;
--! MM slave MAC REGISTER waitrequest
avs_macReg_waitrequest : out std_logic;
--! MM slave MAC REGISTER byteenable
avs_macReg_byteenable : in std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
--! MM slave MAC REGISTER address
avs_macReg_address : in std_logic_vector(cMacRegAddrWidth-1 downto 1);
--! MM slave MAC REGISTER writedata
avs_macReg_writedata : in std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MM slave MAC REGISTER readdata
avs_macReg_readdata : out std_logic_vector(cMacRegDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC TIMER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC TIMER chipselect
avs_macTimer_chipselect : in std_logic;
--! MM slave MAC TIMER write
avs_macTimer_write : in std_logic;
--! MM slave MAC TIMER read
avs_macTimer_read : in std_logic;
--! MM slave MAC TIMER waitrequest
avs_macTimer_waitrequest : out std_logic;
--! MM slave MAC TIMER address
avs_macTimer_address : in std_logic_vector(cMacTimerAddrWidth-1 downto 2);
--! MM slave MAC TIMER writedata
avs_macTimer_writedata : in std_logic_vector(cMacTimerDataWidth-1 downto 0);
--! MM slave MAC TIMER readdata
avs_macTimer_readdata : out std_logic_vector(cMacTimerDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC PACKET BUFFER chipselect
avs_pktBuf_chipselect : in std_logic;
--! MM slave MAC PACKET BUFFER write
avs_pktBuf_write : in std_logic;
--! MM slave MAC PACKET BUFFER read
avs_pktBuf_read : in std_logic;
--! MM slave MAC PACKET BUFFER waitrequest
avs_pktBuf_waitrequest : out std_logic;
--! MM slave MAC PACKET BUFFER byteenable
avs_pktBuf_byteenable : in std_logic_vector(cPktBufDataWidth/8-1 downto 0);
--! MM slave MAC PACKET BUFFER address (width given by gPacketBufferLog2Size)
avs_pktBuf_address : in std_logic_vector(gPacketBufferLog2Size-1 downto 2);
--! MM slave MAC PACKET BUFFER writedata
avs_pktBuf_writedata : in std_logic_vector(cPktBufDataWidth-1 downto 0);
--! MM slave MAC PACKET BUFFER readdata
avs_pktBuf_readdata : out std_logic_vector(cPktBufDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! MM master MAC DMA write
avm_dma_write : out std_logic;
--! MM master MAC DMA read
avm_dma_read : out std_logic;
--! MM master MAC DMA waitrequest
avm_dma_waitrequest : in std_logic;
--! MM master MAC DMA readdatavalid
avm_dma_readdatavalid : in std_logic;
--! MM master MAC DMA byteenable
avm_dma_byteenable : out std_logic_vector(gDmaDataWidth/8-1 downto 0);
--! MM master MAC DMA address
avm_dma_address : out std_logic_vector(gDmaAddrWidth-1 downto 0);
--! MM master MAC DMA burstcount
avm_dma_burstcount : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA writedata
avm_dma_writedata : out std_logic_vector(gDmaDataWidth-1 downto 0);
--! MM master MAC DMA readdata
avm_dma_readdata : in std_logic_vector(gDmaDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
ins_timerIrq_irq : out std_logic;
--! MAC interrupt
ins_macIrq_irq : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Rx data valid ports
coe_rmii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
coe_rmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
coe_rmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
coe_rmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
coe_rmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
coe_mii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
coe_mii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
coe_mii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
coe_mii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
coe_mii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
coe_mii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
coe_mii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
coe_smi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
coe_smi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/OI (tri-state buffer)
coe_smi_dio : inout std_logic_vector(gSmiPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
coe_pktActivity : out std_logic;
--! MAC TIMER outputs
coe_macTimerOut : out std_logic_vector(gTimerCount-1 downto 0)
);
end alteraOpenmacTop;
architecture rtl of alteraOpenmacTop is
--! Byte address of macReg
signal macReg_address : std_logic_vector(avs_macReg_address'left downto 0);
--! Byte address of macTimer
signal macTimer_address : std_logic_vector(avs_macTimer_address'left downto 0);
--! Byte address of pktBuf
signal pktBuf_address : std_logic_vector(avs_pktBuf_address'left downto 0);
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
ins_macIrq_irq <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => coe_rmii_txEnable,
oData => coe_rmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => coe_mii_txEnable,
oData => coe_mii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Assign byte addresses.
macReg_address <= avs_macReg_address & "0"; --word to byte
macTimer_address <= avs_macTimer_address & "00"; --dword to byte
pktBuf_address <= avs_pktBuf_address & "00"; --dword to byte
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => coe_rmii_rxDataValid,
iData => coe_rmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => coe_mii_rxDataValid,
iData => coe_mii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO buffers
coe_smi_dio <= smi_data_out when smi_data_outEnable = cActivated else
(others => 'Z');
-- Simply assign the input vector.
smi_data_in <= coe_smi_dio;
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerCount => gTimerCount,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => csi_mainClk_clock,
iRst => rsi_mainRst_reset,
iDmaClk => csi_dmaClk_clock,
iDmaRst => rsi_dmaRst_reset,
iPktBufClk => csi_pktClk_clock,
iPktBufRst => rsi_pktRst_reset,
iClk2x => csi_mainClkx2_clock,
iMacReg_chipselect => avs_macReg_chipselect,
iMacReg_write => avs_macReg_write,
iMacReg_read => avs_macReg_read,
oMacReg_waitrequest => avs_macReg_waitrequest,
iMacReg_byteenable => avs_macReg_byteenable,
iMacReg_address => macReg_address,
iMacReg_writedata => avs_macReg_writedata,
oMacReg_readdata => avs_macReg_readdata,
iMacTimer_chipselect => avs_macTimer_chipselect,
iMacTimer_write => avs_macTimer_write,
iMacTimer_read => avs_macTimer_read,
oMacTimer_waitrequest => avs_macTimer_waitrequest,
iMacTimer_address => macTimer_address,
iMacTimer_writedata => avs_macTimer_writedata,
oMacTimer_readdata => avs_macTimer_readdata,
iPktBuf_chipselect => avs_pktBuf_chipselect,
iPktBuf_write => avs_pktBuf_write,
iPktBuf_read => avs_pktBuf_read,
oPktBuf_waitrequest => avs_pktBuf_waitrequest,
iPktBuf_byteenable => avs_pktBuf_byteenable,
iPktBuf_address => pktBuf_address,
iPktBuf_writedata => avs_pktBuf_writedata,
oPktBuf_readdata => avs_pktBuf_readdata,
oDma_write => avm_dma_write,
oDma_read => avm_dma_read,
iDma_waitrequest => avm_dma_waitrequest,
iDma_readdatavalid => avm_dma_readdatavalid,
oDma_byteenable => avm_dma_byteenable,
oDma_address => avm_dma_address,
oDma_burstcount => avm_dma_burstcount,
oDma_burstcounter => open, --current burst counter state unused
oDma_writedata => avm_dma_writedata,
iDma_readdata => avm_dma_readdata,
oMacTimer_interrupt => ins_timerIrq_irq,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => coe_rmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => coe_mii_rxError,
iMii_RxClk => coe_mii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => coe_mii_txClk,
onPhy_reset => coe_smi_nPhyRst,
oSmi_clk => coe_smi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => coe_pktActivity,
oMacTimer => coe_macTimerOut
);
end rtl;
| gpl-2.0 | e335725f266ead07102793c4fa628a59 | 0.497486 | 5.291181 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/i2c_slave_read_tb.vhd | 1 | 7,010 | -- i2c_slave_tb.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity i2c_slave_read_tb is
end entity;
architecture behavior of i2c_slave_read_tb is
-- Component Declaration for the Unit Under Test (UUT)
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic := '0'; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0) := (others => '0'); -- rx, data received
rx_recv: out std_logic := '0'; -- rx received, high active
busy: out std_logic := '0'; -- busy, high active
sda: inout std_logic := 'Z'; -- serial data of I2C
scl: inout std_logic := 'Z'); -- serial clock of I2C
end component;
constant RSTDEF: std_logic := '0';
--Inputs
signal rst: std_logic := RSTDEF;
signal clk: std_logic := '0';
signal swrst: std_logic := RSTDEF;
signal en: std_logic := '0';
signal tx_data: std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal sda: std_logic := '1';
signal scl: std_logic := '1';
--Outputs
signal tx_sent: std_logic;
signal rx_data: std_logic_vector(7 downto 0);
signal rx_recv: std_logic;
signal busy: std_logic;
-- Clock period definitions
constant clk_period: time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave
generic map(RSTDEF => RSTDEF,
ADDRDEF => "0010111") -- address 0x17
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
tx_data => tx_data,
tx_sent => tx_sent,
rx_data => rx_data,
rx_recv => rx_recv,
busy => busy,
sda => sda,
scl => scl);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- sends a single bit over I2C
procedure send_bit(tosend: std_logic) is
begin
scl <= '0';
sda <= tosend;
-- wait for delay element to take over new value
wait for 25*clk_period;
-- allow slave to read
scl <= '1';
wait for clk_period;
end procedure;
-- receive a single bit over I2C
procedure recv_bit is
begin
scl <= '0';
sda <= 'Z';
wait for clk_period;
scl <= '1';
wait for clk_period;
end procedure;
-- sends start / repeated start condition over I2C
procedure send_start is
begin
send_bit('1');
-- rise sda without changing clk
sda <= '0';
wait for 25*clk_period;
end procedure;
-- sends stop condition over I2C
procedure send_stop is
begin
send_bit('0');
-- rise sda without changing clk
sda <= '1';
wait for 25*clk_period;
end procedure;
-- wait for an ack from slave over I2C
procedure wait_ack is
begin
send_bit('Z');
-- wait additional cycle for slave to release SDA again
scl <= '0';
wait for clk_period;
end procedure;
-- send ack to slave
procedure send_ack is
begin
send_bit('0');
end procedure;
-- send nack to slave
procedure send_nack is
begin
send_bit('1');
end procedure;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= not RSTDEF;
swrst <= not RSTDEF;
en <= '1';
-- init transmission
send_start;
-- send correct address
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('1'); -- direction bit
-- set data which should be transmitted to master
tx_data <= "10011001";
-- receive acknowledge
wait_ack;
-- recv data
-- should match tx_data from above
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
-- send acknowledge of first byte to slave
send_ack;
-- set another byte to send to master
tx_data <= "10100111";
-- recv data
-- should match tx_data from above
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
-- send acknowledge of second byte to slave
send_ack;
-- send repeated start condition
-- with new address
send_start;
-- send wrong address
-- slave should go into idle mode
send_bit('1'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('1'); -- direction bit
-- recv data
-- slave should not send anything
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
-- send nack to slave
send_nack;
-- terminate transmission
send_stop;
wait;
end process;
end;
| mit | bb153d81e1cb63f5866519432ac81f43 | 0.478745 | 4.233092 | false | false | false | false |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_phy_alt_mem_phy_seq.vhd | 1 | 648,298 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_s4_amphy_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr3_s4_amphy_phy_alt_mem_phy_record_pkg;
--
package body ddr3_s4_amphy_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr3_s4_amphy_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
--
package ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg;
--
package body ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 8;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_iram_ram;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr3_s4_amphy_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr3_s4_amphy_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr3_s4_amphy_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_admin;
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_mmi;
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_iram;
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_dgrb;
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_dgwb;
--
use work.ddr3_s4_amphy_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr3_s4_amphy_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr3_s4_amphy_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr3_s4_amphy_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr3_s4_amphy_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr3_s4_amphy_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr3_s4_amphy_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr3_s4_amphy_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr3_s4_amphy_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| lgpl-3.0 | 0572fecf1c93a85b92ced40d587dc217 | 0.441883 | 4.418185 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/bigfile.vhd | 1 | 20,863 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
-- CONNECTIVITY DEFINITION
entity bigfile is
port (
-- from external pins
sysclk : in std_logic;
g_zaq_in : in std_logic_vector(31 downto 0);
g_aux : in std_logic_vector(31 downto 0);
scanb : in std_logic;
g_wrb : in std_logic;
g_rdb : in std_logic;
g_noop_clr : in std_logic_vector(31 downto 0);
swe_ed : in std_logic;
swe_lv : in std_logic;
din : in std_logic_vector(63 downto 0);
g_dout_w0x0f : in std_logic_vector(4 downto 0);
n9_bit_write : in std_logic;
-- from reset_gen block
reset : in std_logic;
alu_u : in std_logic_vector(31 downto 0);
debct_ping : in std_logic;
g_sys_in : out std_logic_vector(31 downto 0);
g_zaq_in_rst_hold : out std_logic_vector(31 downto 0);
g_zaq_hhh_enb : out std_logic_vector(31 downto 0);
g_zaq_out : out std_logic_vector(31 downto 0);
g_dout : out std_logic_vector(31 downto 0);
g_zaq_ctl : out std_logic_vector(31 downto 0);
g_zaq_qaz_hb : out std_logic_vector(31 downto 0);
g_zaq_qaz_lb : out std_logic_vector(31 downto 0);
gwerth : out std_logic_vector(31 downto 0);
g_noop : out std_logic_vector(31 downto 0);
g_vector : out std_logic_vector(8*32-1 downto 0);
swe_qaz1 : out std_logic_vector(31 downto 0)
);
end bigfile;
-- IMPLEMENTATION
architecture rtl of bigfile is
-- constants
constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000";
constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001";
constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010";
constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011";
constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100";
constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101";
constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110";
constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111";
constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000";
constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001";
constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010";
constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011";
constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100";
constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101";
constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110";
constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111";
constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000";
constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001";
constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010";
constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011";
constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100";
constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101";
constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110";
constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111";
-- comment
signal g_t_klim_dout : std_logic_vector(31 downto 0);
signal g_t_u_dout : std_logic_vector(31 downto 0);
signal g_t_l_dout : std_logic_vector(31 downto 0);
signal g_t_hhh_l_dout : std_logic_vector(31 downto 0);
signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0);
signal g_secondary_t_l_dout : std_logic_vector(31 downto 0);
signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used
signal g_e_z_dout : std_logic_vector(31 downto 0);
signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0);
signal g_style_vfr_dout : std_logic_vector(31 downto 0);
signal g_style_klim_dout : std_logic_vector(31 downto 0);
signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0);
signal g_style_t_y_dout : std_logic_vector(31 downto 0);
signal g_n_l_dout : std_logic_vector(31 downto 0);
signal g_n_vfr_dout : std_logic_vector(31 downto 0);
signal g_e_n_r_dout : std_logic_vector(31 downto 0);
signal g_n_r_bne_dout : std_logic;
signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0);
signal g_alu_l_dout : std_logic_vector(31 downto 0);
signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0);
signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0);
signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0);
signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0);
signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0);
-- other
signal q_g_zaq_in : std_logic_vector(31 downto 0);
signal q2_g_zaq_in : std_logic_vector(31 downto 0);
signal q3_g_zaq_in : std_logic_vector(31 downto 0);
signal q_g_zaq_in_cd : std_logic_vector(3 downto 0);
signal q_g_style_vfr_dout : std_logic_vector(31 downto 0);
signal q_g_unzq : std_logic_vector(3 downto 0);
-- i
signal g_n_active : std_logic_vector(31 downto 0);
-- inter
signal g_zaq_in_y : std_logic_vector(31 downto 0);
signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0);
signal g_zaq_out_i : std_logic_vector(31 downto 0);
signal g_zaq_ctl_i : std_logic_vector(31 downto 0);
signal g_sys_in_i : std_logic_vector(31 downto 0);
signal g_sys_in_ii : std_logic_vector(31 downto 0);
signal g_dout_i : std_logic_vector(31 downto 0);
begin
-- qaz out
g_zaq_out_i <=
-- if secondary
(g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or
-- if alu
(g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or
-- otherwise
(not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout);
-- Changed
g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout;
-- qaz
-- JLB
g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or
(g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i));
-- mux
--vnavigatoroff
g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000";
--vnavigatoron
g_zaq_hhh_enb <= not(g_t_hhh_l_dout);
g_zaq_qaz_hb <= g_t_qaz_mult_high_dout;
g_zaq_qaz_lb <= g_t_qaz_mult_low_dout;
-- Dout
g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else
g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else
g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else
g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else
g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else
g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else
("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else
g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else
g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else
g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else
g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else
g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else
g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else
g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else
g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else
g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else
("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else
g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else
g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else
g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else
g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else
gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else
g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else
gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else
"00000000000000000000000000000000";
g_dout <= g_dout_i when g_rdb = '0' else (others => '1');
-- this can be used to use zzz1
g_style_main_reset_hold_dout_proc :
process(sysclk)
begin
if( sysclk'event and sysclk = '1' ) then
if( scanb = '1' ) then
if( reset = '1' ) then
g_style_main_reset_hold_dout <= g_zaq_in;
end if;
--vnavigatoroff
else
g_style_main_reset_hold_dout <= q2_g_zaq_in;
end if;
--vnavigatoron
end if;
end process;
-- qaz
g_zaq_in_rst_hold <= g_style_main_reset_hold_dout;
-- Din
g_doutister_proc :
process(reset, sysclk)
variable g_dout_w0x0f_v : std_logic_vector(4 downto 0);
begin
if( reset /= '0' ) then
g_t_klim_dout <= (others => '0');
g_t_u_dout <= (others => '0');
g_t_l_dout <= (others => '0');
g_t_hhh_l_dout <= (others => '0');
g_t_jkl_sink_l_dout <= (others => '0');
g_secondary_t_l_dout <= (others => '0');
g_style_c_l_dout <= (others => '0');
g_e_z_dout <= (others => '0');
g_n_both_qbars_l_dout <= (others => '0');
g_style_klim_dout <= (others => '0');
g_style_t_y_dout <= (others => '0');
g_n_l_dout <= (others => '0');
g_e_n_r_dout <= (others => '0');
g_n_r_bne_dout <= '0';
g_n_div_rebeq_dout <= (others => '1');
g_alu_l_dout <= (others => '0');
g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low
g_t_qaz_mult_high_dout <= (others => '0');
gwerthernal_style_u_dout <= (others => '0');
gwerthernal_style_l_dout <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
-- clear
g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr;
if( g_wrb = '0' ) then
-- because we now...
for i in 0 to 1 loop
if( i = 0 ) then
g_dout_w0x0f_v := g_dout_w0x0f;
elsif( i = 1 ) then
if( n9_bit_write = '1' ) then
-- set
g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
else
exit;
end if;
--vnavigatoroff
else
-- not possible but added for code coverage's sake
end if;
--vnavigatoron
case g_dout_w0x0f_v is
when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32);
when g_t_u_w0x0f =>
-- output klim
for j in 0 to 31 loop
if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then
g_t_u_dout(j) <= din(32*i+j);
end if;
end loop;
when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32);
when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32);
when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32);
when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32);
when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32);
when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32);
when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32);
when g_style_vfr_w0x0f => null; -- read-only register
when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32);
when g_unklimed_style_vfr_w0x0f => null; -- read-only register
when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32);
when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32);
when g_n_vfr_w0x0f => null; -- writes
when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32);
when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32);
when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or
g_n_div_rebeq_dout; -- a '1' writes
when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32);
when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32);
when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32);
when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32);
when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32);
--vnavigatoroff
when others => null;
--vnavigatoron
end case;
end loop;
end if;
end if;
end process;
-- sample
g_zaq_in_sample_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_zaq_in <= (others => '0');
q2_g_zaq_in <= (others => '0');
q3_g_zaq_in <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
q_g_zaq_in <= g_zaq_in;
q2_g_zaq_in <= q_g_zaq_in;
q3_g_zaq_in <= g_zaq_in_y;
end if;
end process;
-- vfr register
g_unklimed_style_vfr_dout <= q2_g_zaq_in;
-- switch
g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in;
-- qaz
g_style_vfr_dout <= -- top 2
(g_zaq_in_y(31 downto 4) &
-- FSM
(( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
-- otherwise just use
(not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0))));
-- in scan mode
g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1'
--vnavigatoroff
else g_style_t_y_dout;
--vnavigatoron
g_sys_in_i <= (-- top 28
(g_zaq_in_y_no_dout(31 downto 4) &
-- is enabled
(( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
-- otherwise just use
(not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0)))));
g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout );
g_sys_in <= g_sys_in_ii;
lpq_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_zaq_in_cd <= (others => '0');
q_g_unzq <= (others => '1');
elsif( sysclk'event and sysclk = '1' ) then
-- sample
if( debct_ping = '1') then
-- taken
for i in 0 to 3 loop
if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
q_g_unzq(i) <= '1';
else
if( q_g_unzq(i) = '0' ) then
q_g_zaq_in_cd(i) <= g_zaq_in_y(i);
else
q_g_unzq(i) <= '0';
end if;
end if;
end loop;
else
for i in 0 to 3 loop
if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
q_g_unzq(i) <= '1';
end if;
end loop;
end if;
end if;
end process;
-- generate lqqs
sample_forwerth_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_style_vfr_dout <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
if( scanb = '1' ) then
q_g_style_vfr_dout <= g_style_vfr_dout;
--vnavigatoroff
else
-- in scan
q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii;
end if;
--vnavigatoron
end if;
end process;
-- generate
g_n_active <= -- 1 to 0
(((q_g_style_vfr_dout and not g_style_vfr_dout) or
-- get this
(not q_g_style_vfr_dout and g_style_vfr_dout and
g_n_both_qbars_l_dout))) and
-- must be
g_n_l_dout;
-- check for lqq active and set lqq vfr register
-- also clear
n_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
g_n_vfr_dout <= (others => '0');
gwerth <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
for i in 0 to 31 loop
-- lqq
-- vfr matches
if( g_n_active(i) = '1' ) then
gwerth(i) <= '1';
if( g_e_z_dout(i) = '1' ) then
-- lqq
g_n_vfr_dout(i) <= '1';
else
g_n_vfr_dout(i) <= q_g_style_vfr_dout(i);
end if;
else
-- clear
if( g_e_z_dout(i) = '0' ) then
g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign
-- in both
if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then
gwerth(i) <= '0';
end if;
else
-- write
if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then
gwerth(i) <= '0';
g_n_vfr_dout(i) <= '0';
end if;
end if;
end if;
end loop;
end if;
end process;
----
-- Create the Lqq
createwerth_vec_proc :
process( g_n_r_bne_dout, g_e_n_r_dout)
variable imod8, idiv8 : integer;
begin
for i in 0 to 31 loop
imod8 := i mod 8;
idiv8 := i / 8;
if( g_n_r_bne_dout = '0' ) then
-- non-unique
g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
else
-- unique
if( imod8 = 0 ) then
g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
else
g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) +
to_unsigned(imod8, 8));
end if;
end if;
end loop;
end process;
----
-- Qaz
g_noop <= g_n_div_rebeq_dout;
create_g_ack_bne_proc :
process( swe_ed,swe_lv,g_e_z_dout)
begin
for i in 0 to 31 loop
if( g_e_z_dout(i) = '1') then
swe_qaz1(i) <= swe_ed;
else
swe_qaz1(i) <= swe_lv;
end if;
end loop;
end process;
end rtl;
| apache-2.0 | 449b86a9e288570b540e9d0dbada309a | 0.496669 | 2.887213 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openmac-rtl-ea.vhd | 2 | 69,417 | -------------------------------------------------------------------------------
--! @file openmac-rtl-ea.vhd
--
--! @brief openMAC core
--
--! @details This is the openMAC core file implementing the MAC functionality.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2009
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
--! use global library
use work.global.all;
entity openmac is
generic (
--! Dma address high bit
gDmaHighAddr : in integer := 16;
--! Enable MAC timer
gTimerEnable : in boolean := false;
--! Enable Timer triggered Tx
gTimerTrigTx : in boolean := false;
--! Enable Auto-response delay
gAutoTxDel : in boolean := false
);
port (
--! Reset
iRst : in std_logic;
--! Clock (RMII, 50 MHz)
iClk : in std_logic;
--! Write to RAM or content (low-active)
inWrite : in std_logic;
--! Select RAM (descriptor and Rx filter)
iSelectRam : in std_logic;
--! Select content (Tx/Rx status/control registers)
iSelectCont : in std_logic;
--! Byteenable (low-active)
inByteenable : in std_logic_vector(1 downto 0);
--! Address for RAM or content
iAddress : in std_logic_vector(10 downto 1);
--! Writedata to RAM or content
iWritedata : in std_logic_vector(15 downto 0);
--! Readdata from RAM or content
oReaddata : out std_logic_vector(15 downto 0);
--! Tx interrupt request (low-active)
onTxIrq : out std_logic;
--! Rx interrupt request (low-active)
onRxIrq : out std_logic;
--! Tx begin interrupt request (low-active)
onTxBegIrq : out std_logic;
--! DMA read transfer for frame done
oDmaReadDone : out std_logic;
--! DMA write transfer for frame done
oDmaWriteDone : out std_logic;
--! DMA request strobe
oDmaReq : out std_logic;
--! DMA write strobe (low-active)
onDmaWrite : out std_logic;
--! DMA acknowledge input
iDmaAck : in std_logic;
--! DMA request overflow flag
oDmaReqOverflow : out std_logic;
--! DMA read request length
oDmaReadLength : out std_logic_vector(11 downto 0);
--! DMA address
oDmaAddress : out std_logic_vector(gDmaHighAddr downto 1);
--! DMA writedata
oDmaWritedata : out std_logic_vector(15 downto 0);
--! DMA readdata
iDmaReaddata : in std_logic_vector(15 downto 0);
--! RMII Rx data
iRxData : in std_logic_vector(1 downto 0);
--! RMII Rx data valid
iRxDv : in std_logic;
--! RMII Tx data
oTxData : out std_logic_vector(1 downto 0);
--! RMII Tx enable
oTxEn : out std_logic;
--! Hub Rx port (connect to openHUB)
iHubRxPort : in std_logic_vector(1 downto 0);
--! MAC Time
oMacTime : out std_logic_vector(31 downto 0)
);
end entity openmac;
architecture struct OF openmac is
signal Rx_Dv : std_logic;
signal R_Req : std_logic;
signal Auto_Desc : std_logic_vector( 3 downto 0);
signal Zeit : std_logic_vector(31 downto 0);
signal Tx_Dma_Req : std_logic;
signal Rx_Dma_Req : std_logic;
signal Tx_Dma_Ack : std_logic;
signal Rx_Dma_Ack : std_logic;
signal Tx_Ram_Dat : std_logic_vector(15 downto 0);
signal Rx_Ram_Dat : std_logic_vector(15 downto 0);
signal Tx_Dma_Len : std_logic_vector(11 downto 0);
signal Tx_Reg : std_logic_vector(15 downto 0);
signal Rx_Reg : std_logic_vector(15 downto 0);
signal Dma_Tx_Addr : std_logic_vector(oDmaAddress'range);
signal Dma_Rx_Addr : std_logic_vector(oDmaAddress'range);
signal Dma_Req_s : std_logic;
signal Dma_Rw_s : std_logic;
signal halfDuplex : std_logic; -- cActivated ... MAC in half-duplex mode
signal Tx_Active : std_logic; -- cActivated ... TX = Data or CRC
signal Tx_Dma_Very1stOverflow : std_logic; -- cActivated ... very first TX DMA overflow
signal Tx_Col : std_logic;
signal Sel_Tx_Ram : std_logic;
signal Sel_Tx_Reg : std_logic;
signal Tx_LatchH : std_logic_vector(7 downto 0);
signal Tx_LatchL : std_logic_vector(7 downto 0);
begin
oReaddata <= Tx_Ram_Dat when iSelectRam = '1' and Sel_Tx_Ram = '1' else
Rx_Ram_Dat when iSelectRam = '1' else
Tx_Reg when iSelectCont = '1' and Sel_Tx_Reg = '1' else
Rx_Reg;
oMacTime <= Zeit;
oDmaReadLength <= Tx_Dma_Len + 4;
b_DmaObserver : block
signal dmaObserverCounter, dmaObserverCounterNext : std_logic_vector(2 downto 0);
constant cDmaObserverCounterHalf : std_logic_vector(dmaObserverCounter'range) := "110"; --every 8th cycle
constant cDmaObserverCounterFull : std_logic_vector(dmaObserverCounter'range) := "010"; --every 4th cycle
begin
process(iClk, iRst)
begin
if iRst = '1' then
dmaObserverCounter <= (others => cInactivated);
elsif rising_edge(iClk) then
dmaObserverCounter <= dmaObserverCounterNext;
end if;
end process;
oDmaReqOverflow <= --very first TX Dma transfer
Dma_Req_s when Tx_Dma_Very1stOverflow = cActivated and Tx_Active = cInactivated else
--RX Dma transfers and TX Dma transfers without the very first
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterHalf and halfDuplex = cActivated else
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterFull and halfDuplex = cInactivated else
cInactivated;
dmaObserverCounterNext <= --increment counter if DMA Read req (TX) during data and crc
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cActivated
and Tx_Active = cActivated else
--increment counter if DMA Write req (RX)
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cInactivated else
(others => cInactivated); --reset DmaObserverCounter if no oDmaReq
end block;
b_Dma: block
signal Rx_Dma : std_logic;
signal Tx_Dma : std_logic;
begin
oDmaReq <= Dma_Req_s;
Dma_Req_s <= '1' when (Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Rx_Dma_Req = '1' else '0';
onDmaWrite <= Dma_Rw_s;
Dma_Rw_s <= '1' when (Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Tx_Dma = '1' else '0';
oDmaAddress <= Dma_Tx_Addr when (Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Tx_Dma = '1' else Dma_Rx_Addr;
Rx_Dma_Ack <= '1' when Rx_Dma = '1' and iDmaAck = '1' else '0';
pDmaArb: process( iClk, iRst ) is
begin
if iRst = '1' then
Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0';
Tx_LatchH <= (others => '0'); Tx_LatchL <= (others => '0');
Zeit <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerEnable then
Zeit <= Zeit + 1;
end if;
Sel_Tx_Ram <= iAddress(8);
Sel_Tx_Reg <= not iAddress(3);
if iDmaAck = '0' then
if Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0' then Tx_Dma <= '1';
elsif Tx_Dma = '0' and Rx_Dma_Req = '1' then Rx_Dma <= '1';
end if;
else
if Rx_Dma = '1' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0' then Tx_Dma <= '1'; Rx_Dma <= '0';
elsif Tx_Dma = '1' and Rx_Dma_Req = '1' then Tx_Dma <= '0'; Rx_Dma <= '1';
else Tx_Dma <= '0'; Rx_Dma <= '0';
end if;
end if;
if Tx_Dma = '1' and iDmaAck = '1' then Tx_Dma_Ack <= '1';
else Tx_Dma_Ack <= '0';
end if;
if Tx_Dma_Ack = '1' then Tx_LatchL <= iDmaReaddata(15 downto 8);
Tx_LatchH <= iDmaReaddata( 7 downto 0);
end if;
end if;
end process pDmaArb;
end block b_Dma;
b_Full_Tx : block
type tTxState is (
sIdle,
sBop,
sPre,
sTxd,
sCrc,
sCol,
sJam
);
signal Sm_Tx : tTxState;
signal Start_Tx : std_logic;
signal ClrCol : std_logic;
signal Tx_On : std_logic;
signal Dibl_Cnt : std_logic_vector(1 downto 0);
signal F_End : std_logic;
signal Was_Col : std_logic;
signal Block_Col : std_logic;
signal Ipg_Cnt : std_logic_vector(7 downto 0);
signal Tx_Timer : std_logic_vector(7 downto 0);
alias Ipg : std_logic is Ipg_Cnt(7);
alias Tx_Time : std_logic is Tx_Timer(7);
signal Tx_Ipg : std_logic_vector(5 downto 0);
signal Tx_Count : std_logic_vector(11 downto 0);
signal Tx_En : std_logic;
signal F_Val : std_logic;
signal Tx_Half : std_logic;
signal Tx_Sr : std_logic_vector(7 downto 0);
signal F_TxB : std_logic_vector(7 downto 0);
signal Crc : std_logic_vector(31 downto 0);
signal CrcDin : std_logic_vector(1 downto 0);
signal Tx_Dat : std_logic_vector(1 downto 0);
signal Col_Cnt : std_logic_vector(3 downto 0);
signal Auto_Coll : std_logic;
signal Rnd_Num : std_logic_vector(9 downto 0);
signal Retry_Cnt : std_logic_vector(9 downto 0);
signal Max_Retry : std_logic_vector(3 downto 0);
begin
oTxEn <= Tx_En;
oTxData <= Tx_Dat;
halfDuplex <= Tx_Half;
Tx_Active <= cActivated when Sm_Tx = sTxd or Sm_Tx = sCrc else cInactivated;
pTxSm: process ( iClk, iRst ) is
begin
if iRst = '1' then
Sm_Tx <= sIdle;
elsif rising_edge( iClk ) then
if Sm_Tx = sIdle or Sm_Tx = sBop or Dibl_Cnt = "11" then
case Sm_Tx is
when sIdle => if Start_Tx = '1'
and (Tx_Half = '0' or Rx_Dv = '0')
and Ipg = '0' then Sm_Tx <= sBop; end if;
when sBop => Sm_Tx <= sPre;
when sPre => if Tx_Time = '1' then Sm_Tx <= sTxd; end if;
when sTxd => if Was_Col = '1' then Sm_Tx <= sCol;
elsif Tx_Count = 0 then Sm_Tx <= sCrc; end if;
when sCol => Sm_Tx <= sJam;
when sJam => if Tx_Time = '1' then Sm_Tx <= sIdle;
end if;
when sCrc => if Was_Col = '1' then Sm_Tx <= sCol;
elsif Tx_Time = '1' then Sm_Tx <= sIdle; end if;
when others => NULL;
end case;
end if;
end if;
end process pTxSm;
pTxCtl: process ( iClk, iRst ) is
variable vPreload : std_logic_vector(Tx_Timer'range);
variable vLoad : std_logic;
begin
if iRst = '1' then
Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0';
Ipg_Cnt <= (others => '0'); Tx_Timer <= (others => '0'); Tx_Sr <= (others => '0');
elsif rising_edge( iClk ) then
if Sm_Tx = sBop then Dibl_Cnt <= "00";
else Dibl_Cnt <= Dibl_Cnt + 1;
end if;
if Tx_En = '1' then Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7);
elsif Rx_Dv = '1' and Tx_Half = '1' then Ipg_Cnt <= "10" & Tx_Ipg;
elsif Ipg = '1' then Ipg_Cnt <= Ipg_Cnt - 1;
end if;
if Dibl_Cnt = "11" and Sm_Tx = sCrc and Tx_Time = '1' then F_End <= '1';
elsif Dibl_Cnt = "11" and Sm_Tx = sCol then
if Col_Cnt = (Max_Retry - 1) then F_End <= '1';
elsif Col_Cnt < x"E" then Tx_Col <= '1';
else F_End <= '1';
end if;
else F_End <= '0';
Tx_Col <= '0';
end if;
if Tx_Half = '1' and Rx_Dv = '1'
and (Sm_Tx = sPre or Sm_Tx = sTxd) then Was_Col <= '1';
elsif Sm_Tx = sCol then Was_Col <= '0';
end if;
if Sm_Tx = sCol then Block_Col <= '1';
elsif Auto_Coll = '1' then Block_Col <= '0';
elsif Retry_Cnt = 0 then Block_Col <= '0';
end if;
if Dibl_Cnt = "10" and Sm_Tx = sPre and Tx_Time = '1' then F_Val <= '1';
elsif Dibl_Cnt = "10" and Sm_Tx = sTxd then F_Val <= '1';
else F_Val <= '0';
end if;
vLoad := '0';
if Sm_Tx = sBop then vPreload := x"06"; vLoad := '1';
elsif Sm_Tx = sTxd then vPreload := x"02"; vLoad := '1';
elsif Sm_Tx = sCol then vPreload := x"01"; vLoad := '1';
elsif Tx_Time = '1' then vPreload := x"3e"; vLoad := '1';
end if;
if Dibl_Cnt = "11" or Sm_Tx = sBop then
if vLoad = '1' then Tx_Timer <= vPreload;
else Tx_Timer <= Tx_Timer - 1;
end if;
end if;
if F_Val = '1' then Tx_Sr <= F_TxB;
else Tx_Sr <= "00" & Tx_Sr(7 downto 2);
end if;
if Sm_Tx = sPre then Tx_En <= '1';
elsif Sm_Tx = sIdle or (Sm_Tx = sJam and Tx_Time = '1') then Tx_En <= '0';
end if;
if Sm_Tx = sPre and Tx_Time = '1' and Dibl_Cnt = "11" then Tx_Dat <= "11";
elsif Sm_Tx = sPre then Tx_Dat <= "01";
elsif Sm_Tx = sTxd then Tx_Dat <= CrcDin;
elsif Sm_Tx = sCrc then Tx_Dat <= not Crc(30) & not Crc(31);
elsif Sm_Tx = sCol or Sm_Tx = sJam then Tx_Dat <= "11";
else Tx_Dat <= "00";
end if;
end if;
end process pTxCtl;
pBackDel: process ( iClk, iRst ) is
begin
if iRst = '1' then
Rnd_Num <= (others => '0');
Col_Cnt <= (others => '0');
Retry_Cnt <= (others => '0');
elsif rising_edge( iClk ) then
Rnd_Num <= Rnd_Num(8 downto 0) & (Rnd_Num(9) xor not Rnd_Num(2));
if ClrCol = '1' then Col_Cnt <= x"0";
elsif Dibl_Cnt = "11" and Sm_Tx = sCol then Col_Cnt <= Col_Cnt + 1;
end if;
if Dibl_Cnt = "11" then
if Tx_On = '0' or Auto_Coll = '1' then Retry_Cnt <= (others => '0');
elsif Sm_Tx = sCol then
for i in 0 to 9 loop
if Col_Cnt >= i then Retry_Cnt(i) <= Rnd_Num(i);
else Retry_Cnt(i) <= '0';
end if;
end loop;
elsif Sm_Tx /= sJam and Tx_Time = '1' and Retry_Cnt /= 0 then Retry_Cnt <= Retry_Cnt - 1;
end if;
end if;
end if;
end process pBackDel;
CrcDin <= Tx_Sr(1 downto 0);
Calc: process ( iClk, Crc, CrcDin, Sm_Tx ) is
variable H : std_logic_vector(1 downto 0);
begin
H(0) := Crc(31) xor CrcDin(0);
H(1) := Crc(30) xor CrcDin(1);
if rising_edge( iClk ) then
if Sm_Tx = sPre then Crc <= x"FFFFFFFF";
elsif Sm_Tx = sCrc then Crc <= Crc(29 downto 0) & "00";
else
Crc( 0) <= H(1);
Crc( 1) <= H(0) xor H(1);
Crc( 2) <= Crc( 0) xor H(0) xor H(1);
Crc( 3) <= Crc( 1) xor H(0) ;
Crc( 4) <= Crc( 2) xor H(1);
Crc( 5) <= Crc( 3) xor H(0) xor H(1);
Crc( 6) <= Crc( 4) xor H(0) ;
Crc( 7) <= Crc( 5) xor H(1);
Crc( 8) <= Crc( 6) xor H(0) xor H(1);
Crc( 9) <= Crc( 7) xor H(0) ;
Crc(10) <= Crc( 8) xor H(1);
Crc(11) <= Crc( 9) xor H(0) xor H(1);
Crc(12) <= Crc(10) xor H(0) xor H(1);
Crc(13) <= Crc(11) xor H(0) ;
Crc(14) <= Crc(12) ;
Crc(15) <= Crc(13) ;
Crc(16) <= Crc(14) xor H(1);
Crc(17) <= Crc(15) xor H(0) ;
Crc(18) <= Crc(16) ;
Crc(19) <= Crc(17) ;
Crc(20) <= Crc(18) ;
Crc(21) <= Crc(19) ;
Crc(22) <= Crc(20) xor H(1);
Crc(23) <= Crc(21) xor H(0) xor H(1);
Crc(24) <= Crc(22) xor H(0) ;
Crc(25) <= Crc(23) ;
Crc(26) <= Crc(24) xor H(1);
Crc(27) <= Crc(25) xor H(0) ;
Crc(28) <= Crc(26) ;
Crc(29) <= Crc(27) ;
Crc(30) <= Crc(28) ;
Crc(31) <= Crc(29) ;
end if;
end if;
end process Calc;
bTxDesc: block
type tDescState is (
sIdle,
sLen,
sTimL,
sTimH,
sAdrH,
sAdrL,
sReq,
sBegL,
sBegH,
sDel,
sData,
sStat,
sColl
);
signal Dsm : tDescState;
signal Tx_Dsm_Next : tDescState;
signal DescRam_Out : std_logic_vector(15 downto 0);
signal DescRam_In : std_logic_vector(15 downto 0);
alias TX_LEN : std_logic_vector(11 downto 0) is DescRam_Out(11 downto 0);
alias TX_OWN : std_logic is DescRam_Out(8);
alias TX_LAST : std_logic is DescRam_Out(9);
alias TX_READY : std_logic is DescRam_Out(10);
alias TX_BEGDEL : std_logic is DescRam_Out(12);
alias TX_BEGON : std_logic is DescRam_Out(13);
alias TX_TIME : std_logic is DescRam_Out(14);
alias TX_RETRY : std_logic_vector( 3 downto 0) is DescRam_Out(3 downto 0);
signal Ram_Be : std_logic_vector( 1 downto 0);
signal Ram_Wr : std_logic;
signal Desc_We : std_logic;
signal Desc_Addr : std_logic_vector( 7 downto 0);
signal DescIdx : std_logic_vector( 2 downto 0);
signal Last_Desc : std_logic;
signal ZeitL : std_logic_vector(15 downto 0);
signal Tx_Ie : std_logic;
signal Tx_Wait : std_logic;
signal Tx_BegInt : std_logic;
signal Tx_BegSet : std_logic;
signal Tx_Early : std_logic;
signal Tx_Del : std_logic;
signal Ext_Tx : std_logic;
signal Ext_Ack : std_logic;
signal Tx_Desc : std_logic_vector( 3 downto 0);
signal Tx_Desc_One : std_logic_vector( 3 downto 0);
signal Ext_Desc : std_logic_vector( 3 downto 0);
signal Tx_Icnt : std_logic_vector( 4 downto 0);
signal Tx_SoftInt : std_logic;
signal Sel_TxH : std_logic;
signal Sel_TxL : std_logic;
signal H_Byte : std_logic;
signal Tx_Buf : std_logic_vector( 7 downto 0);
signal Tx_Idle : std_logic;
signal TxInt : std_logic;
signal Tx_Beg : std_logic;
signal Tx_Sync : std_logic;
signal Tx_Ident : std_logic_vector( 1 downto 0);
signal Tx_Cmp_High : std_logic_vector(15 downto 0);
signal Start_TxS : std_logic;
signal Tx_Dma_Out : std_logic;
signal Tx_Del_Cnt : std_logic_vector(32 downto 0);
alias Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high);
signal Tx_Del_Run : std_logic;
signal Tx_Done : std_logic;
begin
oDmaReadDone <= Tx_Done;
Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0';
Tx_Dma_Very1stOverflow <= cActivated when Dibl_Cnt = "01" and Sm_Tx = sPre and Tx_Timer(7) = '1' else cInactivated;
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '1' else '0';
Ram_Be(1) <= '1' when inWrite = '1' or inByteenable(1) = '0' else '0';
Ram_Be(0) <= '1' when inWrite = '1' or inByteenable(0) = '0' else '0';
DescIdx <= "000" when Desc_We = '0' and Tx_Dsm_Next = sIdle else
"000" when Desc_We = '1' and Dsm = sIdle else
"001" when Desc_We = '0' and Tx_Dsm_Next = sLen else
"001" when Desc_We = '1' and Dsm = sLen else
"010" when Desc_We = '0' and Tx_Dsm_Next = sAdrH else
"010" when Desc_We = '1' and Dsm = sAdrH else
"011" when Desc_We = '0' and Tx_Dsm_Next = sAdrL else
"011" when Desc_We = '1' and Dsm = sAdrL else
"100" when Desc_We = '0' and Tx_Dsm_Next = sBegH else
"100" when Desc_We = '1' and Dsm = sBegH else
"101" when Desc_We = '0' and Tx_Dsm_Next = sBegL else
"101" when Desc_We = '1' and Dsm = sBegL else
"110" when Desc_We = '0' and Tx_Dsm_Next = sTimH else
"110" when Desc_We = '1' and Dsm = sTimH else
"111" when Desc_We = '0' and Tx_Dsm_Next = sTimL else
"111" when Desc_We = '1' and Dsm = sTimL else
"111" when Desc_We = '0' and Tx_Dsm_Next = sData else
"111" when Desc_We = '1' and Dsm = sData else
"000";
Desc_We <= '1' when Dsm = sTimL or Dsm = sTimH or Dsm = sStat else '0';
Desc_Addr <= '1' & Tx_Desc & DescIdx when Ext_Tx = '0' else
'1' & Ext_Desc & DescIdx;
gTxTime: if gTimerEnable generate
DescRam_In <= Zeit(15 downto 0) when Dsm = sTimH else
ZeitL when Dsm = sTimL else
x"000" & "01" & Tx_Ident when Dsm = sBegL else
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
end generate;
gnTxTime: if not gTimerEnable generate
DescRam_In <= x"000" & "01" & Tx_Ident when Dsm = sBegL else
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
end generate;
--! This DPRAM holds the Tx descriptor accessible by the host and the DMA.
TXRAM : entity work.dpRam
generic map (
gWordWidth => iWritedata'length,
gNumberOfWords => 256,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => iAddress(8 downto 1),
iByteenable_A => Ram_Be,
iWritedata_A => iWritedata,
oReaddata_A => Tx_Ram_Dat,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => Desc_We,
iByteenable_B => (others => cActivated),
iAddress_B => Desc_Addr,
iWritedata_B => DescRam_In,
oReaddata_B => DescRam_Out
);
assert not( gTimerTrigTx and not gTimerEnable )
report "Time Triggered Tx needs Timer!"
severity failure;
pTxSm: process( Dsm,
Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait,
Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg, Tx_Half, Tx_Del_End,
iRxDv )
begin
Tx_Dsm_Next <= Dsm;
case Dsm is
when sIdle => if Tx_On = '1' and TX_OWN = '1' and Retry_Cnt = 0 then
if (Ext_Tx = '1' and Ext_Ack = '0') or Tx_Wait = '0' then
Tx_Dsm_Next <= sAdrH; --sLen;
end if;
end if;
when sLen => if Tx_Sync = '0' then Tx_Dsm_Next <= sReq; --sAdrH;
else Tx_Dsm_Next <= sBegH;
end if;
when sBegH => Tx_Dsm_Next <= sBegL;
when sBegL => if Tx_On = '0' then Tx_Dsm_Next <= sIdle;
elsif Tx_Sync = '0' then
if Tx_Del = '1' then Tx_Dsm_Next <= sDel;
elsif Sm_Tx = sPre then
Tx_Dsm_Next <= sTimH;
end if;
elsif Tx_Sync = '1' and Tx_Beg = '1' and Tx_Half = '1' and iRxDv = '1' then
Tx_Dsm_Next <= sColl;
elsif Tx_Beg = '1' then Tx_Dsm_Next <= sReq;
end if;
when sDel => if Tx_On = '0' then Tx_Dsm_Next <= sIdle; --avoid FSM hang
elsif Tx_Del_End = '1' then Tx_Dsm_Next <= sTimH;
end if;
when sAdrH => Tx_Dsm_Next <= sAdrL;
when sAdrL => Tx_Dsm_Next <= sLen; --sReq;
--leaving sAdrL and entering sReq leads to the very first Tx_Dma_Req
-- this enables early dma req at the beginning of IPG (auto-resp)
when sReq => if Tx_On = '0' then Tx_Dsm_Next <= sIdle;
elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH;
elsif Tx_Sync = '0' then Tx_Dsm_Next <= sBegL;
elsif Sm_Tx = sBop then Tx_Dsm_Next <= sTimH;
end if;
when sTimH => Tx_Dsm_Next <= sTimL;
when sTimL => Tx_Dsm_Next <= sData;
when sData => if F_End = '1' then Tx_Dsm_Next <= sStat;
elsif Tx_Col = '1' then Tx_Dsm_Next <= sColl;
end if;
when sStat => Tx_Dsm_Next <= sIdle;
when sColl => if sm_tx = sIdle then
if Tx_Sync = '1' then Tx_Dsm_Next <= sStat;
else Tx_Dsm_Next <= sIdle;
end if;
end if;
when others =>
end case;
end process pTxSm;
pTxSmClk : process(iRst, iClk)
begin
if iRst = cActivated then
Dsm <= sIdle;
elsif rising_edge(iClk) then
Dsm <= Tx_Dsm_Next;
end if;
end process pTxSmClk;
pTxControl: process( iRst, iClk )
begin
if iRst = '1' then
Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0';
Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0';
Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (others => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0');
ZeitL <= (others => '0'); Tx_Count <= (others => '0'); Tx_Ident <= "00";
Dma_Tx_Addr <= (others => '0'); Tx_Cmp_High <= (others => '0');
Tx_Del_Run <= '0';
Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0'); Tx_Dma_Len <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerTrigTx = true then
if Tx_Sync = '1' and Dsm = sBegL and (DescRam_Out & Tx_Cmp_High ) = Zeit then Tx_Beg <= '1';
else Tx_Beg <= '0';
end if;
end if;
if Dsm = sStat and Desc_We = '1' then ClrCol <= '1';
else ClrCol <= '0';
end if;
if gTimerEnable then
if Dsm = sTimH then ZeitL <= Zeit(31 downto 16);
end if;
end if;
if Ext_Ack = '0' and R_Req = '1' then Ext_Desc <= Auto_Desc;
Ext_Ack <= '1';
elsif Ext_Tx = '1' or Tx_On = '0' then Ext_Ack <= '0';
end if;
if Dsm = sIdle and Ext_Ack = '1' then Ext_Tx <= '1';
elsif Dsm = sStat or Tx_Col = '1' or Tx_On = '0' then Ext_Tx <= '0';
end if;
if (F_End = '1' or Tx_On = '0'
or (Tx_Col = '1' and Ext_Tx = '1' )
or dsm = sColl ) then Start_TxS <= '0';
Auto_Coll <= Auto_Coll or (Tx_Col and Ext_Tx);
elsif Dsm = sReq and Tx_Del = '0' then Start_TxS <= '1';
elsif Dsm = sDel and Tx_Del_End = '1' then Start_TxS <= '1';
elsif Sm_Tx = sIdle then Auto_Coll <= '0';
end if;
if Dsm = sIdle then Last_Desc <= TX_LAST;
end if;
if Dsm = sLen then Tx_Count <= TX_LEN; Tx_Dma_Len <= TX_LEN; --add CRC
elsif F_Val = '1' then Tx_Count <= Tx_Count - 1;
end if;
if Dsm = sBegH then Tx_Cmp_High <= DescRam_Out;
end if;
if Dsm = sIdle and Tx_On = '1' and TX_OWN = '1' and Retry_Cnt = 0 then
if Ext_Tx = '1' or Tx_Wait = '0' then
if gTimerTrigTx then Tx_Sync <= TX_TIME;
else Tx_Sync <= '0';
end if;
Max_Retry <= TX_RETRY;
Tx_Early <= TX_BEGON;
if gAutoTxDel = true then Tx_Del <= TX_BEGDEL;
end if;
end if;
elsif Dsm = sTimH then Tx_BegSet <= Tx_Early;
elsif Dsm = sTimL then Tx_BegSet <= '0';
elsif Dsm = sIdle then Tx_Del <= '0';
end if;
if gAutoTxDel = true and Tx_Del = '1' then
if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0';
Tx_Del_Cnt(15 downto 0) <= DescRam_Out;
elsif Dsm = sBegL then Tx_Del_Cnt(31 downto 16) <= DescRam_Out;
elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1;
end if;
if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg
elsif Tx_Del_End = '1' then Tx_Del_Run <= '0';
end if;
end if;
if Dsm = sAdrL then --Dma_Tx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
Dma_Tx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
Tx_Ident <= DescRam_Out(15 downto 14);
elsif Tx_Dma_Ack = '1' then Dma_Tx_Addr(15 downto 1) <= Dma_Tx_Addr(15 downto 1) + 1;
end if;
if Dsm = sAdrH then Dma_Tx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
-- Dma_Tx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
-- Tx_Ident <= DescRam_Out(15 downto 14);
elsif Tx_Dma_Ack = '1' and Dma_Tx_Addr(15 downto 1) = x"FFF" & "111" then
Dma_Tx_Addr(oDmaAddress'high downto 16) <= Dma_Tx_Addr(oDmaAddress'high downto 16) + 1;
end if;
if DSM = sAdrL
or (F_Val = '1' and H_Byte = '0') then Tx_Dma_Req <= '1';
elsif Tx_Dma_Ack = '1' then Tx_Dma_Req <= '0';
end if;
if Sm_Tx = sBop then H_Byte <= '0';
elsif F_Val = '1' then H_Byte <= not H_Byte;
end if;
if F_Val = '1' then Tx_Buf <= Tx_LatchL;
end if;
if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1';
elsif Sm_Tx = sBop then Tx_Dma_Out <= '0';
end if;
end if;
end process pTxControl;
Start_Tx <= '1' when Start_TxS = '1' and Block_Col = '0' else
'1' when not gAutoTxDel and not gTimerTrigTx and R_Req = '1' else
'0';
F_TxB <= Tx_LatchH when H_Byte = '0' else
Tx_Buf;
onTxIrq <= '1' when (Tx_Icnt = 0 and Tx_SoftInt = '0') or Tx_Ie = '0' else '0';
Tx_Idle <= '1' when Sm_Tx = sIdle and Dsm = sIdle else '0';
Tx_Reg(15 downto 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) or Tx_Icnt(3)) & Tx_Icnt(2 downto 0)
& Tx_On & Tx_BegInt & Tx_Idle & "0" ;
Tx_Reg( 3 downto 0) <= Tx_Desc;
Sel_TxH <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '0' and Ram_Be(1) = '1' else '0';
Sel_TxL <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '0' and Ram_Be(0) = '1' else '0';
Tx_Desc <= Tx_Desc_One;
Tx_SoftInt <= '0';
pTxRegs: process( iRst, iClk )
begin
if iRst = '1' then
Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; onTxBegIrq <= '0';
Tx_Desc_One <= (others => '0');
Tx_Icnt <= (others => '0'); TxInt <= '0'; Tx_BegInt <= '0';
Tx_Ipg <= conv_std_logic_vector( 42, 6);
elsif rising_edge( iClk ) then
if Sel_TxL = '1' then
if iAddress(2 downto 1) = "00" then Tx_On <= iWritedata( 7);
elsif iAddress(2 downto 1) = "01" and iWritedata( 7) = '1' then Tx_On <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata( 7) = '1' then Tx_On <= '0';
end if;
end if;
if Tx_BegSet = '1' and Tx_Ie = '1' then Tx_BegInt <= '1';
elsif Sel_TxL = '1' and iAddress(2 downto 1) = "01" and iWritedata( 6) = '1' then Tx_BegInt <= '1';
elsif Sel_TxL = '1' and iAddress(2 downto 1) = "10" and iWritedata( 6) = '1' then Tx_BegInt <= '0';
end if;
onTxBegIrq <= not Tx_BegInt;
if Sel_TxL = '1' and iAddress(2 downto 1) = "11" then Tx_Desc_One <= iWritedata( 3 downto 0);
elsif Dsm = sStat and Ext_Tx = '0' then
if Last_Desc = '1' then Tx_Desc_One <= x"0";
else Tx_Desc_One <= Tx_Desc + 1;
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Ie <= iWritedata(15);
elsif iAddress(2 downto 1) = "01" and iWritedata(15) = '1' then Tx_Ie <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(15) = '1' then Tx_Ie <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Half <= iWritedata(13);
elsif iAddress(2 downto 1) = "01" and iWritedata(13) = '1' then Tx_Half <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(13) = '1' then Tx_Half <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Wait <= iWritedata(12);
elsif iAddress(2 downto 1) = "01" and iWritedata(12) = '1' then Tx_Wait <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(12) = '1' then Tx_Wait <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "11" and iWritedata(14) = '1' then Tx_Ipg <= iWritedata(13 downto 8);
end if;
end if;
if Tx_Ie = '1' and Dsm = sStat and Desc_We = '1' then TxInt <= '1';
else TxInt <= '0';
end if;
if Sel_TxH = '1' and iAddress(2 downto 1) = "10" and iWritedata(8) = '1'
and Tx_Icnt /= 0 then Tx_Icnt <= Tx_Icnt - not TxInt;
elsif TxInt = '1' and Tx_Icnt /= "11111" then Tx_Icnt <= Tx_Icnt + 1;
end if;
end if;
end process pTxRegs;
end block bTxDesc;
end block b_Full_Tx;
b_Full_Rx: block
type tRxState is (
sIdle,
sSof,
sRxd
);
signal Sm_Rx : tRxState;
signal Rx_Dat : std_logic_vector(1 downto 0);
signal Rx_DatL : std_logic_vector(1 downto 0);
signal Tx_Timer : std_logic_vector(7 downto 0);
signal Dibl_Cnt : std_logic_vector(1 downto 0);
signal Crc : std_logic_vector(31 downto 0);
signal nCrc : std_logic_vector(31 downto 0);
signal CrcDin : std_logic_vector(1 downto 0);
signal F_Err : std_logic;
signal P_Err : std_logic;
signal N_Err : std_logic;
signal A_Err : std_logic;
signal F_End : std_logic;
signal F_Val : std_logic;
signal Rx_Beg : std_logic;
signal Rx_Sr : std_logic_vector(7 downto 0);
signal nCrc_Ok : std_logic;
signal Crc_Ok : std_logic;
signal WrDescStat : std_logic;
signal PreCount : std_logic_vector(4 downto 0);
signal PreBeg : std_logic;
signal PreErr : std_logic;
signal Rx_DvL : std_logic;
signal Diag : std_logic;
begin
Rx_Beg <= '1' when Rx_Dv = '1' and Sm_Rx = sSof and Rx_Dat = "11" else '0';
nCrc_Ok <= '1' when nCrc = x"C704DD7B" else '0';
rxsm: process ( iClk, iRst ) is
begin
if iRst = '1' then
Sm_Rx <= sIdle;
elsif rising_edge( iClk ) then
if Sm_Rx = sIdle or Sm_Rx = sRxd or Sm_Rx = sSof or Dibl_Cnt = "11" then
case Sm_Rx is
when sIdle => if Rx_Dv = '1' then Sm_Rx <= sSof; end if;
when sSof => if Rx_Dat = "11" then Sm_Rx <= sRxd;
elsif Rx_Dv = '0' then Sm_Rx <= sIdle; end if;
when sRxd => if Rx_Dv = '0' then Sm_Rx <= sIdle; end if;
when others => NULL;
end case;
end if;
end if;
end process rxsm;
pRxCtl: process ( iClk, iRst ) is
variable vPreload : std_logic_vector(Tx_Timer'range);
variable vLoad : std_logic;
begin
if iRst = '1' then
Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (others => '0');
F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0';
A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0';
elsif rising_edge( iClk ) then
Rx_DatL <= iRxData;
Rx_Dat <= Rx_DatL;
if Rx_Dv = '0' and iRxDv = '1' then Rx_Dv <= '1';
elsif Rx_Dv = '1' and iRxDv = '0' and Dibl_Cnt(0) = '1' then Rx_Dv <= '0';
end if;
if Rx_Beg = '1' then Dibl_Cnt <= "00";
else Dibl_Cnt <= Dibl_Cnt + 1;
end if;
Crc_Ok <= nCrc_Ok;
if (Sm_Rx = sRxd and Rx_Dv = '0') then F_End <= '1';
F_Err <= not Crc_Ok;
else F_End <= '0';
end if;
if Dibl_Cnt = "11" and Sm_Rx = sRxd then F_Val <= '1';
else F_Val <= '0';
end if;
if WrDescStat = '1' then A_Err <= '0';
elsif F_End = '1' and Dibl_Cnt /= 1 then A_Err <= '1';
end if;
if Rx_Dv = '0' or Rx_Dat(0) = '0' then PreCount <= (others => '1');
else PreCount <= PreCount - 1;
end if;
if Rx_Dv = '0' then PreBeg <= '0';
elsif Rx_Dat = "01" then PreBeg <= '1';
end if;
if WrDescStat = '1' then N_Err <= '0';
elsif Sm_Rx = sSof and Rx_Dv = '0' then N_Err <= '1';
end if;
if Rx_DvL = '0' then PreErr <= '0';
elsif PreBeg = '0' and (Rx_Dat = "10" or Rx_Dat = "11") then PreErr <= '1';
elsif PreBeg = '1' and (Rx_Dat = "10" or Rx_Dat = "00") then PreErr <= '1';
end if;
if WrDescStat = '1' then P_Err <= '0';
elsif Rx_Beg = '1' and PreErr = '1' then P_Err <= '1';
elsif Rx_Beg = '1' and PreCount /= 0 then P_Err <= '1';
end if;
Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 downto 2);
Rx_DvL <= Rx_Dv;
end if;
end process pRxCtl;
CrcDin <= Rx_Dat;
Calc: process ( iClk, Crc, nCrc, CrcDin, Sm_Rx ) is
variable H : std_logic_vector(1 downto 0);
begin
H(0) := Crc(31) xor CrcDin(0);
H(1) := Crc(30) xor CrcDin(1);
if Sm_Rx = sSof then nCrc <= x"FFFFFFFF";
else
nCrc( 0) <= H(1);
nCrc( 1) <= H(0) xor H(1);
nCrc( 2) <= Crc( 0) xor H(0) xor H(1);
nCrc( 3) <= Crc( 1) xor H(0) ;
nCrc( 4) <= Crc( 2) xor H(1);
nCrc( 5) <= Crc( 3) xor H(0) xor H(1);
nCrc( 6) <= Crc( 4) xor H(0) ;
nCrc( 7) <= Crc( 5) xor H(1);
nCrc( 8) <= Crc( 6) xor H(0) xor H(1);
nCrc( 9) <= Crc( 7) xor H(0) ;
nCrc(10) <= Crc( 8) xor H(1);
nCrc(11) <= Crc( 9) xor H(0) xor H(1);
nCrc(12) <= Crc(10) xor H(0) xor H(1);
nCrc(13) <= Crc(11) xor H(0) ;
nCrc(14) <= Crc(12) ;
nCrc(15) <= Crc(13) ;
nCrc(16) <= Crc(14) xor H(1);
nCrc(17) <= Crc(15) xor H(0) ;
nCrc(18) <= Crc(16) ;
nCrc(19) <= Crc(17) ;
nCrc(20) <= Crc(18) ;
nCrc(21) <= Crc(19) ;
nCrc(22) <= Crc(20) xor H(1);
nCrc(23) <= Crc(21) xor H(0) xor H(1);
nCrc(24) <= Crc(22) xor H(0) ;
nCrc(25) <= Crc(23) ;
nCrc(26) <= Crc(24) xor H(1);
nCrc(27) <= Crc(25) xor H(0) ;
nCrc(28) <= Crc(26) ;
nCrc(29) <= Crc(27) ;
nCrc(30) <= Crc(28) ;
nCrc(31) <= Crc(29) ;
end if;
if rising_edge( iClk ) then
Crc <= nCrc;
end if;
end process Calc;
bRxDesc: block
type tDescState is (
sIdle,
sLen,
sTimL,
sTimH,
sAdrH,
sAdrL,
sData,
sOdd,
sStat,
sLenW
);
signal Dsm : tDescState;
signal Rx_Dsm_Next : tDescState;
signal Rx_Buf : std_logic_vector(7 downto 0);
signal Rx_LatchH : std_logic_vector(7 downto 0);
signal Rx_LatchL : std_logic_vector(7 downto 0);
signal Rx_Ovr : std_logic;
signal DescRam_Out : std_logic_vector(15 downto 0);
signal DescRam_In : std_logic_vector(15 downto 0);
alias RX_LEN : std_logic_vector(11 downto 0) is DescRam_Out(11 downto 0);
alias RX_OWN : std_logic is DescRam_Out(8);
alias RX_LAST : std_logic is DescRam_Out(9);
signal Ram_Be : std_logic_vector(1 downto 0);
signal Ram_Wr : std_logic;
signal Desc_We : std_logic;
signal Desc_Addr : std_logic_vector(7 downto 0);
signal ZeitL : std_logic_vector(15 downto 0);
signal Rx_On : std_logic;
signal Rx_Ie : std_logic;
signal Sel_RxH : std_logic;
signal Sel_RxL : std_logic;
signal Rx_Desc : std_logic_vector(3 downto 0);
signal Match_Desc : std_logic_vector(3 downto 0);
signal Rx_Icnt : std_logic_vector(4 downto 0);
signal Rx_Lost : std_logic;
signal Last_Desc : std_logic;
signal Answer_Tx : std_logic;
signal DescIdx : std_logic_vector( 2 downto 0);
signal Rx_Count : std_logic_vector(11 downto 0);
signal Rx_Limit : std_logic_vector(11 downto 0);
signal Match : std_logic;
signal Filt_Cmp : std_logic;
signal Rx_Idle : std_logic;
signal RxInt : std_logic;
signal Hub_Rx_L : std_logic_vector(1 downto 0);
signal Rx_Dma_Out : std_logic;
signal Rx_Done : std_logic;
begin
process(iRst, iClk)
variable doPulse : std_logic;
begin
if iRst = cActivated then
Rx_Done <= cInactivated;
doPulse := cInactivated;
elsif rising_edge(iClk) then
Rx_Done <= cInactivated;
if Dsm /= sIdle and Rx_Dsm_Next = sIdle then
-- RX is done
doPulse := cActivated;
end if;
if doPulse = cActivated and Rx_Dma_Req = cInactivated and Rx_Count = 0 then
-- RX is done and there is no dma request
Rx_Done <= cActivated;
doPulse := cInactivated;
end if;
end if;
end process;
oDmaWriteDone <= Rx_Done;
WrDescStat <= '1' when Dsm = sStat else '0';
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '1' else '0';
Ram_Be(1) <= '1' when inWrite = '1' or inByteenable(1) = '0' else '0';
Ram_Be(0) <= '1' when inWrite = '1' or inByteenable(0) = '0' else '0';
DescIdx <= "001" when Desc_We = '0' and (Rx_Dsm_Next = sLen or Rx_Dsm_Next = sLenW) else
"001" when Desc_We = '1' and (Dsm = sLen or Dsm = sLenW) else
"010" when Desc_We = '0' and Rx_Dsm_Next = sAdrH else
"010" when Desc_We = '1' and Dsm = sAdrH else
"011" when Desc_We = '0' and Rx_Dsm_Next = sAdrL else
"011" when Desc_We = '1' and Dsm = sAdrL else
"110" when Desc_We = '0' and Rx_Dsm_Next = sTimH else
"110" when Desc_We = '1' and Dsm = sTimH else
"111" when Desc_We = '0' and Rx_Dsm_Next = sTimL else
"111" when Desc_We = '1' and Dsm = sTimL else
"000";
Desc_We <= '1' when Dsm = sTimL or Dsm = sTimH else
'1' when (Dsm = sLenW or Dsm = sStat) and Match = '1' else '0';
Desc_Addr <= "0" & Rx_Desc & DescIdx;
gRxTime: if gTimerEnable generate
DescRam_In <= Zeit(15 downto 0) when Dsm = sTimH else
ZeitL when Dsm = sTimL else
x"0" & Rx_Count when Dsm = sLenW else
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
end generate;
ngRxTime: if not gTimerEnable generate
DescRam_In <= x"0" & Rx_Count when Dsm = sLenW else
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
end generate;
--! This DPRAM holds the Rx descriptor accessible by the host and the DMA.
RXRAM : entity work.dpRam
generic map (
gWordWidth => iWritedata'length,
gNumberOfWords => 256,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => iAddress(8 downto 1),
iByteenable_A => Ram_Be,
iWritedata_A => iWritedata,
oReaddata_A => Rx_Ram_Dat,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => Desc_We,
iByteenable_B => (others => cActivated),
iAddress_B => Desc_Addr,
iWritedata_B => DescRam_In,
oReaddata_B => DescRam_Out
);
pRxSm: process( Dsm,
Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count )
begin
Rx_Dsm_Next <= Dsm;
case Dsm is
when sIdle => if Rx_Beg = '1' and Rx_On = '1' and RX_OWN = '1' then
Rx_Dsm_Next <= sLen;
end if;
when sLen => Rx_Dsm_Next <= sAdrH;
when sAdrH => Rx_Dsm_Next <= sAdrL;
when sAdrL => Rx_Dsm_Next <= sTimH;
when sTimH => Rx_Dsm_Next <= sTimL;
when sTimL => Rx_Dsm_Next <= sData;
when sData => if F_End = '1' then
if F_Err = '0'
or Diag = '1' then Rx_Dsm_Next <= sStat;
else Rx_Dsm_Next <= sIdle;
end if;
end if;
when sStat => Rx_Dsm_Next <= sLenW;
when sLenW => if Rx_Count(0) = '0' then
Rx_Dsm_Next <= sIdle;
else Rx_Dsm_Next <= sOdd;
end if;
when sOdd => Rx_Dsm_Next <= sIdle;
when others =>
end case;
end process pRxSm;
pRxSmClk : process(iRst, iClk)
begin
if iRst = cActivated then
Dsm <= sIdle;
elsif rising_edge(iClk) then
Dsm <= Rx_Dsm_Next;
end if;
end process pRxSmClk;
pRxControl: process( iRst, iClk )
begin
if iRst = '1' then
Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0';
Rx_Count <= (others => '0');
Rx_Buf <= (others => '0'); Rx_LatchL <= (others => '0'); Rx_LatchH <= (others => '0');
Dma_Rx_Addr <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerEnable then
if Dsm = sTimH then ZeitL <= Zeit(31 downto 16);
end if;
end if;
if Dsm = sIdle then Rx_Count <= (others => '0');
Last_Desc <= RX_LAST;
elsif F_Val = '1' then Rx_Count <= Rx_Count + 1;
end if;
if Dsm = sLen then Rx_Limit <= RX_LEN;
Hub_Rx_L <= iHubRxPort;
end if;
if F_Val = '1' then Rx_Buf <= Rx_Sr;
end if;
if (F_Val = '1' and Rx_Count(0) = '1') or Dsm = sStat then Rx_LatchH <= Rx_Buf;
Rx_LatchL <= Rx_Sr;
if Rx_Dma_Req = '1' and Sm_Rx /= sIdle then Rx_Dma_Out <= '1';
end if;
elsif Dsm = sLen then Rx_Dma_Out <= '0';
end if;
if Dsm = sLen then Rx_Ovr <= '0';
elsif F_Val = '1' and Rx_Limit = Rx_Count then Rx_Ovr <= '1';
end if;
if Dsm = sAdrL then --Dma_Rx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
Dma_Rx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
elsif Rx_Dma_Ack = '1' then Dma_Rx_Addr(15 downto 1) <= Dma_Rx_Addr(15 downto 1) + 1;
end if;
if Dsm = sAdrH then Dma_Rx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
--Dma_Rx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
elsif Rx_Dma_Ack = '1' and Dma_Rx_Addr(15 downto 1) = x"FFF" & "111" then
Dma_Rx_Addr(oDmaAddress'high downto 16) <= Dma_Rx_Addr(oDmaAddress'high downto 16) + 1;
end if;
if Filt_Cmp = '0' and Match ='0' then Rx_Dma_Req <= '0';
elsif (Dsm = sOdd and Rx_Ovr = '0')
or (Dsm = sData and Rx_Ovr = '0' and F_Val = '1' and Rx_Count(0) = '1') then Rx_Dma_Req <= '1';
elsif Rx_Dma_Ack = '1' then Rx_Dma_Req <= '0';
end if;
end if;
end process pRxControl;
oDmaWritedata <= Rx_LatchL & Rx_LatchH; --Rx_LatchH & Rx_LatchL;
onRxIrq <= '1' when Rx_Icnt = 0 or Rx_Ie = '0' else '0';
Rx_Idle <= '1' when Sm_Rx = sIdle else '0';
Rx_Reg(15 downto 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) or Rx_Icnt(3)) & Rx_Icnt(2 downto 0)
& Rx_On & "0" & Rx_Idle & Rx_Lost;
Rx_Reg( 3 downto 0) <= Rx_Desc;
bFilter: block
signal Ram_Addr : std_logic_vector(7 downto 0);
signal Ram_BeH : std_logic_vector(1 downto 0);
signal Ram_BeL : std_logic_vector(1 downto 0);
signal Ram_Wr : std_logic;
signal Filter_Addr : std_logic_vector(6 downto 0);
signal Filter_Out_H : std_logic_vector(31 downto 0);
signal Filter_Out_L : std_logic_vector(31 downto 0);
alias DIRON_0 : std_logic is Filter_Out_H(11);
alias DIRON_1 : std_logic is Filter_Out_H(27);
alias DIRON_2 : std_logic is Filter_Out_L(11);
alias DIRON_3 : std_logic is Filter_Out_L(27);
alias TX_0 : std_logic is Filter_Out_H(7);
alias TX_1 : std_logic is Filter_Out_H(23);
alias TX_2 : std_logic is Filter_Out_L(7);
alias TX_3 : std_logic is Filter_Out_L(23);
alias ON_0 : std_logic is Filter_Out_H(6);
alias ON_1 : std_logic is Filter_Out_H(22);
alias ON_2 : std_logic is Filter_Out_L(6);
alias ON_3 : std_logic is Filter_Out_L(22);
alias DESC_0 : std_logic_vector(3 downto 0) is Filter_Out_H(3 downto 0);
alias DESC_1 : std_logic_vector(3 downto 0) is Filter_Out_H(19 downto 16);
alias DESC_2 : std_logic_vector(3 downto 0) is Filter_Out_L(3 downto 0);
alias DESC_3 : std_logic_vector(3 downto 0) is Filter_Out_L(19 downto 16);
signal Byte_Cnt : std_logic_vector(4 downto 0) := (others => '0');
signal Erg0 : std_logic_vector(7 downto 0);
signal Erg1 : std_logic_vector(7 downto 0);
signal Erg2 : std_logic_vector(7 downto 0);
signal Erg3 : std_logic_vector(7 downto 0);
signal Mat_Reg : std_logic_vector(15 downto 0);
signal Filt_Idx : std_logic_vector(1 downto 0);
signal Mat_Sel : std_logic_vector(3 downto 0);
signal M_Prio : std_logic_vector(2 downto 0);
alias Found : std_logic is M_Prio(2);
begin
Ram_Addr <= iAddress(9 downto 8) & iAddress(5 downto 1) & iAddress(6);
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '0' else '0';
Ram_BeH(1) <= '1' when inWrite = '1' or (inByteenable(1) = '0' and iAddress(7) = '0') else '0';
Ram_BeH(0) <= '1' when inWrite = '1' or (inByteenable(0) = '0' and iAddress(7) = '0') else '0';
Ram_BeL(1) <= '1' when inWrite = '1' or (inByteenable(1) = '0' and iAddress(7) = '1') else '0';
Ram_BeL(0) <= '1' when inWrite = '1' or (inByteenable(0) = '0' and iAddress(7) = '1') else '0';
Filter_Addr <= Dibl_Cnt & Byte_Cnt;
--! This simplex DPRAM holds the higher dword for the Rx packet filters.
FILTERRAMHIGH : entity work.dpRamSplx
generic map (
gWordWidthA => iWritedata'length,
gByteenableWidthA => Ram_BeH'length,
gNumberOfWordsA => 256,
gWordWidthB => Filter_Out_H'length,
gNumberOfWordsB => 128,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => Ram_Addr,
iByteenable_A => Ram_BeH,
iWritedata_A => iWritedata,
iClk_B => iClk,
iEnable_B => cActivated,
iAddress_B => Filter_Addr,
oReaddata_B => Filter_Out_H
);
--! This simplex DPRAM holds the lower dword for the Rx packet filters.
FILTERRAMLOW : entity work.dpRamSplx
generic map (
gWordWidthA => iWritedata'length,
gByteenableWidthA => Ram_BeL'length,
gNumberOfWordsA => 256,
gWordWidthB => Filter_Out_H'length,
gNumberOfWordsB => 128,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => Ram_Addr,
iByteenable_A => Ram_BeL,
iWritedata_A => iWritedata,
iClk_B => iClk,
iEnable_B => cActivated,
iAddress_B => Filter_Addr,
oReaddata_B => Filter_Out_L
);
Erg0 <= (Rx_Buf xor Filter_Out_H( 7 downto 0)) and Filter_Out_H(15 downto 8);
Erg1 <= (Rx_Buf xor Filter_Out_H(23 downto 16)) and Filter_Out_H(31 downto 24);
Erg2 <= (Rx_Buf xor Filter_Out_L( 7 downto 0)) and Filter_Out_L(15 downto 8);
Erg3 <= (Rx_Buf xor Filter_Out_L(23 downto 16)) and Filter_Out_L(31 downto 24);
genMatSel: for i in 0 to 3 generate
Mat_Sel(i) <= Mat_Reg( 0 + i) when Filt_Idx = "00" else
Mat_Reg( 4 + i) when Filt_Idx = "01" else
Mat_Reg( 8 + i) when Filt_Idx = "10" else
Mat_Reg(12 + i); -- when Filt_Idx = "11";
end generate;
M_Prio <= "000" when Filt_Cmp = '0' or Match = '1' else
"100" when Mat_Sel(0) = '1' and On_0 = '1' and (DIRON_0 = '0') else
"101" when Mat_Sel(1) = '1' and On_1 = '1' and (DIRON_1 = '0') else
"110" when Mat_Sel(2) = '1' and On_2 = '1' and (DIRON_2 = '0') else
"111" when Mat_Sel(3) = '1' and On_3 = '1' and (DIRON_3 = '0') else
"000";
pFilter: process( iRst, iClk )
begin
if iRst = '1' then
Filt_Idx <= "00"; Match <= '0';
Filt_Cmp <= '0'; Mat_Reg <= (others => '0'); Byte_Cnt <= (others =>'0');
Match_Desc <= (others => '0');Auto_Desc <= (others =>'0'); Answer_Tx <= '0';
elsif rising_edge( iClk ) then
Filt_Idx <= Dibl_Cnt;
if Dibl_Cnt = "11" and Rx_Count(5) = '0' then Byte_Cnt <= Rx_Count(Byte_Cnt'range);
end if;
if Dsm = sTiml then Filt_Cmp <= '1';
elsif Rx_Dv = '0' or (F_Val = '1' and Rx_Count(5) = '1') then Filt_Cmp <= '0';
end if;
if Dsm = sTimL then Mat_Reg <= (others => '1');
else
for i in 0 to 3 loop
if Erg0 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 0) <= '0'; end if;
if Erg1 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 1) <= '0'; end if;
if Erg2 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 2) <= '0'; end if;
if Erg3 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 3) <= '0'; end if;
end loop;
end if;
if Dsm = sTimL then Match <= '0';
elsif Found = '1' then Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 downto 0);
if M_Prio(1 downto 0) = "00" then Answer_Tx <= TX_0; Auto_Desc <= DESC_0;
elsif M_Prio(1 downto 0) = "01" then Answer_Tx <= TX_1; Auto_Desc <= DESC_1;
elsif M_Prio(1 downto 0) = "10" then Answer_Tx <= TX_2; Auto_Desc <= DESC_2;
elsif M_Prio(1 downto 0) = "11" then Answer_Tx <= TX_3; Auto_Desc <= DESC_3;
end if;
elsif F_End = '1' then Answer_Tx <= '0';
end if;
end if;
end process pFilter;
R_Req <= Answer_Tx when F_End = '1' and F_Err = '0' else '0';
end block bFilter;
Sel_RxH <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '1' and inByteenable(1) = '0' else '0';
Sel_RxL <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '1' and inByteenable(0) = '0' else '0';
pRxRegs: process( iRst, iClk )
begin
if iRst = '1' then
Rx_Desc <= (others => '0'); Rx_On <= '0';
Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (others => '0'); RxInt <= '0'; Diag <= '0';
elsif rising_edge( iClk ) then
if Sel_RxH = '1' then
if iAddress(2 downto 1) = "00" then Rx_Ie <= iWritedata(15);
elsif iAddress(2 downto 1) = "01" and iWritedata(15) = '1' then Rx_Ie <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(15) = '1' then Rx_Ie <= '0';
end if;
end if;
if Sel_RxH = '1' then
if iAddress(2 downto 1) = "00" then Diag <= iWritedata(12);
elsif iAddress(2 downto 1) = "01" and iWritedata(12) = '1' then Diag <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(12) = '1' then Diag <= '0';
end if;
end if;
if Sel_RxL = '1' then
if iAddress(2 downto 1) = "00" then Rx_On <= iWritedata( 7);
elsif iAddress(2 downto 1) = "01" and iWritedata( 7) = '1' then Rx_On <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata( 7) = '1' then Rx_On <= '0';
end if;
end if;
if Rx_Beg = '1' and (RX_OWN = '0' or Rx_On = '0') then Rx_Lost <= '1';
elsif Sel_RxL = '1' and iAddress(2 downto 1) = "10" and iWritedata( 4) = '1' then Rx_Lost <= '0';
end if;
if Sel_RxL = '1' and iAddress(2 downto 1) = "11" then Rx_Desc <= iWritedata( 3 downto 0);
elsif Dsm = sLenW and Desc_We = '1' then
if Last_Desc = '1' then Rx_Desc <= x"0";
else Rx_Desc <= Rx_Desc + 1;
end if;
end if;
if Rx_Ie = '1' and Desc_We = '1' and Dsm = sStat then RxInt <= '1';
else RxInt <= '0';
end if;
if Sel_RxH = '1' and iAddress(2 downto 1) = "10" and iWritedata(8) = '1'
and Rx_Icnt /= 0 then Rx_Icnt <= Rx_Icnt - not RxInt;
elsif RxInt = '1' and Rx_Icnt /= "11111" then Rx_Icnt <= Rx_Icnt + 1;
end if;
end if;
end process pRxRegs;
end block bRxDesc;
end block b_Full_Rx;
end architecture struct; | gpl-2.0 | 56029eefd391c77f16f63a2630ee33a3 | 0.437299 | 3.655643 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/gh_fifo_async16_sr.vhd | 1 | 5,969 | ---------------------------------------------------------------------
-- Filename: gh_fifo_async16_sr.vhd
--
--
-- Description:
-- an Asynchronous FIFO
--
-- Copyright (c) 2006 by George Huber
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 12/17/06 h lefevre Initial revision
--
--------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity gh_fifo_async16_sr is
GENERIC (data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
full : out STD_LOGIC);
end entity;
architecture a of gh_fifo_async16_sr is
type ram_mem_type is array (15 downto 0)
of STD_LOGIC_VECTOR (data_width-1 downto 0);
signal ram_mem : ram_mem_type;
signal iempty : STD_LOGIC;
signal ifull : STD_LOGIC;
signal add_WR_CE : std_logic;
signal add_WR : std_logic_vector(4 downto 0); -- 4 bits are used to address MEM
signal add_WR_GC : std_logic_vector(4 downto 0); -- 5 bits are used to compare
signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags
signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk
signal add_RD_CE : std_logic;
signal add_RD : std_logic_vector(4 downto 0);
signal add_RD_GC : std_logic_vector(4 downto 0);
signal add_RD_GCwc : std_logic_vector(4 downto 0);
signal n_add_RD : std_logic_vector(4 downto 0);
signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk
signal srst_w : STD_LOGIC;
signal isrst_w : STD_LOGIC;
signal srst_r : STD_LOGIC;
signal isrst_r : STD_LOGIC;
begin
--------------------------------------------
------- memory -----------------------------
--------------------------------------------
process (clk_WR)
begin
if (rising_edge(clk_WR)) then
if ((WR = '1') and (ifull = '0')) then
ram_mem(CONV_INTEGER(add_WR(3 downto 0))) <= D;
end if;
end if;
end process;
Q <= ram_mem(CONV_INTEGER(add_RD(3 downto 0)));
-----------------------------------------
----- Write address counter -------------
-----------------------------------------
add_WR_CE <= '0' when (ifull = '1') else
'0' when (WR = '0') else
'1';
n_add_WR <= add_WR + x"1";
process (clk_WR,rst)
begin
if (rst = '1') then
add_WR <= (others => '0');
add_RD_WS <= "11000";
add_WR_GC <= (others => '0');
elsif (rising_edge(clk_WR)) then
add_RD_WS <= add_RD_GCwc;
if (srst_w = '1') then
add_WR <= (others => '0');
add_WR_GC <= (others => '0');
elsif (add_WR_CE = '1') then
add_WR <= n_add_WR;
add_WR_GC(0) <= n_add_WR(0) xor n_add_WR(1);
add_WR_GC(1) <= n_add_WR(1) xor n_add_WR(2);
add_WR_GC(2) <= n_add_WR(2) xor n_add_WR(3);
add_WR_GC(3) <= n_add_WR(3) xor n_add_WR(4);
add_WR_GC(4) <= n_add_WR(4);
else
add_WR <= add_WR;
add_WR_GC <= add_WR_GC;
end if;
end if;
end process;
full <= ifull;
ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to "00000"
'0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11000"
'1';
-----------------------------------------
----- Read address counter --------------
-----------------------------------------
add_RD_CE <= '0' when (iempty = '1') else
'0' when (RD = '0') else
'1';
n_add_RD <= add_RD + x"1";
process (clk_RD,rst)
begin
if (rst = '1') then
add_RD <= (others => '0');
add_WR_RS <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (rising_edge(clk_RD)) then
add_WR_RS <= add_WR_GC;
if (srst_r = '1') then
add_RD <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (add_RD_CE = '1') then
add_RD <= n_add_RD;
add_RD_GC(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GC(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GC(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GC(3) <= n_add_RD(3) xor n_add_RD(4);
add_RD_GC(4) <= n_add_RD(4);
add_RD_GCwc(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GCwc(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GCwc(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GCwc(3) <= n_add_RD(3) xor (not n_add_RD(4));
add_RD_GCwc(4) <= (not n_add_RD(4));
else
add_RD <= add_RD;
add_RD_GC <= add_RD_GC;
add_RD_GCwc <= add_RD_GCwc;
end if;
end if;
end process;
empty <= iempty;
iempty <= '1' when (add_WR_RS = add_RD_GC) else
'0';
----------------------------------
--- sync rest stuff --------------
--- srst is sync with clk_WR -----
--- srst_r is sync with clk_RD ---
----------------------------------
process (clk_WR,rst)
begin
if (rst = '1') then
srst_w <= '0';
isrst_r <= '0';
elsif (rising_edge(clk_WR)) then
isrst_r <= srst_r;
if (srst = '1') then
srst_w <= '1';
elsif (isrst_r = '1') then
srst_w <= '0';
end if;
end if;
end process;
process (clk_RD,rst)
begin
if (rst = '1') then
srst_r <= '0';
isrst_w <= '0';
elsif (rising_edge(clk_RD)) then
isrst_w <= srst_w;
if (isrst_w = '1') then
srst_r <= '1';
else
srst_r <= '0';
end if;
end if;
end process;
end architecture;
| apache-2.0 | 2c37be507528473c18040dbcc601ed4f | 0.489194 | 2.700905 | false | false | false | false |
dangpzanco/sistemas-digitais | DecodeHEX.vhd | 1 | 760 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity DecodeHEX is
port (I: in std_logic_vector(3 downto 0);
O: out std_logic_vector(6 downto 0)
);
end DecodeHEX;
architecture DEC_estr of DecodeHEX is
begin
O <= "1000000" when I = "0000" else
"1111001" when I = "0001" else
"0100100" when I = "0010" else
"0110000" when I = "0011" else
"0011001" when I = "0100" else
"0010010" when I = "0101" else
"0000010" when I = "0110" else
"1111000" when I = "0111" else
"0000000" when I = "1000" else
"0011000" when I = "1001" else
"0001000" when I = "1010" else
"0000011" when I = "1011" else
"1000110" when I = "1100" else
"0100001" when I = "1101" else
"0000110" when I = "1110" else
"0001110";
end DEC_estr; | mit | a73e1f40946302266457c537b20be6d2 | 0.621053 | 2.889734 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx_instr.vhdl | 1 | 11,479 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_instr.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:34:41 $
--
--------------------------------------------------------------------------
--
-- Package specification for DLX instructions
--
use std.textio.line,
work.dlx_types.all;
package dlx_instr is
-- A dlx instruction is 32 bits wide. There are three instruction formats:
--
-- I-type:
-- 0 5 6 10 11 15 16 31
-- +----------------------------------------------------------------+
-- | opcode | rs1 | rd | immed16 |
-- +----------------------------------------------------------------+
--
-- R-type:
-- 0 5 6 10 11 15 16 20 21 25 26 31
-- +----------------------------------------------------------------+
-- | opcode | rs1 | rs2 | rd | | func |
-- +----------------------------------------------------------------+
--
-- J-type:
-- 0 5 6 31
-- +----------------------------------------------------------------+
-- | opcode | immed26 |
-- +----------------------------------------------------------------+
--
subtype dlx_opcode is bit_vector(0 to 5);
subtype dlx_sp_func is bit_vector(0 to 5);
subtype dlx_fp_func is bit_vector(0 to 4);
subtype dlx_reg_addr is bit_vector(0 to 4);
subtype dlx_immed16 is bit_vector(0 to 15);
subtype dlx_immed26 is bit_vector(0 to 25);
constant op_special : dlx_opcode := B"000000";
constant op_fparith : dlx_opcode := B"000001";
constant op_j : dlx_opcode := B"000010";
constant op_jal : dlx_opcode := B"000011";
constant op_beqz : dlx_opcode := B"000100";
constant op_bnez : dlx_opcode := B"000101";
constant op_bfpt : dlx_opcode := B"000110";
constant op_bfpf : dlx_opcode := B"000111";
constant op_addi : dlx_opcode := B"001000";
constant op_addui : dlx_opcode := B"001001";
constant op_subi : dlx_opcode := B"001010";
constant op_subui : dlx_opcode := B"001011";
constant op_andi : dlx_opcode := B"001100";
constant op_ori : dlx_opcode := B"001101";
constant op_xori : dlx_opcode := B"001110";
constant op_lhi : dlx_opcode := B"001111";
constant op_rfe : dlx_opcode := B"010000";
constant op_trap : dlx_opcode := B"010001";
constant op_jr : dlx_opcode := B"010010";
constant op_jalr : dlx_opcode := B"010011";
constant op_slli : dlx_opcode := B"010100";
constant op_undef_15 : dlx_opcode := B"010101";
constant op_srli : dlx_opcode := B"010110";
constant op_srai : dlx_opcode := B"010111";
constant op_seqi : dlx_opcode := B"011000";
constant op_snei : dlx_opcode := B"011001";
constant op_slti : dlx_opcode := B"011010";
constant op_sgti : dlx_opcode := B"011011";
constant op_slei : dlx_opcode := B"011100";
constant op_sgei : dlx_opcode := B"011101";
constant op_undef_1E : dlx_opcode := B"011110";
constant op_undef_1F : dlx_opcode := B"011111";
constant op_lb : dlx_opcode := B"100000";
constant op_lh : dlx_opcode := B"100001";
constant op_undef_22 : dlx_opcode := B"100010";
constant op_lw : dlx_opcode := B"100011";
constant op_lbu : dlx_opcode := B"100100";
constant op_lhu : dlx_opcode := B"100101";
constant op_lf : dlx_opcode := B"100110";
constant op_ld : dlx_opcode := B"100111";
constant op_sb : dlx_opcode := B"101000";
constant op_sh : dlx_opcode := B"101001";
constant op_undef_2A : dlx_opcode := B"101010";
constant op_sw : dlx_opcode := B"101011";
constant op_undef_2C : dlx_opcode := B"101100";
constant op_undef_2D : dlx_opcode := B"101101";
constant op_sf : dlx_opcode := B"101110";
constant op_sd : dlx_opcode := B"101111";
constant op_sequi : dlx_opcode := B"110000";
constant op_sneui : dlx_opcode := B"110001";
constant op_sltui : dlx_opcode := B"110010";
constant op_sgtui : dlx_opcode := B"110011";
constant op_sleui : dlx_opcode := B"110100";
constant op_sgeui : dlx_opcode := B"110101";
constant op_undef_36 : dlx_opcode := B"110110";
constant op_undef_37 : dlx_opcode := B"110111";
constant op_undef_38 : dlx_opcode := B"111000";
constant op_undef_39 : dlx_opcode := B"111001";
constant op_undef_3A : dlx_opcode := B"111010";
constant op_undef_3B : dlx_opcode := B"111011";
constant op_undef_3C : dlx_opcode := B"111100";
constant op_undef_3D : dlx_opcode := B"111101";
constant op_undef_3E : dlx_opcode := B"111110";
constant op_undef_3F : dlx_opcode := B"111111";
constant sp_func_nop : dlx_sp_func := B"000000";
constant sp_func_undef_01 : dlx_sp_func := B"000001";
constant sp_func_undef_02 : dlx_sp_func := B"000010";
constant sp_func_undef_03 : dlx_sp_func := B"000011";
constant sp_func_sll : dlx_sp_func := B"000100";
constant sp_func_undef_05 : dlx_sp_func := B"000101";
constant sp_func_srl : dlx_sp_func := B"000110";
constant sp_func_sra : dlx_sp_func := B"000111";
constant sp_func_undef_08 : dlx_sp_func := B"001000";
constant sp_func_undef_09 : dlx_sp_func := B"001001";
constant sp_func_undef_0A : dlx_sp_func := B"001010";
constant sp_func_undef_0B : dlx_sp_func := B"001011";
constant sp_func_undef_0C : dlx_sp_func := B"001100";
constant sp_func_undef_0D : dlx_sp_func := B"001101";
constant sp_func_undef_0E : dlx_sp_func := B"001110";
constant sp_func_undef_0F : dlx_sp_func := B"001111";
constant sp_func_sequ : dlx_sp_func := B"010000";
constant sp_func_sneu : dlx_sp_func := B"010001";
constant sp_func_sltu : dlx_sp_func := B"010010";
constant sp_func_sgtu : dlx_sp_func := B"010011";
constant sp_func_sleu : dlx_sp_func := B"010100";
constant sp_func_sgeu : dlx_sp_func := B"010101";
constant sp_func_undef_16 : dlx_sp_func := B"010110";
constant sp_func_undef_17 : dlx_sp_func := B"010111";
constant sp_func_undef_18 : dlx_sp_func := B"011000";
constant sp_func_undef_19 : dlx_sp_func := B"011001";
constant sp_func_undef_1A : dlx_sp_func := B"011010";
constant sp_func_undef_1B : dlx_sp_func := B"011011";
constant sp_func_undef_1C : dlx_sp_func := B"011100";
constant sp_func_undef_1D : dlx_sp_func := B"011101";
constant sp_func_undef_1E : dlx_sp_func := B"011110";
constant sp_func_undef_1F : dlx_sp_func := B"011111";
constant sp_func_add : dlx_sp_func := B"100000";
constant sp_func_addu : dlx_sp_func := B"100001";
constant sp_func_sub : dlx_sp_func := B"100010";
constant sp_func_subu : dlx_sp_func := B"100011";
constant sp_func_and : dlx_sp_func := B"100100";
constant sp_func_or : dlx_sp_func := B"100101";
constant sp_func_xor : dlx_sp_func := B"100110";
constant sp_func_undef_27 : dlx_sp_func := B"100111";
constant sp_func_seq : dlx_sp_func := B"101000";
constant sp_func_sne : dlx_sp_func := B"101001";
constant sp_func_slt : dlx_sp_func := B"101010";
constant sp_func_sgt : dlx_sp_func := B"101011";
constant sp_func_sle : dlx_sp_func := B"101100";
constant sp_func_sge : dlx_sp_func := B"101101";
constant sp_func_undef_2E : dlx_sp_func := B"101110";
constant sp_func_undef_2F : dlx_sp_func := B"101111";
constant sp_func_movi2s : dlx_sp_func := B"110000";
constant sp_func_movs2i : dlx_sp_func := B"110001";
constant sp_func_movf : dlx_sp_func := B"110010";
constant sp_func_movd : dlx_sp_func := B"110011";
constant sp_func_movfp2i : dlx_sp_func := B"110100";
constant sp_func_movi2fp : dlx_sp_func := B"110101";
constant sp_func_undef_36 : dlx_sp_func := B"110110";
constant sp_func_undef_37 : dlx_sp_func := B"110111";
constant sp_func_undef_38 : dlx_sp_func := B"111000";
constant sp_func_undef_39 : dlx_sp_func := B"111001";
constant sp_func_undef_3A : dlx_sp_func := B"111010";
constant sp_func_undef_3B : dlx_sp_func := B"111011";
constant sp_func_undef_3C : dlx_sp_func := B"111100";
constant sp_func_undef_3D : dlx_sp_func := B"111101";
constant sp_func_undef_3E : dlx_sp_func := B"111110";
constant sp_func_undef_3F : dlx_sp_func := B"111111";
constant fp_func_addf : dlx_fp_func := B"00000";
constant fp_func_subf : dlx_fp_func := B"00001";
constant fp_func_multf : dlx_fp_func := B"00010";
constant fp_func_divf : dlx_fp_func := B"00011";
constant fp_func_addd : dlx_fp_func := B"00100";
constant fp_func_subd : dlx_fp_func := B"00101";
constant fp_func_multd : dlx_fp_func := B"00110";
constant fp_func_divd : dlx_fp_func := B"00111";
constant fp_func_cvtf2d : dlx_fp_func := B"01000";
constant fp_func_cvtf2i : dlx_fp_func := B"01001";
constant fp_func_cvtd2f : dlx_fp_func := B"01010";
constant fp_func_cvtd2i : dlx_fp_func := B"01011";
constant fp_func_cvti2f : dlx_fp_func := B"01100";
constant fp_func_cvti2d : dlx_fp_func := B"01101";
constant fp_func_mult : dlx_fp_func := B"01110";
constant fp_func_div : dlx_fp_func := B"01111";
constant fp_func_eqf : dlx_fp_func := B"10000";
constant fp_func_nef : dlx_fp_func := B"10001";
constant fp_func_ltf : dlx_fp_func := B"10010";
constant fp_func_gtf : dlx_fp_func := B"10011";
constant fp_func_lef : dlx_fp_func := B"10100";
constant fp_func_gef : dlx_fp_func := B"10101";
constant fp_func_multu : dlx_fp_func := B"10110";
constant fp_func_divu : dlx_fp_func := B"10111";
constant fp_func_eqd : dlx_fp_func := B"11000";
constant fp_func_ned : dlx_fp_func := B"11001";
constant fp_func_ltd : dlx_fp_func := B"11010";
constant fp_func_gtd : dlx_fp_func := B"11011";
constant fp_func_led : dlx_fp_func := B"11100";
constant fp_func_ged : dlx_fp_func := B"11101";
constant fp_func_undef_1E : dlx_fp_func := B"11110";
constant fp_func_undef_1F : dlx_fp_func := B"11111";
subtype dlx_opcode_num is natural range 0 to 63;
subtype dlx_sp_func_num is natural range 0 to 63;
subtype dlx_fp_func_num is natural range 0 to 31;
subtype instr_name is string(1 to 8);
type opcode_name_array is array (dlx_opcode_num) of instr_name;
type sp_func_name_array is array (dlx_sp_func_num) of instr_name;
type fp_func_name_array is array (dlx_fp_func_num) of instr_name;
constant opcode_names : opcode_name_array;
constant sp_func_names : sp_func_name_array;
constant fp_func_names : fp_func_name_array;
type immed_size is (immed_size_16, immed_size_26);
subtype reg_index is natural range 0 to 31;
constant link_reg : reg_index := 31;
procedure write_instr (L : inout line; instr : in dlx_word);
end dlx_instr;
| apache-2.0 | de2bd2af6e963ece90e8614101768ab6 | 0.605105 | 2.973064 | false | false | false | false |
hoglet67/AtomGodilVideo | src/DCM/DCM2.vhd | 1 | 2,128 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM2 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCM2;
architecture BEHAVIORAL of DCM2 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_MULTIPLY => 3,
CLKFX_DIVIDE => 7,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | cbb09dfb7e08e141e6d1a63e1fbfa602 | 0.398496 | 4.334012 | false | false | false | false |
hoglet67/AtomGodilVideo | src/VGA80x40/vga80x40.vhd | 1 | 13,323 | -- Hi Emacs, this is -*- mode: vhdl; -*-
----------------------------------------------------------------------------------------------------
--
-- Monocrome Text Mode Video Controller VHDL Macro
-- 80x40 characters. Pixel resolution is 640x480/60Hz
--
-- Copyright (c) 2007 Javier Valcarce Garca, [email protected]
-- $Id$
--
----------------------------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga80x40 is
port (
reset : in std_logic;
clk25MHz : in std_logic;
TEXT_A : out std_logic_vector(12 downto 0); -- text buffer
TEXT_D : in std_logic_vector(07 downto 0);
FONT_A : out std_logic_vector(11 downto 0); -- font buffer
FONT_D : in std_logic_vector(07 downto 0);
--
ocrx : in std_logic_vector(07 downto 0); -- OUTPUT regs
ocry : in std_logic_vector(07 downto 0);
octl : in std_logic_vector(07 downto 0);
octl2 : in std_logic_vector(07 downto 0);
--
R : out std_logic;
G : out std_logic;
B : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
blank : out std_logic
);
end vga80x40;
architecture rtl of vga80x40 is
signal R_int : std_logic;
signal G_int : std_logic;
signal B_int : std_logic;
signal hsync_int : std_logic;
signal vsync_int : std_logic;
signal active : std_logic;
signal hctr : integer range 799 downto 0;
signal vctr : integer range 525 downto 0;
-- character/pixel position on the screen
signal scry : integer range 039 downto 0; -- chr row < 40 (6 bits)
signal scry_r: integer range 039 downto 0; -- chr row < 40 (6 bits)
signal scrx : integer range 079 downto 0; -- chr col < 80 (7 bits)
signal scrx_r: integer range 079 downto 0; -- chr col < 80 (7 bits)
signal chry : integer range 011 downto 0; -- chr high < 12 (4 bits)
signal chry_r: integer range 011 downto 0; -- chr high < 12 (4 bits)
signal chrx : integer range 007 downto 0; -- chr width < 08 (3 bits)
signal losr_ce : std_logic;
signal losr_ld : std_logic;
signal losr_do : std_logic;
signal y : std_logic; -- character luminance pixel value (0 or 1)
signal ys : std_logic; -- character luminance pixel value (0 or 1) after semigraphic attribute
signal yu : std_logic; -- character luminance pixel value (0 or 1) after underline attribute
signal ya : std_logic; -- character luminance pixel value (0 or 1) after all attrributes
-- Data byte for the current character (before the font mapping) used for semi graphics
signal data : std_logic_vector(7 downto 0);
-- Colour attributes byte for the current character
signal attrtmp : std_logic_vector(7 downto 0);
signal attr : std_logic_vector(7 downto 0);
-- control io register
signal ctl : std_logic_vector(7 downto 0);
signal vga_en : std_logic;
signal cur_en : std_logic;
signal cur_mode : std_logic;
signal cur_blink : std_logic;
signal ctl_r : std_logic;
signal ctl_g : std_logic;
signal ctl_b : std_logic;
signal ctl_r_bg : std_logic;
signal ctl_g_bg : std_logic;
signal ctl_b_bg : std_logic;
signal ctl_attr : std_logic;
component ctrm
generic (
M : integer := 08);
port (
reset : in std_logic; -- asyncronous reset
clk : in std_logic;
ce : in std_logic; -- enable counting
rs : in std_logic; -- syncronous reset
do : out integer range (M-1) downto 0
);
end component;
component losr
generic (
N : integer := 04);
port (
reset : in std_logic;
clk : in std_logic;
load : in std_logic;
ce : in std_logic;
do : out std_logic;
di : in std_logic_vector(N-1 downto 0));
end component;
begin
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- hsync generator, initialized with '1'
process (reset, clk25MHz)
begin
if reset = '1' then
hsync_int <= '1';
elsif rising_edge(clk25MHz) then
if (hctr > 663) and (hctr < 757) then
hsync_int <= '0';
else
hsync_int <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- vsync generator, initialized with '1'
process (reset, clk25MHz)
begin
if reset = '1' then
vsync_int <= '1';
elsif rising_edge(clk25MHz) then
if (vctr > 499) and (vctr < 502) then
vsync_int <= '0';
else
vsync_int <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Blank signal, 0 = no draw, 1 = visible/draw zone
-- Proboscide99 31/08/08
-- blank <= '0' when (hctr > 639) or (vctr > 479) else '1';
active <= '0' when (hctr < 8) or (hctr > 647) or (vctr > 479) else '1';
blank <= not active;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- flip-flips for sync of R, G y B signal, initialized with '0'
process (reset, clk25MHz)
begin
if reset = '1' then
R <= '0';
G <= '0';
B <= '0';
elsif rising_edge(clk25MHz) then
R <= R_int;
G <= G_int;
B <= B_int;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Control register. Individual control signal
cur_mode <= octl(4);
cur_blink <= octl(5);
cur_en <= octl(6);
vga_en <= octl(7);
ctl_attr <= octl(3);
ctl_r <= octl(2);
ctl_g <= octl(1);
ctl_b <= octl(0);
ctl_r_bg <= octl2(2);
ctl_g_bg <= octl2(1);
ctl_b_bg <= octl2(0);
-- counters, hctr, vctr, srcx, srcy, chrx, chry
-- TODO: OPTIMIZE THIS
counters : block
signal hctr_ce : std_logic;
signal hctr_rs : std_logic;
signal vctr_ce : std_logic;
signal vctr_rs : std_logic;
signal chrx_ce : std_logic;
signal chrx_rs : std_logic;
signal chry_ce : std_logic;
signal chry_rs : std_logic;
signal scrx_ce : std_logic;
signal scrx_rs : std_logic;
signal scry_ce : std_logic;
signal scry_rs : std_logic;
signal hctr_639 : std_logic;
signal vctr_479 : std_logic;
signal chrx_007 : std_logic;
signal chry_011 : std_logic;
signal scrx_079 : std_logic;
signal read_attr : std_logic;
-- RAM read, ROM read
signal ram_tmp : integer range 6400 downto 0; --13 bits
signal rom_tmp : integer range 3070 downto 0;
begin
U_HCTR : ctrm generic map (M => 800) port map (
reset =>reset, clk=>clk25MHz, ce =>hctr_ce, rs =>hctr_rs, do => hctr);
U_VCTR : ctrm generic map (M => 526) port map (reset, clk25MHz, vctr_ce, vctr_rs, vctr);
hctr_ce <= '1';
hctr_rs <= '1' when hctr = 799 else '0';
vctr_ce <= '1' when hctr = 663 else '0';
vctr_rs <= '1' when vctr = 525 else '0';
U_CHRX: ctrm generic map (M => 008) port map (reset, clk25MHz, chrx_ce, chrx_rs, chrx);
U_CHRY: ctrm generic map (M => 012) port map (reset, clk25MHz, chry_ce, chry_rs, chry);
U_SCRX: ctrm generic map (M => 080) port map (reset, clk25MHz, scrx_ce, scrx_rs, scrx);
U_SCRY: ctrm generic map (M => 040) port map (reset, clk25MHz, scry_ce, scry_rs, scry);
hctr_639 <= '1' when hctr = 639 else '0';
vctr_479 <= '1' when vctr = 479 else '0';
chrx_007 <= '1' when chrx = 007 else '0';
chry_011 <= '1' when chry = 011 else '0';
scrx_079 <= '1' when scrx = 079 else '0';
chrx_rs <= chrx_007 or hctr_639;
chrx_ce <= '1' and active;
chry_rs <= chry_011 or vctr_479;
chry_ce <= hctr_639 and active;
scrx_ce <= chrx_007;
scrx_rs <= hctr_639;
scry_ce <= chry_011 and hctr_639;
scry_rs <= vctr_479;
-- Proboscide99 31/08/08
-- ram_tmp <= scry * 80 + scrx + 1 when ((scrx_079 = '0')) else
-- scry * 80 when ((chry_011 = '0') and (scrx_079 = '1')) else
-- 0 when ((chry_011 = '1') and (scrx_079 = '1'));
read_attr <= '1' when chrx = 000 or chrx = 001 or chrx = 002 or chrx = 003 else '0';
ram_tmp <= scry * 80 + scrx + 3200 when read_attr = '1' else scry * 80 + scrx;
TEXT_A <= std_logic_vector(TO_UNSIGNED(ram_tmp, 13));
rom_tmp <= TO_INTEGER(unsigned(TEXT_D)) * 16 + chry;
FONT_A <= std_logic_vector(TO_UNSIGNED(rom_tmp, 12));
end block;
process (clk25MHz)
begin
if rising_edge(clk25MHz) then
if (chrx = 003) then
attrtmp <= TEXT_D;
end if;
if (chrx = 007) then
attr <= attrtmp;
data <= TEXT_D;
end if;
if (losr_ld = '1') then
scrx_r <= scrx;
scry_r <= scry;
chry_r <= chry;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
U_LOSR : losr generic map (N => 8)
port map (reset, clk25MHz, losr_ld, losr_ce, losr_do, FONT_D);
losr_ce <= active;
losr_ld <= '1' when (chrx = 007) else '0';
-- Apply the underline attriute to the luminance
yu <= not y when ((attr(3) = '1') and (chry_r = 0010)) else y;
-- Generate the semigraphic pixel data
ys <= '1' when
(data(0) = '1' and (chrx >= 004) and (chry_r >= 008)) or
(data(1) = '1' and (chrx < 004) and (chry_r >= 008)) or
(data(2) = '1' and (chrx >= 004) and (chry_r >= 004) and (chry_r < 008)) or
(data(3) = '1' and (chrx < 004) and (chry_r >= 004) and (chry_r < 008)) or
(data(4) = '1' and (chrx >= 004) and (chry_r < 004)) or
(data(5) = '1' and (chrx < 004) and (chry_r < 004)) else '0';
ya <= ys when (attr(7) = '1') else yu;
-- video out, vga_en control signal enable/disable vga signal
R_int <= (((not ctl_attr) and ((y and ctl_r) or ((not y) and ctl_r_bg))) or
(ctl_attr and ((ya and attr(2)) or ((not ya) and attr(6))))) and active;
G_int <= (((not ctl_attr) and ((y and ctl_g) or ((not y) and ctl_g_bg))) or
(ctl_attr and ((ya and attr(1)) or ((not ya) and attr(5))))) and active;
B_int <= (((not ctl_attr) and ((y and ctl_b) or ((not y) and ctl_b_bg))) or
(ctl_attr and ((ya and attr(0)) or ((not ya) and attr(4))))) and active;
hsync <= hsync_int and vga_en;
vsync <= vsync_int and vga_en;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Hardware Cursor
hw_cursor : block
signal small : std_logic;
signal curen2 : std_logic;
signal slowclk : std_logic;
signal curpos : std_logic;
signal yint : std_logic;
signal crx_tmp : integer range 079 downto 0;
signal cry_tmp : integer range 039 downto 0;
signal crx : integer range 079 downto 0;
signal cry : integer range 039 downto 0;
signal counter : unsigned(22 downto 0);
begin
-- slowclk for blink hardware cursor
counter <= counter + 1 when rising_edge(clk25MHz);
slowclk <= counter(22); --2.98Hz
crx <= TO_INTEGER(unsigned(ocrx(6 downto 0)));
cry <= TO_INTEGER(unsigned(ocry(5 downto 0)));
--
curpos <= '1' when (scry_r = cry) and (scrx_r = crx) else '0';
small <= '1' when (chry_r > 8) else '0';
curen2 <= (slowclk or (not cur_blink)) and cur_en;
yint <= '1' when cur_mode = '0' else small;
y <= (yint and curpos and curen2) xor losr_do;
end block;
end rtl;
| apache-2.0 | 04ece42b9a41de6fd13e3a77f00f033a | 0.501764 | 3.473149 | false | false | false | false |
fgr1986/ddr_MIG_ctrl_interface | src/hdl/tb/example_top.vhd | 1 | 15,638 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
-- generic (
--
-- --***************************************************************************
-- -- Traffic Gen related parameters
-- --***************************************************************************
-- BL_WIDTH : integer := 10;
-- PORT_MODE : string := "BI_MODE";
-- DATA_MODE : std_logic_vector(3 downto 0) := "0010";
-- ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
-- TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
-- EYE_TEST : string := "FALSE";
-- -- set EYE_TEST = "TRUE" to probe memory
-- -- signals. Traffic Generator will only
-- -- write to one single location and no
-- -- read transactions will be generated.
-- DATA_PATTERN : string := "DGEN_ALL";
-- -- For small devices, choose one only.
-- -- For large device, choose "DGEN_ALL"
-- -- "DGEN_HAMMER", "DGEN_WALKING1",
-- -- "DGEN_WALKING0","DGEN_ADDR","
-- -- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
-- CMD_PATTERN : string := "CGEN_ALL";
-- -- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- -- "CGEN_SEQUENTIAL", "CGEN_ALL"
-- BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
-- END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
-- MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
-- --Possible Parameters
-- --1.BANK_ROW_COLUMN : Address mapping is
-- -- in form of Bank Row Column.
-- --2.ROW_BANK_COLUMN : Address mapping is
-- -- in the form of Row Bank Column.
-- --3.TG_TEST : Scrambles Address bits
-- -- for distributed Addressing.
-- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
-- CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
-- WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
-- RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--
-- --***************************************************************************
-- -- The following parameters refer to width of various ports
-- --***************************************************************************
-- BANK_WIDTH : integer := 3;
-- -- # of memory Bank Address bits.
-- COL_WIDTH : integer := 10;
-- -- # of memory Column Address bits.
-- CS_WIDTH : integer := 1;
-- -- # of unique CS outputs to memory.
-- DQ_WIDTH : integer := 16;
-- -- # of DQ (data)
-- DQS_WIDTH : integer := 2;
-- DQS_CNT_WIDTH : integer := 1;
-- -- = ceil(log2(DQS_WIDTH))
-- DRAM_WIDTH : integer := 8;
-- -- # of DQ per DQS
-- ECC_TEST : string := "OFF";
-- RANKS : integer := 1;
-- -- # of Ranks.
-- ROW_WIDTH : integer := 13;
-- -- # of memory Row Address bits.
-- ADDR_WIDTH : integer := 27;
-- -- # = RANK_WIDTH + BANK_WIDTH
-- -- + ROW_WIDTH + COL_WIDTH;
-- -- Chip Select is always tied to low for
-- -- single rank devices
-- --***************************************************************************
-- -- The following parameters are mode register settings
-- --***************************************************************************
-- BURST_MODE : string := "8";
-- -- DDR3 SDRAM:
-- -- Burst Length (Mode Register 0).
-- -- # = "8", "4", "OTF".
-- -- DDR2 SDRAM:
-- -- Burst Length (Mode Register).
-- -- # = "8", "4".
-- --***************************************************************************
-- -- Simulation parameters
-- --***************************************************************************
-- SIMULATION : string := "FALSE";
-- -- Should be TRUE during design simulations and
-- -- FALSE during implementations
--
-- --***************************************************************************
-- -- IODELAY and PHY related parameters
-- --***************************************************************************
-- TCQ : integer := 100;
--
-- DRAM_TYPE : string := "DDR2";
--
--
-- --***************************************************************************
-- -- System clock frequency parameters
-- --***************************************************************************
-- nCK_PER_CLK : integer := 4;
-- -- # of memory CKs per fabric CLK
--
-- --***************************************************************************
-- -- Debug parameters
-- --***************************************************************************
-- DEBUG_PORT : string := "OFF";
-- -- # = "ON" Enable debug signals/controls.
-- -- = "OFF" Disable debug signals/controls.
--
-- --***************************************************************************
-- -- Temparature monitor parameter
-- --***************************************************************************
-- TEMP_MON_CONTROL : string := "INTERNAL"
-- -- # = "INTERNAL", "EXTERNAL"
--
-- -- RST_ACT_LOW : integer := 1
-- -- =1 for active low reset,
-- -- =0 for active high.
-- );
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- -- clogb2 function - ceiling of log base 2
-- function clogb2 (size : integer) return integer is
-- variable base : integer := 1;
-- variable inp : integer := 0;
-- begin
-- inp := size - 1;
-- while (inp > 1) loop
-- inp := inp/2 ;
-- base := base + 1;
-- end loop;
-- return base;
-- end function;function STR_TO_INT(BM : string) return integer is
-- begin
-- if(BM = "8") then
-- return 8;
-- elsif(BM = "4") then
-- return 4;
-- else
-- return 0;
-- end if;
-- end function;
--
-- constant RANK_WIDTH : integer := clogb2(RANKS);
--
-- function XWIDTH return integer is
-- begin
-- if(CS_WIDTH = 1) then
-- return 0;
-- else
-- return RANK_WIDTH;
-- end if;
-- end function;
--
--
--
-- constant CMD_PIPE_PLUS1 : string := "ON";
-- -- add pipeline stage between MC and PHY
-- constant tPRDI : integer := 1000000;
-- -- memory tPRDI paramter in pS.
-- constant DATA_WIDTH : integer := 16;
-- constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
-- constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
-- constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
-- constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--
-- --***************************************************************************
-- -- Traffic Gen related parameters (derived)
-- --***************************************************************************
-- constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
-- constant MASK_SIZE : integer := DATA_WIDTH/8;
signal s_init_calibration_complete : std_logic;
-- Start of User Design memory_ctrl component
component memory_ctrl
port
(-- Clock in ports
clk_100MHz_i : in std_logic;
rstn_i : in std_logic;
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface signals
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
begin
--***************************************************************************
cmp_memory_ctrl : entity work.memory_ctrl
port map (
clk_100MHz_i => sys_clk_i,
rstn_i => sys_rst,
init_calib_complete_o => s_init_calibration_complete,
-- DDR2 interface signals
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n );
init_calib_complete <= s_init_calibration_complete;
tg_compare_error <= '0';
end architecture arch_example_top;
| gpl-3.0 | f84f36d59a381a86ec882b1f5006b8f8 | 0.43535 | 4.498849 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/dynamicBridgeRtl.vhd | 2 | 16,398 | -------------------------------------------------------------------------------
--! @file dynamicBridgeRtl.vhd
--
--! @brief Dynamic Bridge for translating static to dynamic memory spaces
--
--! @details The Dynamic Bridge component translates a static memory mapping
--! into a dynamic memory map that can be changed during runtime.
--! This enhances the functionality of an ordinary memory mapped bridge logic.
--! Additionally several memory spaces can be configured (compilation).
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
-------------------------------------------------------------------------------
--! @brief Dynamic bridge translates a fixed address space into a flexible one.
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge has an input port with a fixed (before runtime) memory
--! mapping, which is translated to a flexible address space mapping.
--! The flexible address space can be changed during runtime in order to
--! redirect accesses from the input to other locations.
--! The base addresses for the static port are set by generic gBaseAddressArray.
--! The base addresses for the dynamic port are set through the BaseSet port
-------------------------------------------------------------------------------
entity dynamicBridge is
generic (
--! number of static address spaces
gAddressSpaceCount : natural := 2;
--! select wheather DPRAM or registers will be used as memory (false = 0, true /= 0)
gUseMemBlock : integer := 0;
--! base addresses in static address space (note: last-1 = high address)
gBaseAddressArray : tArrayStd32 := (x"0000_1000" , x"0000_2000" , x"0000_3000")
);
port (
-- Global
--! component-wide clock signal
iClk : in std_logic;
--! component-wide reset signal
iRst : in std_logic;
-- Bridge
--! address of static address space
iBridgeAddress : in std_logic_vector;
--! Request strobe
iBridgeRequest : in std_logic;
--! address of dynamic address space (translated input)
oBridgeAddress : out std_logic_vector;
--! Select signal of any address space selected
oBridgeSelectAny : out std_logic;
--! select signals of all address spaces
oBridgeSelect : out std_logic_vector(gAddressSpaceCount-1 downto 0);
--! Bridge output valid
oBridgeValid : out std_logic;
-- BaseSet Memory Mapped Write Bus
--! BaseSet write strobe
iBaseSetWrite : in std_logic;
--! BaseSet read strobe
iBaseSetRead : in std_logic;
--! BaseSet byteenable
iBaseSetByteenable : in std_logic_vector;
--! BaseSet address bus
iBaseSetAddress : in std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! BaseSet write data bus
iBaseSetData : in std_logic_vector;
--! BaseSet read data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
oBaseSetAck : out std_logic
);
end dynamicBridge;
-------------------------------------------------------------------------------
--! @brief Register Transfer Level of Dynamic Bridge device
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge rtl applies generated address decoders
--! to generate select signals for the static address spaces.
--! The select signals are forwarded register file holding the base address
--! offsets in the dynamic memory space. The input address is manipulated with
--! arithmetic operators to gain the output address. The lut file holds the
--! base addresses in the static memory space.
-------------------------------------------------------------------------------
architecture rtl of dynamicBridge is
--! Bridge cycle delay
constant cBridgeCycleDelay : natural := 3;
--! Bridge read path enable all bytes
constant cByteenableAllOnes : std_logic_vector(iBaseSetByteenable'range) :=
(others => cActivated);
--! convert address array into stream
constant cBaseAddressArrayStd : std_logic_vector
((gAddressSpaceCount+1)*cArrayStd32ElementSize-1 downto 0) :=
CONV_STDLOGICVECTOR(gBaseAddressArray, gBaseAddressArray'length);
--! Input address register
signal inAddrReg : std_logic_vector(iBridgeAddress'range);
--! Request rising edge
signal bridgeRequest_rising : std_logic;
--! Input address store strobe
signal inAddrStore : std_logic;
--! Request acknowledge terminal count strobe
signal reqAckTcnt : std_logic;
--! address decoder select signals one hot coded
signal addrDecSelOneHot : std_logic_vector(gAddressSpaceCount-1 downto 0);
--! address decoder select signals binary coded
signal addrDecSelBinary : std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! selected static lut file base offset
signal lutFileBase : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment
signal addrSpaceOffset : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment (unregistered)
signal addrSpaceOffset_unreg : std_logic_vector(inAddrReg'range);
--! Dynamic address offset within selected static space
signal dynamicOffset : std_logic_vector(iBaseSetData'range);
--! Translated address
signal translateAddress : std_logic_vector(maximum(iBaseSetData'high, oBridgeAddress'high) downto inAddrReg'low);
begin
-- assert
assert (cBridgeCycleDelay > 0)
report "Set cBridgeCycleDelay > 0"
severity failure;
-- export
oBridgeSelect <= addrDecSelOneHot;
oBridgeSelectAny <= OR_REDUCE(addrDecSelOneHot);
oBridgeValid <= reqAckTcnt;
oBridgeAddress <= translateAddress(oBridgeAddress'range);
--! Store the input address with the request strobe
storeAddr : process(iRst, iClk)
begin
if iRst = cActivated then
inAddrReg <= (others => cInactivated);
elsif rising_edge(iClk) then
if inAddrStore = cActivated then
inAddrReg <= iBridgeAddress;
end if;
end if;
end process;
--! Get rising edge of request signaling
reqEdge : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iBridgeRequest,
oRising => bridgeRequest_rising,
oFalling => open,
oAny => open
);
inAddrStore <= bridgeRequest_rising;
--! Generate the request acknowledge signal
reqAck : entity work.cnt
generic map (
gCntWidth => logDualis(cBridgeCycleDelay+1),
gTcntVal => cBridgeCycleDelay
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => iBridgeRequest,
iSrst => cInactivated,
oCnt => open,
oTcnt => reqAckTcnt
);
--! Generate Address Decoders
genAddressDecoder : for i in 0 to gAddressSpaceCount-1 generate
insAddressDecoder : entity work.addrDecode
generic map (
gAddrWidth => inAddrReg'length,
gBaseAddr => to_integer(unsigned(gBaseAddressArray(i)(inAddrReg'range))),
gHighAddr => to_integer(unsigned(gBaseAddressArray(i+1)(inAddrReg'range))-1)
)
port map (
iEnable => iBridgeRequest,
iAddress => inAddrReg,
oSelect => addrDecSelOneHot(i)
);
end generate;
--! Convert one hot from address decoder to binary
insBinaryEncoder : entity work.binaryEncoder
generic map (
gDataWidth => gAddressSpaceCount
)
port map (
iOneHot => addrDecSelOneHot,
oBinary => addrDecSelBinary
);
--! select static base address in lut file
insLutFile : entity work.lutFile
generic map (
gLutCount => gAddressSpaceCount,
gLutWidth => cArrayStd32ElementSize,
gLutInitValue => cBaseAddressArrayStd(cBaseAddressArrayStd'left downto cArrayStd32ElementSize)
-- omit high address of last memory map
)
port map (
iAddrRead => addrDecSelBinary,
oData => lutFileBase
);
-- calculate address offset within static space
addrSpaceOffset_unreg <= std_logic_vector(
unsigned(inAddrReg) - unsigned(lutFileBase)
);
--! Registers to break combinational path of lut file output.
regAddrSpace : process(iRst, iClk)
begin
if iRst = cActivated then
addrSpaceOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
addrSpaceOffset <= addrSpaceOffset_unreg;
end if;
end process;
REGFILE : if gUseMemBlock = 0 generate
signal dynamicOffset_unreg : std_logic_vector(dynamicOffset'range);
begin
--! select dynamic base address in register file
insRegFile : entity work.registerFile
generic map (
gRegCount => gAddressSpaceCount
)
port map (
iClk => iClk,
iRst => iRst,
iWriteA => iBaseSetWrite,
iWriteB => cInactivated, -- write port B unused
iByteenableA => iBaseSetByteenable,
iByteenableB => cByteenableAllOnes,
iAddrA => iBaseSetAddress,
iAddrB => addrDecSelBinary,
iWritedataA => iBaseSetData,
oReaddataA => oBaseSetData,
iWritedataB => iBaseSetData, -- write port B unused
oReaddataB => dynamicOffset_unreg
);
regDynOff : process(iRst, iClk)
begin
if iRst = cActivated then
dynamicOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
dynamicOffset <= dynamicOffset_unreg;
end if;
end process;
BASESETACK : oBaseSetAck <= iBaseSetWrite or iBaseSetRead;
end generate REGFILE;
DPRAM : if gUseMemBlock /= 0 generate
-- Clip dpr word width to values of power 2 (e.g. 8, 16, 32)
constant cDprWordWidth : natural := 2**logDualis(iBaseSetData'length);
constant cDprAddrWidth : natural := logDualis(gAddressSpaceCount);
constant cDprReadDel : natural := 1;
type tDprPort is record
write : std_logic;
read : std_logic;
address : std_logic_vector(cDprAddrWidth-1 downto 0);
byteenable : std_logic_vector(cDprWordWidth/8-1 downto 0);
writedata : std_logic_vector(cDprWordWidth-1 downto 0);
readdata : std_logic_vector(cDprWordWidth-1 downto 0);
end record;
signal dprPortA : tDprPort;
signal dprPortA_readAck : std_logic;
signal dprPortB : tDprPort;
begin
--! This combinatoric process assigns base sets to the dpr.
--! The default assignments avoid warnings in synthesize tools.
dprAssign : process (
iBaseSetByteenable,
iBaseSetData
)
begin
--default assignments
dprPortA.byteenable <= (others => cInactivated);
dprPortA.writedata <= (others => cInactivated);
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata <= (others => cInactivated);
dprPortA.byteenable(iBaseSetByteenable'range) <= iBaseSetByteenable;
dprPortA.writedata(iBaseSetData'range) <= iBaseSetData;
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata(iBaseSetData'range) <= iBaseSetData;
end process;
dprPortA.write <= iBaseSetWrite;
dprPortA.read <= iBaseSetRead;
dprPortA.address <= iBaseSetAddress;
oBaseSetData <= dprPortA.readdata(oBaseSetData'range);
dprPortB.write <= cInactivated; --unused
dprPortB.read <= cActivated; --unused
dprPortB.address <= addrDecSelBinary;
dynamicOffset <= dprPortB.readdata(dynamicOffset'range);
insDPRAM: entity work.dpRam
generic map(
gWordWidth => cDprWordWidth,
gNumberOfWords => gAddressSpaceCount
)
port map(
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => dprPortA.write,
iAddress_A => dprPortA.address,
iByteEnable_A => dprPortA.byteenable,
iWritedata_A => dprPortA.writedata,
oReaddata_A => dprPortA.readdata,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => dprPortB.write,
iAddress_B => dprPortB.address,
iByteEnable_B => dprPortB.byteenable,
iWritedata_B => dprPortB.writedata,
oReaddata_B => dprPortB.readdata
);
BASESETACK : oBaseSetAck <= dprPortA.write or dprPortA_readAck;
--! Generate the read acknowledge signal
rdAck : entity work.cnt
generic map (
gCntWidth => logDualis(cDprReadDel+1),
gTcntVal => cDprReadDel
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => dprPortA.read,
iSrst => cInactivated,
oCnt => open,
oTcnt => dprPortA_readAck
);
end generate DPRAM;
-- calculate translated address offset in dynamic space
translateAddress <= std_logic_vector(
unsigned(dynamicOffset) + unsigned(addrSpaceOffset)
);
end rtl;
| gpl-2.0 | 86f54204a4dc813c2b5ef58593b12103 | 0.587145 | 5.090966 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/leak.vhdl | 1 | 12,511 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity leak is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_passive_conductance : in sfixed (-22 downto -53);
exposure_conductance_passive_g : out sfixed (-22 downto -53);
derivedvariable_conductance_passive_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_passive_g_in : in sfixed (-22 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end leak;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of leak is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_conductance_channelg : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_channelg_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component passive
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal passive_Component_done : STD_LOGIC ; signal Exposure_conductance_passive_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
passive_uut : passive
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => passive_Component_done,
param_conductance_conductance => param_conductance_passive_conductance,
requirement_voltage_v => requirement_voltage_v,
Exposure_conductance_g => Exposure_conductance_passive_g_internal,
derivedvariable_conductance_g_out => derivedvariable_conductance_passive_g_out,
derivedvariable_conductance_g_in => derivedvariable_conductance_passive_g_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_conductance_passive_g <= Exposure_conductance_passive_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_conductance_passive_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_conductance_passive_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
derivedvariable_conductance_channelg_next <= resize(( exposure_conductance_passive_g_internal ),-22,-53);
derivedvariable_conductance_geff_next <= resize(( derivedvariable_conductance_channelg_next * param_none_number ),-22,-53);
derivedvariable_current_i_next <= resize(( derivedvariable_conductance_geff_next * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_conductance_channelg <= derivedvariable_conductance_channelg_next;
derivedvariable_conductance_geff <= derivedvariable_conductance_geff_next;
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(passive_component_done,CLK)
begin
if (passive_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | a90e2f2984b710b080cc9b1f7eec35e1 | 0.548397 | 4.060695 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/fft_helpers.vhd | 1 | 3,986 | -- fft_helpers.vhd
--
-- Created on: 13 Jul 2017
-- Author: Fabian Meyer
--
-- This package provides a complex datatype and associated helper functions
-- for easier computation of a FFT. Operations are implemented using fixed
-- point arithmetic.
--
-- This code is mostly based on the sample provided by vapin, but made
-- synthesisable
-- http://vhdlguru.blogspot.de/2011/06/non-synthesisable-vhdl-code-for-8-point.html
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;
use ieee.numeric_std.all;
-- declare package with helper functions for FFT
package fft_helpers is
-- define decimal and fractional length of fixed point numbers
constant DECLEN: natural := 16;
constant FRACLEN: natural := 8;
constant FIXLEN: natural := DECLEN + FRACLEN;
constant FIXZERO: signed(DECLEN+FRACLEN-1 downto 0) := (others => '0');
-- define complex number datatype, which will make the code more readable
type complex is
record
r: signed(DECLEN+FRACLEN-1 downto 0);
i: signed(DECLEN+FRACLEN-1 downto 0);
end record;
constant COMPZERO: complex := (FIXZERO, FIXZERO);
-- array type for complex numbers
type complex_arr is array (natural range <>) of complex;
-- Adds two complex numbers
function add (n1,n2: complex) return complex;
-- Subtracts two complex numbers
function sub (n1,n2: complex) return complex;
-- Multiplies two complex numbers
function mult (n1,n2: complex) return complex;
-- converts two real numbers into a complex
function to_complex(r,i: real) return complex;
end fft_helpers;
package body fft_helpers is
function add (n1,n2: complex) return complex is
variable res: complex;
begin
-- simply use fixed point arithmetic addition
res.r := resize(n1.r + n2.r, DECLEN+FRACLEN);
res.i := resize(n1.i + n2.i, DECLEN+FRACLEN);
return res;
end add;
--subtraction of complex numbers.
function sub(n1,n2: complex) return complex is
variable res: complex;
begin
-- simply use fixed point arithmetic subtraction
res.r := resize(n1.r - n2.r, DECLEN+FRACLEN);
res.i := resize(n1.i - n2.i, DECLEN+FRACLEN);
return res;
end sub;
--multiplication of complex numbers.
function mult(n1,n2: complex) return complex is
-- variable ac: signed(DECLEN+FRACLEN-1 downto 0);
-- variable bd: signed(DECLEN+FRACLEN-1 downto 0);
variable res: complex;
begin
-- complex multiplication: A + jB * C + jD
-- can be calculated as
-- re: (A*C) - (B*D)
-- im: (A*D) + (B*C)
res.r := resize(resize(n1.r * n2.r, DECLEN+FRACLEN) -
resize(n1.i * n2.i, DECLEN+FRACLEN),
DECLEN+FRACLEN);
res.i := resize(resize(n1.r * n2.i, DECLEN+FRACLEN) +
resize(n1.i * n2.r, DECLEN+FRACLEN),
DECLEN+FRACLEN);
-- complex multiplication: A + jB * C + jD
-- can be calculated as
-- re: (A*C) - (B*D)
-- im: (A+B) * (C+D) - (A*C) - (B*D)
-- ac := resize(n1.r * n2.r, DECLEN+FRACLEN);
-- bd := resize(n1.i * n2.i, DECLEN+FRACLEN);
--
-- res.r := resize(ac - bd, DECLEN+FRACLEN);
-- res.i := resize(
-- resize(
-- resize(
-- resize(n1.r + n1.i, DECLEN+FRACLEN) *
-- resize(n2.r + n2.i, DECLEN+FRACLEN),
-- DECLEN+FRACLEN) -
-- ac, DECLEN+FRACLEN) -
-- bd, DECLEN+FRACLEN);
return res;
end mult;
function to_complex(r,i: real) return complex is
variable res: complex;
begin
res.r := signed(to_slv(to_sfixed(r, DECLEN-1, -FRACLEN)));
res.i := signed(to_slv(to_sfixed(i, DECLEN-1, -FRACLEN)));
return res;
end;
end fft_helpers;
| mit | 04f5bbe4227799ff7f1153d665310a35 | 0.591821 | 3.460069 | false | false | false | false |
hoglet67/AtomGodilVideo | src/RAM/VideoRam.vhd | 2 | 1,382 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VideoRam is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(12 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(12 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end VideoRam;
architecture BEHAVIORAL of VideoRam is
-- Shared memory
type ram_type is array (8191 downto 0) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type;
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra(12 downto 0))) := dina;
end if;
douta <= RAM(conv_integer(addra(12 downto 0)));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb(12 downto 0))) := dinb;
end if;
doutb <= RAM(conv_integer(addrb(12 downto 0)));
end if;
end process;
end BEHAVIORAL;
| apache-2.0 | d1dcfb8ba8c7812a529e859e576bbc81 | 0.565123 | 3.571059 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_A/RCA:NTSC Demo Barebones/CPLD Firmware/VGAtonic_Firmware.vhd | 1 | 3,907 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
-- SPI Select (Master is AVR)
AVR_CPLD_EXT_1 : in STD_LOGIC;
-- SPI Pins from Outside World
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD : in STD_LOGIC; -- Active low
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
-- Using this as our SEL pin due to timer issues
AVR_CPLD_EXT_2 : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC := 'Z';
-- NTSC
LUMA : inout STD_LOGIC_VECTOR(3 downto 0);
SYNC : inout STD_LOGIC;
COLORBURST : inout STD_LOGIC;
-- CPLD_GPIO : out STD_LOGIC := '0';
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code for NTSC
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
LUMA : INOUT std_logic_vector(3 downto 0);
SYNC : INOUT std_logic;
COLORBURST : INOUT std_logic;
-- CPLD_GPIO : OUT std_logic;
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and NTSC output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SEL_SPI => AVR_CPLD_EXT_1,
EXT_SCK => EXT_SCK,
EXT_SEL => EXT_SEL_CPLD,
EXT_MOSI => EXT_MOSI,
EXT_MISO => EXT_MISO,
AVR_SCK => AVR_SCK,
AVR_SEL => AVR_CPLD_EXT_2,
AVR_MOSI => AVR_MOSI,
-- AVR_MISO => AVR_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
LUMA => LUMA,
COLORBURST => COLORBURST,
SYNC => SYNC,
-- CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
| mit | 5e60985f466dfcba5368081a3be8c949 | 0.617353 | 2.757234 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_gray_clock_crosser.vhd | 2 | 3,820 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_gray_clock_crosser is
generic
(
WIDTH : integer := 8
);
port
(
-- clock and reset
inclock : in std_logic;
outclock : in std_logic;
inena : in std_logic;
outena : in std_logic;
reset : in std_logic;
-- data input and output
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_gray_clock_crosser is
-- this signal holds the input data converted to gray format
signal gray_data : std_logic_vector(WIDTH - 1 downto 0);
-- a shift register, to carry the gray data across the clock domains avoiding metastability
constant SHIFT_REGISTER_LENGTH : integer := 3;
type shift_register_type is array(integer range <>) of std_logic_vector(WIDTH - 1 downto 0);
signal shift_register : shift_register_type(SHIFT_REGISTER_LENGTH - 1 downto 0);
attribute altera_attribute : string;
attribute altera_attribute OF shift_register: SIGNAL IS "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute preserve: boolean;
attribute preserve of shift_register: signal is true;
-- a register for the output, converted back to binary
signal q_reg : std_logic_vector(WIDTH - 1 downto 0);
begin
-- check generics
assert WIDTH > 0
report "Generic WIDTH must greater than zero"
severity ERROR;
-- convert input to gray format
to_gray : process (inclock, reset)
begin
if reset = '1' then
gray_data <= (others => '0');
elsif inclock'EVENT and inclock = '1' then
if inena = '1' then
gray_data <= data xor ('0' & data(WIDTH - 1 downto 1));
end if;
end if;
end process;
-- shift register to cross clock domains and avoid metastability
shift_reg : process (outclock, reset)
begin
if reset = '1' then
shift_register <= (others => (others => '0'));
elsif outclock'EVENT and outclock = '1' then
--if outena = '1' then
for i in 0 to SHIFT_REGISTER_LENGTH - 2 loop
shift_register(i) <= shift_register(i + 1);
end loop;
shift_register(SHIFT_REGISTER_LENGTH - 1) <= gray_data; -- this statement crosses clock domains
--end if;
end if;
end process;
-- convert the output of the shift register back to binary for output
from_gray : process (outclock, reset)
constant ZEROS : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
variable partial_xor : std_logic_vector(WIDTH - 1 downto 0);
variable i : integer;
begin
if reset = '1' then
q_reg <= (others => '0');
elsif outclock'EVENT and outclock = '1' then
if outena = '1' then
partial_xor := shift_register(0);
i := 1;
while i < WIDTH loop
partial_xor := partial_xor xor (ZEROS(i - 1 downto 0) & shift_register(0)(WIDTH - 1 downto i));
i := i + 1;
end loop;
q_reg <= partial_xor;
end if;
end if;
end process;
-- drive output lines
q <= q_reg;
end architecture rtl;
| mit | af09711c03ab56a7500e4ef1470a586e | 0.693979 | 3.494968 | false | false | false | false |
hoglet67/AtomGodilVideo | src/mouse/MouseRefComp.vhd | 1 | 5,695 | ----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is the structural VHDL code of the
-- Digilent Mouse Reference Component.
-- It instantiates three components:
-- - ps2interface
-- - mouse_controller
-- - resolution_mouse_informer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
entity MouseRefComp is
generic (
MainClockSpeed : integer
);
port (
CLK : in std_logic;
RESOLUTION : in std_logic;
RST : in std_logic;
SWITCH : in std_logic;
LEFT : out std_logic;
MIDDLE : out std_logic;
NEW_EVENT : out std_logic;
RIGHT : out std_logic;
XPOS : out std_logic_vector (9 downto 0);
YPOS : out std_logic_vector (9 downto 0);
ZPOS : out std_logic_vector (3 downto 0);
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic);
end MouseRefComp;
architecture Structural of MouseRefComp is
signal TX_DATA : std_logic_vector (7 downto 0);
signal bitSetMaxX : std_logic;
signal vecValue : std_logic_vector (9 downto 0);
signal bitRead : std_logic;
signal bitWrite : std_logic;
signal bitErr : std_logic;
signal bitSetX : std_logic;
signal bitSetY : std_logic;
signal bitSetMaxY : std_logic;
signal vecRxData : std_logic_vector (7 downto 0);
component mouse_controller
port ( clk : in std_logic;
rst : in std_logic;
read : in std_logic;
write : out std_logic;
err : in std_logic;
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic;
value : in std_logic_vector (9 downto 0);
rx_data : in std_logic_vector (7 downto 0);
tx_data : out std_logic_vector (7 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
xpos : out std_logic_vector (9 downto 0);
ypos : out std_logic_vector (9 downto 0);
zpos : out std_logic_vector (3 downto 0);
new_event : out std_logic);
end component;
component resolution_mouse_informer
port ( clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic;
value : out std_logic_vector (9 downto 0));
end component;
component ps2interface
generic (
MainClockSpeed : integer
);
port ( clk : in std_logic;
rst : in std_logic;
read : out std_logic;
write : in std_logic;
rx_data : out std_logic_vector (7 downto 0);
tx_data : in std_logic_vector (7 downto 0);
busy : out std_logic;
err : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic);
end component;
begin
MouseCtrlInst : mouse_controller
port map (clk=>CLK,
rst=>RST,
read=>bitRead,
write=>bitWrite,
err=>bitErr,
setmax_x=>bitSetMaxX,
setmax_y=>bitSetMaxY,
setx=>bitSetX,
sety=>bitSetY,
value(9 downto 0)=>vecValue(9 downto 0),
rx_data(7 downto 0)=>vecRxData(7 downto 0),
tx_data(7 downto 0)=>TX_DATA(7 downto 0),
left=>LEFT,
middle=>MIDDLE,
right=>RIGHT,
xpos(9 downto 0)=>XPOS(9 downto 0),
ypos(9 downto 0)=>YPOS(9 downto 0),
zpos(3 downto 0)=>ZPOS(3 downto 0),
new_event=>NEW_EVENT);
ResMouseInfInst : resolution_mouse_informer
port map (clk=>CLK,
resolution=>RESOLUTION,
rst=>RST,
switch=>SWITCH,
setmax_x=>bitSetMaxX,
setmax_y=>bitSetMaxY,
setx=>bitSetX,
sety=>bitSetY,
value(9 downto 0)=>vecValue(9 downto 0));
Pss2Inst : ps2interface
generic map (MainClockSpeed => MainClockSpeed)
port map (clk=>CLK,
rst=>RST,
tx_data(7 downto 0)=>TX_DATA(7 downto 0),
read=>bitRead,
write=>bitWrite,
busy=>open,
err=>bitErr,
rx_data(7 downto 0)=>vecRxData(7 downto 0),
ps2_clk=>PS2_CLK,
ps2_data=>PS2_DATA);
end Structural;
| apache-2.0 | f889cfebe6c038d552263e4cad95dc25 | 0.468832 | 4.103026 | false | false | false | false |
s-kostyuk/course_project_csch | final_processor/top.vhd | 1 | 1,422 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 4;
M: integer := 8
);
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
COP : in std_logic;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(2*N-1 downto 0);
IRQ1, IRQ2 : out std_logic
);
end top;
architecture top of top is
component control_unit
port (
clk,rst : in STD_LOGIC;
X: in STD_LOGIC_vector(10 downto 1);
Y: out STD_LOGIC_vector(25 downto 1);
COP : in std_logic);
end component;
component operational_unit port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(25 downto 1);
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
rl, rh : out STD_LOGIC_VECTOR(N-1 downto 0);
x : out STD_LOGIC_vector(10 downto 1);
IRQ1, IRQ2 : out std_logic
);
end component;
signal y : std_logic_vector(25 downto 1);
signal x : std_logic_vector(10 downto 1);
signal nclk : std_logic;
signal rl, rh : std_logic_vector(N-1 downto 0);
begin
nclk <= not clk;
dd1 : control_unit port map (clk=>clk, rst=>rst, x=>x, y=>y, COP=>COP);
dd2 : operational_unit port map (
clk => nclk, rst => rst, d1 => d1, d2 => d2,
y => y, x => x, rl => rl, rh => rh,
IRQ1 => IRQ1, IRQ2 => IRQ2
);
r <= rh & rl;
end top; | mit | c2d60e20ed0d6f5df9ad2e82017959ed | 0.581575 | 2.693182 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_std_logic_vector_delay.vhd | 2 | 2,557 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_std_logic_vector_delay is
generic
(
WIDTH : integer := 1;
DELAY : integer := 0
);
port
(
-- clock, enable and reset
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
-- input and output
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_std_logic_vector_delay is
begin
-- check generics
assert WIDTH > 0
report "Generic WIDTH must be greater than zero"
severity ERROR;
assert DELAY >= 0
report "Generic DELAY must greater than or equal to zero"
severity ERROR;
-- if zero delay is requested, just combinationally pass through
no_delay_gen :
if DELAY = 0 generate
begin
q <= data;
end generate;
-- if one or more cycles of delay have been requested, build a simple
-- shift register and do the delaying
some_delay_gen :
if DELAY > 0 generate
-- shift register, to do the required delaying
type shift_register_type is array(integer range <>) of std_logic_vector(WIDTH - 1 downto 0);
signal shift_register : shift_register_type(DELAY - 1 downto 0);
begin
-- clocked process to update shift register
shift_reg : process (clock, reset)
begin
if reset = '1' then
shift_register <= (others => (others => '0'));
elsif clock'EVENT and clock = '1' then
if ena = '1' then
for i in 0 to DELAY - 2 loop
shift_register(i) <= shift_register(i + 1);
end loop;
shift_register(DELAY - 1) <= data;
end if;
end if;
end process;
-- assign output from end of shift register
q <= shift_register(0);
end generate;
end ;
| mit | ad1def9fba54c165e47af5aa17210789 | 0.70747 | 3.581232 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/based.vhd | 1 | 379 | LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity based is port( sysclk : in std_logic);
end based;
architecture rtl of based is
signal foo,foo2,foo8,foo10,foo11,foo16 : integer;
begin
foo <= 123;
foo2 <= 2#00101101110111#;
foo8 <= 8#0177362#;
foo10<= 10#01234#;
foo11<= 11#01234#;
foo16<= 16#12af#;
end rtl;
| apache-2.0 | 1f11f87977b53b7d7e75c76eaa96b0e4 | 0.693931 | 2.807407 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_combined/top.vhd | 1 | 1,418 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 4;
M: integer := 8
);
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
COP : in std_logic;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(2*N-1 downto 0);
IRQ1, IRQ2 : out std_logic
);
end top;
architecture top of top is
component control_unit
port (
clk,rst : in STD_LOGIC;
X: in STD_LOGIC_vector(10 downto 0);
Y: out STD_LOGIC_vector(25 downto 1));
end component;
component operational_unit port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(25 downto 1);
COP : in std_logic;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
rl, rh : out STD_LOGIC_VECTOR(N-1 downto 0);
x : out STD_LOGIC_vector(10 downto 0);
IRQ1, IRQ2 : out std_logic
);
end component;
signal y : std_logic_vector(25 downto 1);
signal x : std_logic_vector(10 downto 0);
signal nclk : std_logic;
signal rl, rh : std_logic_vector(N-1 downto 0);
begin
nclk <= not clk;
dd1 : control_unit port map (clk=>clk, rst=>rst, x=>x, y=>y);
dd2 : operational_unit port map (
clk => clk, rst => rst, d1 => d1, d2 => d2,
y => y, x => x, rl => rl, rh => rh, COP => COP,
IRQ1 => IRQ1, IRQ2 => IRQ2
);
r <= rh & rl;
end top; | mit | 656892f8462b9d151c461797b25d6955 | 0.582511 | 2.685606 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx-rtl.vhdl | 1 | 10,019 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx-rtl.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:54:44 $
--
--------------------------------------------------------------------------
--
-- Register transfer level architecture of DLX processor.
--
use std.textio.all,
work.images.image_hex,
work.bv_arithmetic.all,
work.dlx_instr.all,
work.alu_types.all;
architecture rtl of dlx is
component alu
port (s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
latch_en : in bit;
func : in alu_func;
zero, negative, overflow : out bit);
end component;
component reg_file
port (a1 : in dlx_reg_addr; -- port1 address
q1 : out dlx_word; -- port1 read data
a2 : in dlx_reg_addr; -- port2 address
q2 : out dlx_word; -- port2 read data
a3 : in dlx_reg_addr; -- port3 address
d3 : in dlx_word; -- port3 write data
write_en : in bit); -- port3 write enable
end component;
component latch
port (d : in dlx_word;
q : out dlx_word;
latch_en : in bit);
end component;
component reg_1_out
port (d : in dlx_word;
q : out dlx_word_bus bus;
latch_en : in bit;
out_en : in bit);
end component;
component reg_2_out
port (d : in dlx_word;
q1, q2 : out dlx_word_bus bus;
latch_en : in bit;
out_en1, out_en2 : in bit);
end component;
component reg_3_out
port (d : in dlx_word;
q1, q2, q3 : out dlx_word_bus bus;
latch_en : in bit;
out_en1, out_en2, out_en3 : in bit);
end component;
component reg_2_1_out
port (d : in dlx_word;
q1, q2 : out dlx_word_bus bus;
q3 : out dlx_word;
latch_en : in bit;
out_en1, out_en2 : in bit);
end component;
component mux2
port (i0, i1 : in dlx_word;
y : out dlx_word;
sel : in bit);
end component;
component ir
port (d : in dlx_word; -- instruction input from memory
immed_q1, immed_q2 : out dlx_word_bus bus;
ir_out : out dlx_word; -- instruction output to control
latch_en : in bit;
immed_sel1, immed_sel2 : in immed_size; -- select 16-bit or 26-bit immed
immed_unsigned1, immed_unsigned2 : in bit; -- extend immed unsigned/signed
immed_en1, immed_en2 : in bit); -- enable immed const outputs
end component;
component controller
port (phi1, phi2 : in bit;
reset : in bit;
halt : out bit;
width : out mem_width;
write_enable : out bit;
mem_enable : out bit;
ifetch : out bit;
ready : in bit;
alu_latch_en : out bit;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in bit;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
reg_write : out bit;
c_latch_en : out bit;
a_latch_en, a_out_en : out bit;
b_latch_en, b_out_en : out bit;
temp_latch_en, temp_out_en1, temp_out_en2 : out bit;
iar_latch_en, iar_out_en1, iar_out_en2 : out bit;
pc_latch_en, pc_out_en1, pc_out_en2 : out bit;
mar_latch_en, mar_out_en1, mar_out_en2 : out bit;
mem_addr_mux_sel : out bit;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
mdr_mux_sel : out bit;
ir_latch_en : out bit;
ir_immed_sel1, ir_immed_sel2 : out immed_size;
ir_immed_unsigned1, ir_immed_unsigned2 : out bit;
ir_immed_en1, ir_immed_en2 : out bit;
current_instruction : in dlx_word;
const1, const2 : out dlx_word_bus bus);
end component;
signal s1_bus, s2_bus : dlx_word_bus;
signal dest_bus : dlx_word;
signal alu_latch_en : bit;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : bit;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : dlx_reg_addr;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal reg_write : bit;
signal a_out_en, a_latch_en : bit;
signal b_out_en, b_latch_en : bit;
signal c_latch_en : bit;
signal temp_out_en1, temp_out_en2, temp_latch_en : bit;
signal iar_out_en1, iar_out_en2, iar_latch_en : bit;
signal pc_out_en1, pc_out_en2, pc_latch_en : bit;
signal pc_to_mem : dlx_word;
signal mar_out_en1, mar_out_en2, mar_latch_en : bit;
signal mar_to_mem : dlx_word;
signal mem_addr_mux_sel : bit;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : bit;
signal mdr_in : dlx_word;
signal mdr_mux_sel : bit;
signal current_instruction : dlx_word;
signal ir_latch_en : bit;
signal ir_immed_sel1, ir_immed_sel2 : immed_size;
signal ir_immed_unsigned1, ir_immed_unsigned2 : bit;
signal ir_immed_en1, ir_immed_en2 : bit;
begin
the_alu : alu
port map (s1 => s1_bus, s2 => s2_bus, result => dest_bus,
latch_en => alu_latch_en, func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow);
the_reg_file : reg_file
port map (a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write);
c_reg : latch
port map (d => dest_bus, q => reg_file_in, latch_en => c_latch_en);
a_reg : reg_1_out
port map (d => reg_file_out1, q => s1_bus,
latch_en => a_latch_en, out_en => a_out_en);
b_reg : reg_1_out
port map (d => reg_file_out2, q => s2_bus,
latch_en => b_latch_en, out_en => b_out_en);
temp_reg : reg_2_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
latch_en => temp_latch_en,
out_en1 => temp_out_en1, out_en2 => temp_out_en2);
iar_reg : reg_2_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
latch_en => iar_latch_en,
out_en1 => iar_out_en1, out_en2 => iar_out_en2);
pc_reg : reg_2_1_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => pc_to_mem,
latch_en => pc_latch_en,
out_en1 => pc_out_en1, out_en2 => pc_out_en2);
mar_reg : reg_2_1_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => mar_to_mem,
latch_en => mar_latch_en,
out_en1 => mar_out_en1, out_en2 => mar_out_en2);
mem_addr_mux : mux2
port map (i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel);
mdr_reg : reg_3_out
port map (d => mdr_in, q1 => s1_bus, q2 => s2_bus, q3 => d,
latch_en => mdr_latch_en,
out_en1 => mdr_out_en1, out_en2 => mdr_out_en2,
out_en3 => mdr_out_en3);
mdr_mux : mux2
port map (i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel);
instr_reg : ir
port map (d => d, immed_q1 => s1_bus, immed_q2 => s2_bus,
ir_out => current_instruction,
latch_en => ir_latch_en,
immed_sel1 => ir_immed_sel1, immed_sel2 => ir_immed_sel2,
immed_unsigned1 => ir_immed_unsigned1,
immed_unsigned2 => ir_immed_unsigned2,
immed_en1 => ir_immed_en1, immed_en2 => ir_immed_en2);
the_controller : controller
port map (phi1, phi2, reset, halt,
width, write_enable, mem_enable, ifetch, ready,
alu_latch_en, alu_function, alu_zero, alu_negative, alu_overflow,
reg_s1_addr, reg_s2_addr, reg_dest_addr, reg_write,
c_latch_en, a_latch_en, a_out_en, b_latch_en, b_out_en,
temp_latch_en, temp_out_en1, temp_out_en2,
iar_latch_en, iar_out_en1, iar_out_en2,
pc_latch_en, pc_out_en1, pc_out_en2,
mar_latch_en, mar_out_en1, mar_out_en2, mem_addr_mux_sel,
mdr_latch_en, mdr_out_en1, mdr_out_en2,
mdr_out_en3, mdr_mux_sel,
ir_latch_en, ir_immed_sel1, ir_immed_sel2,
ir_immed_unsigned1, ir_immed_unsigned2, ir_immed_en1, ir_immed_en2,
current_instruction, s1_bus, s2_bus);
debug_s1 : if debug generate
s1_monitor : process (s1_bus)
variable L : line;
begin
write(L, tag);
write(L, string'(" s1_monitor: "));
write(L, image_hex(s1_bus));
writeline(output, L);
end process s1_monitor;
end generate;
debug_s2 : if debug generate
s2_monitor : process (s2_bus)
variable L : line;
begin
write(L, tag);
write(L, string'(" s2_monitor: "));
write(L, image_hex(s2_bus));
writeline(output, L);
end process s2_monitor;
end generate;
debug_dest : if debug generate
dest_monitor : process (dest_bus)
variable L : line;
begin
write(L, tag);
write(L, string'(" dest_monitor: "));
write(L, image_hex(dest_bus));
writeline(output, L);
end process dest_monitor;
end generate;
end rtl;
| apache-2.0 | 977d5071e7ffe1be7385a1fe2ea2126d | 0.55784 | 3.056437 | false | false | false | false |
dangpzanco/sistemas-digitais | desloca_esquerda.vhd | 1 | 771 | library ieee;
use ieee.std_logic_1164.all;
entity desloca_esquerda is port (
CLK, RST, EN: in std_logic;
sr_in: in std_logic_vector(7 downto 0);
sr_out: out std_logic_vector(7 downto 0);
FlagM: out std_logic_vector(3 downto 0)
);
end desloca_esquerda;
architecture behv of desloca_esquerda is
signal sr: std_logic_vector(7 downto 0);
begin
process(CLK, EN, sr_in)
begin
if RST = '0' then
sr <= (others => '0');
elsif (CLK'event and CLK = '1') then
if EN = '1' then
sr(7 downto 1) <= sr_in(6 downto 0);
sr(0) <= '0';
end if;
end if;
end process;
FlagM(3) <= not (sr(7) or sr(6) or sr(5) or sr(4) or sr(3) or sr(2) or sr(1) or sr(0));
FlagM(2) <= sr(7) or sr(6);
FlagM(1) <= '0';
FlagM(0) <= sr(7);
sr_out <= sr;
end behv;
| mit | 611204c79848ed798bf723606b8c41c2 | 0.601816 | 2.336364 | false | false | false | false |
epall/Computer.Build | templates/alu.vhdl | 1 | 1,692 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY alu IS
GENERIC ( DATA_WIDTH : integer := 8 );
PORT(
clock : IN std_logic;
data_in : IN std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : OUT std_logic_vector(DATA_WIDTH - 1 downto 0);
op : IN std_logic_vector(2 downto 0);
wr_a : IN std_logic;
wr_b : IN std_logic;
rd : IN std_logic;
condition : OUT std_logic
);
END alu;
ARCHITECTURE arch OF alu IS
SIGNAL operand_a : SIGNED(DATA_WIDTH-1 downto 0);
SIGNAL operand_b : SIGNED(DATA_WIDTH-1 downto 0);
SIGNAL result : SIGNED(DATA_WIDTH-1 downto 0);
BEGIN
WITH rd SELECT
data_out <= std_logic_vector(result) WHEN '1',
"ZZZZZZZZ" WHEN OTHERS;
PROCESS(op, operand_a, operand_b)
BEGIN
condition <= '0';
result <= "00000000";
CASE op IS
WHEN "000" =>
result <= operand_a;
WHEN "001" =>
result <= operand_a and operand_b;
WHEN "010" =>
result <= operand_a or operand_b;
WHEN "011" =>
result <= not operand_a;
WHEN "100" =>
result <= operand_a + operand_b;
WHEN "101" =>
result <= operand_a - operand_b;
WHEN "110" =>
IF operand_a = operand_b THEN
condition <= '1';
END IF;
WHEN "111" =>
IF operand_a < operand_b THEN
condition <= '1';
END IF;
END CASE;
END PROCESS;
PROCESS(clock)
BEGIN
IF clock'EVENT AND clock='0' THEN
IF wr_a = '1' THEN
operand_a <= signed(data_in);
ELSIF wr_b = '1' THEN
operand_b <= signed(data_in);
END IF;
END IF;
END PROCESS;
END arch;
| mit | d36b440f47e30f7c39742f8b56a2a7c2 | 0.556147 | 3.377246 | false | false | false | false |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@p@b@s@l@a@v@e@s/_primary.vhd | 3 | 1,233 | library verilog;
use verilog.vl_types.all;
entity MSS_APBSLAVES is
generic(
AWIDTH : integer := 12;
DEPTH : integer := 256;
DWIDTH : integer := 32;
INITFILE : string := " ";
ID : integer := 0;
TPD : integer := 0;
ENFUNC : integer := 0;
DEBUG : integer := 1
);
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PSEL : in vl_logic_vector(15 downto 0);
PADDR : in vl_logic_vector;
PWDATA : in vl_logic_vector;
PRDATA : out vl_logic_vector;
PREADY : out vl_logic;
PSLVERR : out vl_logic;
GPIO_IN : in vl_logic_vector(31 downto 0);
GPIO_OUT : out vl_logic_vector(31 downto 0);
GPIO_OE : out vl_logic_vector(31 downto 0);
GPIO_INT : out vl_logic_vector(31 downto 0);
SOFTRESETS : in vl_logic_vector(10 downto 0)
);
end MSS_APBSLAVES;
| gpl-3.0 | 8192bf84b07a708148f1b3ad19f7dd94 | 0.429846 | 3.990291 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_one_bit_delay.vhd | 2 | 2,222 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity alt_vipvfr131_common_one_bit_delay is
generic
(
DELAY : integer := 0
);
port
(
-- clock, enable and reset
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
-- input and output
data : in std_logic;
q : out std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_one_bit_delay is
begin
-- check generics
assert DELAY >= 0
report "Generic DELAY must greater than or equal to zero"
severity ERROR;
-- if zero delay is requested, just combinationally pass through
no_delay_gen :
if DELAY = 0 generate
begin
q <= data;
end generate;
-- if one or more cycles of delay have been requested, build a simple
-- shift register and do the delaying
some_delay_gen :
if DELAY > 0 generate
-- shift register, to do the required delaying
signal shift_register : std_logic_vector(DELAY - 1 downto 0);
begin
-- clocked process to update shift register
shift_reg : process (clock, reset)
begin
if reset = '1' then
shift_register <= (others => '0');
elsif clock'EVENT and clock = '1' then
if ena = '1' then
for i in 0 to DELAY - 2 loop
shift_register(i) <= shift_register(i + 1);
end loop;
shift_register(DELAY - 1) <= data;
end if;
end if;
end process;
-- assign output from end of shift register
q <= shift_register(0);
end generate;
end ;
| mit | 7796f49089b2e3bfec1955d37eed7e60 | 0.70432 | 3.601297 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_B/Widescreen Version Firmware/CPLD Firmware Widescreen/SPI_Slave.vhd | 1 | 5,306 | -----------------------------------------------------------------------------------
-- Top SPI Speed Calculation for Widescreen (Please check my math - no warranties implied)
-- To determine top speed, look at worst case and count user clocks
-- 1) SPI_CACHE_FULL_FLAG goes high too late for tSU to react
-- 2) CACHE_FULL_FLAG(0) = '1'
-- 3) CACHE_FULL_FLAG(1) = '1'. User Logic sends reset signal.
--
--
-- We can accept up to 7 bits of the full SPI (plus a half clock minus setup
-- time, actually, due to "if (ACK_SPI_BYTE = '1')") based on our code -
-- so 7.5 clocks of SPI cannot be faster than 3 clocks of User Logic. We write
-- the inverse to convert to time, as time is 1/frequency:
--
-- (3/7.5)tUSER < tSPI
--
-- "How much" less is determined by the setup time on the user logic flip flop,
-- so we can constrain it further, and add back the setup time factor:
--
-- (7.5 * tSPI) > (3 * tUSER) + tSU + tSU
-- tSPI > (3*tUSER + 2*tSU)/7.5
--
-- Example: For a 30 MHz User Clock and a Xilinx XC95144XL-10 with an internal
-- logic setup time of 3.0 ns:
--
-- tSPI > ((3 * 33.3333) +(3.0 + 3.0))/7.5 = 14.13333 ns
-- For that part combination and our code, SPI speed shouldn't exceed
-- 70.754 MHz...
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_Slave is
Port (
--------------------------------------------------------
-- SPI Declarations --
--------------------------------------------------------
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
-- One byte FIFO
SPI_DATA_CACHE : out STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- Asynchronous flags for signals to display logic
SPI_CACHE_FULL_FLAG : out STD_LOGIC := '0';
SPI_CMD_RESET_FLAG : out STD_LOGIC := '0';
-- Async Flags returned from user logic
ACK_USER_RESET : in STD_LOGIC;
ACK_SPI_BYTE : in STD_LOGIC
);
end SPI_Slave;
architecture Behavioral of SPI_Slave is
-- Temporary Storage for SPI (Sneaky: cheat by one bit out of 8 to save a flip-flop)
signal SPI_DATA_REG : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
-- Counter for our receiver
signal SCK_COUNTER : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal SCK : STD_LOGIC := '0';
signal SEL : STD_LOGIC := '0';
signal MOSI : STD_LOGIC := '0';
begin
--SEL <= (not SEL_SPI or EXT_SEL) and (SEL_SPI or AVR_SEL); -- Normally High, when SEL_SPI = 0 AVR can drive low.
--SCK <= (not SEL_SPI and AVR_SCK) or (SEL_SPI and EXT_SCK);
--MOSI <= (not SEL_SPI and AVR_MOSI) or (SEL_SPI and EXT_MOSI);
-- Code for SPI receiver
SPI_Logic: process (SEL_SPI, SCK, SEL, ACK_USER_RESET, ACK_SPI_BYTE)
begin
if (SEL_SPI = '1') then
SEL <= AVR_SEL;
SCK <= AVR_SCK;
MOSI <= AVR_MOSI;
else
SEL <= EXT_SEL;
SCK <= EXT_SCK;
MOSI <= EXT_MOSI;
end if;
-- Code to handle 'Mode Reset' in the User Logic
if (ACK_USER_RESET = '1') then -- User Logic acknowledges it was reset
SPI_CMD_RESET_FLAG <= '0';
else -- User doesn't currently acknowledge a reset
if (rising_edge(SEL)) then -- CPLD was just deselected
SPI_CMD_RESET_FLAG <= '1';
end if;
end if;
-- Code to handle our SPI arbitration, reading, and clocking
if (ACK_SPI_BYTE = '1') then -- User Logic acknowledges receiving a byte
-- Lower the Cache Full flag
SPI_CACHE_FULL_FLAG <= '0';
-- If we continue clocking while the user logic is reacting,
-- put it into our data register. This is the logic
-- which limits the top speed of the logic - but usually you'll be
-- hardware limited.
if (rising_edge(SCK)) then
if (SEL = '0') then
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
end if;
else -- NOT currently acknowledging a byte received RISING EDGE
-- Normal, conventional, everyday, typical, average SPI logic begins.
if (rising_edge(SCK)) then
-- Our CPLD is selected
if (SEL = '0') then
-- If we've just received a whole byte...
if (SCK_COUNTER = "111") then
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
-- Put the received byte into the single entry FIFO
SPI_DATA_CACHE <= SPI_DATA_REG(6 downto 0) & MOSI;
-- To: User Logic... "You've got mail."
SPI_CACHE_FULL_FLAG <= '1';
-- We're not full yet so the bits will keep coming
else
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
-- CPLD is NOT selected
else
-- Reset counter, register
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
end if; -- End CPLD Selected
end if; -- End Rising SCK edge
end if; -- end Byte Received
end process; -- end SPI
end Behavioral; | mit | eef1a709d00b4d16b21a4e6ad95f13c5 | 0.575952 | 3.241295 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/parallelInterfaceRtl.vhd | 2 | 16,742 | -------------------------------------------------------------------------------
--! @file parallelInterfaceRtl.vhd
--
--! @brief Parallel Interface for Host Interface
--
--! @details This is the parallel interface implementation for
--! the host interface.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity parallelInterface is
generic (
--! Data bus width
gDataWidth : natural := 16;
--! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE)
gMultiplex : natural := 0
);
port (
-- Parallel Interface
--! Chipselect
iParHostChipselect : in std_logic := cInactivated;
--! Read strobe
iParHostRead : in std_logic := cInactivated;
--! Write strobe
iParHostWrite : in std_logic := cInactivated;
--! Address Latch enable (Multiplexed only)
iParHostAddressLatchEnable : in std_logic := cInactivated;
--! High active Acknowledge
oParHostAcknowledge : out std_logic := cInactivated;
--! Byteenables
iParHostByteenable : in std_logic_vector(gDataWidth/cByte-1 downto 0) := (others => cInactivated);
--! Address bus (Demultiplexed, word-address)
iParHostAddress : in std_logic_vector(15 downto 0) := (others => cInactivated);
--! Data bus out (Demultiplexed)
oParHostData : out std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Data bus in (Demultiplexed)
iParHostData : in std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Data bus outenable (Demultiplexed)
oParHostDataEnable : out std_logic;
--! Address/Data bus out (Multiplexed, word-address))
oParHostAddressData : out std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Address/Data bus in (Multiplexed, word-address))
iParHostAddressData : in std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Address/Data bus outenable (Multiplexed, word-address))
oParHostAddressDataEnable : out std_logic;
-- Clock/Reset sources
--! Clock Source input
iClk : in std_logic:= cInactivated;
--! Reset Source input
iRst : in std_logic:= cInactivated;
-- Memory Mapped Slave for Host
--! MM slave host address
oHostAddress : out std_logic_vector(16 downto 2) := (others => cInactivated);
--! MM slave host byteenable
oHostByteenable : out std_logic_vector(3 downto 0) := (others => cInactivated);
--! MM slave host read
oHostRead : out std_logic := cInactivated;
--! MM slave host readdata
iHostReaddata : in std_logic_vector(31 downto 0) := (others => cInactivated);
--! MM slave host write
oHostWrite : out std_logic := cInactivated;
--! MM slave host writedata
oHostWritedata : out std_logic_vector(31 downto 0) := (others => cInactivated);
--! MM slave host waitrequest
iHostWaitrequest : in std_logic := cInactivated
);
end parallelInterface;
architecture rtl of parallelInterface is
-- address register to store the address populated to the interface
signal addressRegister : std_logic_vector(iParHostAddress'range);
-- register clock enable
signal addressRegClkEnable : std_logic;
-- byteenable register to store byteenable qualifiers
signal byteenableRegister : std_logic_vector(gDataWidth/cByte-1 downto 0);
-- register clock enable
signal byteenableRegClkEnable : std_logic;
-- write data register to store the data populated to the interface
signal writeDataRegister : std_logic_vector(gDataWidth-1 downto 0);
-- register clock enable
signal writeDataRegClkEnable : std_logic;
-- read data register to store the read data populated to the host
signal readDataRegister : std_logic_vector(gDataWidth-1 downto 0);
signal readDataRegister_next : std_logic_vector(gDataWidth-1 downto 0);
-- synchronized signals
signal hostChipselect : std_logic;
signal hostWrite : std_logic;
signal hostWrite_noCs : std_logic;
signal hostRead : std_logic;
signal hostRead_noCs : std_logic;
signal hostAle : std_logic;
signal hostAle_noCs : std_logic;
signal hostAle_noCsEdge : std_logic;
signal hostDataEnable : std_logic;
signal hostDataEnable_reg : std_logic;
signal hostAck : std_logic;
signal hostAck_reg : std_logic;
-- fsm
type tFsm is (sIdle, sDo, sWait);
signal fsm : tFsm;
-- timeout
constant cCountWidth : natural := 4;
signal count : std_logic_vector(cCountWidth-1 downto 0);
alias countTc : std_logic is count(cCountWidth-1);
signal countEn : std_logic;
signal countRst : std_logic;
constant cCountWrAckAct : std_logic_vector(count'range) := "0000";
constant cCountWrAckDea : std_logic_vector(count'range) := "0001";
constant cCountRdAckAct : std_logic_vector(count'range) := "0001";
constant cCountRdAckDea : std_logic_vector(count'range) := "0010";
constant cCountRdEnAct : std_logic_vector(count'range) := "0000";
constant cCountRdEnDea : std_logic_vector(count'range) := "0011";
begin
--! The processes describe the register, which store the unsynchronized
--! inputs!
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
addressRegister <= (others => cInactivated);
byteenableRegister <= (others => cInactivated);
writeDataRegister <= (others => cInactivated);
readDataRegister <= (others => cInactivated);
hostDataEnable_reg <= cInactivated;
hostAck_reg <= cInactivated;
else
hostDataEnable_reg <= hostDataEnable;
hostAck_reg <= hostAck;
if byteenableRegClkEnable = cActivated then
byteenableRegister <= iParHostByteenable;
end if;
if addressRegClkEnable = cActivated then
if gMultiplex = 0 then
addressRegister <= iParHostAddress;
else
addressRegister <= iParHostAddressData;
end if;
end if;
if writeDataRegClkEnable = cActivated then
if gMultiplex = 0 then
writeDataRegister <= iParHostData;
else
writeDataRegister <= iParHostAddressData;
end if;
end if;
if iHostWaitrequest = cInactivated and hostRead = cActivated then
readDataRegister <= readDataRegister_next;
end if;
end if;
end if;
end process;
oHostAddress <= addressRegister(15 downto 1);
oParHostDataEnable <= hostDataEnable_reg;
oParHostAddressDataEnable <= hostDataEnable_reg;
oParHostAcknowledge <= hostAck_reg;
oParHostAddressData <= readDataRegister;
oParHostData <= readDataRegister;
countRst <= cActivated when fsm = sIdle else cInactivated;
countEn <= cActivated when fsm = sWait else cInactivated;
--! combinatoric process for ack and output enable generation
combProc : process (
count,
hostWrite,
hostRead,
fsm
)
begin
-- default assignments to avoid unwanted latches
hostAck <= cInactivated;
hostDataEnable <= cInactivated;
if fsm = sWait then
if hostRead = cActivated then
-- activate ack signal for read
if count >= cCountRdAckAct and count <= cCountRdAckDea then
hostAck <= cActivated;
end if;
-- activate data output for read
if count >= cCountRdEnAct and count <= cCountRdEnDea then
hostDataEnable <= cActivated;
end if;
elsif hostWrite = cActivated then
-- activate ack signal for write
if count >= cCountWrAckAct and count <= cCountWrAckDea then
hostAck <= cActivated;
end if;
end if;
end if;
end process;
--! Fsm to control access and timeout counter
fsmProc : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
fsm <= sIdle;
addressRegClkEnable <= cInactivated;
byteenableRegClkEnable <= cInactivated;
writeDataRegClkEnable <= cInactivated;
oHostWrite <= cInactivated;
oHostRead <= cInactivated;
count <= (others => cInactivated);
else
if countRst = cActivated then
count <= (others => cInactivated);
elsif countEn = cActivated and countTc /= cActivated then
count <= std_logic_vector(unsigned(count) + 1);
end if;
--defaults
addressRegClkEnable <= cInactivated;
byteenableRegClkEnable <= cInactivated;
writeDataRegClkEnable <= cInactivated;
oHostWrite <= cInactivated;
oHostRead <= cInactivated;
if hostAle = cActivated and gMultiplex /= 0 then
addressRegClkEnable <= cActivated;
end if;
case fsm is
when sIdle =>
if hostRead = cActivated or hostWrite = cActivated then
fsm <= sDo;
if gMultiplex = 0 then
addressRegClkEnable <= cActivated;
end if;
byteenableRegClkEnable <= cActivated;
writeDataRegClkEnable <= hostWrite;
end if;
when sDo =>
oHostRead <= hostRead;
oHostWrite <= hostWrite;
if iHostWaitrequest = cInactivated then
fsm <= sWait;
oHostRead <= cInactivated;
oHostWrite <= cInactivated;
end if;
when sWait =>
if countTc = cActivated then
fsm <= sIdle;
end if;
end case;
end if;
end if;
end process;
genHostBusDword : if gDataWidth = cDword generate
begin
oHostByteenable <= byteenableRegister;
oHostWritedata <= writeDataRegister;
readDataRegister_next <= iHostReaddata;
end generate;
genHostBusWord : if gDataWidth = cWord generate
begin
oHostWritedata <= writeDataRegister & writeDataRegister;
busCombProc : process (
byteenableRegister,
addressRegister,
iHostReaddata
)
begin
--default assignments (to avoid evil latches)
oHostByteenable <= (others => cInactivated);
readDataRegister_next <= (others => cInactivated);
-- assign byteenable to lower/upper word
for i in gDataWidth/8-1 downto 0 loop
if addressRegister(addressRegister'right) = cActivated then
-- upper word is selected
oHostByteenable(cWord/cByte+i) <= byteenableRegister(i);
else
-- lower word is selected
oHostByteenable(i) <= byteenableRegister(i);
end if;
end loop;
-- assign lower/upper word to output
for i in gDataWidth-1 downto 0 loop
if addressRegister(addressRegister'right) = cActivated then
-- upper word is selected
readDataRegister_next(i) <= iHostReaddata(cWord+i);
else
-- lower word is selected
readDataRegister_next(i) <= iHostReaddata(i);
end if;
end loop;
end process;
end generate;
-- synchronize all available control signals
syncChipselect : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostChipselect,
oSync => hostChipselect
);
syncWrite : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostWrite,
oSync => hostWrite_noCs
);
hostWrite <= hostChipselect and hostWrite_noCs;
syncRead : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostRead,
oSync => hostRead_noCs
);
hostRead <= hostChipselect and hostRead_noCs;
genSyncAle : if gMultiplex /= 0 generate
begin
syncAle : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostAddressLatchEnable,
oSync => hostAle_noCs
);
edgeAle : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => hostAle_noCs,
oRising => hostAle_noCsEdge,
oFalling => open,
oAny => open
);
hostAle <= hostChipselect and hostAle_noCsEdge;
end generate;
end rtl;
| gpl-2.0 | 8bb1ff3615f0a54c3f7f2c36a15ccb4d | 0.551009 | 5.509049 | false | false | false | false |
fgr1986/ddr_MIG_ctrl_interface | src/hdl/example_top.vhd | 1 | 15,152 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic (
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC_TEST : string := "OFF";
RANKS : integer := 1;
-- # of Ranks.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
TCQ : integer := 100;
DRAM_TYPE : string := "DDR2";
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant DATA_WIDTH : integer := 16;
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
signal s_init_calibration_complete : std_logic;
-- Start of User Design memory_ctrl component
component memory_ctrl
port
(-- Clock in ports
clk_100MHz_i : in std_logic;
rstn_i : in std_logic;
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface signals
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
begin
--***************************************************************************
cmp_memory_ctrl : entity work.memory_ctrl
port map (
clk_100MHz_i => sys_clk_i,
rstn_i => sys_rst,
init_calib_complete_o => s_init_calibration_complete,
-- DDR2 interface signals
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n );
init_calib_complete <= s_init_calibration_complete;
tg_compare_error <= '0';
end architecture arch_example_top;
| gpl-3.0 | 835efe16e1bcf4c13f516bc1ae85f1ae | 0.449314 | 4.773787 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/butterfly.vhd | 1 | 1,481 | -- butterfly.vhd
--
-- Created on: 13 Jul 2017
-- Author: Fabian Meyer
--
-- Butterfly component for the FFT.
library ieee;
library work;
use ieee.std_logic_1164.all;
use work.fft_helpers.all;
entity butterfly is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din1: in complex; -- first complex in val
din2: in complex; -- second complex in val
w: in complex; -- twiddle factor
dout1: out complex; -- first complex out val
dout2: out complex); -- second complex out val
end butterfly;
architecture behavioral of butterfly is
begin
process(rst, clk) is
variable tmp: complex := COMPZERO;
begin
if rst = RSTDEF then
dout1 <= COMPZERO;
dout2 <= COMPZERO;
elsif rising_edge(clk) then
if swrst = RSTDEF then
dout1 <= COMPZERO;
dout2 <= COMPZERO;
elsif en = '1' then
-- do butterfly Operation
-- dout1 = din1 + w * din2
-- dout2 = din1 - w * din2
tmp := mult(w, din2);
dout1 <= add(din1, tmp);
dout2 <= sub(din1, tmp);
end if;
end if;
end process;
end behavioral;
| mit | 2589c894ffc66a0df835328f0485a59c | 0.53815 | 3.907652 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_signed_mul/operational_unit.vhd | 1 | 2,471 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(12 downto 1);
d1 : in STD_LOGIC_VECTOR(N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r:out STD_LOGIC_VECTOR(2*N-1 downto 0);
x:out STD_LOGIC_vector(4 downto 1)
);
end operational_unit;
architecture operational_unit of operational_unit is
signal A,Ain: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal B,Bin: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal CnT, CnTin: std_logic_vector(7 downto 0);
signal C, Cin: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal overflow, carry: std_logic;
signal of_in, cf_in: std_logic;
signal of_sum, cf_sum: std_logic;
signal sum_result: std_logic_vector(N-1 downto 0);
signal TgB, TgBin: std_logic;
component adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end component;
begin
process(clk,rst)is
begin
if rst='0' then
a<=(others=>'0');
b<=(others=>'0');
TgB<='0';
overflow<='0';
Carry <= '0';
CnT<=(others=>'0');
elsif rising_edge(clk)then
A<=Ain;B<=Bin ;CnT <= CnTin; C <= Cin; TgB <= TgBin;
Overflow <= of_in;
Carry <= cf_in;
end if;
end process;
-- Ïîäêëþ÷åíèå ñóììàòîðà
SUM : adder port map(A => C, B => A(N-1 downto 0), Cin => '0', Cout => cf_sum, overflow => of_sum, S => sum_result);
ain<= D1 when y(1)='1'
else a;
bin<= D2 when y(2) = '1'
else C(0) & B(N-1 downto 1) when y(7) = '1'
else b;
Cin <= (others=>'0') when y(3)='1'
else sum_result when y(5) = '1'
else carry & C(N-1 downto 1) when y(9) = '1'
else C(N-1) & C(N-1 downto 1) when y(10) = '1'
else C + not A + 1 when y(11) = '1'
else C;
CnTin <= conv_std_logic_vector(N, 8) when y(4) = '1'
else CnT - 1 when y(8) = '1'
else CnT;
TgBin <= B(0) when y(6) = '1'
else TgB;
R <= C & B when y(12) = '1'
else (others => 'Z');
cf_in <= cf_sum when y(5) = '1'
else carry;
of_in <= of_sum when y(5) = '1'
else overflow;
x(1) <= '1' when B(0) = '1' else '0';
x(2) <= '1' when overflow = '1' else '0';
x(3) <= '1' when CnT = 0 else '0';
x(4) <= '1' when TgB = '1' else '0';
end operational_unit; | mit | e0d6452eb2f8a4ded6512eb1217794a4 | 0.569405 | 2.413086 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_fifo_usedw_calculator.vhd | 2 | 13,582 | -- Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_fifo_usedw_calculator is
generic
(
WIDTH : integer := 8;
DEPTH : integer := 9;
READ_TO_WRITE_DELAY : integer := 3;
WRITE_TO_READ_DELAY : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE
);
port
(
-- clocks, enables and reset
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
-- triggers
wrreq : in std_logic;
rdreq : in std_logic;
-- information signals calculated (write side)
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
-- information signals calculated (read side)
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_fifo_usedw_calculator is
-- internal registers for the fullness/emptiness monitoring output ports
signal rdusedw_reg : unsigned(WIDTH - 1 downto 0);
signal wrusedw_reg : unsigned(WIDTH - 1 downto 0);
signal full_reg : std_logic;
signal almost_full_reg : std_logic;
signal empty_reg : std_logic;
signal almost_empty_reg : std_logic;
begin
-- check generics
assert WIDTH > 0
report "Generic WIDTH must greater than zero"
severity ERROR;
assert READ_TO_WRITE_DELAY >= 0
report "Generic READ_TO_WRITE_DELAY must greater than or equal to zero"
severity ERROR;
assert WRITE_TO_READ_DELAY >= 0
report "Generic WRITE_TO_READ_DELAY must greater than or equal to zero"
severity ERROR;
-- in single clock mode, just delay the signals using shift registers and
-- update rdusedw and wrusedw accordingly
-- if both delays are zero, rdusedw and wrusedw will be the same, however
-- we need do nothing about this because any synthesis tool will fold such
-- obvious bits of identical logic together
single_clock_gen :
if CLOCKS_ARE_SAME generate
-- delayed (possibly by zero cycles!) versions of rdreq and wrreq
signal rdreq_delay, wrreq_delay : std_logic;
signal wrreq_to_delayer : std_logic;
begin
-- delaying unit for read
rdreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => READ_TO_WRITE_DELAY
)
port map
(
clock => rdclock,
ena => rdena,
reset => reset,
data => rdreq,
q => rdreq_delay
);
-- delaying unit for write
-- note that this is enabled on the rdena, because the rdena stalls all of the interesting
-- logic of the fifo, whereas the wrena just stalls a little bit of write logic
wrreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => WRITE_TO_READ_DELAY
)
port map
(
clock => rdclock,
ena => '1',
reset => reset,
data => wrreq_to_delayer,
q => wrreq_delay
);
wrreq_to_delayer <= wrreq and wrena;
-- this process updates the wrusedw and full signals
update_write_fullness_signals : process (wrclock, reset)
begin
if reset = '1' then
-- start empty
full_reg <= '0';
almost_full_reg <= '0';
wrusedw_reg <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
-- update based on (possibly) delayed rdreq and up to date wrreq values
if (rdreq_delay = '1' and rdena = '1') and (wrreq = '0' or wrena = '0') then
-- reading and not writing decreases the used words in a fifo
full_reg <= '0';
if wrusedw_reg = to_unsigned(DEPTH - 1, WIDTH) then
almost_full_reg <= '0';
end if;
wrusedw_reg <= wrusedw_reg - 1;
elsif (rdreq_delay = '0' or rdena = '0') and (wrreq = '1' and wrena = '1') then
-- writing and not reading increases the used words in a fifo
if wrusedw_reg = to_unsigned(DEPTH - 1, WIDTH) then
full_reg <= '1';
end if;
if wrusedw_reg = to_unsigned(maximum(DEPTH - 2, 0), WIDTH) then
almost_full_reg <= '1';
end if;
wrusedw_reg <= wrusedw_reg + 1;
end if;
end if;
end process;
-- drive output lines from registers
wrusedw <= std_logic_vector(wrusedw_reg);
full <= full_reg;
almost_full <= almost_full_reg when DEPTH > 1 else '1';
-- this process updates the read side rdusedw and empty signals
update_read_emptiness_signals : process (rdclock, reset)
begin
if reset = '1' then
-- start empty
empty_reg <= '1';
almost_empty_reg <= '1';
rdusedw_reg <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
-- update based on up to date rdreq and (possibly) delayed wrreq values
-- update based on up to date rdreq and (possibly) delayed wrreq values
if (rdreq = '1' and rdena = '1') and wrreq_delay = '0' then
-- reading and not writing decreases the used words in the fifo
if rdusedw_reg = to_unsigned(1, WIDTH) then
empty_reg <= '1';
end if;
if rdusedw_reg = to_unsigned(2, WIDTH) then
almost_empty_reg <= '1';
end if;
rdusedw_reg <= rdusedw_reg - 1;
elsif (rdreq = '0' or rdena = '0') and wrreq_delay = '1' then
-- writing and not reading increases the used words in the fifo
empty_reg <= '0';
if rdusedw_reg = to_unsigned(1, WIDTH) then
almost_empty_reg <= '0';
end if;
rdusedw_reg <= rdusedw_reg + 1;
end if;
end if;
end process;
-- drive output lines from registers
rdusedw <= std_logic_vector(rdusedw_reg);
empty <= empty_reg;
almost_empty <= almost_empty_reg when DEPTH > 1 else '1';
end generate;
-- in dual clock mode, need to maintain separate counters which only increment
-- cross clock domains by converting to gray, avoiding metastability with shift
-- registers and converting back
dual_clock_gen :
if CLOCKS_ARE_SAME = FALSE generate
-- these counters are incremented when rdreqs and wrreqs happen
-- they are then propagated across the clock domains and positive
-- deltas in their values are looked for at the other side
signal wrcounter, rdcounter : unsigned(WIDTH - 1 downto 0);
-- the counters in their destination once they've crossed the clock domains
signal clock_crossed_wrcounter, clock_crossed_rdcounter : std_logic_vector(WIDTH - 1 downto 0);
-- monitoring how much the counters have changed
signal clock_crossed_wrcounter_prev, clock_crossed_rdcounter_prev : std_logic_vector(WIDTH - 1 downto 0);
signal writes_this_read_cycle, reads_this_write_cycle : std_logic_vector(WIDTH - 1 downto 0);
-- sometimes extra delay is required after the clock crossing delay
signal writes_this_read_cycle_delay, reads_this_write_cycle_delay : std_logic_vector(WIDTH - 1 downto 0);
begin
-- update the rdcounter in response to rdreq on the rdclock
update_rdcounter : process (rdclock, reset)
begin
if reset = '1' then
rdcounter <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
if rdena = '1' then
if rdreq = '1' then
rdcounter <= rdcounter + 1;
end if;
end if;
end if;
end process;
-- update the wrcounter in response to wrreq on the wrclock
update_wrcounter : process (wrclock, reset)
begin
if reset = '1' then
wrcounter <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
if wrena = '1' then
if wrreq = '1' then
wrcounter <= wrcounter + 1;
end if;
end if;
end if;
end process;
-- propagate the wrcounter across to the read clock domain and monitor
-- how much it advances each cycle
wrcounter_to_rdclock : alt_vipvfr131_common_gray_clock_crosser
generic map
(
WIDTH => WIDTH
)
port map
(
inclock => wrclock,
outclock => rdclock,
inena => wrena,
outena => '1',
reset => reset,
data => std_logic_vector(wrcounter),
q => clock_crossed_wrcounter
);
-- track the previous value of clock_crossed_wrcounter
update_clock_crossed_wrcounter_prev : process (rdclock, reset)
begin
if reset = '1' then
clock_crossed_wrcounter_prev <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
clock_crossed_wrcounter_prev <= clock_crossed_wrcounter;
end if;
end process;
-- combinationally update the wrcounter delta this read cycle
writes_this_read_cycle <= std_logic_vector(unsigned(clock_crossed_wrcounter) - unsigned(clock_crossed_wrcounter_prev));
-- propagate the rdcounter across to the write clock domain and monitor
-- how much it advances each cycle
rdcounter_to_wrclock : alt_vipvfr131_common_gray_clock_crosser
generic map
(
WIDTH => WIDTH
)
port map
(
inclock => rdclock,
outclock => wrclock,
inena => rdena,
outena => '1',
reset => reset,
data => std_logic_vector(rdcounter),
q => clock_crossed_rdcounter
);
-- track the previous value of clock_crossed_rdcounter
update_clock_crossed_rdcounter_prev : process (wrclock, reset)
begin
if reset = '1' then
clock_crossed_rdcounter_prev <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
clock_crossed_rdcounter_prev <= clock_crossed_rdcounter;
end if;
end process;
-- combinationally update the rdcounter delta this read cycle
reads_this_write_cycle <= std_logic_vector(unsigned(clock_crossed_rdcounter) - unsigned(clock_crossed_rdcounter_prev));
-- delay writes_this_read_cycle as requested
writes_this_read_cycle_delayer : alt_vipvfr131_common_std_logic_vector_delay
generic map
(
WIDTH => WIDTH,
DELAY => WRITE_TO_READ_DELAY
)
port map
(
clock => rdclock,
ena => '1',
reset => reset,
data => writes_this_read_cycle,
q => writes_this_read_cycle_delay
);
-- delay reads_this_write_cycle as requested
reads_this_write_cycle_delayer : alt_vipvfr131_common_std_logic_vector_delay
generic map
(
WIDTH => WIDTH,
DELAY => READ_TO_WRITE_DELAY
)
port map
(
clock => wrclock,
ena => '1',
reset => reset,
data => reads_this_write_cycle,
q => reads_this_write_cycle_delay
);
-- this process updates the wrusedw and full signals
update_write_fullness_signals : process (wrclock, reset)
variable new_wrusedw : unsigned(WIDTH - 1 downto 0);
begin
if reset = '1' then
-- start empty
full_reg <= '0';
almost_full_reg <= '0';
wrusedw_reg <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
-- update based on wrreq and the number of reads which we've been told about
-- this write cycle
new_wrusedw := wrusedw_reg;
if wrreq = '1' and wrena = '1' then
new_wrusedw := new_wrusedw + 1;
end if;
new_wrusedw := new_wrusedw - unsigned(reads_this_write_cycle_delay); -- should not be possible for this to make it go negative
-- update full
if new_wrusedw = to_unsigned(DEPTH, WIDTH) then
full_reg <= '1';
else
full_reg <= '0';
end if;
-- update almost full
if new_wrusedw >= to_unsigned(DEPTH - 1, WIDTH) then
almost_full_reg <= '1';
else
almost_full_reg <= '0';
end if;
-- update wrusedw_reg itself
wrusedw_reg <= new_wrusedw;
end if;
end process;
-- drive output lines from registers
wrusedw <= std_logic_vector(wrusedw_reg);
full <= full_reg;
almost_full <= almost_full_reg when DEPTH > 1 else '1';
-- this process updates the rdusedw and empty signals
update_read_emptiness_signals : process (rdclock, reset)
variable new_rdusedw : unsigned(WIDTH - 1 downto 0);
begin
if reset = '1' then
-- start empty
empty_reg <= '1';
almost_empty_reg <= '1';
rdusedw_reg <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
-- update based on wrreq and the number of reads which we've been told about
-- this write cycle
new_rdusedw := rdusedw_reg;
if rdreq = '1' and rdena = '1' then
new_rdusedw := new_rdusedw - 1;
end if;
new_rdusedw := new_rdusedw + unsigned(writes_this_read_cycle_delay); -- should not be possible for this to make it wrap
-- update empty
if new_rdusedw = to_unsigned(0, WIDTH) then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
-- update almost empty
if new_rdusedw <= to_unsigned(1, WIDTH) then
almost_empty_reg <= '1';
else
almost_empty_reg <= '0';
end if;
-- update rdusedw_reg itself
rdusedw_reg <= new_rdusedw;
end if;
end process;
-- drive output lines from registers
rdusedw <= std_logic_vector(rdusedw_reg);
empty <= empty_reg;
almost_empty <= almost_empty_reg when DEPTH > 1 else '1';
end generate;
end;
| mit | 5e21cd552c4c32e90c30530a26696477 | 0.652849 | 3.400601 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/openmac/src/axi_openmac-rtl-ea.vhd | 2 | 75,126 | -------------------------------------------------------------------------------
--! @file axi_openmac-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Xilinx
--
--! @details This is the openMAC toplevel for Xilinx platform with AXI.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
--! Common Xilinx library
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
--! AXI Lite IPIF library
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
--! AXI Master Burst library
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
--! Unisim library used for ODDR2 instance.
library unisim;
use unisim.vcomponents.oddr2;
entity axi_openmac is
generic (
-----------------------------------------------------------------------
-- General parameters
-----------------------------------------------------------------------
--! Xilinx FPGA familiy
C_FAMILY : string := "spartan6";
-----------------------------------------------------------------------
-- AXI DMA
-----------------------------------------------------------------------
--! AXI master DMA address width
C_M_AXI_MAC_DMA_ADDR_WIDTH : integer := 32;
--! AXI master DMA data width
C_M_AXI_MAC_DMA_DATA_WIDTH : integer := 32;
--! AXI master DMA native data width
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : integer := 32;
--! AXI master DMA burst length width
C_M_AXI_MAC_DMA_LENGTH_WIDTH : integer := 12;
--! AXI master DMA burst length
C_M_AXI_MAC_DMA_MAX_BURST_LEN : integer := 16;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave REG address ranges
C_S_AXI_MAC_REG_NUM_ADDR_RANGES : integer := 2;
--! AXI slave REG range 0 base
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 0 high
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG range 1 base
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 1 high
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_REG_MIN_SIZE : std_logic_vector := x"00001fff";
--! AXI slave REG data width
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
--! AXI slave REG address width
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
--! AXI slave REG clock frequency
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 50000000;
--! AXI slave REG use write strobes
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
--! AXI slave REG enable data phase timeout timer
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave PKT base
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave PKT high
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_PKT_MIN_SIZE : std_logic_vector := x"0000ffff";
--! AXI slave PKT data width
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
--! AXI slave PKT address width
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
--! AXI slave PKT use write strobes
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
--! AXI slave PKT enable data phase timeout timer
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk50 : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk100 : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! AXI slave REG clock
S_AXI_MAC_REG_ACLK : in std_logic;
--! AXI slave REG reset (low-active)
S_AXI_MAC_REG_ARESETN : in std_logic;
--! AXI slave REG address read valid
S_AXI_MAC_REG_ARVALID : in std_logic;
--! AXI slave REG address write valid
S_AXI_MAC_REG_AWVALID : in std_logic;
--! AXI slave REG response ready
S_AXI_MAC_REG_BREADY : in std_logic;
--! AXI slave REG read ready
S_AXI_MAC_REG_RREADY : in std_logic;
--! AXI slave REG write valid
S_AXI_MAC_REG_WVALID : in std_logic;
--! AXI slave REG read address
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write address
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write data
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG write strobe
S_AXI_MAC_REG_WSTRB : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
--! AXI slave REG read address ready
S_AXI_MAC_REG_ARREADY : out std_logic;
--! AXI slave REG write address ready
S_AXI_MAC_REG_AWREADY : out std_logic;
--! AXI slave REG write response valid
S_AXI_MAC_REG_BVALID : out std_logic;
--! AXI slave REG read valid
S_AXI_MAC_REG_RVALID : out std_logic;
--! AXI slave REG write ready
S_AXI_MAC_REG_WREADY : out std_logic;
--! AXI slave REG write response
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave REG read data
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG read response
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! AXI slave PKT clock
S_AXI_MAC_PKT_ACLK : in std_logic;
--! AXI slave PKT reset (low-active)
S_AXI_MAC_PKT_ARESETN : in std_logic;
--! AXI slave PKT address read valid
S_AXI_MAC_PKT_ARVALID : in std_logic;
--! AXI slave PKT address write valid
S_AXI_MAC_PKT_AWVALID : in std_logic;
--! AXI slave PKT response ready
S_AXI_MAC_PKT_BREADY : in std_logic;
--! AXI slave PKT read ready
S_AXI_MAC_PKT_RREADY : in std_logic;
--! AXI slave PKT write valid
S_AXI_MAC_PKT_WVALID : in std_logic;
--! AXI slave PKT read address
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write address
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write data
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT write strobe
S_AXI_MAC_PKT_WSTRB : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
--! AXI slave PKT read address ready
S_AXI_MAC_PKT_ARREADY : out std_logic;
--! AXI slave PKT write address ready
S_AXI_MAC_PKT_AWREADY : out std_logic;
--! AXI slave PKT write response valid
S_AXI_MAC_PKT_BVALID : out std_logic;
--! AXI slave PKT read valid
S_AXI_MAC_PKT_RVALID : out std_logic;
--! AXI slave PKT write ready
S_AXI_MAC_PKT_WREADY : out std_logic;
--! AXI slave PKT write response
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave PKT read data
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT read response
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! DMA master clock
M_AXI_MAC_DMA_ACLK : in std_logic;
--! DMA master reset (low-active)
M_AXI_MAC_DMA_ARESETN : in std_logic;
--! AXI master DMA error
M_AXI_MAC_DMA_MD_ERROR : out std_logic;
--! AXI master DMA read address ready
M_AXI_MAC_DMA_ARREADY : in std_logic;
--! AXI master DMA write address ready
M_AXI_MAC_DMA_AWREADY : in std_logic;
--! AXI master DMA write response ready
M_AXI_MAC_DMA_BVALID : in std_logic;
--! AXI master DMA read last
M_AXI_MAC_DMA_RLAST : in std_logic;
--! AXI master DMA read valid
M_AXI_MAC_DMA_RVALID : in std_logic;
--! AXI master DMA write ready
M_AXI_MAC_DMA_WREADY : in std_logic;
--! AXI master DMA write response
M_AXI_MAC_DMA_BRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read data
M_AXI_MAC_DMA_RDATA : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA read response
M_AXI_MAC_DMA_RRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read address valid
M_AXI_MAC_DMA_ARVALID : out std_logic;
--! AXI master DMA write address valid
M_AXI_MAC_DMA_AWVALID : out std_logic;
--! AXI master DMA response ready
M_AXI_MAC_DMA_BREADY : out std_logic;
--! AXI master DMA read ready
M_AXI_MAC_DMA_RREADY : out std_logic;
--! AXI master DMA write last
M_AXI_MAC_DMA_WLAST : out std_logic;
--! AXI master DMA write valid
M_AXI_MAC_DMA_WVALID : out std_logic;
--! AXI master DMA read address
M_AXI_MAC_DMA_ARADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_ARBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_ARCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_ARLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_ARPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_ARSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write address
M_AXI_MAC_DMA_AWADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_AWBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_AWCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_AWLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_AWPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_AWSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write data
M_AXI_MAC_DMA_WDATA : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA write strobe
M_AXI_MAC_DMA_WSTRB : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
TIMER_IRQ : out std_logic;
--! MAC interrupt
MAC_IRQ : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Clock ports (optional)
oRmii_clk : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data valid ports
iRmii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
iRmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
iRmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
oRmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
oRmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
iMii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
iMii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
iMii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
oMii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
oMii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
iMii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
oSmi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O input
iSmi_dio : in std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O output
oSmi_dio : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O tristate
oSmi_dio_tri : out std_logic;
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oPktActivity : out std_logic;
--! MAC TIMER outputs
oMacTimerOut : out std_logic_vector(gTimerCount-1 downto 0);
testPort : out std_logic_vector(255 downto 0)
);
end axi_openmac;
architecture rtl of axi_openmac is
--! Address zero padding vector
constant cZeroPadAddress : std_logic_vector(31 downto 0) := (others => cInactivated);
--! Address array for MAC REG IPIF
constant cMacReg_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_HIGHADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_HIGHADDR)
);
--! Address array for PKT BUF IPIF
constant cPktBuf_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_PKT_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_PKT_HIGHADDR)
);
--! Chipselect for MAC REG --> MAC REG
constant cMacReg_csMacReg : natural := 1;
--! Chipselect for MAC REG --> MAC TIMER
constant cMacReg_csMacTimer : natural := 0;
--! Chipselect for PKT BUF
constant cPktBuf_cs : natural := 0;
--! Clock Reset type
type tClkRst is record
clk : std_logic;
rst : std_logic;
regClk : std_logic;
regRst : std_logic;
dmaClk : std_logic;
dmaRst : std_logic;
pktClk : std_logic;
pktRst : std_logic;
clk2x : std_logic;
end record;
--! Mac Reg type
type tMacReg is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(cMacRegAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacRegDataWidth-1 downto 0);
readdata : std_logic_vector(cMacRegDataWidth-1 downto 0);
end record;
--! Mac Timer type
type tMacTimer is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
address : std_logic_vector(cMacTimerAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
readdata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
end record;
--! Pkt Buf type
type tPktBuf is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gPacketBufferLog2Size-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Dma type
type tDma is record
write : std_logic;
read : std_logic;
waitrequest : std_logic;
readdatavalid : std_logic;
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! AXI lite slave for MAC REG
type tAxiSlaveMacReg is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI lite slave for PKT BUF
type tAxiSlavePktBuf is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cPktBuf_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI master for DMA
type tAxiMasterDma is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
md_error : std_logic;
axi_arready : std_logic;
axi_arvalid : std_logic;
axi_araddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_arlen : std_logic_vector(7 downto 0);
axi_arsize : std_logic_vector(2 downto 0);
axi_arburst : std_logic_vector(1 downto 0);
axi_arprot : std_logic_vector(2 downto 0);
axi_arcache : std_logic_vector(3 downto 0);
axi_rready : std_logic;
axi_rvalid : std_logic;
axi_rdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rlast : std_logic;
axi_awready : std_logic;
axi_awvalid : std_logic;
axi_awaddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_awlen : std_logic_vector(7 downto 0);
axi_awsize : std_logic_vector(2 downto 0);
axi_awburst : std_logic_vector(1 downto 0);
axi_awprot : std_logic_vector(2 downto 0);
axi_awcache : std_logic_vector(3 downto 0);
axi_wready : std_logic;
axi_wvalid : std_logic;
axi_wdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
axi_wlast : std_logic;
axi_bready : std_logic;
axi_bvalid : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
ipif_mstrd_req : std_logic;
ipif_mstwr_req : std_logic;
ipif_mst_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_mst_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_mst_be : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mst_type : std_logic;
ipif_mst_lock : std_logic;
ipif_mst_reset : std_logic;
ipif_mst_cmdack : std_logic;
ipif_mst_cmplt : std_logic;
ipif_mst_error : std_logic;
ipif_mst_rearbitrate : std_logic;
ipif_mst_cmd_timeout : std_logic;
ipif_mstrd_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 );
ipif_mstrd_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstrd_sof_n : std_logic;
ipif_mstrd_eof_n : std_logic;
ipif_mstrd_src_rdy_n : std_logic;
ipif_mstrd_src_dsc_n : std_logic;
ipif_mstrd_dst_rdy_n : std_logic;
ipif_mstrd_dst_dsc_n : std_logic;
ipif_mstwr_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
ipif_mstwr_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstwr_sof_n : std_logic;
ipif_mstwr_eof_n : std_logic;
ipif_mstwr_src_rdy_n : std_logic;
ipif_mstwr_src_dsc_n : std_logic;
ipif_mstwr_dst_rdy_n : std_logic;
ipif_mstwr_dst_dsc_n : std_logic;
end record;
--! Clock xing for MAC REG port
type tClkXingMacRegPort is record
clk : std_logic;
cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
rnw : std_logic;
readdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
wrAck : std_logic;
rdAck : std_logic;
end record;
--! Clock xing for MAC REG
type tClkXingMacReg is record
rst : std_logic;
fast : tClkXingMacRegPort;
slow : tClkXingMacRegPort;
end record;
--! Data width converter for MAC REG
type tConvMacReg is record
rst : std_logic;
clk : std_logic;
master_select : std_logic;
master_write : std_logic;
master_read : std_logic;
master_byteenable : std_logic_vector(3 downto 0);
master_writedata : std_logic_vector(31 downto 0);
master_readdata : std_logic_vector(31 downto 0);
master_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
master_WriteAck : std_logic;
master_ReadAck : std_logic;
slave_select : std_logic;
slave_write : std_logic;
slave_read : std_logic;
slave_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
slave_byteenable : std_logic_vector(1 downto 0);
slave_readdata : std_logic_vector(15 downto 0);
slave_writedata : std_logic_vector(15 downto 0);
slave_ack : std_logic;
end record;
--! IPIF handler for MAC DMA
type tIpifMasterHandler is record
rst : std_logic;
clk : std_logic;
ipif_cmdAck : std_logic;
ipif_cmplt : std_logic;
ipif_error : std_logic;
ipif_rearbitrate : std_logic;
ipif_cmdTimeout : std_logic;
ipif_type : std_logic;
ipif_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_be : std_logic_vector(3 downto 0);
ipif_lock : std_logic;
ipif_reset : std_logic;
ipif_rdData : std_logic_vector(31 downto 0);
ipif_rdRem : std_logic_vector(3 downto 0);
ipif_rdReq : std_logic;
nIpif_rdSof : std_logic;
nIpif_rdEof : std_logic;
nIpif_rdSrcRdy : std_logic;
nIpif_rdSrcDsc : std_logic;
nIpif_rdDstRdy : std_logic;
nIpif_rdDstDsc : std_logic;
ipif_wrData : std_logic_vector(31 downto 0);
ipif_wrRem : std_logic_vector(3 downto 0);
ipif_wrReq : std_logic;
nIpif_wrSof : std_logic;
nIpif_wrEof : std_logic;
nIpif_wrSrcRdy : std_logic;
nIpif_wrSrcDsc : std_logic;
nIpif_wrDstRdy : std_logic;
nIpif_wrDstDsc : std_logic;
masterRead : std_logic;
masterWrite : std_logic;
masterAddress : std_logic_vector(gDmaAddrWidth-1 downto 0);
masterWritedata : std_logic_vector(31 downto 0);
masterBurstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterBurstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterReaddata : std_logic_vector(31 downto 0);
masterWaitrequest : std_logic;
masterReaddatavalid : std_logic;
end record;
--! Clock and resets
signal intf_clkRst : tClkRst;
--! Mac Reg
signal intf_macReg : tMacReg;
--! Mac Timer
signal intf_macTimer : tMacTimer;
--! Packet buffer
signal intf_pktBuf : tPktBuf;
--! Dma
signal intf_dma : tDma;
--! Mac Reg IPIF
signal ipif_macReg : tAxiSlaveMacReg;
--! Packet buffer IPIF
signal ipif_pktBuf : tAxiSlavePktBuf;
--! Dma IPIF
signal ipif_dma : tAxiMasterDma;
--! Clock Xing for MAC REG IPIF
signal xing_macReg : tClkXingMacReg;
--! Dara width converter for MAC REG IPIF
signal conv_macReg : tConvMacReg;
--! Dma IPIF master handler
signal ipif_dmaMasterHdler : tIpifMasterHandler;
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
MAC_IRQ <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => oRmii_txEnable,
oData => oRmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => oMii_txEnable,
oData => oMii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Clock and resets
intf_clkRst.clk <= iClk50;
intf_clkRst.clk2x <= iClk100;
intf_clkRst.regClk <= S_AXI_MAC_REG_ACLK;
intf_clkRst.pktClk <= S_AXI_MAC_PKT_ACLK;
intf_clkRst.dmaClk <= M_AXI_MAC_DMA_ACLK;
intf_clkRst.rst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.regRst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.pktRst <= not S_AXI_MAC_PKT_ARESETN;
intf_clkRst.dmaRst <= not M_AXI_MAC_DMA_ARESETN;
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => iRmii_rxDataValid,
iData => iRmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => iMii_rxDataValid,
iData => iMii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO (the tristate buffer shall be assigned by toplevel)
oSmi_dio <= smi_data_out;
oSmi_dio_tri <= not smi_data_outEnable;
smi_data_in <= iSmi_dio;
---------------------------------------------------------------------------
-- Map Instances
---------------------------------------------------------------------------
-- MAC REG --> ipif_macReg
ipif_macReg.axi_aclk <= intf_clkRst.regClk;
ipif_macReg.axi_aresetn <= not intf_clkRst.regRst;
ipif_macReg.axi_awaddr <= S_AXI_MAC_REG_AWADDR;
ipif_macReg.axi_awvalid <= S_AXI_MAC_REG_AWVALID;
S_AXI_MAC_REG_AWREADY <= ipif_macReg.axi_awready;
ipif_macReg.axi_wdata <= S_AXI_MAC_REG_WDATA;
ipif_macReg.axi_wstrb <= S_AXI_MAC_REG_WSTRB;
ipif_macReg.axi_wvalid <= S_AXI_MAC_REG_WVALID;
S_AXI_MAC_REG_WREADY <= ipif_macReg.axi_wready;
S_AXI_MAC_REG_BRESP <= ipif_macReg.axi_bresp;
S_AXI_MAC_REG_BVALID <= ipif_macReg.axi_bvalid;
ipif_macReg.axi_bready <= S_AXI_MAC_REG_BREADY;
ipif_macReg.axi_araddr <= S_AXI_MAC_REG_ARADDR;
ipif_macReg.axi_arvalid <= S_AXI_MAC_REG_ARVALID;
S_AXI_MAC_REG_ARREADY <= ipif_macReg.axi_arready;
S_AXI_MAC_REG_RDATA <= ipif_macReg.axi_rdata;
S_AXI_MAC_REG_RRESP <= ipif_macReg.axi_rresp;
S_AXI_MAC_REG_RVALID <= ipif_macReg.axi_rvalid;
ipif_macReg.axi_rready <= S_AXI_MAC_REG_RREADY;
-- xing_macReg <-- conv_macReg or intf_macTimer
--! This process assigns the read and ack path from macReg and macTimer
--! to the clock crossing slow inputs, depending on the selected target.
ASSIGN_XING_MACREG : process (conv_macReg, intf_macTimer)
begin
-- default is MAC REG source
xing_macReg.slow.readdata <= conv_macReg.master_readdata;
xing_macReg.slow.wrAck <= conv_macReg.master_WriteAck;
xing_macReg.slow.rdAck <= conv_macReg.master_ReadAck;
if intf_macTimer.chipselect = cActivated then
xing_macReg.slow.readdata <= intf_macTimer.readdata;
xing_macReg.slow.wrAck <= intf_macTimer.write and not intf_macTimer.waitrequest;
xing_macReg.slow.rdAck <= intf_macTimer.read and not intf_macTimer.waitrequest;
end if;
end process ASSIGN_XING_MACREG;
-- ipif_macReg --> xing_macReg
--unused output: ipif_macReg.ipif_resetn;
xing_macReg.rst <= intf_clkRst.regRst;
xing_macReg.fast.clk <= ipif_macReg.ipif_clk;
xing_macReg.slow.clk <= intf_clkRst.clk;
xing_macReg.fast.rnw <= ipif_macReg.ipif_rnw;
xing_macReg.fast.cs <= ipif_macReg.ipif_cs;
ipif_macReg.ipif_rddata <= xing_macReg.fast.readdata;
ipif_macReg.ipif_wrack <= xing_macReg.fast.wrAck;
ipif_macReg.ipif_rdack <= xing_macReg.fast.rdAck;
ipif_macReg.ipif_error <= cInactivated; --unused
-- ipif_macReg --> conv_macReg | xing_macReg --> conv_macReg
conv_macReg.rst <= intf_clkRst.rst;
conv_macReg.clk <= intf_clkRst.clk;
conv_macReg.master_select <= xing_macReg.slow.cs(cMacReg_csMacReg);
conv_macReg.master_write <= not xing_macReg.slow.rnw;
conv_macReg.master_read <= xing_macReg.slow.rnw;
conv_macReg.master_byteenable <= ipif_macReg.ipif_be;
conv_macReg.master_writedata <= ipif_macReg.ipif_wrdata;
conv_macReg.master_address <= ipif_macReg.ipif_addr(conv_macReg.master_address'range);
-- conv_macReg --> intf_macReg
intf_macReg.chipselect <= conv_macReg.slave_select;
intf_macReg.write <= conv_macReg.slave_write;
intf_macReg.read <= conv_macReg.slave_read;
intf_macReg.address <= conv_macReg.slave_address(intf_macReg.address'range);
intf_macReg.byteenable <= conv_macReg.slave_byteenable;
conv_macReg.slave_readdata <= intf_macReg.readdata;
intf_macReg.writedata <= conv_macReg.slave_writedata;
conv_macReg.slave_ack <= not intf_macReg.waitrequest;
-- ipif_macReg --> intf_macTimer | xing_macReg --> intf_macTimer
intf_macTimer.chipselect <= xing_macReg.slow.cs(cMacReg_csMacTimer);
intf_macTimer.write <= not xing_macReg.slow.rnw;
intf_macTimer.read <= xing_macReg.slow.rnw;
intf_macTimer.address <= ipif_macReg.ipif_addr(intf_macTimer.address'range);
intf_macTimer.writedata <= ipif_macReg.ipif_wrdata;
-- MAC PKT --> ipif_pktBuf
ipif_pktBuf.axi_aclk <= intf_clkRst.pktClk;
ipif_pktBuf.axi_aresetn <= not intf_clkRst.pktRst;
ipif_pktBuf.axi_awaddr <= S_AXI_MAC_PKT_AWADDR;
ipif_pktBuf.axi_awvalid <= S_AXI_MAC_PKT_AWVALID;
S_AXI_MAC_PKT_AWREADY <= ipif_pktBuf.axi_awready;
ipif_pktBuf.axi_wdata <= S_AXI_MAC_PKT_WDATA;
ipif_pktBuf.axi_wstrb <= S_AXI_MAC_PKT_WSTRB;
ipif_pktBuf.axi_wvalid <= S_AXI_MAC_PKT_WVALID;
S_AXI_MAC_PKT_WREADY <= ipif_pktBuf.axi_wready;
S_AXI_MAC_PKT_BRESP <= ipif_pktBuf.axi_bresp;
S_AXI_MAC_PKT_BVALID <= ipif_pktBuf.axi_bvalid;
ipif_pktBuf.axi_bready <= S_AXI_MAC_PKT_BREADY;
ipif_pktBuf.axi_araddr <= S_AXI_MAC_PKT_ARADDR;
ipif_pktBuf.axi_arvalid <= S_AXI_MAC_PKT_ARVALID;
S_AXI_MAC_PKT_ARREADY <= ipif_pktBuf.axi_arready;
S_AXI_MAC_PKT_RDATA <= ipif_pktBuf.axi_rdata;
S_AXI_MAC_PKT_RRESP <= ipif_pktBuf.axi_rresp;
S_AXI_MAC_PKT_RVALID <= ipif_pktBuf.axi_rvalid;
ipif_pktBuf.axi_rready <= S_AXI_MAC_PKT_RREADY;
-- ipif_pktBuf --> intf_pktBuf
--unused output: ipif_pktBuf.ipif_clk
--unused output: ipif_pktBuf.ipif_resetn
intf_pktBuf.address <= ipif_pktBuf.ipif_addr(intf_pktBuf.address'range);
intf_pktBuf.write <= not ipif_pktBuf.ipif_rnw;
intf_pktBuf.read <= ipif_pktBuf.ipif_rnw;
intf_pktBuf.byteenable <= ipif_pktBuf.ipif_be;
intf_pktBuf.chipselect <= ipif_pktBuf.ipif_cs(cPktBuf_cs);
intf_pktBuf.writedata <= ipif_pktBuf.ipif_wrdata;
ipif_pktBuf.ipif_rddata <= intf_pktBuf.readdata;
ipif_pktBuf.ipif_wrack <= intf_pktBuf.chipselect and intf_pktBuf.write and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_rdack <= intf_pktBuf.chipselect and intf_pktBuf.read and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_error <= cInactivated; --unused
-- MAC DMA --> ipif_dma
ipif_dma.axi_aclk <= intf_clkRst.dmaClk;
ipif_dma.axi_aresetn <= not intf_clkRst.dmaRst;
M_AXI_MAC_DMA_MD_ERROR <= ipif_dma.md_error;
ipif_dma.axi_arready <= M_AXI_MAC_DMA_ARREADY;
M_AXI_MAC_DMA_ARVALID <= ipif_dma.axi_arvalid;
M_AXI_MAC_DMA_ARADDR <= ipif_dma.axi_araddr;
M_AXI_MAC_DMA_ARLEN <= ipif_dma.axi_arlen;
M_AXI_MAC_DMA_ARSIZE <= ipif_dma.axi_arsize;
M_AXI_MAC_DMA_ARBURST <= ipif_dma.axi_arburst;
M_AXI_MAC_DMA_ARPROT <= ipif_dma.axi_arprot;
M_AXI_MAC_DMA_ARCACHE <= ipif_dma.axi_arcache;
M_AXI_MAC_DMA_RREADY <= ipif_dma.axi_rready;
ipif_dma.axi_rvalid <= M_AXI_MAC_DMA_RVALID;
ipif_dma.axi_rdata <= M_AXI_MAC_DMA_RDATA;
ipif_dma.axi_rresp <= M_AXI_MAC_DMA_RRESP;
ipif_dma.axi_rlast <= M_AXI_MAC_DMA_RLAST;
ipif_dma.axi_awready <= M_AXI_MAC_DMA_AWREADY;
M_AXI_MAC_DMA_AWVALID <= ipif_dma.axi_awvalid;
M_AXI_MAC_DMA_AWADDR <= ipif_dma.axi_awaddr;
M_AXI_MAC_DMA_AWLEN <= ipif_dma.axi_awlen;
M_AXI_MAC_DMA_AWSIZE <= ipif_dma.axi_awsize;
M_AXI_MAC_DMA_AWBURST <= ipif_dma.axi_awburst;
M_AXI_MAC_DMA_AWPROT <= ipif_dma.axi_awprot;
M_AXI_MAC_DMA_AWCACHE <= ipif_dma.axi_awcache;
ipif_dma.axi_wready <= M_AXI_MAC_DMA_WREADY;
M_AXI_MAC_DMA_WVALID <= ipif_dma.axi_wvalid;
M_AXI_MAC_DMA_WDATA <= ipif_dma.axi_wdata;
M_AXI_MAC_DMA_WSTRB <= ipif_dma.axi_wstrb;
M_AXI_MAC_DMA_WLAST <= ipif_dma.axi_wlast;
M_AXI_MAC_DMA_BREADY <= ipif_dma.axi_bready;
ipif_dma.axi_bvalid <= M_AXI_MAC_DMA_BVALID;
ipif_dma.axi_bresp <= M_AXI_MAC_DMA_BRESP;
-- ipif_dma --> ipif_dmaMasterHdler
ipif_dmaMasterHdler.rst <= intf_clkRst.dmaRst;
ipif_dmaMasterHdler.clk <= intf_clkRst.dmaClk;
ipif_dma.ipif_mstrd_req <= ipif_dmaMasterHdler.ipif_rdReq;
ipif_dma.ipif_mstwr_req <= ipif_dmaMasterHdler.ipif_wrReq;
ipif_dma.ipif_mst_addr <= ipif_dmaMasterHdler.ipif_addr(ipif_dma.ipif_mst_addr'range);
ipif_dma.ipif_mst_length <= ipif_dmaMasterHdler.ipif_length;
ipif_dma.ipif_mst_be <= ipif_dmaMasterHdler.ipif_be;
ipif_dma.ipif_mst_type <= ipif_dmaMasterHdler.ipif_type;
ipif_dma.ipif_mst_lock <= ipif_dmaMasterHdler.ipif_lock;
ipif_dma.ipif_mst_reset <= ipif_dmaMasterHdler.ipif_reset;
ipif_dmaMasterHdler.ipif_cmdAck <= ipif_dma.ipif_mst_cmdack;
ipif_dmaMasterHdler.ipif_cmplt <= ipif_dma.ipif_mst_cmplt;
ipif_dmaMasterHdler.ipif_error <= ipif_dma.ipif_mst_error;
ipif_dmaMasterHdler.ipif_rearbitrate <= ipif_dma.ipif_mst_rearbitrate;
ipif_dmaMasterHdler.ipif_cmdTimeout <= ipif_dma.ipif_mst_cmd_timeout;
ipif_dmaMasterHdler.ipif_rdData <= ipif_dma.ipif_mstrd_d;
ipif_dmaMasterHdler.ipif_rdRem <= ipif_dma.ipif_mstrd_rem;
ipif_dmaMasterHdler.nIpif_rdSof <= ipif_dma.ipif_mstrd_sof_n;
ipif_dmaMasterHdler.nIpif_rdEof <= ipif_dma.ipif_mstrd_eof_n;
ipif_dmaMasterHdler.nIpif_rdSrcRdy <= ipif_dma.ipif_mstrd_src_rdy_n;
ipif_dmaMasterHdler.nIpif_rdSrcDsc <= ipif_dma.ipif_mstrd_src_dsc_n;
ipif_dma.ipif_mstrd_dst_rdy_n <= ipif_dmaMasterHdler.nIpif_rdDstRdy;
ipif_dma.ipif_mstrd_dst_dsc_n <= ipif_dmaMasterHdler.nIpif_rdDstDsc;
ipif_dma.ipif_mstwr_d <= ipif_dmaMasterHdler.ipif_wrData;
ipif_dma.ipif_mstwr_rem <= ipif_dmaMasterHdler.ipif_wrRem;
ipif_dma.ipif_mstwr_sof_n <= ipif_dmaMasterHdler.nIpif_wrSof;
ipif_dma.ipif_mstwr_eof_n <= ipif_dmaMasterHdler.nIpif_wrEof;
ipif_dma.ipif_mstwr_src_rdy_n <= ipif_dmaMasterHdler.nIpif_wrSrcRdy;
ipif_dma.ipif_mstwr_src_dsc_n <= ipif_dmaMasterHdler.nIpif_wrSrcDsc;
ipif_dmaMasterHdler.nIpif_wrDstRdy <= ipif_dma.ipif_mstwr_dst_rdy_n;
ipif_dmaMasterHdler.nIpif_wrDstDsc <= ipif_dma.ipif_mstwr_dst_dsc_n;
-- ipif_dmaMasterHdler --> intf_dma
ipif_dmaMasterHdler.masterRead <= intf_dma.read;
ipif_dmaMasterHdler.masterWrite <= intf_dma.write;
ipif_dmaMasterHdler.masterAddress <= intf_dma.address;
ipif_dmaMasterHdler.masterWritedata <= intf_dma.writedata;
ipif_dmaMasterHdler.masterBurstcount <= intf_dma.burstcount;
ipif_dmaMasterHdler.masterBurstcounter <= intf_dma.burstcounter;
intf_dma.readdata <= ipif_dmaMasterHdler.masterReaddata;
intf_dma.waitrequest <= ipif_dmaMasterHdler.masterWaitrequest;
intf_dma.readdatavalid <= ipif_dmaMasterHdler.masterReaddatavalid;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerCount => gTimerCount,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => intf_clkRst.clk,
iRst => intf_clkRst.rst,
iDmaClk => intf_clkRst.dmaClk,
iDmaRst => intf_clkRst.dmaRst,
iPktBufClk => intf_clkRst.pktClk,
iPktBufRst => intf_clkRst.pktRst,
iClk2x => intf_clkRst.clk2x,
iMacReg_chipselect => intf_macReg.chipselect,
iMacReg_write => intf_macReg.write,
iMacReg_read => intf_macReg.read,
oMacReg_waitrequest => intf_macReg.waitrequest,
iMacReg_byteenable => intf_macReg.byteenable,
iMacReg_address => intf_macReg.address,
iMacReg_writedata => intf_macReg.writedata,
oMacReg_readdata => intf_macReg.readdata,
iMacTimer_chipselect => intf_macTimer.chipselect,
iMacTimer_write => intf_macTimer.write,
iMacTimer_read => intf_macTimer.read,
oMacTimer_waitrequest => intf_macTimer.waitrequest,
iMacTimer_address => intf_macTimer.address,
iMacTimer_writedata => intf_macTimer.writedata,
oMacTimer_readdata => intf_macTimer.readdata,
iPktBuf_chipselect => intf_pktBuf.chipselect,
iPktBuf_write => intf_pktBuf.write,
iPktBuf_read => intf_pktBuf.read,
oPktBuf_waitrequest => intf_pktBuf.waitrequest,
iPktBuf_byteenable => intf_pktBuf.byteenable,
iPktBuf_address => intf_pktBuf.address,
iPktBuf_writedata => intf_pktBuf.writedata,
oPktBuf_readdata => intf_pktBuf.readdata,
oDma_write => intf_dma.write,
oDma_read => intf_dma.read,
iDma_waitrequest => intf_dma.waitrequest,
iDma_readdatavalid => intf_dma.readdatavalid,
oDma_byteenable => intf_dma.byteenable,
oDma_address => intf_dma.address,
oDma_burstcount => intf_dma.burstcount,
oDma_burstcounter => intf_dma.burstcounter,
oDma_writedata => intf_dma.writedata,
iDma_readdata => intf_dma.readdata,
oMacTimer_interrupt => TIMER_IRQ,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => iRmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => iMii_rxError,
iMii_RxClk => iMii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => iMii_txClk,
onPhy_reset => oSmi_nPhyRst,
oSmi_clk => oSmi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => oPktActivity,
oMacTimer => oMacTimerOut
);
--! The MAC REG AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_REG_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cMacReg_addressArray,
C_ARD_NUM_CE_ARRAY => (1, 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_macReg.axi_aclk,
S_AXI_ARESETN => ipif_macReg.axi_aresetn,
S_AXI_AWADDR => ipif_macReg.axi_awaddr,
S_AXI_AWVALID => ipif_macReg.axi_awvalid,
S_AXI_AWREADY => ipif_macReg.axi_awready,
S_AXI_WDATA => ipif_macReg.axi_wdata,
S_AXI_WSTRB => ipif_macReg.axi_wstrb,
S_AXI_WVALID => ipif_macReg.axi_wvalid,
S_AXI_WREADY => ipif_macReg.axi_wready,
S_AXI_BRESP => ipif_macReg.axi_bresp,
S_AXI_BVALID => ipif_macReg.axi_bvalid,
S_AXI_BREADY => ipif_macReg.axi_bready,
S_AXI_ARADDR => ipif_macReg.axi_araddr,
S_AXI_ARVALID => ipif_macReg.axi_arvalid,
S_AXI_ARREADY => ipif_macReg.axi_arready,
S_AXI_RDATA => ipif_macReg.axi_rdata,
S_AXI_RRESP => ipif_macReg.axi_rresp,
S_AXI_RVALID => ipif_macReg.axi_rvalid,
S_AXI_RREADY => ipif_macReg.axi_rready,
Bus2IP_Clk => ipif_macReg.ipif_clk,
Bus2IP_Resetn => ipif_macReg.ipif_resetn,
Bus2IP_Addr => ipif_macReg.ipif_addr,
Bus2IP_RNW => ipif_macReg.ipif_rnw,
Bus2IP_BE => ipif_macReg.ipif_be,
Bus2IP_CS => ipif_macReg.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_macReg.ipif_wrdata,
IP2Bus_Data => ipif_macReg.ipif_rddata,
IP2Bus_WrAck => ipif_macReg.ipif_wrack,
IP2Bus_RdAck => ipif_macReg.ipif_rdack,
IP2Bus_Error => ipif_macReg.ipif_error
);
--! The clock Xing ipcore transfers the signals in the AXI clock domain to
--! the iClk50 domain.
THEMACREG_CLKXING : entity work.clkXing
generic map (
gCsNum => xing_macReg.fast.cs'length,
gDataWidth => xing_macReg.fast.readdata'length
)
port map (
iArst => xing_macReg.rst,
iFastClk => xing_macReg.fast.clk,
iFastCs => xing_macReg.fast.cs,
iFastRNW => xing_macReg.fast.rnw,
oFastReaddata => xing_macReg.fast.readdata,
oFastWrAck => xing_macReg.fast.wrAck,
oFastRdAck => xing_macReg.fast.rdAck,
iSlowClk => xing_macReg.slow.clk,
oSlowCs => xing_macReg.slow.cs,
oSlowRNW => xing_macReg.slow.rnw,
iSlowReaddata => xing_macReg.slow.readdata,
iSlowWrAck => xing_macReg.slow.wrAck,
iSlowRdAck => xing_macReg.slow.rdAck
);
--! The memory mapped slave converter changes from AXI's data width to 16 bit.
THEMACREG_MMCONV : entity work.mmSlaveConv
generic map (
gEndian => gEndianness,
gMasterAddrWidth => conv_macReg.master_address'length
)
port map (
iRst => conv_macReg.rst,
iClk => conv_macReg.clk,
iMaster_select => conv_macReg.master_select,
iMaster_write => conv_macReg.master_write,
iMaster_read => conv_macReg.master_read,
iMaster_byteenable => conv_macReg.master_byteenable,
iMaster_writedata => conv_macReg.master_writedata,
oMaster_readdata => conv_macReg.master_readdata,
iMaster_address => conv_macReg.master_address,
oMaster_WriteAck => conv_macReg.master_WriteAck,
oMaster_ReadAck => conv_macReg.master_ReadAck,
oSlave_select => conv_macReg.slave_select,
oSlave_write => conv_macReg.slave_write,
oSlave_read => conv_macReg.slave_read,
oSlave_address => conv_macReg.slave_address,
oSlave_byteenable => conv_macReg.slave_byteenable,
iSlave_readdata => conv_macReg.slave_readdata,
oSlave_writedata => conv_macReg.slave_writedata,
iSlave_ack => conv_macReg.slave_ack
);
--! Generate the packet buffer IPIF if any location is set to local.
GEN_THEMACPKT : if gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal generate
--! The MAC PKT BUF AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_PKT_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cPktBuf_addressArray,
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_pktBuf.axi_aclk,
S_AXI_ARESETN => ipif_pktBuf.axi_aresetn,
S_AXI_AWADDR => ipif_pktBuf.axi_awaddr,
S_AXI_AWVALID => ipif_pktBuf.axi_awvalid,
S_AXI_AWREADY => ipif_pktBuf.axi_awready,
S_AXI_WDATA => ipif_pktBuf.axi_wdata,
S_AXI_WSTRB => ipif_pktBuf.axi_wstrb,
S_AXI_WVALID => ipif_pktBuf.axi_wvalid,
S_AXI_WREADY => ipif_pktBuf.axi_wready,
S_AXI_BRESP => ipif_pktBuf.axi_bresp,
S_AXI_BVALID => ipif_pktBuf.axi_bvalid,
S_AXI_BREADY => ipif_pktBuf.axi_bready,
S_AXI_ARADDR => ipif_pktBuf.axi_araddr,
S_AXI_ARVALID => ipif_pktBuf.axi_arvalid,
S_AXI_ARREADY => ipif_pktBuf.axi_arready,
S_AXI_RDATA => ipif_pktBuf.axi_rdata,
S_AXI_RRESP => ipif_pktBuf.axi_rresp,
S_AXI_RVALID => ipif_pktBuf.axi_rvalid,
S_AXI_RREADY => ipif_pktBuf.axi_rready,
Bus2IP_Clk => ipif_pktBuf.ipif_clk,
Bus2IP_Resetn => ipif_pktBuf.ipif_resetn,
Bus2IP_Addr => ipif_pktBuf.ipif_addr,
Bus2IP_RNW => ipif_pktBuf.ipif_rnw,
Bus2IP_BE => ipif_pktBuf.ipif_be,
Bus2IP_CS => ipif_pktBuf.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_pktBuf.ipif_wrdata,
IP2Bus_Data => ipif_pktBuf.ipif_rddata,
IP2Bus_WrAck => ipif_pktBuf.ipif_wrack,
IP2Bus_RdAck => ipif_pktBuf.ipif_rdack,
IP2Bus_Error => ipif_pktBuf.ipif_error
);
end generate GEN_THEMACPKT;
GEN_THEMACDMA : if gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern generate
--! The MAC DMA AXI master IPIF converts the AXI interface to IPIF.
THEMACDMA_AXI : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_ADDR_PIPE_DEPTH => 1,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
m_axi_aclk => ipif_dma.axi_aclk,
m_axi_aresetn => ipif_dma.axi_aresetn,
md_error => ipif_dma.md_error,
m_axi_arready => ipif_dma.axi_arready,
m_axi_arvalid => ipif_dma.axi_arvalid,
m_axi_araddr => ipif_dma.axi_araddr,
m_axi_arlen => ipif_dma.axi_arlen,
m_axi_arsize => ipif_dma.axi_arsize,
m_axi_arburst => ipif_dma.axi_arburst,
m_axi_arprot => ipif_dma.axi_arprot,
m_axi_arcache => ipif_dma.axi_arcache,
m_axi_rready => ipif_dma.axi_rready,
m_axi_rvalid => ipif_dma.axi_rvalid,
m_axi_rdata => ipif_dma.axi_rdata,
m_axi_rresp => ipif_dma.axi_rresp,
m_axi_rlast => ipif_dma.axi_rlast,
m_axi_awready => ipif_dma.axi_awready,
m_axi_awvalid => ipif_dma.axi_awvalid,
m_axi_awaddr => ipif_dma.axi_awaddr,
m_axi_awlen => ipif_dma.axi_awlen,
m_axi_awsize => ipif_dma.axi_awsize,
m_axi_awburst => ipif_dma.axi_awburst,
m_axi_awprot => ipif_dma.axi_awprot,
m_axi_awcache => ipif_dma.axi_awcache,
m_axi_wready => ipif_dma.axi_wready,
m_axi_wvalid => ipif_dma.axi_wvalid,
m_axi_wdata => ipif_dma.axi_wdata,
m_axi_wstrb => ipif_dma.axi_wstrb,
m_axi_wlast => ipif_dma.axi_wlast,
m_axi_bready => ipif_dma.axi_bready,
m_axi_bvalid => ipif_dma.axi_bvalid,
m_axi_bresp => ipif_dma.axi_bresp,
ip2bus_mstrd_req => ipif_dma.ipif_mstrd_req,
ip2bus_mstwr_req => ipif_dma.ipif_mstwr_req,
ip2bus_mst_addr => ipif_dma.ipif_mst_addr,
ip2bus_mst_length => ipif_dma.ipif_mst_length,
ip2bus_mst_be => ipif_dma.ipif_mst_be,
ip2bus_mst_type => ipif_dma.ipif_mst_type,
ip2bus_mst_lock => ipif_dma.ipif_mst_lock,
ip2bus_mst_reset => ipif_dma.ipif_mst_reset,
bus2ip_mst_cmdack => ipif_dma.ipif_mst_cmdack,
bus2ip_mst_cmplt => ipif_dma.ipif_mst_cmplt,
bus2ip_mst_error => ipif_dma.ipif_mst_error,
bus2ip_mst_rearbitrate => ipif_dma.ipif_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_dma.ipif_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_dma.ipif_mstrd_d,
bus2ip_mstrd_rem => ipif_dma.ipif_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_dma.ipif_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_dma.ipif_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_dma.ipif_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_dma.ipif_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_dma.ipif_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_dma.ipif_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_dma.ipif_mstwr_d,
ip2bus_mstwr_rem => ipif_dma.ipif_mstwr_rem,
ip2bus_mstwr_sof_n => ipif_dma.ipif_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_dma.ipif_mstwr_eof_n,
ip2bus_mstwr_src_rdy_n => ipif_dma.ipif_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_dma.ipif_mstwr_src_dsc_n,
bus2ip_mstwr_dst_rdy_n => ipif_dma.ipif_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_dma.ipif_mstwr_dst_dsc_n
);
--! The IPIF master handler converts the IPIF master signals to the
--! openMAC's DMA interface.
THEMACDMA_IPIF_HANDLER : entity work.ipifMasterHandler
generic map (
gMasterAddrWidth => ipif_dmaMasterHdler.masterAddress'length,
gMasterBurstCountWidth => ipif_dmaMasterHdler.masterBurstcount'length,
gIpifAddrWidth => ipif_dmaMasterHdler.ipif_addr'length,
gIpifLength => ipif_dmaMasterHdler.ipif_length'length
)
port map (
iRst => ipif_dmaMasterHdler.rst,
iClk => ipif_dmaMasterHdler.clk,
iIpif_cmdAck => ipif_dmaMasterHdler.ipif_cmdAck,
iIpif_cmplt => ipif_dmaMasterHdler.ipif_cmplt,
iIpif_error => ipif_dmaMasterHdler.ipif_error,
iIpif_rearbitrate => ipif_dmaMasterHdler.ipif_rearbitrate,
iIpif_cmdTimeout => ipif_dmaMasterHdler.ipif_cmdTimeout,
oIpif_type => ipif_dmaMasterHdler.ipif_type,
oIpif_addr => ipif_dmaMasterHdler.ipif_addr,
oIpif_length => ipif_dmaMasterHdler.ipif_length,
oIpif_be => ipif_dmaMasterHdler.ipif_be,
oIpif_lock => ipif_dmaMasterHdler.ipif_lock,
oIpif_reset => ipif_dmaMasterHdler.ipif_reset,
iIpif_rdData => ipif_dmaMasterHdler.ipif_rdData,
iIpif_rdRem => ipif_dmaMasterHdler.ipif_rdRem,
oIpif_rdReq => ipif_dmaMasterHdler.ipif_rdReq,
inIpif_rdSof => ipif_dmaMasterHdler.nIpif_rdSof,
inIpif_rdEof => ipif_dmaMasterHdler.nIpif_rdEof,
inIpif_rdSrcRdy => ipif_dmaMasterHdler.nIpif_rdSrcRdy,
inIpif_rdSrcDsc => ipif_dmaMasterHdler.nIpif_rdSrcDsc,
onIpif_rdDstRdy => ipif_dmaMasterHdler.nIpif_rdDstRdy,
onIpif_rdDstDsc => ipif_dmaMasterHdler.nIpif_rdDstDsc,
oIpif_wrData => ipif_dmaMasterHdler.ipif_wrData,
oIpif_wrRem => ipif_dmaMasterHdler.ipif_wrRem,
oIpif_wrReq => ipif_dmaMasterHdler.ipif_wrReq,
onIpif_wrSof => ipif_dmaMasterHdler.nIpif_wrSof,
onIpif_wrEof => ipif_dmaMasterHdler.nIpif_wrEof,
onIpif_wrSrcRdy => ipif_dmaMasterHdler.nIpif_wrSrcRdy,
onIpif_wrSrcDsc => ipif_dmaMasterHdler.nIpif_wrSrcDsc,
inIpif_wrDstRdy => ipif_dmaMasterHdler.nIpif_wrDstRdy,
inIpif_wrDstDsc => ipif_dmaMasterHdler.nIpif_wrDstDsc,
iMasterRead => ipif_dmaMasterHdler.masterRead,
iMasterWrite => ipif_dmaMasterHdler.masterWrite,
iMasterAddress => ipif_dmaMasterHdler.masterAddress,
iMasterWritedata => ipif_dmaMasterHdler.masterWritedata,
iMasterBurstcount => ipif_dmaMasterHdler.masterBurstcount,
iMasterBurstcounter => ipif_dmaMasterHdler.masterBurstcounter,
oMasterReaddata => ipif_dmaMasterHdler.masterReaddata,
oMasterWaitrequest => ipif_dmaMasterHdler.masterWaitrequest,
oMasterReaddatavalid => ipif_dmaMasterHdler.masterReaddatavalid
);
end generate GEN_THEMACDMA;
GEN_RMII_CLK : if gPhyPortType = cPhyPortRmii generate
GEN_ODDR2 : for i in oRmii_clk'range generate
signal rmiiClk : std_logic;
signal nRmiiClk : std_logic;
begin
-- Assign rmii clock (used by openMAC) and the inverted to ODDR2.
rmiiClk <= intf_clkRst.clk;
nRmiiClk <= not rmiiClk;
--! This is a dual data rate output FF used to output the internal
--! RMII clock.
THEODDR2 : oddr2
generic map (
DDR_ALIGNMENT => "NONE", -- align D0 with C0 and D1 with C1 edge
INIT => '0', -- initialize Q with '0'
SRTYPE => "SYNC" -- take default, since RS are unused
)
port map (
D0 => cActivated,
D1 => cInactivated,
C0 => rmiiClk,
C1 => nRmiiClk,
CE => cActivated,
R => cInactivated, --unused
S => cInactivated, --unused
Q => oRmii_clk(i)
);
end generate GEN_ODDR2;
end generate GEN_RMII_CLK;
---------------------------------------------------------------------------
-- TEST VECTOR
---------------------------------------------------------------------------
TEST_ASSIGN : process (
intf_macReg, intf_macTimer, intf_dma, intf_pktBuf,
ipif_macReg, ipif_dma, ipif_pktBuf,
xing_macReg
)
constant cTestPortMode : string := "MAC_REG";
begin
-- default is zero
testPort <= (others => cInactivated);
case cTestPortMode is
when "MAC_REG" =>
testPort(181 downto 179) <= intf_macReg.chipselect & intf_macReg.write & intf_macReg.read;
testPort(178) <= intf_macReg.waitrequest;
testPort(177 downto 176) <= intf_macReg.byteenable;
testPort(172 downto 160) <= intf_macReg.address;
testPort(159 downto 144) <= intf_macReg.writedata;
testPort(143 downto 128) <= intf_macReg.readdata;
testPort(104 downto 102) <= ipif_macReg.ipif_cs & ipif_macReg.ipif_rnw;
testPort(101 downto 100) <= ipif_macReg.ipif_wrack & ipif_macReg.ipif_rdack;
testPort(99 downto 96) <= ipif_macReg.ipif_be;
testPort(95 downto 64) <= ipif_macReg.ipif_addr;
testPort(63 downto 32) <= ipif_macReg.ipif_wrdata;
testPort(31 downto 0) <= ipif_macReg.ipif_rddata;
when "MAC_DMA" =>
testPort(255 downto 251) <= intf_dma.read & intf_dma.write & intf_dma.waitrequest & intf_dma.readdatavalid & ipif_dma.ipif_mst_type;
testPort(244 downto 240) <= ipif_dma.ipif_mstwr_req & ipif_dma.ipif_mstwr_sof_n & ipif_dma.ipif_mstwr_eof_n &
ipif_dma.ipif_mstwr_src_rdy_n & ipif_dma.ipif_mstwr_dst_rdy_n;
testPort(234 downto 230) <= ipif_dma.ipif_mstrd_req & ipif_dma.ipif_mstrd_sof_n & ipif_dma.ipif_mstrd_eof_n &
ipif_dma.ipif_mstrd_src_rdy_n & ipif_dma.ipif_mstrd_dst_rdy_n;
testPort(142 downto 140) <= ipif_dma.ipif_mst_cmplt & ipif_dma.ipif_mst_error & ipif_dma.ipif_mst_cmd_timeout;
testPort(ipif_dma.ipif_mst_length'length+120-1 downto 120) <= ipif_dma.ipif_mst_length;
testPort(intf_dma.burstcount'length+110-1 downto 110) <= intf_dma.burstcount;
testPort(intf_dma.burstcounter'length+96-1 downto 96) <= intf_dma.burstcounter;
testPort(95 downto 64) <= intf_dma.address;
testPort(63 downto 32) <= intf_dma.writedata;
testPort(31 downto 0) <= intf_dma.readdata;
when others =>
assert (FALSE) report "Unknown Test Port mode!" severity failure;
end case;
end process TEST_ASSIGN;
end rtl;
| gpl-2.0 | a4fc4175b5622fd53338760c83ce5300 | 0.523787 | 4.045122 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MINIUART/utils.vhd | 1 | 4,045 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : utils.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
-- Description: VHDL utility file
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Philippe CARTON 19 December 2001 New model
-- [email protected]
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Synchroniser:
-- Synchronize an input signal (C1) with an input clock (C).
-- The result is the O signal which is synchronous of C, and persist for
-- one C clock period.
--------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.std_logic_1164.all;
entity synchroniser is
port (
C1 : in std_logic;-- Asynchronous signal
C : in std_logic;-- Clock
O : out std_logic);-- Synchronised signal
end synchroniser;
architecture Behaviour of synchroniser is
signal C1A : std_logic;
signal C1S : std_logic;
signal R : std_logic;
begin
RiseC1A : process(C1,R)
begin
if Rising_Edge(C1) then
C1A <= '1';
end if;
if (R = '1') then
C1A <= '0';
end if;
end process;
SyncP : process(C,R)
begin
if Rising_Edge(C) then
if (C1A = '1') then
C1S <= '1';
else C1S <= '0';
end if;
if (C1S = '1') then
R <= '1';
else R <= '0';
end if;
end if;
if (R = '1') then
C1S <= '0';
end if;
end process;
O <= C1S;
end Behaviour;
-------------------------------------------------------------------------------
-- Counter
-- This counter is a parametrizable clock divider.
-- The count value is the generic parameter Count.
-- It is CE enabled. (it will count only if CE is high).
-- When it overflow, it will emit a pulse on O.
-- It can be reseted to 0.
-------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Counter is
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
Count : in std_logic_vector (15 downto 0); -- Count revolution
O : out std_logic); -- Output
end Counter;
architecture Behaviour of Counter is
begin
counter : process(Clk,Reset,Count)
variable Cnt : unsigned (15 downto 0);
begin
if Reset = '1' then
Cnt := unsigned(Count);
O <= '0';
elsif Rising_Edge(Clk) then
if CE = '1' then
if Cnt = 1 then
O <= '1';
Cnt := unsigned(Count);
else
O <= '0';
Cnt := Cnt - 1;
end if;
else O <= '0';
end if;
end if;
end process;
end Behaviour;
| apache-2.0 | 60e029214a920254b069f70f2a5da860 | 0.416811 | 4.401523 | false | false | false | false |
riverever/verilogTestSuit | ivltests/vhdl_test7.vhd | 2 | 662 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
tmp := input; -- use multiple assignments to the same variable
tmp := (7 => input(7), others => '1'); -- inluding slices in a process
output <= tmp;
end process;
end;
| gpl-2.0 | d3838334b5a5a49eeef4f9d4ec78eafc | 0.608761 | 3.540107 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/kChans.vhdl | 1 | 17,209 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity kChans is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_k_conductance : in sfixed (-22 downto -53);
exposure_conductance_k_g : out sfixed (-22 downto -53);
derivedvariable_conductance_k_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_k_g_in : in sfixed (-22 downto -53);
param_none_k_n_instances : in sfixed (18 downto -13);
exposure_none_k_n_fcond : out sfixed (18 downto -13);
exposure_none_k_n_q : out sfixed (18 downto -13);
statevariable_none_k_n_q_out : out sfixed (18 downto -13);
statevariable_none_k_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_k_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_k_n_fcond_in : in sfixed (18 downto -13);
param_per_time_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_k_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_k_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end kChans;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of kChans is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_conductance_channelg : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_channelg_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component k
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
param_none_n_instances : in sfixed (18 downto -13);
exposure_none_n_fcond : out sfixed (18 downto -13);
exposure_none_n_q : out sfixed (18 downto -13);
statevariable_none_n_q_out : out sfixed (18 downto -13);
statevariable_none_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_n_fcond_in : in sfixed (18 downto -13);
param_per_time_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_n_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal k_Component_done : STD_LOGIC ; signal Exposure_conductance_k_g_internal : sfixed (-22 downto -53);
signal Exposure_none_k_n_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_k_n_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_k_n_forwardRaten1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_k_n_reverseRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
k_uut : k
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => k_Component_done,
param_conductance_conductance => param_conductance_k_conductance,
requirement_voltage_v => requirement_voltage_v,
Exposure_conductance_g => Exposure_conductance_k_g_internal,
derivedvariable_conductance_g_out => derivedvariable_conductance_k_g_out,
derivedvariable_conductance_g_in => derivedvariable_conductance_k_g_in,
param_none_n_instances => param_none_k_n_instances,
Exposure_none_n_fcond => Exposure_none_k_n_fcond_internal,
Exposure_none_n_q => Exposure_none_k_n_q_internal,
statevariable_none_n_q_out => statevariable_none_k_n_q_out,
statevariable_none_n_q_in => statevariable_none_k_n_q_in,
derivedvariable_none_n_fcond_out => derivedvariable_none_k_n_fcond_out,
derivedvariable_none_n_fcond_in => derivedvariable_none_k_n_fcond_in,
param_per_time_n_forwardRaten1_rate => param_per_time_k_n_forwardRaten1_rate,
param_voltage_n_forwardRaten1_midpoint => param_voltage_k_n_forwardRaten1_midpoint,
param_voltage_n_forwardRaten1_scale => param_voltage_k_n_forwardRaten1_scale,
param_voltage_inv_n_forwardRaten1_scale_inv => param_voltage_inv_k_n_forwardRaten1_scale_inv,
Exposure_per_time_n_forwardRaten1_r => Exposure_per_time_k_n_forwardRaten1_r_internal,
derivedvariable_per_time_n_forwardRaten1_r_out => derivedvariable_per_time_k_n_forwardRaten1_r_out,
derivedvariable_per_time_n_forwardRaten1_r_in => derivedvariable_per_time_k_n_forwardRaten1_r_in,
param_per_time_n_reverseRaten1_rate => param_per_time_k_n_reverseRaten1_rate,
param_voltage_n_reverseRaten1_midpoint => param_voltage_k_n_reverseRaten1_midpoint,
param_voltage_n_reverseRaten1_scale => param_voltage_k_n_reverseRaten1_scale,
param_voltage_inv_n_reverseRaten1_scale_inv => param_voltage_inv_k_n_reverseRaten1_scale_inv,
Exposure_per_time_n_reverseRaten1_r => Exposure_per_time_k_n_reverseRaten1_r_internal,
derivedvariable_per_time_n_reverseRaten1_r_out => derivedvariable_per_time_k_n_reverseRaten1_r_out,
derivedvariable_per_time_n_reverseRaten1_r_in => derivedvariable_per_time_k_n_reverseRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_conductance_k_g <= Exposure_conductance_k_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_conductance_k_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_conductance_k_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
derivedvariable_conductance_channelg_next <= resize(( exposure_conductance_k_g_internal ),-22,-53);
derivedvariable_conductance_geff_next <= resize(( derivedvariable_conductance_channelg_next * param_none_number ),-22,-53);
derivedvariable_current_i_next <= resize(( derivedvariable_conductance_geff_next * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_conductance_channelg <= derivedvariable_conductance_channelg_next;
derivedvariable_conductance_geff <= derivedvariable_conductance_geff_next;
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(k_component_done,CLK)
begin
if (k_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | 446eeaa1fd3339a805a18f0c911273ba | 0.59835 | 3.544593 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/ParamExp.vhdl | 1 | 7,317 | --
-- Parameterisable N to M mux.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Done : Out Std_logic;
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end ParamExp;
architecture RTL of ParamExp is
type MEM is array (0 to 7) of sfixed(BIT_TOP downto BIT_BOTTOM);
signal ISPOSITIVE : STD_LOGIC := '0';
signal ISGREATERTHANONE : STD_LOGIC := '0';
signal X_integer : sfixed(BIT_TOP downto 0);
signal X_fraction : sfixed(0 downto BIT_BOTTOM);
signal Output_int : sfixed(BIT_TOP downto BIT_BOTTOM);
signal Done_int : Std_logic;
signal output_fraction : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_fraction_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal current_term : sfixed(BIT_TOP downto BIT_BOTTOM);
signal current_term_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal COUNT_FRACTION : unsigned(3 downto 0);
signal COUNT_FRACTION_next : unsigned(3 downto 0);
signal DONEFRACTION : STD_LOGIC := '0';
signal DONEFRACTION_next : STD_LOGIC := '0';
signal output_integer : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_integer_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal COUNT_INTEGER : unsigned(BIT_TOP+1 downto 0);
signal COUNT_INTEGER_next : unsigned(BIT_TOP+1 downto 0);
signal DONEINTEGER : STD_LOGIC := '0';
signal DONEINTEGER_next : STD_LOGIC := '0';
signal E : sfixed(BIT_TOP downto BIT_BOTTOM) := to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM);
signal EInv : sfixed(BIT_TOP downto BIT_BOTTOM) := resize(reciprocal(to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM)),BIT_TOP,BIT_BOTTOM);
signal EMul : sfixed(BIT_TOP downto BIT_BOTTOM);
signal n1: sfixed (BIT_TOP downto 0);
signal n2: sfixed (n1'high + 1 downto n1'low);
signal n3: ufixed (BIT_TOP + 1 downto 0);
begin
splitUpXProcess: process(X,X_integer,ispositive,E,EInv)
begin
X_integer <= resize(abs(X) - 0.5,BIT_TOP,0);
X_fraction <= resize(abs(X) - X_integer,0,BIT_BOTTOM);
if To_slv ( resize ( X ,BIT_TOP,BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '0' then
ISPOSITIVE <= '1';
else
ISPOSITIVE <= '0';
end if;
if (ISPOSITIVE = '1') then
EMul <= E;
else
EMul <= EInv;
end if;
end process splitUpXProcess;
fractionCombProcess: process(COUNT_FRACTION,Start,output_fraction,current_term,X_fraction,ISPOSITIVE,current_term_next,init_model)
variable MEM8Xsfixed : MEM := (to_sfixed (1,BIT_TOP, BIT_BOTTOM),to_sfixed (0.5,BIT_TOP, BIT_BOTTOM),to_sfixed (0.33333333,BIT_TOP, BIT_BOTTOM),to_sfixed (0.25,BIT_TOP, BIT_BOTTOM),
to_sfixed (0.2,BIT_TOP, BIT_BOTTOM),to_sfixed (0.16666666667,BIT_TOP, BIT_BOTTOM),to_sfixed (0.142857142857,BIT_TOP, BIT_BOTTOM),to_sfixed (0.125,BIT_TOP, BIT_BOTTOM));
variable MEM8XsfixedOutTemp : sfixed(BIT_TOP downto BIT_BOTTOM);
begin
output_fraction_next <= output_fraction;
COUNT_FRACTION_next <= COUNT_FRACTION;
current_term_next <= current_term;
DONEFRACTION_next <= '0';
MEM8XsfixedOutTemp := MEM8Xsfixed(to_integer(unsigned(COUNT_FRACTION(2 downto 0))));
current_term_next <= resize(MEM8XsfixedOutTemp *
resize(X_fraction * current_term,BIT_TOP, BIT_BOTTOM),BIT_TOP, BIT_BOTTOM);
if init_model = '1' then
DONEFRACTION_next <= '1';
COUNT_FRACTION_next <= "1001";
output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if Start = '1' then
DONEFRACTION_next <= '0';
COUNT_FRACTION_next <= "0000";
output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
elsif COUNT_FRACTION = "1001" then
DONEFRACTION_next <= '1';
current_term_next <= current_term;
else
DONEFRACTION_next <= '0';
if (ISPOSITIVE = '1') then
output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM);
else
if (COUNT_FRACTION(0) = '0') then
output_fraction_next <= resize(output_fraction - current_term_next,BIT_TOP, BIT_BOTTOM);
else
output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM);
end if;
end if;
COUNT_FRACTION_next <= COUNT_FRACTION + 1;
end if;
end if;
end process fractionCombProcess;
fractionSynProcess: process(clk)
variable Sel : integer;
begin
if clk'event and clk = '1' then
output_fraction <= output_fraction_next;
COUNT_FRACTION <= COUNT_FRACTION_next;
current_term <= current_term_next;
DONEFRACTION <= DONEFRACTION_next;
--report "The value of output_fraction = " & real'image(to_real(output_fraction)) & " and current_term " &
-- real'image(to_real(current_term));
end if;
end process fractionSynProcess;
integerCombProcess: process(COUNT_INTEGER,output_integer,x_integer,Start,EMul,init_model)
begin
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= COUNT_INTEGER;
output_integer_next <= output_integer;
if init_model = '1' then
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= to_unsigned(0,COUNT_INTEGER_next'length);
output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if Start = '1' then
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= unsigned(ufixed(abs(X_integer)));
output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if COUNT_INTEGER = 0 then
DONEINTEGER_next <= '1';
COUNT_INTEGER_next <= COUNT_INTEGER;
output_integer_next <= output_integer;
else
DONEINTEGER_next <= '0';
output_integer_next <= resize(output_integer * EMul,BIT_TOP,BIT_BOTTOM);
COUNT_INTEGER_next <= COUNT_INTEGER - 1;
end if;
end if;
end if;
end process integerCombProcess;
integerSynProcess: process(clk,x_integer,count_integer,output_integer)
begin
COUNT_INTEGER <= COUNT_INTEGER;
output_integer <= output_integer;
if clk = '1' and clk'event then
COUNT_INTEGER <= COUNT_INTEGER_next;
output_integer <= output_integer_next;
DONEINTEGER <= DONEINTEGER_next;
end if;
end process integerSynProcess;
outputCombProcess: process(output_fraction,output_integer,DONEINTEGER,DONEFRACTION)
begin
Output_int <= resize(output_fraction * output_integer,BIT_TOP, BIT_BOTTOM);
if DONEFRACTION = '1' and DONEINTEGER = '1' then
Done_int <= '1';
else
Done_int <= '0';
end if;
end process outputCombProcess;
Done <= Done_int;
Output <= Output_int;
--process (DONEFRACTION)
--begin
-- if (DONEFRACTION'event or DONEINTEGER'event) and DONEFRACTION = '1' and DONEINTEGER = '1' then
-- report "The value of X_integer = " & real'image(to_real(X_integer)) & " and X_fraction " & real'image(to_real(X_fraction));
-- report "The value of exp( " & real'image(to_real(X)) & " ) = " &
-- real'image(to_real(output_integer)) & " * " & real'image(to_real(output_fraction));
-- end if;
--end process;
end RTL;
| lgpl-3.0 | 64baedbc97ba1dba103d02de219f90e4 | 0.684297 | 3.003695 | false | false | false | false |
kristofferkoch/ethersound | txcrc.vhd | 1 | 6,560 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:53:34 07/04/2008
-- Design Name:
-- Module Name: txcrc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity txcrc is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data_o : out STD_LOGIC_VECTOR (7 downto 0);
data_send : out STD_LOGIC;
data_o_req : in STD_LOGIC;
data_i : in STD_LOGIC_VECTOR (7 downto 0);
data_i_v : in STD_LOGIC;
data_i_req : out STD_LOGIC);
end txcrc;
architecture Behavioral of txcrc is
function nextCRC32_D8 (
Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0)
) return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NewCRC: std_logic_vector(31 downto 0);
begin
-- D(0) := Data(7);
-- D(1) := Data(6);
-- D(2) := Data(5);
-- D(3) := Data(4);
-- D(4) := Data(3);
-- D(5) := Data(2);
-- D(6) := Data(1);
-- D(7) := Data(0);
D(0) := Data(3);
D(1) := Data(2);
D(2) := Data(1);
D(3) := Data(0);
D(4) := Data(7);
D(5) := Data(6);
D(6) := Data(5);
D(7) := Data(4);
C := CRC;
NewCRC(0) := D(6) xor D(0) xor C(24) xor C(30);
NewCRC(1) := D(7) xor D(6) xor D(1) xor D(0) xor C(24) xor C(25) xor
C(30) xor C(31);
NewCRC(2) := D(7) xor D(6) xor D(2) xor D(1) xor D(0) xor C(24) xor
C(25) xor C(26) xor C(30) xor C(31);
NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(25) xor C(26) xor
C(27) xor C(31);
NewCRC(4) := D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(24) xor
C(26) xor C(27) xor C(28) xor C(30);
NewCRC(5) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(1) xor
D(0) xor C(24) xor C(25) xor C(27) xor C(28) xor C(29) xor
C(30) xor C(31);
NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor
C(25) xor C(26) xor C(28) xor C(29) xor C(30) xor C(31);
NewCRC(7) := D(7) xor D(5) xor D(3) xor D(2) xor D(0) xor C(24) xor
C(26) xor C(27) xor C(29) xor C(31);
NewCRC(8) := D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor C(24) xor
C(25) xor C(27) xor C(28);
NewCRC(9) := D(5) xor D(4) xor D(2) xor D(1) xor C(1) xor C(25) xor
C(26) xor C(28) xor C(29);
NewCRC(10) := D(5) xor D(3) xor D(2) xor D(0) xor C(2) xor C(24) xor
C(26) xor C(27) xor C(29);
NewCRC(11) := D(4) xor D(3) xor D(1) xor D(0) xor C(3) xor C(24) xor
C(25) xor C(27) xor C(28);
NewCRC(12) := D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor D(0) xor
C(4) xor C(24) xor C(25) xor C(26) xor C(28) xor C(29) xor
C(30);
NewCRC(13) := D(7) xor D(6) xor D(5) xor D(3) xor D(2) xor D(1) xor
C(5) xor C(25) xor C(26) xor C(27) xor C(29) xor C(30) xor
C(31);
NewCRC(14) := D(7) xor D(6) xor D(4) xor D(3) xor D(2) xor C(6) xor
C(26) xor C(27) xor C(28) xor C(30) xor C(31);
NewCRC(15) := D(7) xor D(5) xor D(4) xor D(3) xor C(7) xor C(27) xor
C(28) xor C(29) xor C(31);
NewCRC(16) := D(5) xor D(4) xor D(0) xor C(8) xor C(24) xor C(28) xor
C(29);
NewCRC(17) := D(6) xor D(5) xor D(1) xor C(9) xor C(25) xor C(29) xor
C(30);
NewCRC(18) := D(7) xor D(6) xor D(2) xor C(10) xor C(26) xor C(30) xor
C(31);
NewCRC(19) := D(7) xor D(3) xor C(11) xor C(27) xor C(31);
NewCRC(20) := D(4) xor C(12) xor C(28);
NewCRC(21) := D(5) xor C(13) xor C(29);
NewCRC(22) := D(0) xor C(14) xor C(24);
NewCRC(23) := D(6) xor D(1) xor D(0) xor C(15) xor C(24) xor C(25) xor
C(30);
NewCRC(24) := D(7) xor D(2) xor D(1) xor C(16) xor C(25) xor C(26) xor
C(31);
NewCRC(25) := D(3) xor D(2) xor C(17) xor C(26) xor C(27);
NewCRC(26) := D(6) xor D(4) xor D(3) xor D(0) xor C(18) xor C(24) xor
C(27) xor C(28) xor C(30);
NewCRC(27) := D(7) xor D(5) xor D(4) xor D(1) xor C(19) xor C(25) xor
C(28) xor C(29) xor C(31);
NewCRC(28) := D(6) xor D(5) xor D(2) xor C(20) xor C(26) xor C(29) xor
C(30);
NewCRC(29) := D(7) xor D(6) xor D(3) xor C(21) xor C(27) xor C(30) xor
C(31);
NewCRC(30) := D(7) xor D(4) xor C(22) xor C(28) xor C(31);
NewCRC(31) := D(5) xor C(23) xor C(29);
return NewCRC;
end nextCRC32_D8;
-- type state_t is (Idle, TX, st_CRC);
-- signal state:state_t;
--
-- signal ireg:std_logic_vector(7 downto 0);
-- signal counter:integer range 0 to 3;
-- signal crc, nextcrc:std_logic_vector(31 downto 0);
begin
data_o <= data_i when state = stCRC else crcmux;
-- nextcrc <= nextCRC32_D8(ireg, crc);
-- process(sysclk) is
-- begin
-- if rising_edge(sysclk) then
-- if reset = '1' then
-- data_i_req <= '0';
-- data_send <= '0';
-- state <= Idle;
-- crc <= (OTHERS => '1');
-- data_o <= (OTHERS => '0');
-- else
-- case state is
-- when TX =>
-- if data_o_req = '1' then
-- data_o <= ireg;
-- crc <= nextcrc;
-- data_send <= '1';
-- data_i_req <= '1';
-- else
-- data_i_req <= '0';
-- end if;
-- if data_i_v = '1' then
-- ireg <= data_i;
-- else
-- state <= st_CRC;
-- counter <= 3;
-- ireg <= (OTHERS => '0');
-- end if;
-- when st_CRC =>
-- if data_o_req = '1' then
-- --data_o <= crc(counter*8+7 downto counter*8);
-- data_o(7) <= not crc(counter*8);
-- data_o(6) <= not crc(counter*8+1);
-- data_o(5) <= not crc(counter*8+2);
-- data_o(4) <= not crc(counter*8+3);
-- data_o(3) <= not crc(counter*8+4);
-- data_o(2) <= not crc(counter*8+5);
-- data_o(1) <= not crc(counter*8+6);
-- data_o(0) <= not crc(counter*8+7);
--
-- if counter = 0 then
-- state <= Idle;
-- data_i_req <= '1';
-- else
-- counter <= counter - 1;
-- data_i_req <= '0';
-- end if;
-- end if;
-- when others => --Idle
-- crc <= (OTHERS => '1');
-- if data_o_req = '1' then
-- data_send <= '0';
-- end if;
-- if data_i_v = '1' then
-- ireg <= data_i;
-- data_i_req <= '0';
-- state <= TX;
-- else
-- data_i_req <= '1';
-- end if;
-- end case;
-- end if;
-- end if;
-- end process;
end Behavioral;
| gpl-3.0 | fc827f4746c7793e0148f8065ef6d9b2 | 0.496646 | 2.257398 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/boards/terasic-de2-115/mn-dual-hostif-gpio/quartus/toplevel.vhd | 2 | 11,719 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of dual Nios MN design
--
--! @details This is the toplevel of the dual Nios MN FPGA design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- LED green
LEDG : out std_logic_vector(1 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- BENCHMARK
BENCHMARK : out std_logic_vector(7 downto 0);
-- BENCHMARK_AP
BENCHMARK_AP : out std_logic_vector(7 downto 0)
);
end toplevel;
architecture rtl of toplevel is
component mnDualHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
status_led_pio_export : out std_logic_vector(1 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
host_0_sdram_0_addr : out std_logic_vector(12 downto 0);
host_0_sdram_0_ba : out std_logic_vector(1 downto 0);
host_0_sdram_0_cas_n : out std_logic;
host_0_sdram_0_cke : out std_logic;
host_0_sdram_0_cs_n : out std_logic;
host_0_sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
host_0_sdram_0_dqm : out std_logic_vector(3 downto 0);
host_0_sdram_0_ras_n : out std_logic;
host_0_sdram_0_we_n : out std_logic;
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic
);
end component mnDualHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
inst : component mnDualHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
status_led_pio_export => LEDG,
host_0_benchmark_pio_export => BENCHMARK_AP,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
host_0_sdram_0_addr => SDRAM_ADDR,
host_0_sdram_0_ba => SDRAM_BA,
host_0_sdram_0_cas_n => SDRAM_CAS_n,
host_0_sdram_0_cke => SDRAM_CKE,
host_0_sdram_0_cs_n => SDRAM_CS_n,
host_0_sdram_0_dq => SDRAM_DQ,
host_0_sdram_0_dqm => SDRAM_DQM,
host_0_sdram_0_ras_n => SDRAM_RAS_n,
host_0_sdram_0_we_n => SDRAM_WE_n,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
end rtl;
| gpl-2.0 | 089f0f90a6f87c96ff975b0054349d9b | 0.464459 | 3.991485 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/m.vhdl | 1 | 20,346 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity m is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRatem1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end m;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of m is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_pow_fcond_power_result1_A : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_A_next : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X_next : sfixed(18 downto -13);
signal pow_fcond_power_result1 : sfixed(18 downto -13);
signal statevariable_none_noregime_q_temp_1 : sfixed (18 downto -13);
signal statevariable_none_noregime_q_temp_1_next : sfixed (18 downto -13);
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
Component ParamPow is
generic(
BIT_TOP : integer := 11;
BIT_BOTTOM : integer := -12);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_rateScale : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_rateScale_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_per_time_alpha : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_alpha_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_none_fcond : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fcond_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_time_tau : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
signal DerivedVariable_time_tau_next : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_none_q_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component forwardRatem1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal forwardRatem1_Component_done : STD_LOGIC ; signal Exposure_per_time_forwardRatem1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component reverseRatem1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal reverseRatem1_Component_done : STD_LOGIC ; signal Exposure_per_time_reverseRatem1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
forwardRatem1_uut : forwardRatem1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => forwardRatem1_Component_done,
param_per_time_rate => param_per_time_forwardRatem1_rate,
param_voltage_midpoint => param_voltage_forwardRatem1_midpoint,
param_voltage_scale => param_voltage_forwardRatem1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_forwardRatem1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_forwardRatem1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_forwardRatem1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_forwardRatem1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_forwardRatem1_r <= Exposure_per_time_forwardRatem1_r_internal;
reverseRatem1_uut : reverseRatem1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => reverseRatem1_Component_done,
param_per_time_rate => param_per_time_reverseRatem1_rate,
param_voltage_midpoint => param_voltage_reverseRatem1_midpoint,
param_voltage_scale => param_voltage_reverseRatem1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_reverseRatem1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_reverseRatem1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_reverseRatem1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_reverseRatem1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_reverseRatem1_r <= Exposure_per_time_reverseRatem1_r_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRatem1_r_internal,exposure_per_time_reverseRatem1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
pre_pow_fcond_power_result1_A_next <= resize( statevariable_none_q_in ,18,-13);
pre_pow_fcond_power_result1_X_next <= resize( param_none_instances ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_pow_fcond_power_result1_A <= to_sfixed(0,18,-13);
pre_pow_fcond_power_result1_X <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_pow_fcond_power_result1_A <= pre_pow_fcond_power_result1_A_next ;
pre_pow_fcond_power_result1_X <= pre_pow_fcond_power_result1_X_next ;
end if;
end if;end if; subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamPow_fcond_power_result1 : ParamPow
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_pow_fcond_power_result1_X ,
A => pre_pow_fcond_power_result1_A ,
Output => pow_fcond_power_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRatem1_r_internal,exposure_per_time_reverseRatem1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
derivedvariable_per_time_alpha_next <= resize(( exposure_per_time_forwardRatem1_r_internal ),18,-2);
derivedvariable_per_time_beta_next <= resize(( exposure_per_time_reverseRatem1_r_internal ),18,-2);
derivedvariable_none_fcond_next <= resize((pow_fcond_power_result1),18,-13);
derivedvariable_none_inf_next <= resize(( derivedvariable_per_time_alpha_next / ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ),18,-13);
derivedvariable_time_tau_next <= resize(( to_sfixed ( 1 ,1 , -1 ) / ( ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ) ),6,-18);
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_m : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_alpha <= derivedvariable_per_time_alpha_next;
derivedvariable_per_time_beta <= derivedvariable_per_time_beta_next;
derivedvariable_none_fcond <= derivedvariable_none_fcond_next;
derivedvariable_none_inf <= derivedvariable_none_inf_next;
derivedvariable_time_tau <= derivedvariable_time_tau_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf ,statevariable_none_q_in)
begin
statevariable_none_noregime_q_temp_1_next <= resize(statevariable_none_q_in + ( ( derivedvariable_none_inf - statevariable_none_q_in ) / derivedvariable_time_tau ) * sysparam_time_timestep,18,-13);
end process state_variable_process_dynamics_comb;
uut_delayDone_statevariable_m : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_dyn_ready
);state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_none_noregime_q_temp_1 <= statevariable_none_noregime_q_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,derivedvariable_none_inf,statevariable_none_noregime_q_temp_1,statevariable_none_q_in,derivedvariable_time_tau,derivedvariable_none_inf)
variable statevariable_none_q_temp_1 : sfixed (18 downto -13);
begin
statevariable_none_q_temp_1 := statevariable_none_noregime_q_temp_1; statevariable_none_q_next <= statevariable_none_q_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_none_q <= statevariable_none_q_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_none_q_out <= statevariable_none_q_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_none_fcond <= derivedvariable_none_fcond_in;derivedvariable_none_fcond_out <= derivedvariable_none_fcond;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(forwardRatem1_component_done,reverseRatem1_component_done,CLK)
begin
if (forwardRatem1_component_done = '1' and reverseRatem1_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | 1172cc388bb45d1a45b27c2d53b0aa20 | 0.604443 | 3.550785 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/controller-behaviour.vhdl | 1 | 29,259 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: controller-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 21:36:38 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of DLX control section.
--
use work.bv_arithmetic.all, std.textio.all;
architecture behaviour of controller is
begin -- behaviour
sequencer : process
alias IR_opcode : dlx_opcode is current_instruction(0 to 5);
alias IR_sp_func : dlx_sp_func is current_instruction(26 to 31);
alias IR_fp_func : dlx_fp_func is current_instruction(27 to 31);
alias IR_rs1 : dlx_reg_addr is current_instruction(6 to 10);
alias IR_rs2 : dlx_reg_addr is current_instruction(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is current_instruction(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is current_instruction(16 to 20);
alias IR_immed16 : dlx_immed16 is current_instruction(16 to 31);
alias IR_immed26 : dlx_immed26 is current_instruction(6 to 31);
variable IR_opcode_num : dlx_opcode_num;
variable IR_sp_func_num : dlx_sp_func_num;
variable IR_fp_func_num : dlx_fp_func_num;
variable result_of_set_is_1, branch_taken : boolean;
variable L : line;
procedure bus_instruction_fetch is
begin
-- use PC as address
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
-- set up memory control signals
width <= width_word after Tpd_clk_ctrl;
ifetch <= '1' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until phi2, then enable IR input
wait until phi2 = '1';
ir_latch_en <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until phi2 = '0';
if reset = '1' then
return;
end if;
exit when ready = '1';
end loop;
-- disable IR input and memory control signals
ir_latch_en <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
end bus_instruction_fetch;
procedure bus_data_read(read_width : in mem_width) is
begin
-- use MAR as address
mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
-- set up memory control signals
width <= read_width after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until phi2, then enable MDR input
wait until phi2 = '1';
mdr_mux_sel <= '1' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until phi2 = '0';
if reset = '1' then
return;
end if;
exit when ready = '1';
end loop;
-- disable MDR input and memory control signals
mdr_latch_en <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
end bus_data_read;
procedure bus_data_write(write_width : in mem_width) is
begin
-- use MAR as address
mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
-- enable MDR output
mdr_out_en3 <= '1' after Tpd_clk_ctrl;
-- set up memory control signals
width <= write_width after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
write_enable <= '1' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until phi2 = '0';
if reset = '1' then
return;
end if;
exit when ready = '1';
end loop;
-- disable MDR output and memory control signals
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
end bus_data_write;
procedure do_set_result is
begin
wait until phi1 = '1';
if result_of_set_is_1 then
const2 <= X"0000_0001" after Tpd_clk_const;
else
const2 <= X"0000_0000" after Tpd_clk_const;
end if;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_set_result;
procedure do_EX_set_unsigned(immed : boolean) is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
if immed then
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '1' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
else
b_out_en <= '1' after Tpd_clk_ctrl;
end if;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_subu after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
if immed then
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
else
b_out_en <= '0' after Tpd_clk_ctrl;
end if;
--
wait until phi2 = '0';
if immed then
case IR_opcode is
when op_sequi =>
result_of_set_is_1 := alu_zero = '1';
when op_sneui =>
result_of_set_is_1 := alu_zero /= '1';
when op_sltui =>
result_of_set_is_1 := alu_overflow = '1';
when op_sgtui =>
result_of_set_is_1 := alu_overflow /= '1' and alu_zero /= '1';
when op_sleui =>
result_of_set_is_1 := alu_overflow = '1' or alu_zero = '1';
when op_sgeui =>
result_of_set_is_1 := alu_overflow /= '1';
when others =>
null;
end case;
else
case IR_sp_func is
when sp_func_sequ =>
result_of_set_is_1 := alu_zero = '1';
when sp_func_sneu =>
result_of_set_is_1 := alu_zero /= '1';
when sp_func_sltu =>
result_of_set_is_1 := alu_overflow = '1';
when sp_func_sgtu =>
result_of_set_is_1 := alu_overflow /= '1' and alu_zero /= '1';
when sp_func_sleu =>
result_of_set_is_1 := alu_overflow = '1' or alu_zero = '1';
when sp_func_sgeu =>
result_of_set_is_1 := alu_overflow /= '1';
when others =>
null;
end case;
end if;
--
do_set_result;
end do_EX_set_unsigned;
procedure do_EX_set_signed(immed : boolean) is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
if immed then
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
else
b_out_en <= '1' after Tpd_clk_ctrl;
end if;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sub after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
if immed then
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
else
b_out_en <= '0' after Tpd_clk_ctrl;
end if;
--
wait until phi2 = '0';
if immed then
case IR_opcode is
when op_seqi =>
result_of_set_is_1 := alu_zero = '1';
when op_snei =>
result_of_set_is_1 := alu_zero /= '1';
when op_slti =>
result_of_set_is_1 := alu_negative = '1';
when op_sgti =>
result_of_set_is_1 := alu_negative /= '1' and alu_zero /= '1';
when op_slei =>
result_of_set_is_1 := alu_negative = '1' or alu_zero = '1';
when op_sgei =>
result_of_set_is_1 := alu_negative /= '1';
when others =>
null;
end case;
else
case IR_sp_func is
when sp_func_seq =>
result_of_set_is_1 := alu_zero = '1';
when sp_func_sne =>
result_of_set_is_1 := alu_zero /= '1';
when sp_func_slt =>
result_of_set_is_1 := alu_negative = '1';
when sp_func_sgt =>
result_of_set_is_1 := alu_negative /= '1' and alu_zero /= '1';
when sp_func_sle =>
result_of_set_is_1 := alu_negative = '1' or alu_zero = '1';
when sp_func_sge =>
result_of_set_is_1 := alu_negative /= '1';
when others =>
null;
end case;
end if;
--
do_set_result;
end do_EX_set_signed;
procedure do_EX_arith_logic is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
b_out_en <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
case IR_sp_func is
when sp_func_add =>
alu_function <= alu_add after Tpd_clk_ctrl;
when sp_func_addu =>
alu_function <= alu_addu after Tpd_clk_ctrl;
when sp_func_sub =>
alu_function <= alu_sub after Tpd_clk_ctrl;
when sp_func_subu =>
alu_function <= alu_subu after Tpd_clk_ctrl;
when sp_func_and =>
alu_function <= alu_and after Tpd_clk_ctrl;
when sp_func_or =>
alu_function <= alu_or after Tpd_clk_ctrl;
when sp_func_xor =>
alu_function <= alu_xor after Tpd_clk_ctrl;
when sp_func_sll =>
alu_function <= alu_sll after Tpd_clk_ctrl;
when sp_func_srl =>
alu_function <= alu_srl after Tpd_clk_ctrl;
when sp_func_sra =>
alu_function <= alu_sra after Tpd_clk_ctrl;
when others =>
null;
end case; -- IR_sp_func
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
b_out_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_arith_logic;
procedure do_EX_arith_logic_immed is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
if IR_opcode = op_addi or IR_opcode = op_subi then
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
else
ir_immed_unsigned2 <= '1' after Tpd_clk_ctrl;
end if;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
case IR_opcode is
when op_addi =>
alu_function <= alu_add after Tpd_clk_ctrl;
when op_subi =>
alu_function <= alu_sub after Tpd_clk_ctrl;
when op_addui =>
alu_function <= alu_addu after Tpd_clk_ctrl;
when op_subui =>
alu_function <= alu_subu after Tpd_clk_ctrl;
when op_andi =>
alu_function <= alu_and after Tpd_clk_ctrl;
when op_ori =>
alu_function <= alu_or after Tpd_clk_ctrl;
when op_xori =>
alu_function <= alu_xor after Tpd_clk_ctrl;
when op_slli =>
alu_function <= alu_sll after Tpd_clk_ctrl;
when op_srli =>
alu_function <= alu_srl after Tpd_clk_ctrl;
when op_srai =>
alu_function <= alu_sra after Tpd_clk_ctrl;
when others =>
null;
end case; -- IR_opcode
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_arith_logic_immed;
procedure do_EX_link is
begin
wait until phi1 = '1';
pc_out_en1 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_link;
procedure do_EX_lhi is
begin
wait until phi1 = '1';
ir_immed_sel1 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned1 <= '1' after Tpd_clk_ctrl;
ir_immed_en1 <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0010" after Tpd_clk_const; -- shift by 16 bits
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sll after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
ir_immed_en1 <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_lhi;
procedure do_EX_branch is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0000" after Tpd_clk_const;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sub after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '0';
if IR_opcode = op_beqz then
branch_taken := alu_zero = '1';
else
branch_taken := alu_zero /= '1';
end if;
end do_EX_branch;
procedure do_EX_load_store is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
mar_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
mar_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_load_store;
procedure do_MEM_jump is
begin
wait until phi1 = '1';
pc_out_en1 <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_26 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_jump;
procedure do_MEM_jump_reg is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_jump_reg;
procedure do_MEM_branch is
begin
wait until phi1 = '1';
pc_out_en1 <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_branch;
procedure do_MEM_load is
begin
wait until phi1 = '1';
bus_data_read(width_word);
if reset = '1' then
return;
end if;
--
wait until phi1 = '1';
mdr_out_en1 <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi1 = '0';
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_load;
procedure do_MEM_store is
begin
wait until phi1 = '1';
b_out_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi1 = '0';
b_out_en <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
mdr_latch_en <= '0' after Tpd_clk_ctrl;
--
wait until phi1 = '1';
bus_data_write(width_word);
end do_MEM_store;
procedure do_WB(Rd : dlx_reg_addr) is
begin
wait until phi1 = '1';
reg_dest_addr <= Rd after Tpd_clk_ctrl;
reg_write <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
reg_write <= '0' after Tpd_clk_ctrl;
end do_WB;
begin -- sequencer
--
----------------------------------------------------------------
-- initialize all control signals
----------------------------------------------------------------
if debug then
write(L, string'("controller: initializing"));
writeline(output, L);
end if;
--
halt <= '0' after Tpd_clk_ctrl;
width <= width_word after Tpd_clk_ctrl;
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
reg_s1_addr <= B"00000" after Tpd_clk_ctrl;
reg_s2_addr <= B"00000" after Tpd_clk_ctrl;
reg_dest_addr <= B"00000" after Tpd_clk_ctrl;
reg_write <= '0' after Tpd_clk_ctrl;
c_latch_en <= '0' after Tpd_clk_ctrl;
a_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
b_latch_en <= '0' after Tpd_clk_ctrl;
b_out_en <= '0' after Tpd_clk_ctrl;
temp_latch_en <= '0' after Tpd_clk_ctrl;
temp_out_en1 <= '0' after Tpd_clk_ctrl;
temp_out_en2 <= '0' after Tpd_clk_ctrl;
iar_latch_en <= '0' after Tpd_clk_ctrl;
iar_out_en1 <= '0' after Tpd_clk_ctrl;
iar_out_en2 <= '0' after Tpd_clk_ctrl;
pc_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
pc_out_en2 <= '0' after Tpd_clk_ctrl;
mar_latch_en <= '0' after Tpd_clk_ctrl;
mar_out_en1 <= '0' after Tpd_clk_ctrl;
mar_out_en2 <= '0' after Tpd_clk_ctrl;
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '0' after Tpd_clk_ctrl;
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
mdr_out_en2 <= '0' after Tpd_clk_ctrl;
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
ir_latch_en <= '0' after Tpd_clk_ctrl;
ir_immed_sel1 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned1 <= '0' after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en1 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
const1 <= null after Tpd_clk_const;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '0' and reset = '0';
--
----------------------------------------------------------------
-- control loop
----------------------------------------------------------------
loop
--
----------------------------------------------------------------
-- fetch next instruction (IF)
----------------------------------------------------------------
wait until phi1 = '1';
if debug then
write(L, string'("controller: instruction fetch"));
writeline(output, L);
end if;
--
bus_instruction_fetch;
--
----------------------------------------------------------------
-- instruction decode, source register read, and PC increment (ID)
----------------------------------------------------------------
wait until phi1 = '1';
if debug then
write(L, string'("controller: decode, reg-read and PC incr"));
writeline(output, L);
end if;
--
IR_opcode_num := bv_to_natural(IR_opcode);
IR_sp_func_num := bv_to_natural(IR_sp_func);
IR_fp_func_num := bv_to_natural(IR_fp_func);
--
reg_s1_addr <= IR_rs1 after Tpd_clk_ctrl;
reg_s2_addr <= IR_rs2 after Tpd_clk_ctrl;
a_latch_en <= '1' after Tpd_clk_ctrl;
b_latch_en <= '1' after Tpd_clk_ctrl;
--
pc_out_en1 <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0004" after Tpd_clk_const;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_addu after Tpd_clk_ctrl;
--
wait until phi1 = '0';
a_latch_en <= '0' after Tpd_clk_ctrl;
b_latch_en <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
--
----------------------------------------------------------------
-- execute instruction, (EX, MEM, WB)
----------------------------------------------------------------
if debug then
write(L, string'("controller: execute"));
writeline(output, L);
end if;
--
case IR_opcode is
when op_special =>
case IR_sp_func is
when sp_func_nop =>
null;
when sp_func_sequ | sp_func_sneu |
sp_func_sltu | sp_func_sgtu |
sp_func_sleu | sp_func_sgeu =>
do_EX_set_unsigned(immed => false);
do_WB(IR_Rtype_rd);
when sp_func_add | sp_func_addu |
sp_func_sub | sp_func_subu |
sp_func_and | sp_func_or | sp_func_xor |
sp_func_sll | sp_func_srl | sp_func_sra =>
do_EX_arith_logic;
do_WB(IR_Rtype_rd);
when sp_func_seq | sp_func_sne |
sp_func_slt | sp_func_sgt |
sp_func_sle | sp_func_sge =>
do_EX_set_signed(immed => false);
do_WB(IR_Rtype_rd);
when sp_func_movi2s =>
assert false
report "MOVI2S instruction not implemented" severity warning;
when sp_func_movs2i =>
assert false
report "MOVS2I instruction not implemented" severity warning;
when sp_func_movf =>
assert false
report "MOVF instruction not implemented" severity warning;
when sp_func_movd =>
assert false
report "MOVD instruction not implemented" severity warning;
when sp_func_movfp2i =>
assert false
report "MOVFP2I instruction not implemented" severity warning;
when sp_func_movi2fp =>
assert false
report "MOVI2FP instruction not implemented" severity warning;
when others =>
assert false
report "undefined special instruction function" severity error;
end case;
when op_fparith =>
case IR_fp_func is
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu |
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
assert false
report "floating point instructions not implemented" severity warning;
when others =>
assert false
report "undefined floating point instruction function" severity error;
end case;
when op_j =>
do_MEM_jump;
when op_jr =>
do_MEM_jump_reg;
when op_jal =>
do_EX_link;
do_MEM_jump;
do_WB(natural_to_bv(link_reg, 5));
when op_jalr =>
do_EX_link;
do_MEM_jump_reg;
do_WB(natural_to_bv(link_reg, 5));
when op_beqz | op_bnez =>
do_EX_branch;
if branch_taken then
do_MEM_branch;
end if;
when op_bfpt =>
assert false
report "BFPT instruction not implemented" severity warning;
when op_bfpf =>
assert false
report "BFPF instruction not implemented" severity warning;
when op_addi | op_subi |
op_addui | op_subui |
op_andi | op_ori | op_xori |
op_slli | op_srli | op_srai =>
do_EX_arith_logic_immed;
do_WB(IR_Itype_rd);
when op_lhi =>
do_EX_lhi;
do_WB(IR_Itype_rd);
when op_rfe =>
assert false
report "RFE instruction not implemented" severity warning;
when op_trap =>
assert false
report "TRAP instruction encountered, execution halted"
severity note;
wait until phi1 = '1';
halt <= '1' after Tpd_clk_ctrl;
wait until reset = '1';
exit;
when op_seqi | op_snei | op_slti |
op_sgti | op_slei | op_sgei =>
do_EX_set_signed(immed => true);
do_WB(IR_Itype_rd);
when op_lb =>
assert false
report "LB instruction not implemented" severity warning;
when op_lh =>
assert false
report "LH instruction not implemented" severity warning;
when op_lw =>
do_EX_load_store;
do_MEM_load;
exit when reset = '1';
do_WB(IR_Itype_rd);
when op_sw =>
do_EX_load_store;
do_MEM_store;
exit when reset = '1';
when op_lbu =>
assert false
report "LBU instruction not implemented" severity warning;
when op_lhu =>
assert false
report "LHU instruction not implemented" severity warning;
when op_sb =>
assert false
report "SB instruction not implemented" severity warning;
when op_sh =>
assert false
report "SH instruction not implemented" severity warning;
when op_lf =>
assert false
report "LF instruction not implemented" severity warning;
when op_ld =>
assert false
report "LD instruction not implemented" severity warning;
when op_sf =>
assert false
report "SF instruction not implemented" severity warning;
when op_sd =>
assert false
report "SD instruction not implemented" severity warning;
when op_sequi | op_sneui | op_sltui |
op_sgtui | op_sleui | op_sgeui =>
do_EX_set_unsigned(immed => true);
do_WB(IR_Itype_rd);
when others =>
assert false
report "undefined instruction" severity error;
end case;
--
end loop;
--
----------------------------------------------------------------
-- loop exited on reset
----------------------------------------------------------------
assert reset = '1'
report "Internal error: reset code reached with reset = '0'"
severity failure;
--
-- start again
--
end process sequencer;
end behaviour;
| apache-2.0 | ce176a9c6628ba8d0dc0020dfbeb2e9c | 0.533784 | 3.313965 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/phyActGen-rtl-ea.vhd | 2 | 5,098 | -------------------------------------------------------------------------------
--! @file phyActGen-rtl-ea.vhd
--
--! @brief Phy activity generator
--
--! @details The phy activity generator generates a free-running clock-synchronous
--! packet activity signal. This signal can be used to drive an LED.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity phyActGen is
generic (
--! Generated activity frequency of oActivity [Hz]
gActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
gClkFreq : natural := 50e6
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! MAC Tx enable signal
iTxEnable : in std_logic;
--! MAC Rx data valid signal
iRxValid : in std_logic;
--! Generated activity signal
oActivity : out std_logic
);
end phyActGen;
architecture rtl of phyActGen is
--! Obtain maximum counter value to achieve activity frequency
constant cCntMaxValue : natural := gClkFreq / gActivityFreq;
--! Obtain counter width
constant cCntWidth : natural := logDualis(cCntMaxValue);
--! Constant for counter value zero
constant cCntIsZero : std_logic_vector(cCntWidth downto 0) := (others => cInactivated);
--! The counter
signal counter : std_logic_vector(cCntWidth-1 downto 0);
--! Terminal counter
signal counterTc : std_logic;
--! Trigger activity in next cycle due to packet activity
signal triggerActivity : std_logic;
--! Enable activity
signal enableActivity : std_logic;
begin
oActivity <= counter(counter'high) when enableActivity = cActivated else
cInactivated;
ledCntr : process(iRst, iClk)
begin
if iRst = cActivated then
triggerActivity <= cInactivated;
enableActivity <= cInactivated;
elsif rising_edge(iClk) then
--monoflop, of course no default value!
if triggerActivity = cActivated and counterTc = cActivated then
--counter overflow and activity within last cycle
enableActivity <= cActivated;
elsif counterTc = cActivated then
--counter overflow but no activity
enableActivity <= cInactivated;
end if;
--monoflop, of course no default value!
if counterTc = cActivated then
--count cycle over, reset trigger
triggerActivity <= cInactivated;
elsif iTxEnable = cActivated or iRxValid = cActivated then
--activity within cycle
triggerActivity <= cActivated;
end if;
end if;
end process;
theFreeRunCnt : process(iClk, iRst)
begin
if iRst = cActivated then
counter <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
counter <= std_logic_vector(unsigned(counter) - 1);
end if;
end process;
counterTc <= cActivated when counter = cCntIsZero else
cInactivated;
end rtl;
| gpl-2.0 | fa5e4f6b338624d6646cefcdb382971b | 0.615143 | 4.959144 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/reg_3_out-behaviour.vhdl | 1 | 1,851 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_3_out-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:14:21 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register with three tri-state outputs.
--
architecture behaviour of reg_3_out is
begin
reg: process (d, latch_en, out_en1, out_en2, out_en3)
variable latched_value : dlx_word;
begin
if latch_en = '1' then
latched_value := d;
end if;
if out_en1 = '1' then
q1 <= latched_value after Tpd;
else
q1 <= null after Tpd;
end if;
if out_en2 = '1' then
q2 <= latched_value after Tpd;
else
q2 <= null after Tpd;
end if;
if out_en3 = '1' then
q3 <= latched_value after Tpd;
else
q3 <= null after Tpd;
end if;
end process reg;
end behaviour;
| apache-2.0 | d18e78768c00710f1abc697873ecd443 | 0.580767 | 3.762195 | false | false | false | false |
s-kostyuk/course_project_csch | final_processor/decoder.vhd | 1 | 554 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
generic(
N: integer := 4
);
port(D: in std_logic_vector (N-1 downto 0);
En: in std_logic;
Q: out std_logic_vector (2**N -1 downto 0)
);
end entity;
architecture decoder of decoder is
begin
process(D, En) is
variable vQ: std_logic_vector(2**N - 1 downto 0);
begin
vQ := (others => '0');
if (En = '0') then -- Èíâåðñíûé En
vQ(conv_integer(D)) := '1';
end if;
Q <= vQ;
end process;
end architecture; | mit | c7ec77fbbdb22409f12360cb1c71972a | 0.599278 | 2.663462 | false | false | false | false |
matbur95/ucisw-pro | pro4b/master.vhd | 1 | 5,361 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:57 04/05/2017
-- Design Name:
-- Module Name: master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MASTER is
Port ( ADC_DOA : in STD_LOGIC_VECTOR (13 downto 0);
ADC_DOB : in STD_LOGIC_VECTOR (13 downto 0);
ADC_BUSY : in STD_LOGIC;
CLK : in STD_LOGIC;
POS : in STD_LOGIC_VECTOR(19 downto 0);
DATA : in STD_LOGIC;
Line : out STD_LOGIC_VECTOR (63 downto 0);
Blank : out STD_LOGIC_VECTOR (15 downto 0);
ADDR : out STD_LOGIC_VECTOR (13 downto 0);
VGA_COLOR : out STD_LOGIC_VECTOR(2 downto 0);
AMP_WE : out STD_LOGIC;
ADC_Start : out STD_LOGIC;
AMP_DI : out STD_LOGIC_VECTOR (7 downto 0));
end MASTER;
architecture Behavioral of MASTER is
-- constant SIDE : integer := 50;
constant SIDE : signed ( 10 downto 0 ) := to_signed( 20, 11);
constant VMAX : signed ( 10 downto 0 ) := to_signed( 600, 11);
constant HMAX : signed ( 10 downto 0 ) := to_signed( 800, 11);
-- constant HMAX : integer := 800;
-- signal BOX_HPOS : integer range -100 to 1000 := 400;
signal BOX_HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal BOX_VPOS : signed( 10 downto 0) := to_signed( 550, 11 );
constant BOX_VPOS_INIT : signed ( 10 downto 0 ) := to_signed( 550, 11);
constant BOX_HPOS_INIT : signed ( 10 downto 0 ) := to_signed( 0, 11);
-- signal BOX_VPOS : integer range -100 to 1000 := 300;
signal HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal VPOS : signed( 10 downto 0) := to_signed( 0, 11 );
-- signal HPOS : integer range 0 to 800 := 0;
-- signal VPOS : integer range 0 to 600 := 0;
signal VGA_COLOR_INT : STD_LOGIC_VECTOR(2 downto 0);
signal CLKTIME : signed(22 downto 0) := (others =>'0');
signal PLAYTIME : signed(15 downto 0) := to_signed(0, 16);
signal RESTART : STD_LOGIC := '0';
signal TIMER_EN : STD_LOGIC := '1';
begin
-- RESTART <= RESTART2 or RESTART3;
HPOS <= signed('0' & POS(19 downto 10));
VPOS <= signed('0' & POS(9 downto 0));
AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
AMP_DI <= X"22";
ADC_Start <= '1' when HPOS = HMAX and VPOS = VMAX else '0';
Blank <= X"0C30";
Line <= ADC_DOA & "00" & X"00" & ADC_DOB & "00" & X"00" & STD_LOGIC_VECTOR(PLAYTIME);
BOX: process (CLK, HPOS, VPOS)
begin
if rising_edge(CLK) then
if HPOS = 0 and VPOS = 0 then
BOX_HPOS <= BOX_HPOS - signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS + signed(ADC_DOB(13 downto 11));
end if;
if BOX_HPOS < 0 then
BOX_HPOS <= to_signed(0, 11);
elsif BOX_HPOS > HMAX - SIDE then
BOX_HPOS <= HMAX - SIDE;
end if;
if BOX_VPOS < 0 then
BOX_VPOS <= to_signed(0, 11);
elsif BOX_VPOS > VMAX - SIDE then
BOX_VPOS <= VMAX - SIDE;
end if;
if BOX_VPOS < 2 then
TIMER_EN <= '0';
end if;
if RESTART = '1' then
RESTART <= '0';
-- BOX_HPOS <= BOX_HPOS_INIT;
-- BOX_VPOS <= BOX_VPOS_INIT;
BOX_HPOS <= BOX_HPOS + signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS - signed(ADC_DOB(13 downto 11));
end if;
RESTART <= '0';
if DATA = '0' and
HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and
VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
RESTART <= '1';
end if;
end if;
end process BOX;
ADDR <= STD_LOGIC_VECTOR(VPOS(9 downto 3)) & STD_LOGIC_VECTOR(HPOS(9 downto 3));
VGA_COLOR_INT <= B"101" when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else DATA & DATA & not DATA;
-- VGA_COLOR_INT <= DATA & DATA & not DATA;
VGA_COLOR <= VGA_COLOR_INT;
TIMER: process (CLK)
begin
if rising_edge(CLK) then
if RESTART = '1' then
PLAYTIME <= PLAYTIME + 1;
-- PLAYTIME <= to_signed(0, 16);
end if;
if TIMER_EN = '1' then
if CLKTIME = "10011000100101101000000" then -- 5 MHz
CLKTIME <= "00000000000000000000000";
if PLAYTIME = X"ffff" then
PLAYTIME <= to_signed(0, 16);
else
PLAYTIME <= PLAYTIME + 1;
end if;
else
CLKTIME <= CLKTIME + 1;
end if;
end if;
end if;
end process TIMER;
end Behavioral;
| mit | 57039dbf58de2b9f65b0317c0cd967de | 0.531431 | 3.55504 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd | 2 | 35,771 | -- Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_avalon_mm_bursting_master_fifo is
generic (
-- all cusp function units have these
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
-- configuring the avalon port type
ADDR_WIDTH : integer := 16;
DATA_WIDTH : integer := 16;
READ_USED : integer := 1;
WRITE_USED : integer := 1;
-- configuring optimisations
CMD_FIFO_DEPTH : integer := 8;
RDATA_FIFO_DEPTH : integer := 8;
WDATA_FIFO_DEPTH : integer := 8;
WDATA_TARGET_BURST_SIZE : integer := 5;
RDATA_TARGET_BURST_SIZE : integer := 5;
CLOCKS_ARE_SYNC : integer := 1;
ADDRESS_GROUP : integer := 1;
BYTEENABLE_USED : integer := 1;
LEN_BE_WIDTH : integer := 11;
BURST_WIDTH : integer := 6;
-- interrupts
INTERRUPT_USED : INTEGER := 1;
INTERRUPT_WIDTH : INTEGER := 8
);
port (
-- cusp system clock, reset
clock : in std_logic;
reset : in std_logic;
-- interface to cusp
ena : in std_logic := '1';
ready : out std_logic; -- ???
stall : out std_logic;
-- cmd port
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
write : in std_logic := '0';
burst : in std_logic := '0';
len_be : in std_logic_vector(LEN_BE_WIDTH-1 downto 0) := (others => '0');
cenable : in std_logic;
cenable_en : in std_logic;
stall_command : out std_logic; -- JG: new output
-- wdata port
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
wenable : in std_logic;
wenable_en : in std_logic := '0';
stall_write : out std_logic; -- JG: new output
-- rdata port
rdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
renable : in std_logic := '0';
renable_en : in std_logic := '0';
stall_read : out std_logic; -- JG: new output
-- interrupt port
activeirqs : out std_logic_vector(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-- interface to avalon
av_address : out std_logic_vector(ADDR_WIDTH-1 downto 0);
av_burstcount : out std_logic_vector(BURST_WIDTH-1 downto 0);
av_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
av_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
av_write : out std_logic;
av_read : out std_logic;
av_clock : in std_logic;
av_reset : in std_logic := '0';
av_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_interrupt : in std_logic_vector(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
);
end entity;
architecture rtl of alt_vipvfr131_common_avalon_mm_bursting_master_fifo is
COMPONENT sync_vec IS
GENERIC (
WIDTH : INTEGER
);
PORT (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
data_out : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
END COMPONENT;
constant BE_WIDTH : integer := calculate_be_width(DATA_WIDTH);
constant BE_ADDR_BITS : integer := wide_enough_for(BE_WIDTH) - 1;
-- a larger target burst size than there is space in the fifo is unsatisfiable
-- rather than throw an error, we cap it
constant WDATA_TARGET_BURST_SIZE_CAPPED : integer := minimum(WDATA_TARGET_BURST_SIZE, WDATA_FIFO_DEPTH);
constant RDATA_TARGET_BURST_SIZE_CAPPED : integer := minimum(RDATA_TARGET_BURST_SIZE, RDATA_FIFO_DEPTH);
-- each of the three triggers can cause a stall
signal cmd_en_stall, wdata_en_stall, rdata_en_stall : std_logic;
-- a type for "commands"
type command is record
-- base address
addr : unsigned(ADDR_WIDTH - 1 downto 0);
-- if a range command then the range length, if a not range write command then byte enables, otherwise unused
len_be : unsigned(LEN_BE_WIDTH - 1 downto 0);
-- type of command, of the form (Write, Range)
mode : std_logic_vector(1 downto 0);
end record;
-- the width of a command word
constant CMD_WIDTH : integer := ADDR_WIDTH + LEN_BE_WIDTH + 2;
-- the width of the command fifo - less than that of a command word if part of it is known to be constant
function calculate_cmd_fifo_width return integer is
begin
if READ_USED = 1 and WRITE_USED = 1 then
return ADDR_WIDTH + LEN_BE_WIDTH + 2;
else
return ADDR_WIDTH + LEN_BE_WIDTH + 1;
end if;
end function calculate_cmd_fifo_width;
constant CMD_FIFO_WIDTH : integer := calculate_cmd_fifo_width;
-- and some functions for converting from commands to std_logic_vectors...
function to_std_logic_vector(c : command) return std_logic_vector is
variable r : std_logic_vector(CMD_FIFO_WIDTH - 1 downto 0);
begin
if READ_USED = 1 and WRITE_USED = 1 then
r := std_logic_vector(c.addr) & std_logic_vector(c.len_be) & c.mode;
else
-- no need to waste fifo space on a constant if read only or write only
r := std_logic_vector(c.addr) & std_logic_vector(c.len_be) & c.mode(0);
end if;
return r;
end function to_std_logic_vector;
-- ...and back again
function to_command(s : std_logic_vector) return command is
variable u : unsigned(CMD_FIFO_WIDTH - 1 downto 0);
variable r : command;
begin
u := unsigned(s);
if READ_USED = 1 and WRITE_USED = 1 then
r.addr := u(CMD_FIFO_WIDTH - 1 downto LEN_BE_WIDTH + 2);
r.len_be := u(LEN_BE_WIDTH + 1 downto 2);
r.mode := s(1 downto 0);
else
-- either read only or write only
r.addr := u(CMD_FIFO_WIDTH - 1 downto LEN_BE_WIDTH + 1);
r.len_be := u(LEN_BE_WIDTH downto 1);
if READ_USED = 1 then
-- read only, force "write" mode bit to zero
r.mode := '0' & s(0);
else
-- write only, force "write" mode bit to one
r.mode := '1' & s(0);
end if;
end if;
return r;
end function to_command;
-- signals for wdata_fifo ports
signal wdata_fifo_wrusedw : std_logic_vector(wide_enough_for(WDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal wdata_fifo_full : std_logic;
signal wdata_fifo_almost_full : std_logic;
signal wdata_fifo_rdusedw : std_logic_vector(wide_enough_for(WDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal wdata_fifo_empty : std_logic;
signal wdata_fifo_almost_empty : std_logic;
signal wdata_fifo_wrreq : std_logic;
signal wdata_fifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal wdata_fifo_rdreq : std_logic;
signal wdata_fifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
-- derived wdata_fifo_signals
signal wdata_fifo_empty_next : std_logic;
-- signals for rdata_fifo ports
signal rdata_fifo_wrusedw : std_logic_vector(wide_enough_for(RDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal rdata_fifo_full : std_logic;
signal rdata_fifo_almost_full : std_logic;
signal rdata_fifo_rdusedw : std_logic_vector(wide_enough_for(RDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal rdata_fifo_empty : std_logic;
signal rdata_fifo_almost_empty : std_logic;
signal rdata_fifo_wrreq : std_logic;
signal rdata_fifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal rdata_fifo_rdreq : std_logic;
signal rdata_fifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
-- derived rdata_fifo signals
signal outstanding_reads : unsigned(wide_enough_for(RDATA_FIFO_DEPTH + RDATA_TARGET_BURST_SIZE) - 1 downto 0) := (others => '0');
signal rdata_fifo_wrusedw_safe : unsigned(wide_enough_for(RDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal rdata_fifo_has_space_next_threshold : unsigned(wide_enough_for(RDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
-- signal rdata_fifo_has_space_next : std_logic; -- JG: never used
signal rdata_fifo_space_available : unsigned(wide_enough_for(RDATA_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal outstanding_reads_next : unsigned(wide_enough_for(RDATA_FIFO_DEPTH + RDATA_TARGET_BURST_SIZE) - 1 downto 0) := (others => '0');
signal outstanding_reads_valid_next : unsigned(wide_enough_for(RDATA_FIFO_DEPTH + RDATA_TARGET_BURST_SIZE) - 1 downto 0) := (others => '0');
-- signals for cmd_fifo ports
signal cmd_fifo_wrusedw : std_logic_vector(wide_enough_for(CMD_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal cmd_fifo_full : std_logic;
signal cmd_fifo_almost_full : std_logic;
signal cmd_fifo_rdusedw : std_logic_vector(wide_enough_for(CMD_FIFO_DEPTH) - 1 downto 0) := (others => '0');
signal cmd_fifo_empty : std_logic;
signal cmd_fifo_almost_empty : std_logic;
signal cmd_fifo_wrreq : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal cmd_fifo_data : command;
signal cmd_fifo_rdreq : std_logic;
signal cmd_fifo_q_slv : std_logic_vector(CMD_FIFO_WIDTH - 1 downto 0) := (others => '0');
signal cmd_fifo_q : command;
-- signals used by the logic which controls the avalon interface itself
signal active_cmd, active_cmd_next, calculate_active_cmd_next : command := ((others => '0'), (others => '0'), (others => '0'));
signal have_active_cmd, have_active_cmd_next : std_logic;
-- signal active_cmd_expiring : std_logic; -- JG: never used
signal writing, reading : std_logic;
-- signal cmd_fifo_q_has_range_zero_cmd : std_logic; -- JG: never used
signal trying_to_write, trying_to_read : std_logic;
signal byte_enable : std_logic_vector((DATA_WIDTH / 8) - 1 downto 0);
signal stall_int : std_logic;
-- signal trying_to_write_address : std_logic; -- JG: never used
-- signal trying_to_write_address_reg : std_logic; -- JG: never used
-- signal trying_to_write_data : std_logic; -- JG: never used
-- a few handy and gates to help out the cusp internals
signal cmd_en, wdata_en, rdata_en : std_logic;
signal write_count : unsigned(BURST_WIDTH - 1 downto 0);
signal av_burstcount_int : std_logic_vector(BURST_WIDTH-1 downto 0);
signal av_readdatavalid_vec : std_logic_vector(0 downto 0);
signal trying_to_write_next : std_logic;
signal trying_to_read_next : std_logic;
signal write_count_next : unsigned(BURST_WIDTH - 1 downto 0);
signal av_burstcount_int_next : std_logic_vector(BURST_WIDTH-1 downto 0);
signal av_address_int : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal av_address_int_next : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal pipeline3_en : std_logic;
signal pipeline2_en : std_logic;
signal target_burst_size : unsigned(LEN_BE_WIDTH - 1 downto 0);
signal new_cmd : command := ((others => '0'), (others => '0'), (others => '0'));
signal split_valid_next : std_logic;
signal split_valid : std_logic;
signal split_cmd_next : command := ((others => '0'), (others => '0'), (others => '0'));
signal split_cmd : command := ((others => '0'), (others => '0'), (others => '0'));
signal dont_split_burst : std_logic;
signal byte_enable_next : std_logic_vector((DATA_WIDTH / 8) - 1 downto 0);
signal outstanding_writes : unsigned(wide_enough_for(WDATA_FIFO_DEPTH + WDATA_TARGET_BURST_SIZE) - 1 downto 0) := (others => '0');
signal outstanding_writes_valid_next : unsigned(wide_enough_for(WDATA_FIFO_DEPTH + WDATA_TARGET_BURST_SIZE) - 1 downto 0) := (others => '0');
signal wdata_fifo_rdreq_vec : std_logic_vector(0 downto 0);
signal pipeline1_en : std_logic;
signal cmd_fifo_q_reg : command := ((others => '0'), (others => '0'), (others => '0'));
signal cmd_fifo_empty_reg : std_logic;
signal pipeline2_overflow_en : std_logic;
signal wdata_rdena : std_logic;
signal trying_to_write0 : std_logic;
signal trying_to_write1 : std_logic;
signal av_read_int : std_logic;
signal av_read_int0 : std_logic;
signal av_read_int1 : std_logic;
signal av_address0 : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal av_address1 : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal av_burstcount0 : std_logic_vector(BURST_WIDTH-1 downto 0);
signal av_burstcount1 : std_logic_vector(BURST_WIDTH-1 downto 0);
signal av_byteenable0 : std_logic_vector((DATA_WIDTH / 8) - 1 downto 0);
signal av_byteenable1 : std_logic_vector((DATA_WIDTH / 8) - 1 downto 0);
begin
byteenable_used_check_gen :
if BYTEENABLE_USED = 1 generate
assert (BE_WIDTH <= LEN_BE_WIDTH) report "LEN_BE_WIDTH is less than the required byteenable width" SEVERITY failure;
end generate;
assert (LEN_BE_WIDTH >= BURST_WIDTH) report "MAX_BURST is less than the TARGET_BURST_SIZE" SEVERITY failure;
-- a few handy and gates to help out the cusp internals
cmd_en <= cenable and cenable_en;
rdata_en <= renable and renable_en;
wdata_en <= wenable and wenable_en;
-- this generate groups together the largest chunks of code which are only
-- required if this master performs write operations
write_used_gen :
if WRITE_USED = 1 generate
-- wdata_fifo stores words of data waiting to be written
-- input side connected to cusp wdata triggered port
-- output side feeds avalon interface
wdata_fifo : alt_vipvfr131_common_general_fifo
generic map
(
WIDTH => DATA_WIDTH,
DEPTH => WDATA_FIFO_DEPTH,
CLOCKS_ARE_SAME => CLOCKS_ARE_SYNC = 1,
DEVICE_FAMILY => family_string(FAMILY),
RDREQ_TO_Q_LATENCY => 3
)
port map
(
rdclock => av_clock,
wrclock => clock,
rdena => wdata_rdena,
wrena => '1',
reset => reset,
wrusedw => wdata_fifo_wrusedw,
full => wdata_fifo_full,
almost_full => wdata_fifo_almost_full,
rdusedw => wdata_fifo_rdusedw,
empty => wdata_fifo_empty,
almost_empty => wdata_fifo_almost_empty,
wrreq => wdata_fifo_wrreq,
data => wdata_fifo_data,
rdreq => wdata_fifo_rdreq,
q => wdata_fifo_q
);
-- delay the output of the avalon signals when writes are enabled due
-- to the latency in the fifo
write_delay : process (av_clock, reset)
begin
if reset = '1' then
trying_to_write0 <= '0';
trying_to_write1 <= '0';
av_read_int0 <= '0';
av_read_int1 <= '0';
av_address0 <= (others => '0');
av_address1 <= (others => '0');
av_burstcount0 <= (others => '0');
av_burstcount1 <= (others => '0');
av_byteenable0 <= (others => '0');
av_byteenable1 <= (others => '0');
elsif av_clock'EVENT and av_clock = '1' then
if(wdata_rdena = '1') then
trying_to_write0 <= trying_to_write;
trying_to_write1 <= trying_to_write0;
av_read_int0 <= av_read_int;
av_read_int1 <= av_read_int0;
av_address0 <= av_address_int;
av_address1 <= av_address0;
av_burstcount0 <= av_burstcount_int;
av_burstcount1 <= av_burstcount0;
av_byteenable0 <= byte_enable;
av_byteenable1 <= av_byteenable0;
end if;
end if;
end process;
wdata_rdena <= not ((trying_to_write1 or av_read_int1) and av_waitrequest);
-- cusp interface
-- wdata port drives data on to wdata_fifo, stalls when
-- there is an attempt to drive data but the fifo is full
wdata_fifo_data <= wdata;
wdata_fifo_wrreq <= wdata_en and ena; -- this protects us from overwrite
wdata_en_stall <= wdata_en and wdata_fifo_full;
-- avalon interface (signals used only by writing)
-- pull data from the wdata fifo
wdata_fifo_rdreq <= writing;
av_writedata <= wdata_fifo_q;
av_write <= trying_to_write1;
av_read <= av_read_int1;
av_address <= av_address1;
av_burstcount <= av_burstcount1;
av_byteenable <= av_byteenable1;
-- and track whether it will be empty next non-waitrequested cycle
wdata_fifo_empty_next <= wdata_fifo_empty or (trying_to_write and wdata_fifo_almost_empty);
-- keep track of how many write requests are waiting to go out onto the avalon switch fabric
wdata_fifo_rdreq_vec(0) <= wdata_fifo_rdreq;
outstanding_writes_valid_next <= outstanding_writes - 1 when (wdata_fifo_rdreq_vec(0) = '1') else outstanding_writes;
update_outstanding_writes : process (av_clock, reset)
begin
if reset = '1' then
outstanding_writes <= (others => '0');
elsif av_clock'EVENT and av_clock = '1' then
if have_active_cmd_next = '1' and active_cmd_next.mode(1) = '1' and pipeline2_en = '1' then
if active_cmd_next.mode(0) = '0' then
-- single
outstanding_writes <= to_unsigned(to_integer(outstanding_writes_valid_next) + 1, outstanding_writes'length);
else
-- burst
outstanding_writes <= to_unsigned(to_integer(outstanding_writes_valid_next) + to_integer(active_cmd_next.len_be), outstanding_writes'length);
end if;
else
outstanding_writes <= outstanding_writes_valid_next;
end if;
end if;
end process;
end generate;
-- this generate ties off signals not used when not writing to constants
-- doing this prevents there being Xs in the simulation (which can have undesired effects
-- if they are used in command calculations) but ensures that appropriate bits of the
-- command logic are optimised away
write_not_used_gen :
if WRITE_USED /= 1 generate
-- setting the wdata fifo signals to model an empty and inactive fifo should be harmless
wdata_fifo_wrusedw <= (others => '0');
wdata_fifo_rdusedw <= (others => '0');
wdata_fifo_full <= '0';
wdata_fifo_empty <= '1';
wdata_fifo_almost_full <= '0';
wdata_fifo_almost_empty <= '1';
wdata_fifo_q <= (others => '0');
wdata_fifo_data <= (others => '0');
wdata_fifo_wrreq <= '0';
wdata_fifo_rdreq <= '0';
wdata_fifo_empty_next <= '0';
-- no outstanding writes
outstanding_writes <= (others => '0');
-- there can be no wdata stall
wdata_en_stall <= '0';
-- write side of avalon interface is inactive
av_writedata <= (others => '0');
av_write <= '0';
av_read <= av_read_int;
av_address <= av_address_int;
av_burstcount <= av_burstcount_int;
av_byteenable <= byte_enable;
wdata_rdena <= not (av_read_int and av_waitrequest);
end generate;
-- this generate groups together the largest chunks of code which are only
-- required if this master performs read operations
read_used_gen_gen :
if READ_USED = 1 generate
-- rdata_fifo stores words of data which have been received
-- from the avalon interface and a waiting to be read by cusp
-- input side connected to avalon readdata port
-- output side feeds cusp rdata triggered port
rdata_fifo : alt_vipvfr131_common_general_fifo
generic map
(
WIDTH => DATA_WIDTH,
DEPTH => RDATA_FIFO_DEPTH,
CLOCKS_ARE_SAME => CLOCKS_ARE_SYNC = 1,
DEVICE_FAMILY => family_string(FAMILY),
RDREQ_TO_Q_LATENCY => 3
)
port map
(
rdclock => clock,
wrclock => av_clock,
rdena => ena,
wrena => '1',
reset => reset,
wrusedw => rdata_fifo_wrusedw,
full => rdata_fifo_full,
almost_full => rdata_fifo_almost_full,
rdusedw => rdata_fifo_rdusedw,
empty => rdata_fifo_empty,
almost_empty => rdata_fifo_almost_empty,
wrreq => rdata_fifo_wrreq,
data => rdata_fifo_data,
rdreq => rdata_fifo_rdreq,
q => rdata_fifo_q
);
-- cusp interface
-- rdata port reads data from rdata_fifo
rdata <= rdata_fifo_q;
rdata_fifo_rdreq <= rdata_en;
rdata_en_stall <= rdata_en and rdata_fifo_empty;
-- to help control at avalon interface end
-- keep track of how many read requests are out in the avalon switch fabric
-- somewhere - requested but not yet received
av_readdatavalid_vec(0) <= av_readdatavalid;
outstanding_reads_valid_next <= outstanding_reads - 1 when (av_readdatavalid_vec(0) = '1') else outstanding_reads;
update_outstanding_reads : process (av_clock, reset)
begin
if reset = '1' then
outstanding_reads <= (others => '0');
elsif av_clock'EVENT and av_clock = '1' then
if have_active_cmd_next = '1' and active_cmd_next.mode(1) = '0' and pipeline2_en = '1' then
if active_cmd_next.mode(0) = '0' then
-- single
outstanding_reads <= to_unsigned(to_integer(outstanding_reads_valid_next) + 1, outstanding_reads'length);
else
-- burst
outstanding_reads <= to_unsigned(to_integer(outstanding_reads_valid_next) + to_integer(active_cmd_next.len_be), outstanding_reads'length);
end if;
else
outstanding_reads <= outstanding_reads_valid_next;
end if;
end if;
end process;
-- calculate number of used words in the rdata fifo, taking into account words
-- that may be used before the next cusp read by read requests already issued
rdata_fifo_space_available <= RDATA_FIFO_DEPTH - unsigned(rdata_fifo_wrusedw);
-- avalon interface (signals used only be reading)
-- accept read data from the avalon interface and put it in the rdata_fifo
-- note that there is no protection from overwrite here - we protect ourselves
-- by ensuring that we don't issue more read requests than we can cope with
rdata_fifo_data <= av_readdata;
rdata_fifo_wrreq <= av_readdatavalid;
av_read_int <= trying_to_read;
end generate;
-- this generate ties off signals not used when not reading to constants
-- doing this prevents there being Xs in the simulation (which can have undesired effects
-- if they are used in command calculations) but ensures that appropriate bits of the
-- command logic are optimised away
read_not_used_gen :
if READ_USED /= 1 generate
-- setting the rdata fifo signals to model an empty and inactive fifo should be harmless
rdata_fifo_wrusedw <= (others => '0');
rdata_fifo_rdusedw <= (others => '0');
rdata_fifo_full <= '0';
rdata_fifo_empty <= '1';
rdata_fifo_almost_full <= '0';
rdata_fifo_almost_empty <= '1';
rdata_fifo_q <= (others => '0');
rdata_fifo_data <= (others => '0');
rdata_fifo_wrreq <= '0';
rdata_fifo_rdreq <= '0';
-- rdata port is inactive, there can be no rdata stall
rdata <= (others => '0');
rdata_en_stall <= '0';
-- no outstanding reads
outstanding_reads <= (others => '0');
-- zero the bits of logic which are used to help the command system know whether reads are ok
rdata_fifo_wrusedw_safe <= (others => '0');
rdata_fifo_has_space_next_threshold <= (others => '0');
-- rdata_fifo_has_space_next <= '0'; -- JG: never used
-- read side of avalon interface is inactive
av_read_int <= '0';
end generate;
-- cmd_fifo stores "commands" from cusp to be processed by
-- the avalon side
-- each command consists of an address, a len_be word and two mode bits
cmd_fifo : alt_vipvfr131_common_general_fifo
generic map
(
WIDTH => CMD_FIFO_WIDTH,
DEPTH => CMD_FIFO_DEPTH,
CLOCKS_ARE_SAME => CLOCKS_ARE_SYNC = 1,
DEVICE_FAMILY => family_string(FAMILY),
RDREQ_TO_Q_LATENCY => 1
)
port map
(
rdclock => av_clock,
wrclock => clock,
rdena => '1',
wrena => '1',
reset => reset,
wrusedw => cmd_fifo_wrusedw,
full => cmd_fifo_full,
almost_full => cmd_fifo_almost_full,
rdusedw => cmd_fifo_rdusedw,
empty => cmd_fifo_empty,
almost_empty => cmd_fifo_almost_empty,
wrreq => cmd_fifo_wrreq,
data => to_std_logic_vector(cmd_fifo_data),
rdreq => cmd_fifo_rdreq,
q => cmd_fifo_q_slv
);
-- the cusp interface consists of three triggered ports
-- cmd (command), wdata (write data) and rdata (read data)
-- plus some stall and enable signals and so on
-- stall when any of the triggers have caused a stall
stall_int <= cmd_en_stall or wdata_en_stall or rdata_en_stall;
ready <= not stall_int;
stall <= stall_int;
-- JG: new outputs to provide stall signals individually
stall_command <= cmd_en_stall;
stall_write <= wdata_en_stall;
stall_read <= rdata_en_stall;
-- cmd port drives commands on to cmd_fifo, stalls when
-- there is an attempt to drive data but the fifo is full
mode <= write & burst;
cmd_fifo_data <= (unsigned(addr), unsigned(len_be), mode);
cmd_fifo_wrreq <= '1' when cmd_en = '1'
and ena = '1' -- this protects us from overflow
and (burst = '0' or unsigned(len_be) > to_unsigned(0, LEN_BE_WIDTH)) else -- this discards range zero commands
'0';
cmd_en_stall <= cmd_en and cmd_fifo_full;
-- the avalon interface reads commands from the command fifo
-- and issues read and write requests, using data from the wdata
-- fifo for the writes
-- it also responds to the requested read data coming back from
-- the avalon switch fabric by putting it into the rdata fifo
-- pipeline3, issues reads and writes to the avalon mm switch fabric
pipeline3_en <= '1' when wdata_rdena = '1' and write_count = to_unsigned(1, BURST_WIDTH) else '0';
-- pipeline2, decides whether there is enough space/data available to issue the next command
pipeline2_en <= pipeline3_en and not (have_active_cmd and not (trying_to_read_next or trying_to_write_next));
-- pipeline2_overflow, uses the split_cmd register to store an extra cmd, allowing pipeline1 to stall later than pipeline 2 and 3
-- this breaks the combinatorial path to cmd_fifo_rdreq which greatly improves fmax
pipeline2_overflow_en <= pipeline3_en or (not pipeline2_en and not split_valid);
-- pipeline1, splits commands into smaller bursts
pipeline1_en <= not split_valid;
update_active_cmd : process (av_clock, reset)
begin
if reset = '1' then
write_count <= to_unsigned(1, BURST_WIDTH);
trying_to_write <= '0';
trying_to_read <= '0';
av_burstcount_int <= (others => '0');
av_address_int <= (others => '0');
byte_enable <= (others => '0');
active_cmd <= ((others => '0'), (others => '0'), (others => '0'));
have_active_cmd <= '0';
split_valid <= '0';
split_cmd <= ((others => '0'), (others => '0'), (others => '0'));
cmd_fifo_q_reg <= ((others => '0'), (others => '0'), (others => '0'));
cmd_fifo_empty_reg <= '1';
elsif av_clock'EVENT and av_clock = '1' then
if pipeline3_en = '1' then
write_count <= write_count_next;
trying_to_write <= trying_to_write_next;
trying_to_read <= trying_to_read_next;
av_burstcount_int <= av_burstcount_int_next;
av_address_int <= av_address_int_next;
byte_enable <= byte_enable_next;
else
if wdata_rdena = '1' then
write_count <= write_count - 1;
end if;
end if;
if pipeline2_en = '1' then
active_cmd <= active_cmd_next;
have_active_cmd <= have_active_cmd_next;
end if;
if pipeline2_overflow_en = '1' then
split_valid <= split_valid_next;
split_cmd <= split_cmd_next;
end if;
if pipeline1_en = '1' then
cmd_fifo_q_reg <= cmd_fifo_q;
cmd_fifo_empty_reg <= cmd_fifo_empty;
end if;
end if;
end process;
-- pipeline stage 0
-- the pipeline stage 1 needs data from the fifo under the following conditions
cmd_fifo_rdreq <= pipeline1_en and not cmd_fifo_empty;
cmd_fifo_q <= to_command(cmd_fifo_q_slv);
-- pipeline stage 1
-- if there is a split (burst than needs to be cut down) or a stall further up the pipeline we use the split cmd registers to save the
-- new_cmd. This is then used as the next active cmd.
active_cmd_next <= new_cmd when dont_split_burst = '1' else
(addr => new_cmd.addr, len_be => target_burst_size, mode => new_cmd.mode);
target_burst_size <= to_unsigned(WDATA_TARGET_BURST_SIZE_CAPPED, LEN_BE_WIDTH) when new_cmd.mode(1) = '1' else
to_unsigned(RDATA_TARGET_BURST_SIZE_CAPPED, LEN_BE_WIDTH);
new_cmd <= split_cmd when split_valid = '1' else
cmd_fifo_q_reg;
split_valid_next <= have_active_cmd_next and (not dont_split_burst or not pipeline2_en);
split_cmd_next <= new_cmd when pipeline2_en = '0' else
(addr => (((new_cmd.addr srl BE_ADDR_BITS) + resize(target_burst_size, ADDR_WIDTH)) sll BE_ADDR_BITS), len_be => new_cmd.len_be - target_burst_size, mode => new_cmd.mode);
have_active_cmd_next <= not cmd_fifo_empty_reg or split_valid;
dont_split_burst <= '1' when new_cmd.len_be <= target_burst_size or new_cmd.mode(0) = '0' else '0';
-- pipeline stage 2
-- if byte enables are in use and the next command will be
-- a single write, then pull its byte enables from the bottom
-- bits of len_be
byte_enable_used_gen :
if BYTEENABLE_USED = 1 generate
byte_enable_next <= std_logic_vector(active_cmd.len_be(BE_WIDTH - 1 downto 0)) when active_cmd.mode = "10" else
(others => '1');
end generate;
-- decide whether trying_to_write and trying_to_read should be high on
-- the next non-waitrequested cycle
update_try_to_write : process (have_active_cmd, active_cmd, wdata_fifo_rdusedw, rdata_fifo_space_available, outstanding_reads, outstanding_writes,
trying_to_write, trying_to_read, write_count, av_burstcount_int, av_address_int)
begin
trying_to_write_next <= trying_to_write;
trying_to_read_next <= trying_to_read;
write_count_next <= write_count;
av_burstcount_int_next <= av_burstcount_int;
av_address_int_next <= av_address_int;
if have_active_cmd = '0' then
-- if no active command next cycle, then no reading and no writing
trying_to_write_next <= '0';
trying_to_read_next <= '0';
else
av_address_int_next <= std_logic_vector(active_cmd.addr);
if active_cmd.mode(1) = '1' then
-- if there is enough data available then issue the write
if to_integer(unsigned(wdata_fifo_rdusedw)) >= to_integer(outstanding_writes) then
if active_cmd.mode(0) = '0' then
trying_to_write_next <= '1';
write_count_next <= to_unsigned(1, BURST_WIDTH);
av_burstcount_int_next <= std_logic_vector(to_unsigned(1, BURST_WIDTH));
else
trying_to_write_next <= '1';
write_count_next <= to_unsigned(to_integer(unsigned(active_cmd.len_be)), BURST_WIDTH);
av_burstcount_int_next <= std_logic_vector(resize(active_cmd.len_be, BURST_WIDTH));
end if;
else
trying_to_write_next <= '0';
end if;
-- definitely won't read
trying_to_read_next <= '0';
else
-- if there is enough space available then issue the read
if to_integer(rdata_fifo_space_available) >= to_integer(outstanding_reads) then
if active_cmd.mode(0) = '0' then
trying_to_read_next <= '1';
av_burstcount_int_next <= std_logic_vector(to_unsigned(1, BURST_WIDTH));
else
trying_to_read_next <= '1';
av_burstcount_int_next <= std_logic_vector(resize(active_cmd.len_be, BURST_WIDTH));
end if;
else
trying_to_read_next <= '0';
end if;
-- definitely won't write
trying_to_write_next <= '0';
end if;
end if;
end process;
-- pipeline stage 3
-- determining what the avalon side of the interface is actually doing -
-- a combination of intent and avalon's permission
writing <= trying_to_write and wdata_rdena;
reading <= trying_to_read and wdata_rdena;
-- interrupts
sync_clocks: IF (CLOCKS_ARE_SYNC /= 0) GENERATE
has_irq: IF (INTERRUPT_USED /= 0) GENERATE
activeirq_reg: PROCESS (clock, reset)
BEGIN
IF reset = '1' THEN
activeirqs <= (OTHERS=>'1');
ELSIF Rising_edge(clock) THEN
activeirqs <= av_interrupt;
END IF;
END PROCESS;
END GENERATE;
END GENERATE;
async_clocks: IF (CLOCKS_ARE_SYNC = 0) GENERATE
has_irq: IF (INTERRUPT_USED /= 0) GENERATE
activeirq_reg: sync_vec GENERIC MAP (WIDTH=>INTERRUPT_WIDTH) PORT MAP (clk=>clock, reset=>reset, data_in=>av_interrupt, data_out=>activeirqs);
END GENERATE;
END GENERATE;
end architecture rtl;
| mit | cf3341b0219c8436bf6aca1b301f528f | 0.592156 | 3.601591 | false | false | false | false |
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