repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/core.vhd | 13 | 14,437 | ----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity core is
port(
clock : in std_logic;
cmd : in std_logic_vector (39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector (31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector (35 downto 0);
memoryOut : out std_logic_vector (35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end core;
architecture behavioral of core is
component decoder
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end component;
component flags
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end component;
component sync is
port(
la_input : in std_logic_vector (31 downto 0);
clock : in std_logic;
enableFilter : in std_logic;
enableDemux : in std_logic;
falling : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end component;
component testmode is
port(
clock : in std_logic;
enable : in std_logic;
la_input : in std_logic_vector (31 downto 0);
output : out std_logic_vector (31 downto 0)
);
end component;
component sampler
port(
la_input : in std_logic_vector(31 downto 0);
clock : in std_logic;
exClock : in std_logic;
external : in std_logic;
data : in std_logic_vector(23 downto 0);
wrDivider : in std_logic;
sample : out std_logic_vector(31 downto 0);
ready : out std_logic;
trig_delay : out std_logic_vector(1 downto 0);
num_scheme : in std_logic
);
end component;
component trigger
port(
la_input : in std_logic_vector(31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic_vector(3 downto 0);
wrValue : in std_logic_vector(3 downto 0);
wrConfig : in std_logic_vector(3 downto 0);
arm : in std_logic;
demuxed : in std_logic;
run : out std_logic;
ExtTriggerIn : in std_logic
);
end component;
component group_selector
port(
clock : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_input_ready : in std_logic;
output : out std_logic_vector(31 downto 0);
output_ready : out std_logic;
disabledGroups : in std_logic_vector(3 downto 0)
);
end component;
component rle
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end component;
component controller
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end component;
component muldex
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end component;
signal opcode : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal sample, syncedla_input : std_logic_vector (31 downto 0);
signal sampleClock, run : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted : std_logic;
signal wrFlags, sampleReady, flagRLE, flagTest : std_logic;
signal armLEDreg : std_logic := '0';
signal triggerLEDreg : std_logic := '0';
signal data_rd, data_wr, controller_la_inputReady : std_logic;
signal rle_busy, rle_inp_valid, raw_inp_ready : std_logic;
signal data_size : std_logic_vector(1 downto 0);
signal disabledGroups : std_logic_vector (3 downto 0);
signal la_input_sampler : std_logic_vector(31 downto 0);
signal controller_memoryIn, raw_inp : std_logic_vector (31 downto 0);
signal data_inp, controller_la_input, rle_inp : std_logic_vector (32 downto 0);
signal data_ready, raw_ready, rdstate : std_logic := '0';
signal trig_delay : std_logic_vector(1 downto 0);
signal num_scheme, abort, ident, meta : std_logic;
signal output_i : std_logic_vector (31 downto 0);
signal outputSend_i : std_logic;
signal tx_bytes_i : integer range 0 to 4;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= resetCmd;
--armLED <= not armLEDreg; --Logic Sniffers LEDs are connected to 3.3V so a logic 0 turns the LED on.
--triggerLED <= not triggerLEDreg;
--extClockOut <= sampleClock;
--extTriggerOut <= run;
tx_bytes_i <=
1 when data_size = "01" else
2 when data_size = "10" else
3 when disabledGroups = "1000" and flagRLE = '0' else
3 when disabledGroups = "0100" and flagRLE = '0' else
3 when disabledGroups = "0010" and flagRLE = '0' else
3 when disabledGroups = "0001" and flagRLE = '0' else
4;
-- process commands
process_cmd_block : block
constant rom_size : natural := 18;
type states is (IDLE, IDENTIFY, METADATA, BUSYWAIT);
type rom_type is array (rom_size-1 downto 0) of
std_logic_vector (31 downto 0);
constant rom : rom_type := (
0 => x"00000020", 1 => x"00002120", -- 0x20 0x00000020
2 => x"00220018", 3 => x"23001800", -- 0x21 0x00001800
4 => x"00e1f505", 5 => x"00000024", -- 0x22 0x00001800
6 => x"41204002", 7 => x"704f0102", -- 0x23 0x05f5e100
8 => x"65626e65", 9 => x"2068636e", -- 0x24 0x00000002
10 => x"69676f4c", 11 => x"6e532063", -- 0x40 0x20
12 => x"65666669", 13 => x"31762072", -- 0x41 0x02
14 => x"0031302e", 15 => x"302e3302",
16 => x"48560300", others => x"00004c44"
);
-- 0x01 "Openbench Logic Sniffer v1.01"
-- 0x02 "3.0"
-- 0x03 "VHDL"
signal state : states;
signal send_cmd : std_logic;
signal cmd_output : std_logic_vector (31 downto 0);
signal addr : integer range 0 to rom_size + 1;
begin
tx_bytes <= 4 when send_cmd = '1' else tx_bytes_i;
output <= cmd_output when send_cmd = '1' else output_i;
outputSend <= '1' when send_cmd = '1' else outputSend_i;
process(clock)
begin
if rising_edge(clock) then
case state is
when IDLE =>
if outputBusy = '0' then
if ident = '1' then
state <= IDENTIFY;
end if;
--Disabled, this was wreaking havoc with SPI slave
-- if meta = '1' then
-- state <= METADATA;
-- end if;
end if;
send_cmd <= '0';
addr <= 0;
when IDENTIFY =>
send_cmd <= '1';
cmd_output <= x"534c4131"; -- "SLA1"
state <= IDLE;
when METADATA =>
send_cmd <= '1';
cmd_output <= rom(addr);
addr <= addr + 1;
state <= BUSYWAIT;
when BUSYWAIT =>
send_cmd <= '0';
if outputBusy = '0' and send_cmd = '0' then
if addr = rom_size then
state <= IDLE;
else
state <= METADATA;
end if;
end if;
end case;
end if;
end process;
end block;
--Generates observable trigger and arm LED signals
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if arm = '1' then
-- armLEDreg <= '1';
-- triggerLEDreg <= '0';
-- elsif run = '1' then
-- armLEDreg <= '0';
-- triggerLEDreg <= '1';
-- end if;
-- end if;
-- end process;
-- select between internal and external sampling clock
-- BUFGMUX_intex: BUFGMUX
-- port map (
-- O => sampleClock, -- Clock MUX output
-- I0 => clock, -- Clock0 la_input
-- I1 => la_inputClock, -- Clock1 la_input
-- S => flagExternal -- Clock select la_input
-- );
sampleClock <= clock;
Inst_decoder: decoder
port map(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd,
abort => abort,
ident => ident,
meta => meta
);
Inst_flags: flags
port map(
data => data(10 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
disabledGroups => disabledGroups,
rle => flagRLE,
test_mode => flagTest,
data_size => data_size,
num_scheme => num_scheme
);
Inst_sync: sync
port map(
la_input => la_input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedla_input
);
-- Inst_testmode: testmode
-- port map(
-- clock => clock,
-- enable => flagTest,
-- la_input => syncedla_input,
-- output => la_input_sampler
-- );
Inst_sampler: sampler
port map(
la_input => syncedla_input,
clock => clock,
exClock => la_inputClock,
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
trig_delay => trig_delay,
num_scheme => num_scheme
);
Inst_trigger: trigger
port map(
la_input => sample,
la_inputReady => sampleReady,
data => data,
clock => clock,
reset => resetCmd,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run,
extTriggerIn => extTriggerIn
);
Inst_group_selector: group_selector
port map(
clock => clock,
la_input => sample,
la_input_ready => sampleReady,
output => raw_inp,
output_ready => raw_inp_ready,
disabledGroups => disabledGroups
);
Inst_rle: rle
port map(
clock => clock,
reset => resetCmd,
raw_inp => raw_inp,
fmt_out => controller_memoryIn,
enable => flagRLE,
raw_inp_valid => raw_inp_ready,
rle_inp_valid => rle_inp_valid,
-- start_count => run,
data_size => data_size,
rle_out => controller_la_input,
rle_inp => rle_inp,
rle_out_valid => controller_la_inputReady,
busy => rle_busy,
rle_ready => data_ready,
raw_ready => raw_ready
);
Inst_controller: controller
port map(
clock => clock,
reset => resetCmd,
la_input => controller_la_input,
la_inputReady => controller_la_inputReady,
run => run,
wrSize => wrSize,
data => data,
busy => outputBusy,
send => outputSend_i,
output => output_i,
memoryIn => controller_memoryIn,
memoryOut => data_inp,
memoryRead => data_rd,
memoryWrite => data_wr,
rle_busy => rle_busy,
rle_read => rle_inp_valid,
rle_mode => flagRLE,
rdstate => rdstate,
data_ready => data_ready,
trig_delay => trig_delay,
abort => abort
);
Inst_muldex : muldex
port map(
clock => clock,
reset => resetCmd,
data_inp => data_inp,
data_out => rle_inp,
data_rd => data_rd,
data_wr => data_wr,
mem_inp => memoryIn,
mem_out => memoryOut,
mem_rd => memoryRead,
mem_wr => memoryWrite,
data_size => data_size,
rdstate => rdstate,
data_ready => raw_ready
);
end behavioral;
| mit | 9e4036c70b079f68315ce2d10aab87bc | 0.637044 | 3.003328 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_SPI.vhd | 13 | 8,523 | --
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
| mit | 259ca7e6e897ebd05d6d242f580f6b5f | 0.563769 | 3.229632 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/ENCODER/encoder.vhd | 1 | 1,550 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: pmodenc - Behavioral
-- Description: Process the quadrature signals from the rotary encode on
-- the Digilent PMODENC
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder is
Port ( clk : in STD_LOGIC;
quad : in STD_LOGIC_VECTOR (1 downto 0);
up : out STD_LOGIC;
down : out STD_LOGIC;
error : out STD_LOGIC);
end encoder;
architecture Behavioral of encoder is
signal sr : std_logic_vector(5 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
up <= '0';
down <= '0';
error <= '0';
case sr(3 downto 0) is
when "0100" => down <= '1';
when "1101" => down <= '1';
when "1011" => down <= '1';
when "0010" => down <= '1';
when "1000" => up <= '1';
when "1110" => up <= '1';
when "0111" => up <= '1';
when "0001" => up <= '1';
when "0011" => error <= '1';
when "1100" => error <= '1';
when "0110" => error <= '1';
when "1001" => error <= '1';
when others =>
end case;
sr <= quad & sr(sr'high downto 2);
end if;
end process;
end Behavioral; | mit | 8b8187ebab9ba4e4de830b99e0bd6f75 | 0.413548 | 4.068241 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer.vhd | 1 | 5,832 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file frame_buffer.vhd when simulating
-- the core, frame_buffer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY frame_buffer IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END frame_buffer;
ARCHITECTURE frame_buffer_a OF frame_buffer IS
-- synthesis translate_off
COMPONENT wrapped_frame_buffer
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_frame_buffer USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 15,
c_addrb_width => 15,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 20000,
c_read_depth_b => 20000,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 20000,
c_write_depth_b => 20000,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_frame_buffer
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END frame_buffer_a;
| mit | 69f408cae967b4411fa30778a9a9081a | 0.537037 | 3.95122 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipeline3new.vhd | 1 | 44,247 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev3new is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev3new is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-----------------------------------
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmp1, tmp2, tmp3: unsigned(63 downto 0);
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
signal round: std_logic := '1';
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant SUM1 : std_logic_vector(5 downto 0) := "111101";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WPAD : std_logic_vector(5 downto 0) := "011101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
----------------------------------------------------------------
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
signal w_80 : WORD_VECTOR(0 to 79);
-----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal message0 : std_logic_vector(63 downto 0);
signal message1 : std_logic_vector(63 downto 0);
signal message2 : std_logic_vector(63 downto 0);
signal message3 : std_logic_vector(63 downto 0);
signal message4 : std_logic_vector(63 downto 0);
signal message5 : std_logic_vector(63 downto 0);
signal message6 : std_logic_vector(63 downto 0);
signal message7 : std_logic_vector(63 downto 0);
signal message8 : std_logic_vector(63 downto 0);
signal message9 : std_logic_vector(63 downto 0);
signal message10 : std_logic_vector(63 downto 0);
signal message11 : std_logic_vector(63 downto 0);
signal message12 : std_logic_vector(63 downto 0);
signal message13 : std_logic_vector(63 downto 0);
signal message14 : std_logic_vector(63 downto 0);
signal message15 : std_logic_vector(63 downto 0);
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
--elsif (Opcode2=CH) then
-- register_file(to_integer(unsigned(RX2))) <=
-- (register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RZ2))))xor
-- (not register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RB2))));
-- register_file(to_integer(unsigned(RY2))) <=
-- (register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RA2))))xor
-- (not register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RC2))));
----register_file(to_integer(unsigned(RX2))) <=
--std_logic_vector(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
--register_file(to_integer(unsigned(RY2))) <=
--std_logic_vector(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
-- elsif (Opcode2=MAJ) then
--
---- (register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RZ2))))xor
---- (register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RB2))))xor
---- (register_file(to_integer(unsigned(RZ2))) and register_file(to_integer(unsigned(RB2))));
---- register_file(to_integer(unsigned(RY2))) <=
---- (register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RA2))))xor
---- (register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RC2))))xor
---- (register_file(to_integer(unsigned(RA2))) and register_file(to_integer(unsigned(RC2))));
-- register_file(to_integer(unsigned(RX2))) <=
-- std_logic_vector(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
-- ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
-- ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))(63 downto 32);
-- register_file(to_integer(unsigned(RY2))) <=
-- std_logic_vector(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
-- ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
-- ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))(31 downto 0);
-- elsif (Opcode2=SUM0) then
-- register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39)))(63 downto 32);
-- register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39)))(31 downto 0);
elsif (Opcode2=SUM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))(31 downto 0);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2= MLOAD0) then
message0 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message1 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message2 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message3 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
message4 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message5 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message6 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message7 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
message8 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message9 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message10 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message11 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
message12 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message13 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message14 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message15 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = WPAD) then
w_80(0) <= message0;
w_80(1) <= message1;
w_80(2) <= message2;
w_80(3) <= message3;
w_80(4) <= message4;
w_80(5) <= message5;
w_80(6) <= message6;
w_80(7) <= message7;
w_80(8) <= message8;
w_80(9) <= message9;
w_80(10) <= message10;
w_80(11) <= message11;
w_80(12) <= message12;
w_80(13) <= message13;
w_80(14) <= message14;
w_80(15) <= message15;
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif(Opcode2 = ROUND1) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))))
);
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
elsif(opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = ROUND1) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
elsif (Opcode2 = WPAD) then
w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))) <=
std_logic_vector(
unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 19)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 61)) xor unsigned(shift_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 6)) +
unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-7)) +
unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 1)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 8)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 7))+
unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-16)));
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
stage3 <= S2;
end if;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 41d87307a0dca5ef223db29e24d7462c | 0.659683 | 2.959072 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_mid/bg_mid_sim_netlist.vhdl | 1 | 202,365 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_sim_netlist.vhdl
-- Design : bg_mid
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 4 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_bindec : entity is "bindec";
end bg_mid_bindec;
architecture STRUCTURE of bg_mid_bindec is
begin
ENOUT: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra(2),
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\ENOUT__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(2),
I1 => addra(0),
I2 => addra(1),
O => ena_array(1)
);
\ENOUT__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(0),
I1 => addra(1),
I2 => addra(2),
O => ena_array(2)
);
\ENOUT__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => addra(2),
O => ena_array(3)
);
\ENOUT__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(0),
I1 => addra(2),
I2 => addra(1),
O => ena_array(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
clka : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end bg_mid_blk_mem_gen_mux;
architecture STRUCTURE of bg_mid_blk_mem_gen_mux is
signal \douta[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\(0),
O => douta(0)
);
\douta[10]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[10]_INST_0_i_1_n_0\,
I1 => \douta[10]_INST_0_i_2_n_0\,
O => douta(10),
S => sel_pipe_d1(2)
);
\douta[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6),
O => \douta[10]_INST_0_i_1_n_0\
);
\douta[10]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(6),
I2 => sel_pipe_d1(1),
O => \douta[10]_INST_0_i_2_n_0\
);
\douta[11]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[11]_INST_0_i_1_n_0\,
I1 => \douta[11]_INST_0_i_2_n_0\,
O => douta(11),
S => sel_pipe_d1(2)
);
\douta[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7),
O => \douta[11]_INST_0_i_1_n_0\
);
\douta[11]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(7),
I2 => sel_pipe_d1(1),
O => \douta[11]_INST_0_i_2_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\(0),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\(0),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\(0),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => \douta[4]_INST_0_i_2_n_0\,
O => douta(4),
S => sel_pipe_d1(2)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
O => \douta[4]_INST_0_i_1_n_0\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(0),
I2 => sel_pipe_d1(1),
O => \douta[4]_INST_0_i_2_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => \douta[5]_INST_0_i_2_n_0\,
O => douta(5),
S => sel_pipe_d1(2)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1),
O => \douta[5]_INST_0_i_1_n_0\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(1),
I2 => sel_pipe_d1(1),
O => \douta[5]_INST_0_i_2_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => \douta[6]_INST_0_i_2_n_0\,
O => douta(6),
S => sel_pipe_d1(2)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2),
O => \douta[6]_INST_0_i_1_n_0\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(2),
I2 => sel_pipe_d1(1),
O => \douta[6]_INST_0_i_2_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => \douta[7]_INST_0_i_2_n_0\,
O => douta(7),
S => sel_pipe_d1(2)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3),
O => \douta[7]_INST_0_i_1_n_0\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(3),
I2 => sel_pipe_d1(1),
O => \douta[7]_INST_0_i_2_n_0\
);
\douta[8]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[8]_INST_0_i_1_n_0\,
I1 => \douta[8]_INST_0_i_2_n_0\,
O => douta(8),
S => sel_pipe_d1(2)
);
\douta[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4),
O => \douta[8]_INST_0_i_1_n_0\
);
\douta[8]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(4),
I2 => sel_pipe_d1(1),
O => \douta[8]_INST_0_i_2_n_0\
);
\douta[9]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[9]_INST_0_i_1_n_0\,
I1 => \douta[9]_INST_0_i_2_n_0\,
O => douta(9),
S => sel_pipe_d1(2)
);
\douta[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5),
O => \douta[9]_INST_0_i_1_n_0\
);
\douta[9]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(5),
I2 => sel_pipe_d1(1),
O => \douta[9]_INST_0_i_2_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_prim_wrapper_init is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_mid_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_mid_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF43FFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF73FFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFF43FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"EFFEFFE63EFFEFFEFFEFFEFFFFFFFFFFFDFFDFFDFFDFFDFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FF7FF7FF7FF7FF7FF7FF7FFFFFFFFFF",
INIT_08 => X"FEFFEFFEFFEFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_09 => X"BFFBFFBFFBFFBFFBFFFFFFFF7FF7FF7FF7FF7FF27F7FF7FFFFFFFFFFEFFEFFEF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFDFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF96FFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFBFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFDFFFFFB7FFFFFFFFFFFFFFDFFFFFFF7FFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFEFFFFFFFFFFFFFFFFF7FBFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFF",
INIT_13 => X"FFFFFFDFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFF97FFBFEFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFF97FF7FFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFF737EFFF7FFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFBFFFFDF",
INIT_17 => X"FFFFF7FFFFFFFFFFFFFFFFFFFFFDFFFFF7FFFFFFFFFFFFFFFFFFFFEA7FFFFFFF",
INIT_18 => X"FFFBFFFFFF7FFFFFFDFFFBFDBFFFFFFBFF7FFFFB7FFFFFFFFFFFFFFFFFFFFFF7",
INIT_19 => X"FFFFFEFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFEF7F",
INIT_1A => X"FFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFF7FBFFFDFFFFFFF7FFFFFFFFFDFFBFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FF7FBF7FFFFF7FFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFEDBD7F",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFFFFFFFFFFFFFFFFF7FDFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFB7FFFFFFFFFFFEEFFFFFFDFFFFBFFDFFF7FFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFEFF7FFFFEEFFFFFFFFFFFFBFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFBFFFD",
INIT_23 => X"FFFFFFFFBFFFFFFFFFFFFFFA7FFFFFFFFFFFFFBFFF5F8FDBFFFFFFDFFFFFBFFF",
INIT_24 => X"FFFFFFF97FDFFFFFFFFEFFFFFDFEFFFFFFFFBDFFFFFFFFBFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFBFEBFFFFFFBFEFFBF7FFDFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FEFF7FFDFBEEFFFFFFFFFFFBFFFFFFFFFFFFFFFBFFFF9FFFFFFFFFFB7FFFF7FF",
INIT_27 => X"BBFFFFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFDFA7FFFFEFFFFDFDF7FFFF6FFFE",
INIT_28 => X"FFFFFFEFFFFFFFFFFFFFFEFA6FF7DFFFFFFFFD7BBEEFFFFFFFFEFFFFFEFFFFFF",
INIT_29 => X"FFFFFFFB5FEFFFDF7FFFFFFFEFFF5BDFFFFFDFFFFFFFFFFFFFFFFFFFFFFEFFFF",
INIT_2A => X"FDFFFFFEFB7FFFFDFFFE7FFFFFFFFF7FBEFFFFFFF7FFFDFFFFFFFFFFFFFFFEFF",
INIT_2B => X"FFFFFFFFEFFFB7FFFFFBFFFD7DEFFFFFFFFFFFFFFFFFFFDFFFFBFFD97FFFFEFF",
INIT_2C => X"FFFFFFFFFEFFEFFFFFFFFFFFFFFFF7FEFFBFDFFA3FFFFFFFFF3F7FFFFEFFFF7F",
INIT_2D => X"FFFFFFFFFFFBADFFEFDFFF7B7FFFFFFDFFFFFFFFFFFFFFFFFFFD3FFFE3FFFFFF",
INIT_2E => X"FFFF7FFA7FBB767BFFBFFFFFFFEEFFEFFDBFFFFFFFFDFFFFFFFFFFFFDFFFFFFD",
INIT_2F => X"BB7FFFFFFFF74FFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBDDCCFED",
INIT_30 => X"FEFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFAF77772BF63BFFFDDB7FD16AAD",
INIT_31 => X"FFFFFFFFFFFFFFFEFFBFD2AEBF72F15AFCEED7EA7DE8DFC8B5B76FFFFEFDFFDF",
INIT_32 => X"FFDFADBBFFFF5758AFBF74495DBFD6F3D98FFD6FFFFFABFBFFFFFFFFFFFFFFFF",
INIT_33 => X"DCE6FFF27B42F9AFEB69632F3FFDFFEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"7CEF6EA4DFFF5FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFEFFFFFADBF56D3CFC7B",
INIT_35 => X"7FFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFFFF7AD6FFEFFFE7FE7BF697969FA4FF1",
INIT_36 => X"FFFFFFFFFFFFFFFFFFD91DFB43FD6C69AAFD9FD35DE4F3AEA13F9B4F88BBFDFF",
INIT_37 => X"F6FDFFFEBCECB2FAEAFEBEF33DD4F49EF953DD4F6D6FFFFFFFFFFFFFFFFFDFFF",
INIT_38 => X"9963EB3A12236E9B4AFB2236684FFFFFFDFFFFFFFBFFFDFFFFFFFFFFFFFFFFFF",
INIT_39 => X"B7EAEFBD55BBFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFDAF466DB3ECDE4EF7",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7CECFBBEE1B7D6DD776DD6EFB4EFBDCB5",
INIT_3B => X"FFEFFFBFFFBF7B7FBA66DD59F19AB2765FF6F70128DCD396FC648DCDA7133FFF",
INIT_3C => X"7E5D965F7FFA25A6197CAEB90EEF9E97A6AEEEF9F7A6C2FBFDFFFFFFFFFFFFFF",
INIT_3D => X"AFA95F635D77303C3BB5D773B85CD1FFF7FFFFFFFFFFEFFFFFFFEFBBDBFA7FAE",
INIT_3E => X"54D2319F77BB4F3FFFFFFFFFFFFFFDFFFFEC979E64D7479133B3C9DDDB45E1CE",
INIT_3F => X"FFFFFFFFFFFFF7FFFFEFFC63AB6D9BDBEB7FADBACEF6FBA57876544A6319F7F3",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[0]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5055500505505545404455350500450054605055750555065070030075033055",
INIT_01 => X"0550755570304057505550745555407900554044553505004500542505045434",
INIT_02 => X"4507553053055075070745564540775405550477050733505300064356657072",
INIT_03 => X"5FF9575756550555565755555305505555055553705545505740035000705504",
INIT_04 => X"605555559775597F95F57F5F77B759777D79FF977F7F5777FB77FF95F5F95757",
INIT_05 => X"0055057035500555035705555073550555507007000707455005737075050750",
INIT_06 => X"0540320545557053705005070577007900550357055550735505055555055035",
INIT_07 => X"7037555353505555050005447073475555350534505550705405055745000555",
INIT_08 => X"7977550503575550575453320234000746504505507037755430545050055437",
INIT_09 => X"53020555579F5F977957F777F797DFF57777977F9797F9B77779777F597F7F7F",
INIT_0A => X"4505305070453403753040050057405440505535775573453570003050750565",
INIT_0B => X"9053555300500007005570523503306904537530400500574054300054403703",
INIT_0C => X"5550555050755600545553444455500750455555055005370005505507577555",
INIT_0D => X"7755754777070755577005055535555305055575557505543350670575553444",
INIT_0E => X"0070030735557559D7F775F779F399955F59BDF757F7F99BF77F7F77BF579797",
INIT_0F => X"5534555355050505405053545755455050452050300705000007055705003705",
INIT_10 => X"5000500075555550544505555370507805354050535457554550005425505475",
INIT_11 => X"7755075735002550370555554575457074556055770775507500555055030075",
INIT_12 => X"5504557550457547550455534050555055540700575755672523570300505554",
INIT_13 => X"55275033500535555579595FF5797FF777795775F77F79F77F95F77F57B7D7D7",
INIT_14 => X"0500730355350030505500003005055903005557057055055704555003555070",
INIT_15 => X"5500547547055340355700005005008900505055000030050559035300070555",
INIT_16 => X"3056553075500073350530006435660554405570705070755790535004755505",
INIT_17 => X"5775755055667050567503504750507556506755505055575053053350540006",
INIT_18 => X"055005030500300005353572597537F79F57FF95B77F95F7F577FF79977F5F5F",
INIT_19 => X"5307500555305043050050570505550504035352505053523573353003007550",
INIT_1A => X"0457507503003375035500455430709807730500505705055505545550703050",
INIT_1B => X"7540737063507555070540505574500570057705704055000720500005705707",
INIT_1C => X"7405554505007055047046300075057505075065767755750575555050550555",
INIT_1D => X"53004030505005355050050335755557557755F5979577399F959775BF959597",
INIT_1E => X"7570550300000550757077005300300355000555300705370435030545320303",
INIT_1F => X"0535350353450400735000505070007903307570770053003003053507350707",
INIT_20 => X"0343044070505050555505550405507507503050057750030535073030740303",
INIT_21 => X"0555070550453003053507303074030305353503534504007350005305353503",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => \douta[3]\(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B5DB5DB5C95D6EF67D27EDDC4FA4FA4FB6BB6BB6B92B92B9BBDBBDBB49F49F49",
INIT_01 => X"FEDF9AFB3FDBFDBF59F59F59F7DF7DF75F35F35FB7FB7FB7F6EF6EF67D27D27D",
INIT_02 => X"7D57D57DC79C79C78E78E78EFAAFAAFACD7CD7CDFEDFEDFECFACFACFBEFAD7CD",
INIT_03 => X"6FF6FF6F76F76F769E39E39EABEABEABEABEABEA3CE3E39EABEB3C74157D57D5",
INIT_04 => X"FDBFDBFDBDDBDDBDDBDDBDDBDFFDDBFDBDDBFB7737BB7BB7BB7BB7BBFBFFBFFB",
INIT_05 => X"67D67D6756356356B76B76B42B3EB3EBACFACFAC6AC6AC6AD6ED6ED67D67D67D",
INIT_06 => X"A76A76A638778778E5CE5CE54E54E54ED4ED4ED4EF0EF0EFBB5BB5BB59F59F59",
INIT_07 => X"EF7EF7EFFEBFEBFEAFEAFEAFFAFFAFFA3B53B53BC3BC3BC32E72E72E72A72A72",
INIT_08 => X"D67D67D6FF6FF6FFFABFABFABFEBFEBF7BF7BF7BF5FF5FF57F57F57A57FD7FD7",
INIT_09 => X"9F59F59FDBFDBFDBEFBEFBEF3EB3EB3EB3EB3EB27B7FB7FB7DF7DF7D67D67D67",
INIT_0A => X"75C75C75D71D71D79D79D79A6B9EB9EB8EB8EB8E3AE3AE3AF3AF3AF33D73D73D",
INIT_0B => X"9D79D79A6BDEBDEBCEBCEBCE3EE3EE3EF3AF3AF3BD7BD7BDEBCEBCEB5CF5CF5C",
INIT_0C => X"FFF7F5FB9EB7CFE4AFD7E927BE2D4C4AEBCEBCEB5EF5EF5E75E75E75F71F71F7",
INIT_0D => X"54FBB6EFC7F761CDFF3EFFBDFFDBFF0FD8FCCD9DFAE9DFC77F5657F865DB2BDD",
INIT_0E => X"F9ED77F3FFD766BFBEAE47EF9EF69A3E9B6FFF727E7DD253FFC76DD2BFAEFDA9",
INIT_0F => X"E6DB6B78F6F3B9AFFFFDEBEA7EFD8F9A6EFDFF7DFDDF7DE48E7D67FB48A4CF4F",
INIT_10 => X"AFD743F27D6FEFE7775C69F3BFEEFABF696B7A2FA881A4DEDFB7FFEBDF7FDFF7",
INIT_11 => X"FFEEFFF0F67BE31EFD651CBFF57ED6D5F6F4CB2D7EE3F5F7DBDE3BD2EAF9CDDE",
INIT_12 => X"1C6F5DD7E8FF3D5F3F1774FDCEBF8F4D677E6B71FF55FFFFC57FCF9A73F577CD",
INIT_13 => X"F55DB2FEE35D63F791D2FEFFDFDEF7F7FFFBFFFA7ED1DF37FFF9FF84CEF5FFFD",
INIT_14 => X"AAD9B6FBFFF7B4E3EE31E7F077F7FFCF7F2EFE7F51DAF535F6F3AFEFADFB8BF0",
INIT_15 => X"5FFEBD326ABD361BDB8DCEBC06732D1D9FB3FBF7A9FF21F66EEF3BEBDDFF67FE",
INIT_16 => X"F508FC3A09E1D6FAFE667297F7FFAD3A87D9DCF7B57ADCEEFFFA7D5FFBEF664F",
INIT_17 => X"89D4E74FFBECC10AFF2FFFEDB7BCAFFD735D37FFFEE5FDB79FFB67E87CBEA9DF",
INIT_18 => X"FF9A7FEFED7F67FF5DFDE371BFBFD6D9FF2FFFF2217FF853FE530005357AFEB7",
INIT_19 => X"FBDEAEE070A4BA07DFF1DD42257FB40517E9118293DC3FE5C59883FFCE5CC1EF",
INIT_1A => X"F4A6FAB236FFD54035F5DAD73877778E8EEBD8FFFC903EECFFFAFFFDBD697FFF",
INIT_1B => X"0F9781D280FAA177319C7DDAFF97475FFFFF6DF1FF07FFFFFFBBFD1E3F4AC87D",
INIT_1C => X"AC4ABA69E4D519FF9FFFEFDBD39FFFFFFE9FF8FF37DF4C7FDFFDEFE2697FEA59",
INIT_1D => X"1FFF6FF7FDFFFFFFFFFFFFFF0ED3A05EFFDBE9A8183FE236E7FFF1E3C2E8343E",
INIT_1E => X"FEDDDEEC01836377FFDEBF500C9C166CA2DFDBE0177CF4217C2AFD96D8E2CBFA",
INIT_1F => X"976BE81A3AFE89FF67DFEEF05FC7DBFF13F7DB47041005DF1FFFBFFFDFDDFFFF",
INIT_20 => X"E59EFC760EF8E6D85C9FA0E45AC9C6FA5DFF3FFFBF7BFFF07E67AB778CDF1DE6",
INIT_21 => X"B2F1CF8889BEEC6F24FFC7FB8DAFFFE650399EA530E2E5FE19A86B620C3B2FFF",
INIT_22 => X"087F65BD777F7FF4FE9A7D84E7FF8F77332ECFDA42FED7561FFF79DF9F5BF78C",
INIT_23 => X"EDA4D1B1B39FEF3B5F3B7D3213FE9FD3E6F75FAF7F5F089AADA7BA074FF6B87F",
INIT_24 => X"FD76DFC83D5FFF3B9BDE684E7DBCF5D497609CE91DFFB81F8188759FFC7E04F7",
INIT_25 => X"FF3FABA7F7F386A57B55698F1BBD7BEF70EE97FFFF7578485E751DDDE7E4F856",
INIT_26 => X"CEA875617AA2E6DFFDFD5FFBFBDFD7F1C8EC3679A9FE9F58FFE7F56A19FEF5E6",
INIT_27 => X"2BFEFFEF5FE77E9C973ECBFC4F7F7FA7BE7BFD786F7F7AFBC95DC811FBD6AD18",
INIT_28 => X"29976BEEDFAF5FCC1FFAECFA6FF5D5B4FEE69C3B1EACE17ABF76EDE47E39FAC0",
INIT_29 => X"223F7F4A4FCB5BD77F924B454184118F89C70AFF28F7DF55C57FFF8FFFF6FF6A",
INIT_2A => X"395527AE3853FD9197AA6A939130D26A3EBCDFFFF7FFED7DB6DE7FF9F9FFAAFF",
INIT_2B => X"F68DB15D2EB6A0FF77FB93FD09EE9AFBDD4BFFF27EFF098FFDFB9FD27FD6B27F",
INIT_2C => X"EEEACBBFCAAEEE7F6FBFFFEF9D37A1E8F9BFD1E23FF0070D511755FFCAE7EA3F",
INIT_2D => X"FEFFDFBD5BE7BD7B4F431C724ED35FDC759031FFFFFBB919BF2D2EDD62A7826F",
INIT_2E => X"2CE97FD864420149AF9CB3A7FFAE74AC3D93C78FDEF15BF56EE1D145DE9BE73D",
INIT_2F => X"0037FC7EFFF74A15054399F62F98CA3F52C1413F97DE8D47577FC7FC49922394",
INIT_30 => X"B8979E4FF95F05EFCCB5DDBBCBF5EF6EFBEFB6470F680C6B3870800232DB5A25",
INIT_31 => X"5542EFFDB73DEF96B5B4E04040BF1230CA2D03024CA46C55ADA055F9DCFD259C",
INIT_32 => X"FBDB6DA28E404901046DF00208304000045484449BFF22DB6B67F577DF4FABF5",
INIT_33 => X"34D0E8125200892C2000D9082FFDB15FABAEED3DF19B114F9E27FFD7F7EF7DEF",
INIT_34 => X"448400008FD64D3AED972FAB3F67BEAFCA976BEF5D3DAEBEFAF6420622208A89",
INIT_35 => X"7E35BCFFF219BFBFB17FF2B7BFD8FA36B7D02C8EA14C0D513380003008000844",
INIT_36 => X"2DDFFBEB57EFFCFDEFDD0012206208E08A2C1C423000B198008A920B0A33BC93",
INIT_37 => X"C6CC00420A008AD2020C8E0211102018111111022109D57F03547DF71FFB06DF",
INIT_38 => X"1902A11A1010489A104901041003C5BF148B9FD5F94DA93583A9F7FDFDFBBBDE",
INIT_39 => X"2162A40440B001AA2B3E7BEFD6C7B7CF4ADEEDF8D8FABFD9B9226820073444AA",
INIT_3A => X"2795BE5DEDE74CDFEEFFDBC7E7F1FC8646482A461001010622C548920A404405",
INIT_3B => X"5FE7EFB1915A1245900009005192886E44724002204400022000044000031DD1",
INIT_3C => X"66481158000005A4281802001241960B20872419C1B0CAF52CB796DF5DF67DFF",
INIT_3D => X"420045425906202C0B1190620890011EFF5F62FFEFAD2F5F65E6E09D5D5384A0",
INIT_3E => X"40C0301400A05E0D4FFF7D77F7A5C9FA72C51216280349113296889489202001",
INIT_3F => X"F7FF0BBCFF5F82FFBDC0B4422B7A0050C0682021808601001810100023014303",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[1]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B5DB5DB549556EB679276DD44F24F24FB6BB6BB6A92A92A9BADBADBA49E49E49",
INIT_01 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB6EB6EB679279279",
INIT_02 => X"5D55D55DD79D79D78F38F38FBABBABBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"7FF7FF7FF7FF7FF7CE3CE3CEAEEAEEAEEAAEAAEABCEAE3CEAEEB9C7415DD5DD5",
INIT_04 => X"FDFFDFFDFFDFFDFFDFFDFFDFFFFFDFFDFFDFFBF73FFBFFBFFBFFBFFBFFFFFFFF",
INIT_05 => X"4BD4BD4BD6BD6BD63F23F23433BB3BB3A97A97A97AD7AD7A47E47E4776776776",
INIT_06 => X"E76E76E63C77C77CE5CE5CE5CE5CE5CEDCEDCEDCEF8EF8EFF91F91F99DD9DD9D",
INIT_07 => X"DF7DF7DFFFBFFBFFAFBAFBAFBAFBAFBA3B73B73BE3BE3BE32E72E72E72E72E72",
INIT_08 => X"DC7DC7DCEFCEFCEFEEBEEBEEBEEBEEBEFBEFBEFBFDFFDFFD7DD7DD7A57DD7DD7",
INIT_09 => X"1F71F71FF3BF3BF3AF3AF3AF3AF3AF3AE3EE3EE27E77E77E75E75E75E75E75E7",
INIT_0A => X"EDDEDDED5ED5ED5ED7ED7ED27F3FF3FFBDBBDBBDABDABDABDAFDAFDA7FE7FE7F",
INIT_0B => X"9939939A2BDABDAB4AB4AB4A36E36E3673273273B57B57B5BF6BF6BFF9FF9FF9",
INIT_0C => X"FFFBFDBB0FFDCEB6FFF7FBBF3EBF6DDAC9CC9CC95ED5ED5E55A55A55B71B71B7",
INIT_0D => X"5EDD7FEFC3FFF3AFFBA7DFBDF7EBEF0FD8EED1BDEEEBEFCFEF56FFF8677BABDF",
INIT_0E => X"CDED77FBDFDB5EFFBFB767FB1FFE9A3E9BEFEE325EFFF75AAF6729D2FF26BDF9",
INIT_0F => X"EF7B6F7ABEF79DEFDFEFEB9A76FF9FDEAEFCE73DFD7F6DE5CE5DEFC4B775EFDF",
INIT_10 => X"6BD9937A7DEAE96FF7D7FFE7B7F7FBBFF9FFFA105701B5FF5FBEAEEE9FD7FFF9",
INIT_11 => X"7EE9FF1AEE2F765CCD650E000A82DF95F7E4D93D76EBF5F7F9DE92F6C9F9DDD6",
INIT_12 => X"3E6F4CC017003DFFBF5776F5CEBFCF3DB7FF7BEBFF57FF7FD57FEFB23B5577F9",
INIT_13 => X"D5EFFBBCFB656AF791F0F65EFF9BEFB3FEFB7BFA7DD28B1F29FFFFFC5FF4FBDF",
INIT_14 => X"9B7DB3FFDEDFFF76F767F77016F29BCF79FFFFFFF3DAB1B7F7DB9A0052240FFA",
INIT_15 => X"4FBEFC322EC735EAE2F7FFFFFF736D5DBFB02101170121FF0AE5BBCF7F7D624F",
INIT_16 => X"FAF7FFFFFDA5F6FAF464066808000DFA7BDA6DF6FDDA9BFBFEDA6D4FBBFFDBDF",
INIT_17 => X"89F0C4B04400013FFFFFF7FFB7B4FFFEF7593FFEF77FF6FFBEF7FEA877FFCFEF",
INIT_18 => X"FFFA9FEDEF6FFFFFBDF5427D9EF7FBFBFB2DFFFA1FFF67FCEDEDFFFFFE5A7EA5",
INIT_19 => X"FF76FCFFF7FB6FFFFFFFFFFA7BFFDFFFFCDFFF7D7E283F654D100180220C41EF",
INIT_1A => X"3F3FFFFA5FFFEEFFEF6F276AFFAB668E9AABD00084D03AFEFFFFFFFDBDFFFFFF",
INIT_1B => X"FB5AFE7D7F7FA156311C5D80020447DFFFFFFDB1F6BFFFFFFFEEF7FFCDFFFFFB",
INIT_1C => X"846A2A2804D119FFFFFEF2CB927FFFFFFFF80FFFF93BFFFDBFF7FFFA77FFF7B7",
INIT_1D => X"FFFFDDB6FFFFFFFFFFFFFFFEFFFDFFFFCFFFFFF87FFFFDC9FA9FFF1E3D28243E",
INIT_1E => X"FFFF7FFFFF7DFFDFFFFFFFF87F77FFD7FDB786DFEC09B425450B4C9659C2CAF5",
INIT_1F => X"FFFDFFFA774FFEA8D95EEEBFA3D7589E13D41B09040089FFFFFFF5CA7FA7FFFF",
INIT_20 => X"3E745C4BF9A82558CC8220A45AC996FAFFFFDFBFFFDFFFFFF7FFFFDAFFFDEFFF",
INIT_21 => X"92D9CD030022606FFFFFFE5EFFFFFFFBBFFEF7FFFFBF7ABFFFF7FEFA7BE5FF65",
INIT_22 => X"FFFFFFF3ADFFFFFFADF7EF7BB97BFDFFFFFDFB3A3FAF7957F91B83B974129084",
INIT_23 => X"73FFAF7FBBBF7FEFFFFDFFEA6EBBFB88BD9B55BB8057098A08973A164984A27A",
INIT_24 => X"FFFDCAB87E9CEC336CEC6A5FD988F554874094E15E43021F7EFFFB79DFFDFFFE",
INIT_25 => X"A9B2A3B4AE278AA52017498E395D10EF8FBB66FF55DF9FB7AFBAF3B94F446FFF",
INIT_26 => X"CAB975617A0243DABAF3FB7BAFBD7F5E7FB7FFABA1BC9DEFFF7EBFF277739546",
INIT_27 => X"292F6AD65D67EBF7F9D5F6F60F766F7BFFAF95C85BDCEAABBFCD49154094AC98",
INIT_28 => X"DF7B954E5FAF763FFEF8AEF246B6D7B4B6E4BC3306A8E17C8122ED60461940C0",
INIT_29 => X"FFDF6F4A4F6B1BD749B2EB45498401C17EC30AFD28DF8D45117FFEFF49E48ADF",
INIT_2A => X"31212A8A3053D4502B326A934138D26AAAAD2E59F75B7DF3FDBBDFA8F9FBB279",
INIT_2B => X"8889B05C2C2600D51C337D792DE59ABD67BDEE9A2E7F1F974FDA93D27DBFEE3F",
INIT_2C => X"D31FB8F6DAB7637ED27271EFD9A7A4CAFFBFD17A2AF3B1894D14156F8A8D4A2E",
INIT_2D => X"4E3C303D7FFFBDDF43431E724EDF5FDC51AB507FAF12A9184D2D2CC922A782EF",
INIT_2E => X"EDE97FD86FFBF76BAF883385002476EF7513C78DDCE151F095FEBFFB5A8BEF7D",
INIT_2F => X"FB77FC76A2854A50054191F62F980A3FBF3FFFFCEFDE851277EEC7FEFDDFBFFD",
INIT_30 => X"B0979A4B785F056FB36E35AF7CC5EF7E8B2237EFFFFFAFDF33FFFDDA5FCF7BBD",
INIT_31 => X"ABBD6BBDBDBCBE86F53CFFEEFFFFF7FBFFEBDFCA7DEEF7DFBDBF7FFC6619219E",
INIT_32 => X"A9DBED3FFDFF7FD9AFFFA44A5DBFD6F3DDFF7D6C8535229B4B43F477DF6763F5",
INIT_33 => X"7AF757E27B4AF9AFEB7BFAAF2428B05E23AE6D3D7089154F73DABFD7F6EF5DEE",
INIT_34 => X"7CEF6EB4CF064D98CD972FAABF679AAF75F349BDB934A6BE7A7EDBF76F3CF7FA",
INIT_35 => X"2B17B8FFF211B6BA4EDCBEF7BEF9DF3696F7A9EDDF7FFF6FCFBF6B6869FB47E5",
INIT_36 => X"360FED6B57A7BDD9AFDD1DFB6FFF6DE9AAFDDFB27DE5F63EA9BF9B5FEA11BC07",
INIT_37 => X"D6F9FFFEB7ECBAF8EAFEFEF23DD4D59EF947DD4DEC7AD43E63557DFE1DBB06FF",
INIT_38 => X"9B676B6A16272C0B4ABB627278DFC5BF8C8397BDF94D2D35C6BDD3BDBD5B935E",
INIT_39 => X"16AEE3B9D5F3C1AA0B3E7BEF56C787CFD75EADF9D9FEBFFDBF642593EBFE5E7F",
INIT_3A => X"3715DE5DC1A54CDFEEBB5FCFEFF1FD97C9DF9BED1B7D6DD576DD2EFA6E3B9DB5",
INIT_3B => X"DBE7E8BFFFFF7B7E7B66D459FDDAFF7A5FB6F7120A9AD397DE64A9ADA75A7DD1",
INIT_3C => X"7A5D975F7FFA3D76397CAEB81CAF0D9E86AFCAF0F7B60E755CB53ABF5DF64D75",
INIT_3D => X"EFAB5E224571503070E45715B8CDD9FE7B176F6F6929235F67F7EF6FCFE9FFAE",
INIT_3E => X"5416C1CBF73B1D37CFEF3DDFE7A349DA7AEDD5DA6DD6CF9511A7CBCDFB67DFCF",
INIT_3F => X"F7FF6FF6BF4F827F3BEFFA61BBDFBBCBEB1FADBB4EF2FFF5727ED4C86C1CB7F6",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[2]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"021002232042042040440440444444444404404484084084FFFFFFFFFFFFFFFF",
INIT_02 => X"B7BB7BB7BB7BB7BBFBFFBFFB6FF6FF6F01101101021021020220220222221101",
INIT_03 => X"C5CC5CC55E15E15EFFEFFEFFFDBFDBFDBDDBDDBDDBDDFEFFFDBFFFD4BFB7FB7F",
INIT_04 => X"73173173857857856A56A56AC6AD31738578E627B0AF0AF0AD4AD4AD58D58D58",
INIT_05 => X"FDAFDAFD2DD2DD2DD0DD0DD49F4DF4DF5FB5FB5FA5BA5BA5BA1BA1BA9BE9BE9B",
INIT_06 => X"4DB4DB47A6DA6DA6DA2DA2DABFEBFEBF69B69B69B4DB4DB486E86E86FA6FA6FA",
INIT_07 => X"36D36D3651651651F75F75F74D34D34D6DA6DA6D36D36D36D16D16D1FF5FF5FF",
INIT_08 => X"3AA3AA3AB1EB1EB1D7DD7DD74D34D34DB69B69B68B28B28BBAFBAFBB69A69A69",
INIT_09 => X"A8EA8EA87AC7AC7A55E55E5575575575D51D51D10F58F58FCABCABCAAEAAEAAE",
INIT_0A => X"96B96B96A92A92A9BA9BA9B909E09E0972D72D725525525537537537C13C13C1",
INIT_0B => X"67E67E61767F67F6FD6FD6FDEFDEFDEFCCFCCFCCFECFECFED4DD4DD44F04F04F",
INIT_0C => X"21759F6DF0D65D5928DA0D41CF51F22F3F33F33FB3FB3FB3EB7EB7EB7EF7EF7E",
INIT_0D => X"F326D2B8BC240D704E58E86A8D5F11F937D52F4BD71D54BC74BD654B2E957FED",
INIT_0E => X"73BEAB9532B4EFA5E56AFFACA8E575E375DCBBF979FEC8B77E9EFE7BECFBF3A6",
INIT_0F => X"34A5FDAFD54AFBB964D4B5612FFCF1B17BEBFFD66BCADF9AB3A315FFFFCE1125",
INIT_10 => X"BF3E7EB11A1FBFB75DBFFFFBDA2934794EDAEDFFFFFF5ED0A6FBD5D3657D4A16",
INIT_11 => X"CB7FFFFF35FAABE3B3BAF3FFFFFF602A4ADF7796DBD66FAE973B6F9D3FAE6A2F",
INIT_12 => X"F595FF7FFFFFD3C5FDBB996B3554BCCB6E25DC5662FFFFE97AA350D955BFDBCE",
INIT_13 => X"2A3966D7BFDFF5AEFECF2DF5D4FFFFDCA5DD9D6146FFFCF77E9FFFFFEA8F8DAD",
INIT_14 => X"FF975EC4B5FFFFFBAAB91BBB7FFFFFF5DFFFFFFFFDBDDE6E48BFFFFFFFFFF22F",
INIT_15 => X"F8DFFFF97FFFFFFF1FFFFFFFFFDEBFFBC56FFFFFFFFFFED0FFFF6578CAD7FFFF",
INIT_16 => X"DFFFFFFFFFDF4DA53B9FFFFFFFFFFF05FFF5DE9FB36FFFFFFFFFFAF84FFFFFFC",
INIT_17 => X"FFEFFFFFFFFFFECAFFEC99215EDFFFFFFFFFD625AFFFFFF2652FFFFB7FFFFFFF",
INIT_18 => X"FFFF6E7AB9FFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF3FFFFFFFFFFDABDF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFEDDBF3FFFFFFFFFFFF1A",
INIT_1A => X"FFFFFFF97FFFFFFFFFFFFFFFFFFFDBFFFF7FBFFFFFFFEDC1FFFE44CACBFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFF9FFF3E7FFFFFFFA30FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFE",
INIT_1C => X"FFFFFDFFFFFFF74AFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF",
INIT_1D => X"FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFEF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FCA",
INIT_1F => X"FFFFFFF97FFFFFFFFFFFFBFFFFFFEFEFEEFFEEFFFFFFFF2AFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFF7FB7FFFFFFFFF7F85FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"7FFE77FFFFFFFFBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFD7BFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFC7FFF7FFFFF5",
INIT_24 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFDFFFFDFF7B7EFFFFFFEAFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFF7FFFFFFFFF79E7FEFFB0FFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFF",
INIT_26 => X"BFFFAEDFDFFFFF35FFFFFFFFFFFFFFFFFFFFFFFFFEDBFFFFFFFFFFF97FFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFDEFFFFFFFFFFFFB7FFFFFFFFFFFFFEFFFFFFBF7",
INIT_28 => X"FFFFFFFFFAFAFFFFFFFFFFF97FFFFB7FFFFFFFFFFFFFFFFFFFFF7F9FBFEFFF3F",
INIT_29 => X"FFFFFDF97FFFFFEFFFFFFDFFFFFFFFFFFFFDF5AAFFFAFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFDFFDFFFF7FFFFFFFFF6DFFCFBF95FFFFFFFEFFFFFFFFFFFFFFFF8744DFFF",
INIT_2B => X"FFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9ABFFFFFFFFFFF97FFFFFF6",
INIT_2C => X"FFFFFFFFFFFBFFFFFFFFFFFFB758FFFFFFFF7FF97FFFFFFFFFFFFED6FFFFFFFF",
INIT_2D => X"FFFFFFC280000000FDFDF7893120A027AEFFFFD2FFFFFFFFFFFBFB3EDF7E7F9A",
INIT_2E => X"121680231000001050F7CEFFFFFFFFFFFAFEFDF36FDFFFAFFFFFFFFFFFFCFED7",
INIT_2F => X"0008039BFFFFFFEFFFFE6E7DD16FFFD0FFFFFFFFFFF3FEFFFFFFF80000004000",
INIT_30 => X"FF7DF7B6BFF7FBFAFFFFFFF7FFFF39F5FFFFC800000000000000000100000000",
INIT_31 => X"FFFFFEDAFFFB7FFD7FFF00100000000000000021000000000000002FFFFFFFFB",
INIT_32 => X"7FF40000000000000000000100000000000000037FFFFFFEFFFD9BC9AEFDDC7A",
INIT_33 => X"8000000100000000000000001FFFFFEFFCFBD6EAAFF6FFBAFFFFF67CBF5BAB57",
INIT_34 => X"0000000013FFFFE7BB69DAD5DABFEDF0FFFCFF6B47FFFFDBEFC0000000010000",
INIT_35 => X"F7FED72E2DFE5F4FFFEFE5BEEF16ABFFFD800400008000000000000300000010",
INIT_36 => X"FFF11BDFF8FF56E7720000000000000000000001000000000000000001FFF3FE",
INIT_37 => X"20000000000100000000000100000000000000000007FBD5FEFEE32FE655FDD5",
INIT_38 => X"00000001400002200000000002007FFAFBFD7CD25FF6FFCAFF773F7373EEEEE1",
INIT_39 => X"8000080000083E55F7E38431A9397BFA39A7FA8EAE9171100000000000000000",
INIT_3A => X"FCEFB3EABF7EFF20D77DA030100E026000000000000000000000000100800000",
INIT_3B => X"34DC10000000000000000000000000000000000100000000000000000000027F",
INIT_3C => X"00002000000000000000000300000000000000000000000BEB6FD5D0BB5DFFCA",
INIT_3D => X"0000000100000000000000000000000385E99299B6DEFEAA9D68000000000040",
INIT_3E => X"00000000000000007A34D266997EBEB5AF100000000000000000000000000000",
INIT_3F => X"0891922970B17FC5D40000000000000000000000000000000000000300000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[3]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"09880909880909008888000B09880909880909008888000B0988090988090900",
INIT_01 => X"880988008809000B88880988880988008809000B88880988880988008809000B",
INIT_02 => X"8809880B88090988090988098809880B88090988090988098809880B88090988",
INIT_03 => X"8809888809888809000988008809888809888809000988008809888809888809",
INIT_04 => X"09880909008888000B09880909880909008888000B0988090988090900888800",
INIT_05 => X"09008888000B098809098809090088000B88880988880988008809000B880000",
INIT_06 => X"0B88090988090988098809880B8809880988880988008809000B888809888809",
INIT_07 => X"8809888809000988008809888809888809000988008809888809888809000988",
INIT_08 => X"09008888000B09880909880909008888000B09880909880909008888000B0988",
INIT_09 => X"000B88880988880988008809000B88880988880988008809000B888809888809",
INIT_0A => X"8855777755887777077777778855777755887777077777778855777755887777",
INIT_0B => X"5588557707887777555577075588557707887777555577075588557707887777",
INIT_0C => X"0788777755887707778855770788777755887707778855770788777755887707",
INIT_0D => X"5588550777555577778877775588550777555577778877775588550777555577",
INIT_0E => X"0055887777077777778855777755887777077777778855777755887777077777",
INIT_0F => X"777707777777885577775588777707777755557707558855770788777700FFFF",
INIT_10 => X"7755887707778855770788777755885577075588557707887777555577075588",
INIT_11 => X"0777555577778877775588550777555577778877775588550777555577778877",
INIT_12 => X"7777077777778855777755887777077777778855777755887777077777778855",
INIT_13 => X"7777555577075588557707887777555577075588557707887777555577075588",
INIT_14 => X"770B8877000988098809000D770B8877000988098809000D770B887700098809",
INIT_15 => X"000909098877000D090B8888000909098877000D090B8888000909098877000D",
INIT_16 => X"8877090D09778888770909888877090D09778888770909888877090D09778888",
INIT_17 => X"09770B88770009880977090009770B88770009880977090009770B8877000988",
INIT_18 => X"FF000988098809000D770B8877000988098809000D770B887700098809880900",
INIT_19 => X"88098809000D770B88770009880988000D090B88880009090988770010FF7070",
INIT_1A => X"0D09778888770909888877090D09770B8888000909098877000D090B88880009",
INIT_1B => X"88770009880977090009770B88770009880977090009770B8877000988097709",
INIT_1C => X"88098809000D770B8877000988098809000D770B8877000988098809000D770B",
INIT_1D => X"000D090B8888000909098877000D090B8888000909098877000D090B88880009",
INIT_1E => X"5588440009008855077707005588440009008855077707005588440009008855",
INIT_1F => X"0900775507000700888844070900775507000700888844070900775507000700",
INIT_20 => X"0700770088554407000077880700770088554407000077880700770088554407",
INIT_21 => X"8855880700097788550077078855880700097788550077078855880700097788",
INIT_22 => X"FF00008855077707005588440009008855077707005588440009008855077707",
INIT_23 => X"8855077707005588440009008855070700888844070900775507000700FFFFFF",
INIT_24 => X"0088554407000077880700770088558844070900775507000700888844070900",
INIT_25 => X"0700097788550077078855880700097788550077078855880700097788550077",
INIT_26 => X"8855077707005588440009008855077707005588440009008855077707005588",
INIT_27 => X"0700888844070900775507000700888844070900775507000700888844070900",
INIT_28 => X"097777000B7707BB09880005097777000B7707BB09880005097777000B7707BB",
INIT_29 => X"0B7709BB09770005777777090B7709BB09770005777777090B7709BB09770005",
INIT_2A => X"0977880577097709007709070977880577097709007709070977880577097709",
INIT_2B => X"77097709000B0907BB77880077097709000B0907BB77880077097709000B0907",
INIT_2C => X"FF007707BB09880005097777000B7707BB09880005097777000B7707BB098800",
INIT_2D => X"BB09770005777777090B7709BB09770005777777090B7709BB09770000FF7070",
INIT_2E => X"0577097709007709070977880577097709007709070977880577097709007709",
INIT_2F => X"09000B0907BB77880077097709000B0907BB77880077097709000B0907BB7788",
INIT_30 => X"07BB09880005097777000B7707BB09880005097777000B7707BB098800050977",
INIT_31 => X"0005777777090B7709BB09770005777777090B7709BB09770005777777090B77",
INIT_32 => X"887700097700077777090B99887700097700077777090B998877000977000777",
INIT_33 => X"7700997777770B99887700997700997777770B99887700997700997777770B99",
INIT_34 => X"7777099988880099090099077777099988880099090099077777099988880099",
INIT_35 => X"88887799097799077777090B88887799097799077777090B8888779909779907",
INIT_36 => X"FF0000077777090B99887700097700077777090B99887700097700077777090B",
INIT_37 => X"7777770B99887700997700997777770B99887700997700997777770B00FFFFFF",
INIT_38 => X"9988880099090099077777099988880099090099077777099988880099090099",
INIT_39 => X"99097799077777090B88887799097799077777090B8888779909779907777709",
INIT_3A => X"077777090B99887700097700077777090B99887700097700077777090B998877",
INIT_3B => X"0B99887700997700997777770B99887700997700997777770B99887700997700",
INIT_3C => X"770B77778809770977778800770B77778809770977778800770B777788097709",
INIT_3D => X"8809880977008800070B77778809880977008800070B77778809880977008800",
INIT_3E => X"7700770007777777770988777700770007777777770988777700770007777777",
INIT_3F => X"07770B77778888770900778807770B77778888770900778807770B7777888877",
INIT_40 => X"008809770977778800770B77778809770977778800770B777788097709777788",
INIT_41 => X"0977008800070B77778809880977008800070B7777880988097700880000FFFF",
INIT_42 => X"0007777777770988777700770007777777770988777700770007777777770988",
INIT_43 => X"77778888770900778807770B77778888770900778807770B7777888877090077",
INIT_44 => X"770977778800770B77778809770977778800770B77778809770977778800770B",
INIT_45 => X"8800070B77778809880977008800070B77778809880977008800070B77778809",
INIT_46 => X"0077000B777777880D880B0B0077000B777777880D880B0B0077000B77777788",
INIT_47 => X"777709880D770B0B99770077777709880D770B0B99770077777709880D770B0B",
INIT_48 => X"0D77880B990000770B7709770D77880B990000770B7709770D77880B99000077",
INIT_49 => X"990077770B7709778877880B990077770B7709778877880B990077770B770977",
INIT_4A => X"00777777880D880B0B0077000B777777880D880B0B0077000B777777880D880B",
INIT_4B => X"880D770B0B99770077777709880D770B0B99770077777709880D770B0B0077F8",
INIT_4C => X"0B990000770B7709770D77880B990000770B7709770D77880B990000770B7709",
INIT_4D => X"770B7709778877880B990077770B7709778877880B990077770B770977887788",
INIT_4E => X"77880D880B0B0077000B777777880D880B0B0077000B777777880D880B0B0077",
INIT_4F => X"0B0B99770077777709880D770B0B99770077777709880D770B0B997700777777",
INIT_50 => X"99777777777755885577880B99777777777755885577880B9977777777775588",
INIT_51 => X"77770B885599880B0777777777770B885599880B0777777777770B885599880B",
INIT_52 => X"5599770B0799777777770B555599770B0799777777770B555599770B07997777",
INIT_53 => X"0799777777770B55889977880799777777770B55889977880799777777770B55",
INIT_54 => X"10777755885577880B99777777777755885577880B9977777777775588557788",
INIT_55 => X"885599880B0777777777770B885599880B0777777777770B885599880B00BB99",
INIT_56 => X"0B0799777777770B555599770B0799777777770B555599770B0799777777770B",
INIT_57 => X"7777770B55889977880799777777770B55889977880799777777770B55889977",
INIT_58 => X"55885577880B99777777777755885577880B99777777777755885577880B9977",
INIT_59 => X"880B0777777777770B885599880B0777777777770B885599880B077777777777",
INIT_5A => X"880988880B88097709007777880988880B88097709007777880988880B880977",
INIT_5B => X"0B887777090977770B0988090B887777090977770B0988090B88777709097777",
INIT_5C => X"090900770B88880988887709090900770B88880988887709090900770B888809",
INIT_5D => X"0B880909880B7709770900770B880909880B7709770900770B880909880B7709",
INIT_5E => X"000B88097709007777880988880B88097709007777880988880B880977090077",
INIT_5F => X"77090977770B0988090B887777090977770B0988090B8877770909777700D7F8",
INIT_60 => X"770B88880988887709090900770B88880988887709090900770B888809888877",
INIT_61 => X"09880B7709770900770B880909880B7709770900770B880909880B7709770900",
INIT_62 => X"097709007777880988880B88097709007777880988880B880977090077778809",
INIT_63 => X"77770B0988090B887777090977770B0988090B887777090977770B0988090B88",
INIT_64 => X"0B99777788008809550977770777550009887709777709775577099900098809",
INIT_65 => X"7755885588D77777000055880977007777770755880905885509775555047788",
INIT_66 => X"0B99090B777777998877770055880B7777880B990000770B770B770D09775509",
INIT_67 => X"077788777707778877880088550B77880077778877000988770B887788997788",
INIT_68 => X"0077880B990077770B7705887709778855058809000988880088907788885588",
INIT_69 => X"5588000B7788077709770900990007095588777755007788078877770001F899",
INIT_6A => X"8800070B7777880977777709880955887788550B7700777700770909DD007777",
INIT_6B => X"77770988770909990000770B7700550977079955BB0B99007709550788770900",
INIT_6C => X"887777770B8877887788550B880988880777770B777777000999090900777788",
INIT_6D => X"77887777880B8877550977BB0B77775588000B77880777077709887788770977",
INIT_6E => X"8877999999BB777777770077558870075507775509095588070B770907770577",
INIT_6F => X"098809005507770977770B7777770B770B777700557788558877880988777777",
INIT_70 => X"88778877008877070B0988090B448809000B8800777709880055885577090977",
INIT_71 => X"770B000B008800770B77550909880007990B88098F0B997777885500990B8809",
INIT_72 => X"00000B880077770977008888888877770088057799557755097709005509880B",
INIT_73 => X"770999887709778877007709008877770077880B8877880B990B00880900D799",
INIT_74 => X"0B0B997700777755888800775588770977090988779977099909887707770009",
INIT_75 => X"0009887707887777779900550B778855098877090988008888770055880B7777",
INIT_76 => X"77070B887707880788770988550B770799000B55770088098855887777880788",
INIT_77 => X"07880B0B77550900887788098800097709778877097788880077070055097788",
INIT_78 => X"DDBBDDDDBBDDDDDDBB7707550988990507775509777777885577090577887788",
INIT_79 => X"885509097707000999770B777777098855777709550077008888BBBBBBDDBBBB",
INIT_7A => X"77888877880709000B880577887788770900770B88880588887707098F770955",
INIT_7B => X"550B880988778809008888778877996B88888FBBBB8F8888990B778877888F47",
INIT_7C => X"100700770B888805888888008888557700090977777777888855098804557709",
INIT_7D => X"77880B7777886B770000770B778895778877000977997788070B0B057700D799",
INIT_7E => X"880B078855887799778807770955000788050B00885509888855880988777700",
INIT_7F => X"77078809558877550B7777777709070009880009887777880977887700097799",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"770B09777788778855880B880B887788078855770077007777077788550B0B07",
INIT_01 => X"0B7709047788887788090088777700BB000B770B7700770B880007097755000B",
INIT_02 => X"BBDDBBDDBBDDDDDDBB9999999999998877097777098809558800550077077705",
INIT_03 => X"5588775588990977778877770055880700000077880977099999BBDDBBBBBBBB",
INIT_04 => X"880977880B778877777788550B77077777078888770977557709008800077700",
INIT_05 => X"55887788098877880D7705880B887DDDDDFFFFDDFFDDDD888888880B99058888",
INIT_06 => X"007707888877097755777799000B880B88778809000B0B880B77880955880088",
INIT_07 => X"0B558809000B880877770988770B0B07550B9977090900770B778888550077F8",
INIT_08 => X"77770B0988050B7700778877889999777788995588770977777709770B008809",
INIT_09 => X"8877558877090B88777709888877889955090B770B09880B8807558899777709",
INIT_0A => X"098877000B778809888877055509887777880077098809880077887709888877",
INIT_0B => X"77007777097788558888770B098809097788097777990B88090B777777000977",
INIT_0C => X"BBBBBBBBDDBBDDBBDDBBBBBBBBBB889977880907550777550735997709770977",
INIT_0D => X"00770B0B7707990009078809097709078F99990B777777996B8FBBBBBBBBBBBB",
INIT_0E => X"7777880B55887709090B880B885588770B7788550955880B0977990707770B99",
INIT_0F => X"0B8807778877880B77888F8F88BBBBDDFFFFFFFFFFFFFFFFBBBB6B8877990D09",
INIT_10 => X"000B7788550977880B070B0099889988998877889977888888005555880B0977",
INIT_11 => X"770009779977090499778877777788887788550977770777880955880B00D799",
INIT_12 => X"7788887707778877990099889988778888888888888888886B88887788777788",
INIT_13 => X"550B885509880077557788077700777709887777880977775588770B55097777",
INIT_14 => X"777709997788770977097788778877770055990988887777990B555588770900",
INIT_15 => X"770988888888778809550988097788000977778809775509778800770B779900",
INIT_16 => X"BBBBBBDDBBDDDDDDBBBBBBBBBBBBBBBB99997788777709007788550777007700",
INIT_17 => X"99097788778805099977770977007788998899BB888899BB778899BB99BBBBBB",
INIT_18 => X"0B88055588778855887707770588090B00770477880B778888770B7788885500",
INIT_19 => X"330B880B000B0B778877778888DDDDFFFFFFFFFFFFFFFFFFFFDDDDDDDD889999",
INIT_1A => X"1000770477880B5588889988998F0D0B886B990B880B07B609990B8855888800",
INIT_1B => X"887788770700770B88880788880977880B777788000B7788448888077700BB99",
INIT_1C => X"888833007788770788BB8F8888BB8F7D8F888FBBDD8F8F88886B7788090B0777",
INIT_1D => X"00990900990909770088557709990B09777788770B8807090B880B887788770B",
INIT_1E => X"8807880D770988009988550B0B009988098800995509770B0077007709008877",
INIT_1F => X"77770B04097709775577770B880755887777007755098855880B6B0077000B99",
INIT_20 => X"BBDDBBDDBBBBDDBBBBBB88BBBBDDBBBBBB999999775588777777007777097709",
INIT_21 => X"778877770977075588770B88779988888899BBDD88BB88BBBBBBBB99BBBBBBBB",
INIT_22 => X"DD88DD888F9955880077098800097709880B7700090B99775509007799887777",
INIT_23 => X"09887700880B0B0077DD88DD888F88DDFFFFFFFFFFFFFFDDDDFFFFFFFFFFFF88",
INIT_24 => X"000B0B88998888BB88888F888F6B880B880B6B8888BB8F888F88999977887788",
INIT_25 => X"887788550B7788550955880B0955998877777777097788880B7788000901F899",
INIT_26 => X"88770B007700770B888FBB8FDDFFFFFFFFDDFFFFDDFFDDDDBB88887D0955880B",
INIT_27 => X"0F996B7D889988770B7755887777990077057788090B00550088777777777777",
INIT_28 => X"0B885577887777770B88778877886B009988889999BB88BBBB8FBBBB888F8877",
INIT_29 => X"8FBBBB99886B8F99888888090B880B88550988777709778877880B9988557777",
INIT_2A => X"BB99BBDDBBDDDD88BBBBBBBBBBBBBB8899998899999909778888078805770755",
INIT_2B => X"8809557777887788770988779999BBBBBBBB88BBBB99BB8FBBBBBBBB99BBBB88",
INIT_2C => X"DDDDDDDDDD88880D8F8877880999007709558899888809000977998800070988",
INIT_2D => X"777755BBBB9988BB8FDDDDDDBB88DDFFFFFFDDDDFFFFFFDDFFDDFFFFFFFFDDDD",
INIT_2E => X"00BB88998F77888F88DDBBBBBB88DD88999908888F88BBDDDDDDDDBB8899880B",
INIT_2F => X"0900090B00770477880B44888888889988DD8F888F8899BB8F990F888F00D799",
INIT_30 => X"770B7777888F8F888F8FFFDD8FFFFFFFDDFFBBDDDDBBFFDDDD888F7788880744",
INIT_31 => X"88888888880888BB88880B88009900990988880B007709770988090B00770777",
INIT_32 => X"885588885507098855880B778899888F880B99888FBBDDDDFFFFFFDD8FBB8F7D",
INIT_33 => X"BBDDDDDDDDBB8888888899887709550B0B88550B88880955007777880988880B",
INIT_34 => X"BBBBBBBBDDBBBBBBBBBBBBBBBBBBBBBBBB996B99888899885555777777097709",
INIT_35 => X"777788886B7D0B09997777999988BB9999BBBBBB997D8899BBDDDDBBDDBBBBBB",
INIT_36 => X"DDDDDDDDFFDD9988880B77999977090077885577098877998877887777997799",
INIT_37 => X"888877887DBBDDBBDDDDDDDDBBDDDDDDFFFFFFFFFFFFDDDDDDDDFFFFFFDDFFDD",
INIT_38 => X"108F888FBB8FDDDDFFDDFFFFFFFFFFDD880D6B9988DDDDFFFFFFDDBB8F888F88",
INIT_39 => X"779977777788770B777788070B7D8F8FDD8FFFDDDDFF8FBB88BB888F880099F8",
INIT_3A => X"007700770B8888DDBBFFFFDDDDFFDDFFFF8FFFFFBBFFDDBB88DD888855778877",
INIT_3B => X"7D888F888F7D888899889988880B99889999778855008877777788777788770B",
INIT_3C => X"7709770009888877000977886B888F99887D8F7D88FFFFFFFFFFFFFFFFFFDDBB",
INIT_3D => X"FFFFFFFFFFFFFFFFDDDD885500887777887777880B0777880777885577075588",
INIT_3E => X"BB88BBBBBBDDBBBBBBBBBB99BBBB9999BBBB9999999999770909550588558855",
INIT_3F => X"889999998899998888887D7799BB99998888BB998F88BBBBDDBBDDDDBBBBBBBB",
INIT_40 => X"DDDDFFFFDDFFDDBB9988BB88889977990B778877007700098809776B8F880B88",
INIT_41 => X"777788BB88FFBBDDDD8FDDBBDDDDBBFFDDDDDDDDDDDDDDDDDDDDDDDDDDFFDD8F",
INIT_42 => X"1099BBDDDDDDDDFFDDFFFFFFFFFFFFFFBB88886BBBDDDDDDDDFFDDFFDDDDBBBB",
INIT_43 => X"888F8888886B88888F9988998888BBFFFFFFFFFFFFFFFFFFFFFFFF88DD00D799",
INIT_44 => X"888FBB888F8F8FBB8FDDFFFFBBFFFF8FFFFFDD8FDDBBFFDDFF88DD88888F7D88",
INIT_45 => X"DDBBDD8F88888F8888880F886B8899880B880B99998F886B99880F887D778F88",
INIT_46 => X"88778899887755888F88886B8888888F7D8888DDDDFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFDDDD8F888F8809550B0B77888800777788000900770B77",
INIT_48 => X"BBBBDD99BBBB888F99BB99BB888899996B88998F99999988B677070988778877",
INIT_49 => X"0B889999997799886B999988BB0999090B9999999999BB8888BBBBBBBBBBBBBB",
INIT_4A => X"BBDDDDFFDDDDFFBBBBBBDDBB88BB999999098877888877886B88779999779988",
INIT_4B => X"DDDDDD8FDD88BBBB8F88BBDD8FDDDD8FDDDDDD8FDDDDDD88BBDDDDDDDDDDBBDD",
INIT_4C => X"00DD8FDDDDBBDDFFDDFFFFFFFFFFFFFFFFDDBB8FDDFFDDDDDDDDDDDDDDFFDDFF",
INIT_4D => X"888FDD888F888F8888888888DDDDDDFFFFFFDDFFFFFFDDFFDDFFDDDDDD00D799",
INIT_4E => X"DD8F8F8899DDDDDD88DD8FDDDDBBDDDDBBDD8FBBFFDD8FDDDDDDDDDDDD8F888F",
INIT_4F => X"FFFFFFFFFFDDFF8FBB887D8F6B888899887D8F7D888FBB8F8F888FDDDDDDDDDD",
INIT_50 => X"88997777887709887D88887D8FDDDDFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFDD885577007777778807778888777700770977",
INIT_52 => X"88BBBBBBBB88999988778F88998F999999998877880B77098808775577075509",
INIT_53 => X"8899997D88BB8899776B889988998888887799886B999999BBBBBBBBBBBBBBBB",
INIT_54 => X"DDDDFFFFFFDDDDDDDDBB88BBDDBB88889988770B9977886B8899999988888899",
INIT_55 => X"DDDD8FBBDD8FDD88BB8F8FBBDD88DD88BBBBDDBBBBDD88DDBB8FDDBBDDBB88BB",
INIT_56 => X"10DDBBFFDDFFFFDDFFFFFFFFFFFFFFFFFFFFDDBBDD8FDDBBDD88DDDDDDDDDDDD",
INIT_57 => X"6BBB88FFDDFFDDDDBB998FDDDDFFFFDDFFFFFF8FFFDDFFDDFFDDFFFFDD00BB99",
INIT_58 => X"DDDDBBBB888FBB88DD8FDDDD88DD88DD8F88DDDD88DDDDDDDD8FFFFFFFBB0D77",
INIT_59 => X"FFFFFFFFFFFFFFFFFFDD88BB88DD8FBB8F888888BB88DD8FDDDDDDFFFFFFFFDD",
INIT_5A => X"778800880B8888BB778FDDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF8F887D88887D88889988886B888899998F88",
INIT_5C => X"BBBBBBBBBBBB88BBBB9999BB9988BBBB998899998F7788770577098877777777",
INIT_5D => X"99998888998F9988BB9999887777999999886B7777888F8888BB99BBBB99BB99",
INIT_5E => X"BBDDDDDDDDDDDDDDBB8F8F88887D887D889988999999998899886B8F8F77770B",
INIT_5F => X"DDDDDDDD88BB888FBBDD998FDDBB88BB88DDDDDDDDDDDDBBBB88DDFFDDDDBBDD",
INIT_60 => X"008FFFDDBBDDDDFFDDFFFFFFFFFFFFFFFFFFFFDDBBDDFFDDDDBBDD8FBBDDDDFF",
INIT_61 => X"88BBDDFFFFFFFFFF8F8888FFBBFFDDFFFFFFFFDDFF8FFFFFFFFFFFDDDD00D7F8",
INIT_62 => X"DDDD888FDDBBBB8FBBBBDD8F8FBB8F88DDFFDDDD8F8FDDDDDDFFFFFFFF8FBB88",
INIT_63 => X"FFFFFFFFFFFFFFDDFFDDDD8F8FBBBBBBBBBBBBBB8FDDDDDDFFFFFFFFFFFFFFFF",
INIT_64 => X"886B998899998FBBBBDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFDDDDFFFFFFFFFFFFFFFFFFFFFFFFBB888888776B6B886B8888996B888F7700",
INIT_66 => X"BBBBBB99998899998888998899BB99888F999988779999887788777700770077",
INIT_67 => X"88996B99BB8899998F887D9988998899BB8F88BB889977998FBB8899889999BB",
INIT_68 => X"BBBBDDDDDDDDBBDDBBBB888F88998F99998F88BB99888F998F99887788888899",
INIT_69 => X"FFFFFFDDDDBB88BB88BBBB8888888F888F888F8FDD7DDD88BBBBBBDDDDDD8FBB",
INIT_6A => X"00DDDDFFFFDDDDDDDDDDFFFFFFFFFFFFFFFFFFDDDDDDBBDDDDDDBBBBDDBBBBDD",
INIT_6B => X"8F88BBBBFFFFFFFFFFFFDD8FFFDDFFFFFFFFFFDDFFDDDDFFFFDDFFDDFF01F899",
INIT_6C => X"DDDDDDDD8F888FDD888FDD88DDDDBBFF8FDD8FDDDDDDDDDDDDFFDDFFFFFFFFDD",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFF8FFFFFFFFFFFFFFFFFFFFFFFFFBB",
INIT_6E => X"7788888F888FDD8FFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFDD88BB7D88886B88886B8888998888BB",
INIT_70 => X"BB8899888899997D8888BB999999889977889999889988BB888877770B550B55",
INIT_71 => X"9988BB6BBB888F7D9999BB99889988DDBB88BBBB8888996B8899998899888899",
INIT_72 => X"DDDDDDBBDD88BBBB99BBBBBB88BB997D88BB888899889999999988998F7D9988",
INIT_73 => X"8FDDFFDDDDDDBBDD88BBDD8FBB8F888888BB99BBBB7D88BB8F88BBDDDDDDDDDD",
INIT_74 => X"10DDDDDDFFFFDDDDBBDDDD88BB88DDDDDDDDDDFFDD8888DDDD8FBBDDBB88DDDD",
INIT_75 => X"FFFF8FFFFFFFFFFFFFFFDDFFFFFFFFDDFFDDFFFFFFFF8FFFDD8FDDFFDD0099F8",
INIT_76 => X"DDDDDDDDDDDDDD8FBBDDDDDDDDDDBB8FDDFFFFDDDDDD8FFFDDFFBBFFDDFF8FFF",
INIT_77 => X"FFFFFFFFFFFFFFDDFFFFDDFFFFFFDDFFBBFFDDFFFFFFFFDDFF8FFFDD8FFFDDDD",
INIT_78 => X"BB88DDFFFFFFFFFFFFBBDDBBBBFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFF8FDD888FBB886B8888886BBB88BB88BB",
INIT_7A => X"8F99999999889999999999BB999999997D9999997DBB9988D7770D7788778877",
INIT_7B => X"99999977998F887788886B889988BBBBBBBB8F778899887799BB999977BBBB8F",
INIT_7C => X"DDBBDDBBBBBB888F8F88997799888F88BB888F7788990BBB886BBB778888886B",
INIT_7D => X"DDFFBBDDDDBBBB8FBB889988888F88BB888F888F8F77888F88BB8888DDDDDDDD",
INIT_7E => X"10DDFFFFBBDD8FDDBB88BBBB8F888FDD88DDDDDDFFDDDDBB88BB8FBB8FBBBBBB",
INIT_7F => X"8FDDDD8FDDFFFFFFDDFFFFDDFFDDBBFFFFFFFFDDFFDDDDDDDDDDDDFFFF00D799",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"8FDDDDDD8F88DDDD8F8FDD88888FBB88DDDDDDBBFFFFDDFFFFFFFFDDDDFFFFDD",
INIT_01 => X"DDFFFFFFBBFFFFDDDDFFFFDDDDFFFFFFFFDDFFDDFFDDFFFFDDFFBBFFDDBBFFBB",
INIT_02 => X"8FDDFFFFFFFFFFFFDD8FBB8FFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDDDDD",
INIT_03 => X"DDFFDDFFFFFFDDFFFFFFFFFFFFFFFFFFDDDDBB88888F888F8FBB888F88888888",
INIT_04 => X"99889988888F88998888999988999988770B997799888F8F8877777777097709",
INIT_05 => X"7D88996B88779999779999BBBBBB88BBBB99889999999999886B889999889999",
INIT_06 => X"DDDDDDDD88BBBBDD88BB8FBB8899998FBBBB888F9988BB77BB88998877999999",
INIT_07 => X"BBBBFFDDDD8FDDBBBBDDDD8FBB88BB8FBB88BB88888899998F88BBBBDDBBFFDD",
INIT_08 => X"00DDDDDDFFBBDDDDDDDD8FBBBBDDBB8FDDDD8FDD8F8F888FBB8888BBBB88BB8F",
INIT_09 => X"DDDDDDFFFFDDDDFFFFDD8FDDBBDDDDDDDDFFFFDDFFDDFFBBDD88FFDDDD0077F8",
INIT_0A => X"DDDD8888DDDD7DDD88BB88DDDDDD8FDDBB8888DDDDBBDDBB8FBBFFFFFFFFFFDD",
INIT_0B => X"DDBBDD88DDDDDDDDDDDDFFFFFFDDDDBBFFDDDDFFBBFF8FDDFFDDFFDDDDFFDD8F",
INIT_0C => X"88DDDDDDFFFFDD8F88DD88DD8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDBB8FDD",
INIT_0D => X"DDDDFFDDDDFFDDDDFFFFFFFFFFFFFFFFFF8FDDDDDD8888BBBB8FBB888FDD8FBB",
INIT_0E => X"BB999999BB9999BBBB998FBBBBBB8899BB888899BBBB99999977880988778877",
INIT_0F => X"77990B8899998F8F88886B887D999977778F999977886B88BB99998F0B997D77",
INIT_10 => X"BBDDDD88BB8FBBBB99BB9988BB8F88BB88BBBB8899BBBBBB88999999BB888F99",
INIT_11 => X"DDDDDD888FBBBB8FBBBBBB8888BB888877BBBBBBBB997D8888BB778F88BBBB88",
INIT_12 => X"00BBDDDDDDDD88DD88BB88BB888F88DDBB88DD88DDBBBB8899889988998F88DD",
INIT_13 => X"DDDD8FFFDDDDFF8FDDDD88DD8F88BBDDFFFFDDDD88BB888FBBBBDDFFFF00D799",
INIT_14 => X"8FBB8FDD7DBBBB88BB888F8888BB88888FDDDDDD88FFBBFFDDFFFFFFDDFFFF8F",
INIT_15 => X"8FBB88BBFF88BBDDFFDDDD8FBBDDFFDDDD8FFFBBFFFFDDFFBBDDDDDDDDBBDDDD",
INIT_16 => X"DDBB8FBBDD8FBB88DD888FFFFFFF8FFFDDFF8FFFFFFFFFFFFFFFFFFFDDFFDDDD",
INIT_17 => X"DDDDDDDDFFDDDDDDDDFFFFFFFFFFFFFFDD888FDDDDFFDDFFFFDD8F8FBBBBDD88",
INIT_18 => X"9988999977BBBB888FBBBBBB9988BB99888F88BBBB997D9999888888770B770B",
INIT_19 => X"BB990B9988BB996B8899BB7799888F88BB9977774799889999998F779988886B",
INIT_1A => X"DDBBBBBBBBBBBBBB8F888F88BB888F88998F8F8F8899997D88998FBB888F8899",
INIT_1B => X"88BB8FDDDD88BBDD88BBBB88DDBB888899889988BB88BB88888F887788BB8F88",
INIT_1C => X"00DDDDBBDDDD8FBB8FBB888F88BB88DD88DDDD888FBB8888886B996B7799BBBB",
INIT_1D => X"DDFFDDFFFFFFFFFFDDDDFFFF88DDBB8FDD888F8888887D88DDDD88BBDD00D7F8",
INIT_1E => X"888F88887D9977887799778888778888BB8888DD8F88888FDDDDFFBB8FDDFFFF",
INIT_1F => X"BB8F88DDBBBBDD888FDD88DDDDFFDDDDFFBBDDBBDDDDDDFFBBDD8888DDDDDD88",
INIT_20 => X"888FBB8F888FDD7DDD888F8888FFBBDDDDDDDDDDDD8FDDDD8FFFFFFFDDFF88BB",
INIT_21 => X"BBDDDDDDDDDDDDBBFFDDDDDD88DDDDDDDD8F888FDDBBDD88BBDDDD888FBBBB8F",
INIT_22 => X"997D998F8F88DDBBBB88BBBBBBBB888FBB99BBBBBB997799098F997788778877",
INIT_23 => X"889999BB9988778899886B9999999999778F99886B778F99778888996B999977",
INIT_24 => X"7D88BB8F88BB8F888899BBBB88BB998F8888778899889988BB88998899889999",
INIT_25 => X"BBDDDDBB88DDBBBB8F88DDBB888FBB8F9988889988997D999988997D888888DD",
INIT_26 => X"00DD8FFF888FDDBBDDBBF8888F88BBBB8F8888BB888FBB6B999988886B998F88",
INIT_27 => X"FFFFFFFFFFFFDDFFDD8FFFFFDD8FBBDD888F99BB8FBB88BB88BBDDDD8F01F899",
INIT_28 => X"BB886B99777788770B886B9999889999BB8888BB88DDDDDDDD8FDDFFDDFFFFDD",
INIT_29 => X"DDBBDDBB888F88DDDDBBFF88DDBBDDBBDDDDDDFFBBBBDD8888BBDD8F88BB9988",
INIT_2A => X"BB88BB88BB88BB88DD88BB88DD88DD8FDDBBBB888FDDDDDDDDBBDDDDBBDDDDDD",
INIT_2B => X"DDBBBBBBDDDDDDDD88BB88DD8FBB88DDBBDDDDBB998F88BB8F88888F88888F88",
INIT_2C => X"999977777799BB88BBDDBB88888F8F7799BBBB8FBB99BBBB8877880977777777",
INIT_2D => X"996B88BBBB8FBBBB99BB99888F887D8899886B998899598877998F99887777BB",
INIT_2E => X"88BB8FBBDD8F88BBBBBB886B997D8888778F99997D6B88998899888F99889988",
INIT_2F => X"8FBB88BB8FBBBB8FDDFF8F88BBBB88BB8899888FBB8F888888998877998FBBBB",
INIT_30 => X"00DDDD88BBDDDD8FBB8F8888BBBB8FDD88BBBB888F8899886B886B9999888899",
INIT_31 => X"FFFFFFFFFFFF8FFFBBFFFFDDDD8888BB88BB888F7788DD88DD8888DDBB00D799",
INIT_32 => X"889988990B990977880B478888776B99888F8F888F88BB88DD88DDBBFFDDDDDD",
INIT_33 => X"BB88DDDDFFDDDDDD88BB8FDDBB88DDDDDDDDFF88DD8F88DDDDBB8FBB888F7D88",
INIT_34 => X"88BB88BB88DD888F88BB778F888FBB88BB8FDD8FDD888F88BBFFBB8FDDDDDDBB",
INIT_35 => X"88BB888F88BBDDBB8F8F8888BBBBDD88DD88DD888FBB888FBB888F88888F8888",
INIT_36 => X"9988778888F88899BB99BB8F999988F8BB88BB9999BB887D77770988770B770B",
INIT_37 => X"8877999988BB888F8899887D8899997D8F778877998899779988779999998F88",
INIT_38 => X"BB88BBBBBB99BBBB88BB99888F88BB8F889988998877990B7D9999887799998F",
INIT_39 => X"88BBDDDD88DDDD88DD888FBB888F99886B888F998899997D8F99997799779988",
INIT_3A => X"10FFBBDD8FBB8F88DD88BB888F88BBBBDD8F8FBB8899888F886B880B8899888F",
INIT_3B => X"FFDDFFFFFFFFFFDDDDBBFFBB88DD8F888FBBBB88BB888F88DD8FBBBB880099F8",
INIT_3C => X"990B990988887788998888776B08880B998888BB88888F88BBDD8FDDDDBBFFFF",
INIT_3D => X"FFDDDD8FDDBBBB8FDDDDBB88BB8FBBDD888FDDDDBBDDFFBB888F8888BB887799",
INIT_3E => X"8F888F888F88BB88BB8F88998F888888DD8888BB88BB88DD88DDDD88BB8FDDDD",
INIT_3F => X"998F8F99888FBB88BBBB88BB888F88DDBB8F8FBB88BB8FBB8F88BBDDBB888FBB",
INIT_40 => X"99D76BBB6B88888F9999BB778F999988BB88BBBBBB99BB997707999999999999",
INIT_41 => X"8899BBBBBBBBBB8899BB886B99BB888F77888899888899886B777799990B9999",
INIT_42 => X"998F99BBBB888F8F8899888F886B9999888888999999998899888888000D6B99",
INIT_43 => X"88BB8888BB8888998888889999886B998F997D8888888F998F9988886B8F888F",
INIT_44 => X"0088BBFFBB8888BB88BB88888F887DBB888F8F8899777D8F7799888899889999",
INIT_45 => X"DDDDDD8FFFFFFFBBFF888F888899BB998FBB889988887D8F8F888F88BB0077F8",
INIT_46 => X"6B88998888778877880988998877887709887D88BB8F88BBBBBB7DDD888FDDDD",
INIT_47 => X"DDDDBBDD8FDDDD8FBBDDDD8FDDBB8888DDBBBBDDBBDDBB8FBB88BB8F888F8899",
INIT_48 => X"BB8FBBBB88BBBB888F88886B9988BB8F88BBBBBB88BB88BBDD8FBBDD88DD88DD",
INIT_49 => X"BBBB997D99BB9988998F88888F888F888F8888888F8F8FBB88DDDDDD8888888F",
INIT_4A => X"995988998899999988886B88777788778FBB99BB88886B889988990B99889988",
INIT_4B => X"BB7D77DD88DDDDBB88889999990B778899998F99779977098877887788770B77",
INIT_4C => X"9988998F7799998888999999998899998F998F0B998F9988887D8F99BBBBBB88",
INIT_4D => X"8F88BBBB88BBBB8F8F997D8899998899778877998F9977089988999999889988",
INIT_4E => X"008F8F998888888FBB887D8F8899888899BB99888F99888808888F7709888888",
INIT_4F => X"DDDD8FDDDDDD8FDDDDDDBB8F8F8888889988886B88887788998899998F00D799",
INIT_50 => X"887707777709090077887707770B7777889977776B99888FBB88888F88BBBB8F",
INIT_51 => X"88DD8888DD88BBDD88BBDD888FBB8FDDDD88BB8F88888F8888BB88BB8899996B",
INIT_52 => X"888888888F88888FBB88BB88886B88886B888F778F888F88DD888888BBBBDD8F",
INIT_53 => X"7D8F88BB88BB888F889988BB888899DDBBBBDDBB888888BBBB88BB8888BBBB77",
INIT_54 => X"0B7799BB99999988999977777D99999988779988999988998F77779977997799",
INIT_55 => X"BB99DDBBDDBB8888BB99887DBB99888F8F888899889988997799097709997788",
INIT_56 => X"99998888BB8F99998F889988999988887788BB88BB88996BBB77998899998FBB",
INIT_57 => X"99998888BB998F8899BB77BB990B998899997799770B88BB88990B99886B778F",
INIT_58 => X"1088888F888FBB8888BB77887D888F7D887788BB7777888F996B888877888877",
INIT_59 => X"BB88BBBB8F88DDFF8888BB88888F8FBB8F9999886B6B888888888F889900BB99",
INIT_5A => X"990B880B887777990B770077007788880999997D88777D888F998F77BB888F88",
INIT_5B => X"BB8FDDBBBB8FDD88DDBBDDDD88DDBB8F888F88BB888888BB8FBBBB887D990899",
INIT_5C => X"8F997D99887D8F88888F888FBB886B7D889999888899889988BB8F8F88DDBB88",
INIT_5D => X"99BBBB88DD8FBBBBBBBB8F88BB8F888FBBDDDD8FDDDDBB8FBB888F8F88BB8F8F",
INIT_5E => X"9999888F0F886B99BB9988BB99888899BB8F6B998F99999988886B886B886B88",
INIT_5F => X"88BBBBBBDDBBBB9988999999886B9988779977889999990B998899887788990B",
INIT_60 => X"886B99998899888F88BB6B997D88BB88BB886B99889988998F9988BB888888BB",
INIT_61 => X"998899BB777D99888F8F998899886B6B8F0B9988998899776B88770B77888877",
INIT_62 => X"008F8FBB88BB8FBB88888F88999977777D997D77996B6B8877999999886B0900",
INIT_63 => X"888F888888DDDD888F8F888F8F88888877888F88999999886B8888777D00D7F8",
INIT_64 => X"88550988770B09885509770B09777777889988998F7D99BB8888BB998899778F",
INIT_65 => X"DD88BBDDBBBB8FBBBB7D8888BBBB88BBBB888F88BBBBBB88888F889988888888",
INIT_66 => X"8888997D8899888F8899887D0B7788776B88888FBB6B887D998888888F8888BB",
INIT_67 => X"8888BBDDBBBB88DDBBBBBBDD88DD8FDD8FBBDDDD8899BBBB88DD8888BB8888BB",
INIT_68 => X"990B778F8FF88899779988999988887777999999999988597D77779988778877",
INIT_69 => X"BB77BBBB8888BB889999889988778F888F8F885988770B9977D7990B880B9977",
INIT_6A => X"886B88BB888F8F88BBBBBB88BB998FBB88998FBB8899998899999988889999BB",
INIT_6B => X"99770B77990B9977889977BB7D99777799776B889999990B0B88778877778877",
INIT_6C => X"0077099977777799777709770555777799770977D70777077777997777888F99",
INIT_6D => X"9988998FBB0B778899888F99999977889999998877887D998F7777779900D799",
INIT_6E => X"097755777755777777777D55556B777D770B776B77770B775577037777557777",
INIT_6F => X"BB88BBBB88888899BBBB8888888FBBBBBBBBDD8FBBBBBBBBBB99777777779977",
INIT_70 => X"BB888F8F88BB88998899990B8809777788888899778888779977778877888F88",
INIT_71 => X"DDBBBBDDBB88BBDD8F888FDDDDDDDDBBFFBBDD8FDDDDDDFFDDFFDDDDDDBBDD88",
INIT_72 => X"7788997788886B998888770B99098F88990099886B996B8888778877990B990B",
INIT_73 => X"997D8888BBDD8F77BB8F99889999887D88089999998877888899999977770B88",
INIT_74 => X"BBBBBBBBBBBBBBBBBB99888FBB88BB8F9988888899887D99887D888F8F887D77",
INIT_75 => X"7799770977D70777888F990B770B99990B9977770909887788990B9999886B88",
INIT_76 => X"1077770955775555556B555555097705470555550955556B0977050977095577",
INIT_77 => X"555577997777095577777799770909778F7777777777777777779977070099F8",
INIT_78 => X"556B555507550B770755097755556B4705996B475555777D7705596B55070B55",
INIT_79 => X"998F77889988888F77888FBB8F888FBB8F8F999999777777770777777777550B",
INIT_7A => X"88DDDDBBDD88888F8808098877778899880999990B880977990B997D990B88BB",
INIT_7B => X"DDBBDD88DDDD88DDBBBBDDDDDDDDDDFFDDFFDDDDDDDDDD88DDDD8888888FBBBB",
INIT_7C => X"999977997777778877999977889999990BBB9999889988999999778877777777",
INIT_7D => X"99999999998899889988998F99996B77779909770B9999777788888899887799",
INIT_7E => X"88BB88BBBBBB88BB88BBBBBB8F88BB888F888F8F889988999977997799BB99BB",
INIT_7F => X"05470555550955550955777799777777D707770777779999097777886B778899",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"1055037705557D5507470F336B746B770F77556B770977475509777405770977",
INIT_01 => X"090F77073309550555077707559555354755350555550955555509055500D799",
INIT_02 => X"475555596B777D4777777D556B595555740F5509776B5555557703556B55776B",
INIT_03 => X"88BBBBBB8F8F8888BBBB8899BBBB88BBBB99777799077759556B550905777777",
INIT_04 => X"BB887DDD88DDBBBB8888BBBB9908098877770809887777880988887777887799",
INIT_05 => X"88BBDDDDBBBBDDDDBBDD88BBDDFFDDBBBBBBDD88BB8899888899880B77778888",
INIT_06 => X"0B7788888899990B998899887788888899999999997799886B88889988778877",
INIT_07 => X"889988886B99998F779999889988778888999988776B889999B60999776B8877",
INIT_08 => X"BB8FDDBBBB8FDD8FBBBBBB8888BB8F8899998899990B998888998F8888777799",
INIT_09 => X"770F77556B77097777097755470555550977556B5577057777778847880D99BB",
INIT_0A => X"000755597707095577557709596B477755776B053377550555770F6B556B746B",
INIT_0B => X"777755597D556B475555770B0703556B550509554755770755055577050077F8",
INIT_0C => X"556B5955505955556B5577076B6B776B550505770F476B5547596B7759095547",
INIT_0D => X"770D888899889988BB8F888F7D88999977776B5547775547056B558F55555509",
INIT_0E => X"88998888DD88BB887D9988008877090B770B887D8888000B0809990B9988778F",
INIT_0F => X"DDBBDDBBDDBBDD88DDBBDDDDDDDDBBDDBB888899880B8877880B778800770977",
INIT_10 => X"8877997788888877998877996B8877000B7777990B99777D7788888899779977",
INIT_11 => X"99886B9988998F8899886B99996B7788887777889977990B9988777799777788",
INIT_12 => X"779999BBBBDDBB88BBBB8F88BB88BB88998F8F8F998F8899886B9988888F8877",
INIT_13 => X"55550F55556B0F05356B476B557705053395550555770F550947050955070909",
INIT_14 => X"1035070577550955330F77075950555505770F557D5555095555555500775505",
INIT_15 => X"0599950B55070555556B4755777755076B35773307557755093307073300BB99",
INIT_16 => X"77555555777D33555577595559555555090747556B55557747550F595509776B",
INIT_17 => X"770B000B08990B8888888F8877097707556B470F7777777D330F770555740755",
INIT_18 => X"887788880988880B778877098877880009770B7788770900778877097788880B",
INIT_19 => X"BBDDDD88BBBB8FDDDDDDBBDDDDBB880B880B8888770088777700098809887777",
INIT_1A => X"6B7788779999990B8899990B77990BDD99999988997799889977099988778877",
INIT_1B => X"6B9988996B997777889988998877888F00887709778899779909880788779977",
INIT_1C => X"09777799BB88BBBBBBBB88BB88BB8FBB889988889999990B998899B6888888BB",
INIT_1D => X"5505770F557D555577550547550F74556B7D056B6B0F5533470F550F77555505",
INIT_1E => X"007D3577057707558F555577470F550F7755550547779977550F7D0977075055",
INIT_1F => X"99556B7D5933470B7777056B070555475507033533055505550555330F00D7F8",
INIT_20 => X"0F557D0F55556B550D0B7D550555078F7755595535596B476B555059770F5533",
INIT_21 => X"0B888877000988990B887777556B777755777755550B77355555055509776B55",
INIT_22 => X"050B5507770B9988999988880B88090B880988990B88888F8809778800770899",
INIT_23 => X"BB88DDDDBBDDBBDD8FDDDD88990B777799880B99888F0B88770B885588770B00",
INIT_24 => X"7709778888778877997788999988888888996B77886B77998899880977777777",
INIT_25 => X"88776B998877998F779999779977D7889999779988778877889977997799770B",
INIT_26 => X"7705099977778888BBBB99BB998888998F888F998888998877990B77D7990B99",
INIT_27 => X"0F775555054777990750550F057705557D3355095555550F5555057409050977",
INIT_28 => X"00550509770999053305555555550574090509775305055555445555096B0F55",
INIT_29 => X"55053533475507477D095555359505330955550B33094755095507335501F899",
INIT_2A => X"770555555555596B5577555977075555555555550747556B0907555505555907",
INIT_2B => X"88990B000988770B8877550709555555050F770F776609056B55557777775305",
INIT_2C => X"080988778888880B777705007709995588770B77880500770999008809880009",
INIT_2D => X"BBDDBBBBDDDDDDBBDD88BB7788880B0B880B8877057777090055888809880077",
INIT_2E => X"7777887709997799999999880B09F877778F77886B88880B77097777880B880B",
INIT_2F => X"8FBB886B776B887799990B8899880D7788997788770B9999777D8F7788888877",
INIT_30 => X"0547740907096B8F998FBB88998FBB888899888877778F996B9999BB090D8877",
INIT_31 => X"550F5907740977556B0F55557755770547099977050F7D350905774777550744",
INIT_32 => X"00056B770533095555590507090577477755074409475533538F056B77055509",
INIT_33 => X"075595090709770955557705777709550574090777770555053347550F00D799",
INIT_34 => X"09556B0F474755555977075505596B050F55550F77550F476B77770F55777759",
INIT_35 => X"770B88097777007777440977476B7777779909555559775555555507550F7759",
INIT_36 => X"0988098809077777000B08990B888800770B77007708995588880B77770B0988",
INIT_37 => X"099988DDBB88DDBBBBBB090B077777887777770B08550B880B00770988098888",
INIT_38 => X"9909997777880B77776B77887709778899998F59990877998888558877887788",
INIT_39 => X"997D77999999887799889988998899559988887777770988777788770D88000B",
INIT_3A => X"74050755055577030D55554777997D6B888F99889977996B990B77887788776B",
INIT_3B => X"05555577950977070F550F530774050755050947055509770905770F55555305",
INIT_3C => X"100B050755050947055509770905770F555553050705097455000B7707555509",
INIT_3D => X"0555550F0577770F55595505770755090747350577774409055959550F00D799",
INIT_3E => X"550F055953556B475559550B0555098F070735056B0977097D47557755553309",
INIT_3F => X"07770955097777097777555577530F5555550555555555555577550555557755",
INIT_40 => X"770B0088077709880B8800778809887700090B770B0988070B88090707777709",
INIT_41 => X"887799099977886B7709000D770D998877770B88990B8888770B888807770988",
INIT_42 => X"77887788008F998899889999778899770B998899887D8F880999777709770977",
INIT_43 => X"7799996B77778F99889909990B997788779999880B887777880B058855779977",
INIT_44 => X"0955556B55778F9974550F7405557777778899999988998888998888887D8877",
INIT_45 => X"09550F3235095577555333550709557709745577090F5532094755550F535599",
INIT_46 => X"008F0F7709745577090F5532094755550F5355990755550933008F3377090755",
INIT_47 => X"05770977770974440905550F77747755553377093309057707475533770077F8",
INIT_48 => X"0555550F55336B6B55596B44597705557747094755775599035577556B054759",
INIT_49 => X"7709776B775555770D356B770F05330F7733770F330509355509033509770559",
INIT_4A => X"8877097788090955880777007755770977098888777777887777558877050977",
INIT_4B => X"057709770B5577770B77997777888805880B8809007709770077777788090955",
INIT_4C => X"0B7799779947779907779999997777887799BBBB997788888888990988778877",
INIT_4D => X"99990B5977998888999988777777888F097777777709777777D7880977777788",
INIT_4E => X"747D7755775577050747777D9909555555559909999999777799070977997799",
INIT_4F => X"550F33590F05053305337D0955747D0907557709553335590577050555330905",
INIT_50 => X"0055740907557709553335590577050555330905557D0F745500555509070F77",
INIT_51 => X"095507050F557D0977770955050709770F5305777755950F770533770500D799",
INIT_52 => X"09770777050F555509595555355509770905557705330F7755550B5959775359",
INIT_53 => X"55770D0F553303743577094777555505500D535577777705557D550905775347",
INIT_54 => X"0777770955777777777707070999097777777707777709557709995500777755",
INIT_55 => X"8888770977888809770B8800000B77880B770977770577770777090955777777",
INIT_56 => X"88770B990B0B0988770B889999880B7799889999888899997777097777777777",
INIT_57 => X"0999887799887D776B9999779988098888550B88777788090900997788770977",
INIT_58 => X"05230577095955557747775574777D530F740577777709777788998899099988",
INIT_59 => X"555533355555470977055977090523775509740F55338F355533477755057755",
INIT_5A => X"100953775509740F55338F355533477755057755092355055500090577554474",
INIT_5B => X"7707775555073555053307770B9577775507550509050595077709740900BB99",
INIT_5C => X"0577057774740F7777470977590F7709447455056B7433470F0777556B330777",
INIT_5D => X"03743577050F55740959950F7705550735550B59335507330F35075555090705",
INIT_5E => X"7705557705555507556B55777755775509555577050977050977550555445533",
INIT_5F => X"55770988770B07778888778F9988777777777799073303337709777705555507",
INIT_60 => X"997709888877998877887788090077099988BBBB888899880B8877770B770B77",
INIT_61 => X"99770B5588778F097799887799880B000B995588550B7709880B558877777777",
INIT_62 => X"777755050F5505774777476B7705550F533577776B7407093377770709B69988",
INIT_63 => X"550F3377095905770777550F0577776B05555309553333775955050733770F53",
INIT_64 => X"0077556B05555309553333775955050733770F5305770374550077056B050753",
INIT_65 => X"77336B55770F09550F55550777550B770509050F55550707590F35050501F899",
INIT_66 => X"095559555555055555555555550F5907770F334747770977337477740F770599",
INIT_67 => X"09777D550553440977770F5577550B0555098F070735056B0977097D47550533",
INIT_68 => X"55440F33076B5577594459033509336B6B55595555770555778F077735055509",
INIT_69 => X"090777990900558807880059997777557707770B0535055503743533076B5577",
INIT_6A => X"0B778899770B0B770B09779988BB99779999888FBBBB88779977997788778877",
INIT_6B => X"0B777777B60B7788990B99770B77778899777709555588550B77770B88777788",
INIT_6C => X"057755557777770D6B550F530555777435590705740F77775505557777078809",
INIT_6D => X"557459053377533355470533090577033355770755595505770353550F473355",
INIT_6E => X"000709033355770755595505770353550F473355097755097709075503330977",
INIT_6F => X"556B05775555770555093309590F745509770955557705330F53550B7700D799",
INIT_70 => X"77054755770F55770F556B0909557405555555474747740555590F095555556B",
INIT_71 => X"990903777707330577775533096B445977055577470947557755990355770955",
INIT_72 => X"0759770F6B55094759550F5509057753474477076B5959770555777D09470F77",
INIT_73 => X"9077880777998809770755F805770B6B05470944770533555574097705534409",
INIT_74 => X"8877770B09D7778877998899990B77770B77999988998F7788770B8877097709",
INIT_75 => X"55000909007788777777880B77887777090B77887777097755880B7755888877",
INIT_76 => X"7405050577050555530F7705550F550555550FB6077733050977555533770577",
INIT_77 => X"094435550705090953530F557774057747473333093507550547095333535505",
INIT_78 => X"1055777747473333093507550547095333535505770507775533550577474733",
INIT_79 => X"09555907335574550933057747500507775577070905590974550F77550099F8",
INIT_7A => X"33550F0D5505550F44553555773307775505055905470577554705740F550959",
INIT_7B => X"7707550B0555555577330305075555355509770905557705330F7755550B556B",
INIT_7C => X"05997774770F777D4777336B77596B5955097435550F35555577093355775533",
INIT_7D => X"0B097788770B55777777550955555559775577075533470F0707550977073305",
INIT_7E => X"770B0088777777779977996B77777788770999998F9988990B88777777887788",
INIT_7F => X"770777770977777700777788770777009955550977558807075588770B775509",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"55746B77550F05557D95775555550F6B550F770999500F777705553303070555",
INIT_01 => X"33095505555577550F5555090555740547074747335553055505770F47550977",
INIT_02 => X"100F590547074747335553055505770F475509770574230509550F4705473347",
INIT_03 => X"7705350F77050555070F5307470B35770509555559097774595505054700D799",
INIT_04 => X"0F5555550F74077709050F770333550905350977096B4733556B6B05770F7733",
INIT_05 => X"47550F775505330955537755550977590F7709447455056B7433470F07770547",
INIT_06 => X"55550F55555555337D0F55554759550F557D74090933590F5509440F55050F74",
INIT_07 => X"9988000955770577056B55550F055505556B0577050555055533075505555555",
INIT_08 => X"77777709008809777788778855777777880B7777888809558855880955775577",
INIT_09 => X"6B77055555355555090777555509770009338855070055887707007755090777",
INIT_0A => X"05555577777709070707770755474755559909050753770777050B955507550F",
INIT_0B => X"0977055507050709553355776B05555509555507090505550555075505337705",
INIT_0C => X"00075555095555070905055505550755053377056B5555055505070555093355",
INIT_0D => X"0935740F5533093547055533070955334409550F09557707550577447700D799",
INIT_0E => X"055533550F593347550F055505770709054709550955057747050F7709555505",
INIT_0F => X"770F33775555553355335577555555550F5907770F3347477709773374770555",
INIT_10 => X"476B550F47550F555509770D337D4755057433075547550F5507775533473377",
INIT_11 => X"07097777550509550F0355775505550935445547553333330733357477090F77",
INIT_12 => X"7707777799777788097709778899007777777709777777885509778877007700",
INIT_13 => X"553309320905555555770900558809777709557788077707007709770D888855",
INIT_14 => X"4755550F05555595777705950755473535337777770F530F059977050B956B55",
INIT_15 => X"7455070553773555070F470503475533070553097407770577093507470F0547",
INIT_16 => X"10740533070553097407770577093507470F0547035555090547740733070953",
INIT_17 => X"5509553355055533090F550F097777070555055544093533335509353300BB99",
INIT_18 => X"55774705555059050955550909553344770B7705550F55550F7D500777050555",
INIT_19 => X"0505550F5505050F55090755056B0909557405555555474747740555590F0977",
INIT_1A => X"0F550D05555544595555075509555547033505556B7709550705550555474747",
INIT_1B => X"777755597755747D77770B077777595505777709090507333355330555555533",
INIT_1C => X"558805090B770077557788778809990B88777788778807770B88557709770977",
INIT_1D => X"0F77777777030907335555590755550977770077075500777709003300090955",
INIT_1E => X"05094755320F0509537709777705770F77095507073359770955097753075505",
INIT_1F => X"0535334705050533555577555505095547770577053305470577055547555509",
INIT_20 => X"0005335547770577053305470577055547555509550905743305057755470705",
INIT_21 => X"0577550955090977075505550555057705474705555505550533070F0500D7F8",
INIT_22 => X"074755556B0F595507077707075505770705097705550577550509330F777705",
INIT_23 => X"777D55059977597D555577093335557733077755050559054705775547050777",
INIT_24 => X"55055574070709770577557755556B7733353335350777335577557705595547",
INIT_25 => X"55550B4759557755557774550755477755590F7455550533470D550B5505050F",
INIT_26 => X"07777790557777058807770077990077448809558877778855770B7777777777",
INIT_27 => X"5505327705773353550977353355055555557709550999000055770977888877",
INIT_28 => X"77530B0F055555777755077755550F5505770974550535477733550555557709",
INIT_29 => X"0955090907530935050533050977530933095555090977095323090577050555",
INIT_2A => X"0009550933095555090977095323090577050555095305330977090709335555",
INIT_2B => X"35550B550574770574770933053374093305057709097709350977557701F899",
INIT_2C => X"5947470B55337709770955777709770555775509553355090947445505550955",
INIT_2D => X"3307556B55595555070505778F0F770333550905350977096B4733556B6B0955",
INIT_2E => X"556B550F6B7755555509550F59553507330755330F550333050905470977776B",
INIT_2F => X"557747557705550F55556B6B7709550F556B77057733550F7707057705777755",
INIT_30 => X"09880577888809550B0477880955887700557777880077099977778855885588",
INIT_31 => X"7755550977055553555933095309775577555505335507335509775533078877",
INIT_32 => X"5574773305330533557755090553053333057733530555555553097707050577",
INIT_33 => X"55330907057777550505530F0555745309550977550933077705770555050F55",
INIT_34 => X"1077075309550977550933077705770555050F55057435050507770753090509",
INIT_35 => X"09779507550977057733097733330705095555050B09475505745577070099F8",
INIT_36 => X"77090F05777707057709740F555509550907300B057709770955777705770907",
INIT_37 => X"7705470F773377776B33050907055505770709054709550955057747050F0905",
INIT_38 => X"77057777550F6B55706B777D555577550F350705055505775509055509555555",
INIT_39 => X"07749959555574550F557707770F330509747777746B5377097707550F350705",
INIT_3A => X"5533777755058855007709557707330999000955090777550000095509550977",
INIT_3B => X"05330F7774090307557755777735335505090577090555033355075555555507",
INIT_3C => X"5505070977550505330977440F555307557403550F3309554735333355337733",
INIT_3D => X"07550709555509530F0977090F55057707554409070777095533090F53090933",
INIT_3E => X"1033337707554409070777095533090F530909330F0533557744330577075544",
INIT_3F => X"0955333533055533053347050F7077097703550977770507550B07097700D799",
INIT_40 => X"774455770309550977550777050977330F5533550944330F530F077409030F53",
INIT_41 => X"773347330F7074097707550955770577055555550F5555550974095505097755",
INIT_42 => X"0955333533055533053347050F70770977035509777705530955333533055533",
INIT_43 => X"0905555509770F55550B7455330977330F5533550944330F530F077409030F53",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_prim_width is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_mid_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_mid_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_mid_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => \douta[0]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
\douta[3]\(3 downto 0) => \douta[3]\(3 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[1]\(0) => \douta[1]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[2]\(0) => \douta[2]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[3]\(0) => \douta[3]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized4\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized5\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized6\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized7\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized8\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_mid_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_mid_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_douta : STD_LOGIC;
signal ram_ena_n_0 : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.bg_mid_bindec
port map (
addra(2 downto 0) => addra(14 downto 12),
ena_array(4 downto 0) => ena_array(4 downto 0)
);
\has_mux_a.A\: entity work.bg_mid_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\(0) => ram_douta,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\(0) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\(0) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[8].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_7\,
DOADO(7) => \ramloop[9].ram.r_n_0\,
DOADO(6) => \ramloop[9].ram.r_n_1\,
DOADO(5) => \ramloop[9].ram.r_n_2\,
DOADO(4) => \ramloop[9].ram.r_n_3\,
DOADO(3) => \ramloop[9].ram.r_n_4\,
DOADO(2) => \ramloop[9].ram.r_n_5\,
DOADO(1) => \ramloop[9].ram.r_n_6\,
DOADO(0) => \ramloop[9].ram.r_n_7\,
addra(2 downto 0) => addra(14 downto 12),
clka => clka,
douta(11 downto 0) => douta(11 downto 0)
);
ram_ena: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addra(14),
O => ram_ena_n_0
);
\ramloop[0].ram.r\: entity work.bg_mid_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => ram_douta,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
\douta[3]\(3) => \ramloop[1].ram.r_n_0\,
\douta[3]\(2) => \ramloop[1].ram.r_n_1\,
\douta[3]\(1) => \ramloop[1].ram.r_n_2\,
\douta[3]\(0) => \ramloop[1].ram.r_n_3\,
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(1),
\douta[1]\(0) => \ramloop[2].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(2),
\douta[2]\(0) => \ramloop[3].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(3),
\douta[3]\(0) => \ramloop[4].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[5].ram.r_n_0\,
\douta[11]\(6) => \ramloop[5].ram.r_n_1\,
\douta[11]\(5) => \ramloop[5].ram.r_n_2\,
\douta[11]\(4) => \ramloop[5].ram.r_n_3\,
\douta[11]\(3) => \ramloop[5].ram.r_n_4\,
\douta[11]\(2) => \ramloop[5].ram.r_n_5\,
\douta[11]\(1) => \ramloop[5].ram.r_n_6\,
\douta[11]\(0) => \ramloop[5].ram.r_n_7\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[6].ram.r_n_0\,
\douta[11]\(6) => \ramloop[6].ram.r_n_1\,
\douta[11]\(5) => \ramloop[6].ram.r_n_2\,
\douta[11]\(4) => \ramloop[6].ram.r_n_3\,
\douta[11]\(3) => \ramloop[6].ram.r_n_4\,
\douta[11]\(2) => \ramloop[6].ram.r_n_5\,
\douta[11]\(1) => \ramloop[6].ram.r_n_6\,
\douta[11]\(0) => \ramloop[6].ram.r_n_7\,
ena_array(0) => ena_array(1),
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[7].ram.r_n_0\,
\douta[11]\(6) => \ramloop[7].ram.r_n_1\,
\douta[11]\(5) => \ramloop[7].ram.r_n_2\,
\douta[11]\(4) => \ramloop[7].ram.r_n_3\,
\douta[11]\(3) => \ramloop[7].ram.r_n_4\,
\douta[11]\(2) => \ramloop[7].ram.r_n_5\,
\douta[11]\(1) => \ramloop[7].ram.r_n_6\,
\douta[11]\(0) => \ramloop[7].ram.r_n_7\,
ena_array(0) => ena_array(2),
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[8].ram.r_n_0\,
\douta[11]\(6) => \ramloop[8].ram.r_n_1\,
\douta[11]\(5) => \ramloop[8].ram.r_n_2\,
\douta[11]\(4) => \ramloop[8].ram.r_n_3\,
\douta[11]\(3) => \ramloop[8].ram.r_n_4\,
\douta[11]\(2) => \ramloop[8].ram.r_n_5\,
\douta[11]\(1) => \ramloop[8].ram.r_n_6\,
\douta[11]\(0) => \ramloop[8].ram.r_n_7\,
ena_array(0) => ena_array(3),
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized8\
port map (
DOADO(7) => \ramloop[9].ram.r_n_0\,
DOADO(6) => \ramloop[9].ram.r_n_1\,
DOADO(5) => \ramloop[9].ram.r_n_2\,
DOADO(4) => \ramloop[9].ram.r_n_3\,
DOADO(3) => \ramloop[9].ram.r_n_4\,
DOADO(2) => \ramloop[9].ram.r_n_5\,
DOADO(1) => \ramloop[9].ram.r_n_6\,
DOADO(0) => \ramloop[9].ram.r_n_7\,
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_mid_blk_mem_gen_top;
architecture STRUCTURE of bg_mid_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_mid_blk_mem_gen_generic_cstr
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_mid_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_mid_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_mid_blk_mem_gen_top
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_mid_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_mid_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_mid_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_mid_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_mid_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_mid_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 7.0707579999999997 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_mid_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_mid_blk_mem_gen_v8_3_5 : entity is "bg_mid.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_mid_blk_mem_gen_v8_3_5 : entity is "bg_mid.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_mid_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_mid_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_mid_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_mid_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_mid_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_mid_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_mid_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_mid_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_mid_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_mid_blk_mem_gen_v8_3_5_synth
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_mid : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_mid : entity is "bg_mid,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_mid : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_mid : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_mid;
architecture STRUCTURE of bg_mid is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "5";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 7.0707579999999997 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_mid.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_mid.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 18560;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 18560;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 18560;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 18560;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_mid_blk_mem_gen_v8_3_5
port map (
addra(14 downto 0) => addra(14 downto 0),
addrb(14 downto 0) => B"000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(14 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(14 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(14 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(14 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 09679f463cc501a776be06b306a3873d | 0.71798 | 2.993654 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/example_design/frame_buffer_prod.vhd | 1 | 10,299 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: frame_buffer_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 20000
-- C_READ_DEPTH_A : 20000
-- C_ADDRA_WIDTH : 15
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 20000
-- C_READ_DEPTH_B : 20000
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY frame_buffer_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END frame_buffer_prod;
ARCHITECTURE xilinx OF frame_buffer_prod IS
COMPONENT frame_buffer_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : frame_buffer_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit | cfe1b19940b8e7d3620399826e3970f8 | 0.493446 | 3.844345 | false | false | false | false |
mwswartwout/EECS318 | hw3/problem2/trafficLight.vhd | 1 | 1,922 | library ieee;
use ieee.std_logic_1164.all;
entity trafficLight is
port ( clock : in std_logic;
Sa : in std_logic;
Sb : in std_logic;
Ga : out std_logic;
Ya : out std_logic;
Ra : out std_logic;
Gb : out std_logic;
Yb : out std_logic;
Rb : out std_logic);
end trafficLight;
architecture trafficLight_arch of trafficLight is
type trafficLightState is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12);
type lightState is (green, yellow, red);
begin
process
variable currentState : trafficLightState := s0;
variable nextState : trafficLightState;
variable aLight, bLight : lightState;
procedure changeState is begin
case currentState is
when s0 => nextState := s1; aLight := green; bLight := red;
when s1 => nextState := s2;
when s2 => nextState := s3;
when s3 => nextState := s4;
when s4 => nextState := s5;
when s5 =>
if Sb = '1' then nextState := s6; aLight := yellow; end if;
when s6 => nextState := s7; aLight := red; bLight := green;
when s7 => nextState := s8;
when s8 => nextState := s9;
when s9 => nextState := s10;
when s10 => nextState := s11;
when s11 =>
if Sa = '1' and Sb = '0' then nextState := s12; bLight := yellow; end if;
when s12 => nextState := s0; aLight := green; bLight := yellow;
end case;
end procedure;
procedure changeLights is begin
case aLight is
when green => Ga <= '1'; Ya <= '0'; Ra <= '0';
when yellow => Ga <= '0'; Ya <= '1'; Ra <= '0';
when red => Ga <= '0'; Ya <= '0'; Ra <= '1';
end case;
case bLight is
when green => Gb <= '1'; Yb <= '0'; Rb <= '0';
when yellow => Gb <= '0'; Yb <= '1'; Rb <= '0';
when red => Gb <= '0'; Yb <= '0'; Rb <= '1';
end case;
end procedure;
begin
if (rising_edge(clock)) then changeState; currentState := nextState; changeLights; end if;
wait for 1 ns;
end process;
end trafficLight_arch;
| mit | c3de968b0bfbe49d363e32d4e68fd35b | 0.593132 | 2.885886 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev43.vhd | 1 | 26,797 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev43 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev43 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
signal tmpxx: std_logic_vector(19 downto 0);
signal tmpyy: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDMD2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
--constant LDIX : std_logic_vector(5 downto 0) := "000110";
--constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant STMD : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDMD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : std_logic_vector(31 downto 0);
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal dvect : WORD_VECTOR(0 to 7);
signal wout: std_logic_vector(63 downto 0);
signal lcount: std_logic_vector(31 downto 0);
signal scount: std_logic_vector(31 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2=LDMD) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when ((Opcode3=RETI or Opcode3=LDMD) and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3 = STMD) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when ((Opcode4=SYS or Opcode4=STMD) and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2=STM or Opcode2=STR or Opcode2=WPAD or Opcode2 = LDMD or Opcode2 = STMD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3=LDMD or Opcode3 = STMD) else
true when(Opcode4=SYS or Opcode4=RETI or Opcode4 = STMD) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= x"00000000";
lcount <= x"00000000";
scount <= x"00000000";
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
t1_val <= X"0000000000000000";
t2_val <= X"0000000000000000";
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM or Opcode2 = LDMD) then
MAR <= x"000" & M2;
tmpxx <= std_logic_vector((unsigned(M2) + 1));
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STMD) then
dvect(0) <= std_logic_vector(unsigned(wva) + unsigned(h0));
dvect(1) <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dvect(2) <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dvect(3) <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dvect(4) <= std_logic_vector(unsigned(wve) + unsigned(h4));
dvect(5) <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dvect(6) <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dvect(7) <= std_logic_vector(unsigned(wvh) + unsigned(h7));
MAR <= x"000" & M2;
MDR_out <= dvect(to_integer(unsigned(scount)))(63 downto 32);
tmpyy <= x"000" & std_logic_vector(unsigned(M2) + 1);
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if ((to_integer(unsigned(rcount)) > 0) and (to_integer(unsigned(rcount)) < 16)) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
end if;
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2 = LDMD) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR) then
null;
elsif(Opcode2=STMD) then
register_file(to_integer(unsigned(RX3))) <= MAR;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
rcount <= std_logic_vector((unsigned(rcount)+1));
if (to_integer(unsigned(rcount)) > 15) then
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=LDMD) then
mvect(to_integer(unsigned(lcount)))(63 downto 32) <= MDR_in;
MAR <= x"000" & tmpxx;
register_file(to_integer(unsigned(RX3))) <= std_logic_vector(lcount);
elsif (Opcode3=STM or Opcode3=STR) then
null;
elsif (Opcode3 = STMD) then
register_file(to_integer(unsigned(RY3))) <= tmpyy;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif(Opcode3 = LDMD) then
MDR_in <= MEM_in;
elsif(Opcode3 = STMD) then
MAR <= tmpyy;
MDR_out <= dvect(to_integer(unsigned(scount)))(31 downto 0);
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDMD) then
mvect(to_integer(unsigned(lcount)))(31 downto 0) <= MDR_in;
elsif (Opcode4 = STMD) then
null;
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
if (Opcode4 = LDMD) then
lcount <= std_logic_vector(unsigned(lcount)+1);
elsif (Opcode4 = STMD) then
if (to_integer(unsigned(scount)) = 7) then
scount <= x"00000000";
else
scount <= std_logic_vector(unsigned(scount) + 1);
end if;
end if;
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 79358d20102946ee4d9602f5fcc77941 | 0.611001 | 2.801568 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/title3/title3_sim_netlist.vhdl | 1 | 58,293 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:50 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title3/title3_sim_netlist.vhdl
-- Design : title3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title3_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end title3_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of title3_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000111000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000001110000000000000000000000000000000000000000",
INIT_04 => X"12E5000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"4E30000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000111100000000000000000000000000000000000000000001",
INIT_07 => X"00000000000000000000000000000000000000000001FFE54200000000000000",
INIT_08 => X"0000000000000000000000000000000000000000014FFD442000000000000000",
INIT_09 => X"00000000000000000000017FF7FFC2000021111000000244444444444316FF10",
INIT_0A => X"0000000000000019AAA11DFF5FFB100000000000000000111100000000000000",
INIT_0B => X"13FCBFF7200001EEE20000006FFFFFFFFFFFA27AF91000000000000000000000",
INIT_0C => X"3FADFF51000000000000000004ED111111000000000000000000000000000000",
INIT_0D => X"0006FFFFFFFFFFFF612DF91000000000000000000000000000000000013FFF11",
INIT_0E => X"00004DDFFFFF54444443100000000000000000000000112AFB1000001DFF4100",
INIT_0F => X"F64310000000000000000000000000000000014FFD1112CF8100000000000000",
INIT_10 => X"000000000000000000000000001FB00000002FFE1000001366666666665BFB2D",
INIT_11 => X"000000000000000004FFD10001851392100001110000000002888FFFFFFFFF61",
INIT_12 => X"000011FB11120002FFE11000001FFFFFFFFFFA18FB2BFFD30000000000000000",
INIT_13 => X"80000001EFD100012D700000000000016FFD4444310000000000000000000000",
INIT_14 => X"0000015FF444444FF428FDEFFB200000000000000000000000000000000029FF",
INIT_15 => X"000000000005FFC100000000000000000000000000000001BFFFFC444426FFB1",
INIT_16 => X"FFE22000000000000000000000000000000000008FF91000001FFF10009FF920",
INIT_17 => X"11100000000000000000000000068888AFFFF9BFFB10000003FF444444FF524B",
INIT_18 => X"00000001781000000005EFC2000018FF910005FFF31000011111103CFE411111",
INIT_19 => X"111100000002444CFFFFF40000002BFFFFFFFFFA9FA9FA110000000000000000",
INIT_1A => X"FF400001EFF300001EFFD110002DDDDDDDEFFEDDDDDDDB211111111111111111",
INIT_1B => X"50000000244444445FFFFF28FC1111111111111111111111117FF8100000001D",
INIT_1C => X"C10002EEEEEEEEFFEEEEEEEEBAFFFFFFFFFFFFFFFFFFFC200000000000122BFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF38FFF510000000CFF510001EFF3000002EFF",
INIT_1E => X"11112899999999999999999994000000000000001FFA1000002333333334FFFF",
INIT_1F => X"9999999828FFF710000002FFF10005EF810000003CFE4100011111111EFB2111",
INIT_20 => X"00000000000000000001FFF1000002BFFFFFFFFFFFFFAFFF9EF9999999999999",
INIT_21 => X"1FFF11008FF8000000009FFE310000000001EFF3100000000000000000000000",
INIT_22 => X"FF31000006FE8FFFF5FFE4429FF8441000000000000000000110149FF7110000",
INIT_23 => X"DFFF210000000012FFF100000000000000000000000000000000000000000013",
INIT_24 => X"ACFFFFFF31000000000000000000000002CFFF3100014FFD1008FF8000000002",
INIT_25 => X"0000000000000000000000000000000000000000003FFE1000006FE7FE8FFFFF",
INIT_26 => X"00000000000001ACFE720004FFD1008FF80000000002BFFE41000000002BFF61",
INIT_27 => X"00000000000000000000028FE1000001CFDEFFFFFFFFFFDEFFFE100000000000",
INIT_28 => X"712AFF7008FF800000000002BFFE31000000002BFF6100000000000000000000",
INIT_29 => X"06FFA100000CFFFFFFFFFFFFFACFFFF8000000000000000000000000003EFFDC",
INIT_2A => X"0002DFFF21000000002EFF310000000000000000000000000000000000000000",
INIT_2B => X"FFFE2CFFFFA20000000000000000000000000024FFFFFFFFF9008FF800000000",
INIT_2C => X"FF5110000000000000000000000000000166666666669FFB1000002FF5FFFFFF",
INIT_2D => X"000000000000000000119ADFFFFFB206A910000000000002BFB91000000001AC",
INIT_2E => X"0000000000001FFFFFFFFFFFFFB1000001FF5FFCFCDFEEFC3FFFFF4000000000",
INIT_2F => X"0355AFFA20011000000000000002521000000000002BFFC21000000000000000",
INIT_30 => X"22222220000016FD6FDFFFFA4FFCFFF6F4000000000000000000000000000000",
INIT_31 => X"00000000000000000000002EFFE1000000000000000000000000000122222222",
INIT_32 => X"6FF44F54FFD22000000000000000000000000000000000022220000000000000",
INIT_33 => X"0014B2100000000000000000000000000000000000000000000000003FF3FFFF",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000016FFEB2BBBB41113FFE1000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000003664000002000026651000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title3_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title3_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title3_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \title3_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_01 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_02 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_03 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_04 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_05 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0101014F4F4F4F4F4F4F",
INIT_06 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_07 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0101014F4F4F4F4F4F4F4F",
INIT_08 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_09 => X"01020E05004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0A => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0B => X"040E03004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0C => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F01",
INIT_0D => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F010101014F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0E => X"4F4F4F4F4F4F4F4F4F4F4F010F0F0E0504024F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0F => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_10 => X"4F4F4F4F4F4F4F4F4F01040F0F0D0404024F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_11 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_12 => X"4F4F02010101014F4F4F4F4F4F0204040404040404040404040301060F0F014F",
INIT_13 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F01070F0F070F0F0C024F4F",
INIT_14 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F010101014F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_15 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F01090A0A0A01010D0F0F050F0F0B014F4F4F",
INIT_16 => X"0F0F0F0F0A02070A0F09014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_17 => X"01030F0C0B0F0F07024F4F4F4F010E0E0E024F4F4F4F4F4F060F0F0F0F0F0F0F",
INIT_18 => X"01014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_19 => X"030F0A0D0F0F05014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F040E0D01010101",
INIT_1A => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F01030F0F0F0101",
INIT_1B => X"4F4F00060F0F0F0F0F0F0F0F0F0F0F0F0601020D0F09014F4F4F4F4F4F4F4F4F",
INIT_1C => X"4F4F4F4F4F4F4F4F4F4F4F000101020A0F0B014F4F4F4F4F010D0F0F04014F4F",
INIT_1D => X"4F4F4F4F040D0D0F0F0F0F0F0504040404040403014F4F4F4F4F4F4F4F4F4F4F",
INIT_1E => X"4F4F4F4F0001040F0F0D010101020C0F08014F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_1F => X"0F060403014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_20 => X"4F4F0000020F0F0E014F4F4F4F00010306060606060606060606050B0F0B020D",
INIT_21 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F004F00010F0B4F4F4F",
INIT_22 => X"014F4F4F4F0101014F4F4F4F4F4F000000020808080F0F0F0F0F0F0F0F0F0601",
INIT_23 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00040F0F0D01004F0001080501030902",
INIT_24 => X"0F0F0F0F0F0A01080F0B020B0F0F0D034F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_25 => X"4F4F4F4F01010F0B010101024F4F00020F0F0E01014F4F4F0000010F0F0F0F0F",
INIT_26 => X"060F0F0D0404040403014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_27 => X"084F4F00000000010E0F0D014F4F4F01020D074F4F4F4F4F4F4F4F0000000001",
INIT_28 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0002090F0F",
INIT_29 => X"4F4F4F4F0001050F0F0404040404040F0F0402080F0D0E0F0F0B024F4F4F4F4F",
INIT_2A => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F010B0F0F0F0F0C0404040402060F0F0B01",
INIT_2B => X"4F4F4F4F4F4F4F4F4F0000050F0F0C010000004F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_2C => X"4F4F4F4F4F4F0000080F0F09014F4F4F0000010F0F0F014F4F4F090F0F09024F",
INIT_2D => X"0F0F0E02024F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_2E => X"0A0F0F0F0F090B0F0F0B014F4F4F4F0000030F0F0404040404040F0F0502040B",
INIT_2F => X"0101014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000608080808",
INIT_30 => X"09014F4F00050F0F0F03014F4F4F4F01010101010100030C0F0E040101010101",
INIT_31 => X"4F4F4F4F4F4F4F010708014F4F4F4F4F4F4F00050E0F0C024F4F4F0001080F0F",
INIT_32 => X"0F0F0F0F0F0F0F0A090F0A090F0A01014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_33 => X"010101014F000000000000020404040C0F0F0F0F0F044F4F4F4F4F00020B0F0F",
INIT_34 => X"0D0D0E0F0F0E0D0D0D0D0D0D0D0B020101010101010101010101010101010101",
INIT_35 => X"0F0F044F4F4F4F010E0F0F034F4F4F00010E0F0F0D01014F4F4F020D0D0D0D0D",
INIT_36 => X"010101010101010101010101010101010101070F0F08014F4F4F4F4F4F00010D",
INIT_37 => X"05004F4F4F4F00000204040404040404050F0F0F0F0F02080F0C010101010101",
INIT_38 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0C024F4F4F4F4F4F00000000000102020B0F0F",
INIT_39 => X"0C014F4F4F020E0E0E0E0E0E0E0E0F0F0E0E0E0E0E0E0E0E0B0A0F0F0F0F0F0F",
INIT_3A => X"0F05014F4F4F4F4F4F000C0F0F05014F4F4F010E0F0F034F4F4F4F00020E0F0F",
INIT_3B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F03080F0F",
INIT_3C => X"4F4F4F4F00000000010F0F0A014F4F4F4F4F020303030303030303040F0F0F0F",
INIT_3D => X"01010101020809090909090909090909090909090909090909044F4F4F4F4F4F",
INIT_3E => X"08014F4F4F4F0000030C0F0E04014F000001010101010101010E0F0B02010101",
INIT_3F => X"090909090909090802080F0F0F07014F4F4F4F4F00020F0F0F014F4F4F050E0F",
INIT_40 => X"0F0F0F0F0F0F0F0F0F0F0F0F0A0F0F0F090E0F09090909090909090909090909",
INIT_41 => X"0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00010F0F0F014F4F4F4F4F020B0F",
INIT_42 => X"4F4F00010E0F0F03014F4F4F4F4F000000000000000000000000000000000000",
INIT_43 => X"010F0F0F01014F4F080F0F084F4F4F4F4F4F0000090F0F0E03014F4F4F4F4F4F",
INIT_44 => X"00000000000000000000000000000000000101000104090F0F0701014F4F4F00",
INIT_45 => X"0F0F03014F4F4F0000060F0E080F0F0F0F050F0F0E040402090F0F0804040100",
INIT_46 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000103",
INIT_47 => X"0D0F0F0F02014F4F4F4F4F4F4F4F01020F0F0F014F4F4F4F4F4F4F4F4F4F4F4F",
INIT_48 => X"00020C0F0F0F03014F000001040F0F0D014F00080F0F084F4F4F4F4F4F4F0002",
INIT_49 => X"0A0C0F0F0F0F0F0F03014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000",
INIT_4A => X"4F4F4F4F4F4F4F4F4F00030F0F0E014F4F4F4F00060F0E070F0E080F0F0F0F0F",
INIT_4B => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_4C => X"0F084F4F4F4F4F4F4F0000020B0F0F0E04014F4F4F4F4F4F4F00020B0F0F0601",
INIT_4D => X"4F4F4F4F4F4F4F4F4F4F4F0000010A0C0F0E0702000000040F0F0D014F00080F",
INIT_4E => X"0C0F0D0E0F0F0F0F0F0F0F0F0F0F0D0E0F0F0F0E014F4F4F4F4F4F4F4F4F4F4F",
INIT_4F => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0002080F0E014F4F4F4F0001",
INIT_50 => X"4F4F4F4F0000020B0F0F06014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_51 => X"0701020A0F0F074F00080F0F084F4F4F4F4F4F4F4F0000020B0F0F0E03014F4F",
INIT_52 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000030E0F0F0D0C",
INIT_53 => X"00060F0F0A014F4F4F00000C0F0F0F0F0F0F0F0F0F0F0F0F0F0A0C0F0F0F0F08",
INIT_54 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00",
INIT_55 => X"4F0000020D0F0F0F02014F4F4F4F4F4F0000020E0F0F03014F4F4F4F4F4F4F4F",
INIT_56 => X"4F4F4F4F000002040F0F0F0F0F0F0F0F0F094F00080F0F084F4F4F4F4F4F4F4F",
INIT_57 => X"0F0F0F0E020C0F0F0F0F0A02004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_58 => X"4F0106060606060606060606090F0F0B014F4F4F4F00020F0F050F0F0F0F0F0F",
INIT_59 => X"0F0F0501014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_5A => X"0A09014F4F4F4F4F4F4F4F4F4F0000020B0F0B09014F4F4F4F4F4F0000010A0C",
INIT_5B => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000101090A0D0F0F0F0F0F0B020006",
INIT_5C => X"00010F0F050F0F0C0F0C0D0F0E0E0F0C030F0F0F0F0F04004F4F4F4F4F4F4F4F",
INIT_5D => X"4F4F4F4F4F4F4F4F4F4F4F4F010F0F0F0F0F0F0F0F0F0F0F0F0F0B014F4F4F4F",
INIT_5E => X"4F4F4F4F4F4F4F000000020B0F0F0C02014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_5F => X"000305050A0F0F0A02000001014F4F4F4F4F4F4F4F4F4F4F4F0000020502014F",
INIT_60 => X"0F044F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000000",
INIT_61 => X"020202020202024F4F4F4F0001060F0D060F0D0F0F0F0F0A040F0F0C0F0F0F06",
INIT_62 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00010202020202020202",
INIT_63 => X"4F4F4F4F4F00004F4F4F4F4F4F4F4F4F4F4F4F4F0000020E0F0F0E014F4F4F4F",
INIT_64 => X"4F4F4F4F4F4F4F4F4F4F4F00000000020202024F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_65 => X"060F0F04040F05040F0F0D02024F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_66 => X"4F4F000000000000000000000000004F4F4F4F4F4F4F0000030F0F030F0F0F0F",
INIT_67 => X"000001040B02014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_68 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_69 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000004F4F4F4F",
INIT_6A => X"4F4F0001060F0F0E0B020B0B0B0B04010101030F0F0E014F4F4F4F4F4F4F4F4F",
INIT_6B => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_6C => X"4F4F4F4F4F4F4F4F4F4F4F4F0000000000334F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_6D => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_6E => X"05014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_6F => X"4F4F4F4F4F4F4F4F4F4F4F4F4F00000306060400000000000200004F00020606",
INIT_70 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_71 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F2011004F4F4F4F",
INIT_72 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_73 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_74 => X"000000000000000000000000000000000000004F4F4F4F4F4F0000004F4F4F4F",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title3_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end title3_blk_mem_gen_prim_width;
architecture STRUCTURE of title3_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.title3_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title3_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title3_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \title3_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \title3_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\title3_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title3_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end title3_blk_mem_gen_generic_cstr;
architecture STRUCTURE of title3_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.title3_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\title3_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
douta(7 downto 0) => douta(11 downto 4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title3_blk_mem_gen_top : entity is "blk_mem_gen_top";
end title3_blk_mem_gen_top;
architecture STRUCTURE of title3_blk_mem_gen_top is
begin
\valid.cstr\: entity work.title3_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title3_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end title3_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of title3_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.title3_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of title3_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of title3_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of title3_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of title3_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of title3_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of title3_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of title3_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of title3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of title3_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of title3_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of title3_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of title3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of title3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of title3_blk_mem_gen_v8_3_5 : entity is "title3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of title3_blk_mem_gen_v8_3_5 : entity is "title3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of title3_blk_mem_gen_v8_3_5 : entity is 3725;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of title3_blk_mem_gen_v8_3_5 : entity is 3725;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of title3_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of title3_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of title3_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of title3_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of title3_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of title3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of title3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of title3_blk_mem_gen_v8_3_5 : entity is 3725;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of title3_blk_mem_gen_v8_3_5 : entity is 3725;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of title3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of title3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of title3_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of title3_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of title3_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title3_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of title3_blk_mem_gen_v8_3_5 : entity is "yes";
end title3_blk_mem_gen_v8_3_5;
architecture STRUCTURE of title3_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.title3_blk_mem_gen_v8_3_5_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title3 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of title3 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of title3 : entity is "title3,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of title3 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of title3 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end title3;
architecture STRUCTURE of title3 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "title3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "title3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 3725;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 3725;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 3725;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 3725;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.title3_blk_mem_gen_v8_3_5
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => B"000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 8ef7cc0db94aad2920b5a53289af3ef6 | 0.711663 | 2.709286 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/IO/gpio.vhd | 1 | 1,168 | library ieee;
use ieee.std_logic_1164.all;
entity gpio is
port( clk : in std_logic;
rst : in std_logic;
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
wr : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(7 downto 0);
HEX0, HEX1, HEX2, HEX3: out std_logic_vector(6 downto 0)
);
end;
architecture gpio of gpio is
signal outport : std_logic_vector(31 downto 0);
signal disp : std_logic_vector(15 downto 0);
begin
display3: entity work.sevenseg port map (disp(15 downto 12), hex3);
display2: entity work.sevenseg port map (disp(11 downto 8), hex2);
display1: entity work.sevenseg port map (disp(7 downto 4), hex1);
display0: entity work.sevenseg port map (disp(3 downto 0), hex0);
disp <= outport(15 downto 0) when key(3)='1' else outport(31 downto 16);
process(clk, rst) is
begin
if(rst = '1') then
outport <= (others => '0');
elsif(clk'event and clk = '1') then
if(wr='1') then
outport <= gpio_in;
end if;
gpio_out <= X"000000" & SW;
end if;
end process;
end gpio;
| gpl-3.0 | 2354ef80fa9eba29578f2bddac650d20 | 0.623288 | 2.869779 | false | false | false | false |
huukit/logicsynth | excercises/vhd/audio_codec_model.vhd | 1 | 4,243 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 09
-- Project :
-------------------------------------------------------------------------------
-- File : audio_codec_model.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 14.1.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Ninth excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 14.1.2016 1.0 tuhu Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Define the entity.
entity audio_codec_model is
generic(
data_width_g : integer :=16
);
port(
rst_n : in std_logic;
aud_data_in : in std_logic;
aud_bclk_in : in std_logic;
aud_lrclk_in : in std_logic;
value_left_out : out std_logic_vector(data_width_g - 1 downto 0);
value_right_out : out std_logic_vector(data_width_g - 1 downto 0)
);
end audio_codec_model;
architecture rtl of audio_codec_model is
-- State definitions for internal codec.
type state_type is (wait_for_input, read_left, read_right);
signal present_state_r : state_type;
signal bit_counter_r : integer; -- Number of bits to count per sample.
signal input_buffer_r : std_logic_vector(data_width_g - 1 downto 0); -- Input buffer for incoming bits.
signal input_buffer_l_r : std_logic_vector(data_width_g - 1 downto 0); -- Input buffer for left channel.
signal input_buffer_r_r : std_logic_vector(data_width_g - 1 downto 0); -- Input buffer for right channel.
begin --rtl
-- Assing output registers to outputs.
value_left_out <= input_buffer_l_r;
value_right_out <= input_buffer_r_r;
handle_input : process (aud_bclk_in, rst_n)
begin
if(rst_n = '0') then -- Reset state and output registers.
present_state_r <= wait_for_input;
bit_counter_r <= (data_width_g - 1);
input_buffer_l_r <= (others => '0');
input_buffer_r_r <= (others => '0');
elsif(aud_bclk_in'event and aud_bclk_in = '1') then -- Read input on bclk rising edge.
case present_state_r is -- Handle init and other states.
when wait_for_input => -- First input data, look for direction.
input_buffer_r(bit_counter_r) <= aud_data_in;
if(aud_lrclk_in = '0') then
present_state_r <= read_right;
else
present_state_r <= read_left;
end if;
bit_counter_r <= bit_counter_r - 1;
when read_right => -- Read right channel data.
if(bit_counter_r = 0) then -- Reset counter and change channel if we have all data.
input_buffer_r_r(bit_counter_r) <= aud_data_in;
input_buffer_r_r(data_width_g - 1 downto 1) <= input_buffer_r(data_width_g - 1 downto 1);
-- Note: Is the above line ok? Same for the left channel.
bit_counter_r <= (data_width_g - 1);
present_state_r <= read_left;
else
input_buffer_r(bit_counter_r) <= aud_data_in;
bit_counter_r <= bit_counter_r - 1;
end if;
when read_left => -- Read left channel data.
if(bit_counter_r = 0) then -- Reset counter and change channel if we have all data.
input_buffer_l_r(bit_counter_r) <= aud_data_in;
input_buffer_l_r(data_width_g - 1 downto 1) <= input_buffer_r(data_width_g - 1 downto 1);
bit_counter_r <= (data_width_g - 1);
present_state_r <= read_right;
else
input_buffer_r(bit_counter_r) <= aud_data_in;
bit_counter_r <= bit_counter_r - 1;
end if;
end case;
end if;
end process handle_input;
end rtl; | gpl-2.0 | c28da53381f57f5d9dfbb0a119559f2f | 0.502003 | 3.839819 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_crc16.vhd | 1 | 2,750 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 5187b6352040d00d105068b0777a83fe | 0.548727 | 2.712032 | false | false | false | false |
db-electronics/FMPBC | PBCFM.vhd | 1 | 8,898 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2014 - 2017 René Richard
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library altera;
use altera.altera_primitives_components.all;
entity PBCFM is
generic(
-- 0 = no init code, fm always enabled
-- 1 = regular PBC init code, fm always enabled
-- 2 = db PBC init code, fm can be disabled by holding up during boot
mode_g : integer := 1;
-- amount of time to wait to enable sound output
senCount_g : integer := 256
);
port (
--Z80 control signals (from md obviously)
CLK_p : in std_logic;
nRST_p : in std_logic;
nWR_p : in std_logic;
nRD_p : in std_logic;
nIORQ_p : in std_logic;
nCRTOE_p : in std_logic;
nCART_p : out std_logic;
nRSTG_p : out std_logic;
nRSTS_p : out std_logic;
--non z80 signals
HSCLK_p : in std_logic;
FMEN_p : in std_logic;
--YM2413 control signals
SEN_p : out std_logic;
nYMCS_p : out std_logic;
nYMIC_p : out std_logic;
--address and databus
ADDR_p : in std_logic_vector(7 downto 0);
DATA_p : inout std_logic_vector(7 downto 0)
);
end entity;
architecture PBCFM_a of PBCFM is
--ym2413 signals
signal nkbsel_s : std_logic;
signal nfmcs_s : std_logic;
signal nbitcs_s : std_logic;
--detect bit for Z80 software
signal bitq_s : std_logic;
--internal ym2413 enable signal, disabled by db boot code if up is held on power up
signal enym_s : std_logic;
--internal signal to detect when the boot code disables the ym2413
signal disableym_s : std_logic;
--internal databus signals
signal datain_s : std_logic_vector(7 downto 0);
signal dataout_s : std_logic_vector(7 downto 0);
--signal which enables the stack code to be driven onto the databus
signal doBoot_s : std_logic;
--signal which resets the doBoot flipflop
signal rstStack_s : std_logic;
signal endStack_s : std_logic;
-- Power Base Converter stack init code
-- source http://www.smspower.org/forums/viewtopic.php?t=14084
--21 01 E1 : LD HL, $E101
--25 -- -- : DEC H
--F9 -- -- : LD SP,HL
--C7 -- -- : RST $00
--01 01 -- : LD BC, $xx01
-- Array containing boot ROM of orignal PBC
type PBCROM_t is array (0 to 7) of std_logic_vector(7 downto 0);
constant PCBBootROM : PBCROM_t :=
(x"21",x"01",x"e1",x"25",x"f9",x"c7",x"01",x"01");
-- Array containing ROM of db PBCFM init code
--;*************************************************************
--; Boot section
--;*************************************************************
-- ld sp, $e001 ; setup stack pointer to point to DFFF after reset
-- ld b, $00 ; clear b as iteration counter = 256
---: in a,(IOPortA) ; read joypad
-- bit 0,a ; check if up is pressed
-- jr nz,+ ; if 1, reset and leave FM sound enabled
-- djnz - ; must read 256 times as 0 to disable FM sound
-- nop ; nop, hardware will disable the FM chip if this opcode is read
--+: rst $00 ; reset, nWR signal will disable this small BIOS and enable the game to boot
type dbROM_t is array (0 to 15) of std_logic_vector(7 downto 0);
constant dbBootROM : dbROM_t :=
(x"31",x"01",x"e0",x"06",x"00",x"db",x"dc",x"cb",
x"4f",x"20",x"03",x"10",x"f8",x"00",x"c7",x"00");
-- type dbROM_t is array (0 to 24) of std_logic_vector(7 downto 0);
-- constant dbBootROM : dbROM_t :=
-- (x"f3",x"3e",x"f5",x"d3",x"3f",x"06",x"00",x"e3",
-- x"10",x"fd",x"31",x"01",x"e0",x"06",x"00",x"db",
-- x"dc",x"cb",x"47",x"20",x"03",x"10",x"f8",x"00",
-- x"c7");
--*************************************************************
--LOGIC BEGINS HERE
--*************************************************************
begin
--output to databus
--dataout_s driven by process in PBC Stack Init section
DATA_p <= dataout_s when doBoot_s = '1' and nRD_p = '0' and nCRTOE_p = '0' else --PBC bios code
"ZZZZZ" & "00" & bitq_s when (nbitcs_s = '0' and nRD_p = '0') else --FM detect bit
(others=>'Z');
--read in databus
datain_s <= DATA_p;
--reset signal from reset generator into HRST of Genesis
nRSTG_p <= nRST_p;
nRSTS_p <= nRST_p;
--*************** YM2413 SECTION ***************
--YM2413 signals
nYMIC_p <= nRST_p;
nYMCS_p <= nfmcs_s when nRST_p = '1' else '1';
--generate kbsel internally as it does not exist on MD
nkbsel_s <= '0' when nIORQ_p = '0' and
ADDR_p(7 downto 6)="11"
else '1';
--FM chip at address F0 and F1
nfmcs_s <= '0' when ADDR_p(2 downto 1)="00" and
nkbsel_s = '0' and
nWR_p = '0' and
enym_s = '1'
else '1';
--FM detect bit at address F2
--read bit cs generation
nbitcs_s <= '0' when ADDR_p(2 downto 1)="01" and
nkbsel_s = '0' and
enym_s = '1'
else '1';
-- Instantiate DFF for detect bit
fmcheckFF : DFF
port map (
d => datain_s(0),
clk => nbitcs_s or nWR_p, -- bnand for clarity
clrn => nRST_p,
prn => '1',
q => bitq_s
);
-- internal ym2413 enable signal, on by default, off when boot code disables it
-- by reading the NOP at address 0x0D of the db boot code
-- this only matters for mode_g = 2
disableym_s <= '1' when doBoot_s = '1' and
nCRTOE_p = '0' and
ADDR_p = x"0d"
else '0';
-- sample the pause button (FMEN_p) during reset, hold afterwards
process( nRST_p, FMEN_p)
begin
if nRST_p = '0' then
enym_s <= FMEN_p; -- on by default
else
enym_s <= enym_s;
end if;
end process;
-- after senCount_g amount of nIORQ_p's, enable sound output, not deterministic
-- but is the longest wait time possible with the least amount of macrocells used
process( nRST_p, doBoot_s, nIORQ_p, enym_s)
variable senCount_v : integer range 0 to senCount_g;
begin
if nRST_p = '0' then
SEN_p <= '0';
senCount_v := 0;
elsif doBoot_s = '1' or enym_s = '0' then
SEN_p <= '0';
elsif (rising_edge(nIORQ_p)) then
senCount_v := senCount_v + 1;
if senCount_v = senCount_g then
SEN_p <= '1';
end if;
end if;
end process;
--*************** PBC Stack Init Section ***************
--Cart output enable, don't gate the CRTOE_p if mode_g = 0
nCART_p <= nCRTOE_p when doBoot_s = '0' or mode_g = 0 else '1';
--DFF to determine when to drive stack code onto bus
--enables the doBoot_s at reset, stops it at the first nWR during stack write mode 1
--or after encountering RST opcode in mode 2
process( nRST_p, rstStack_s, doBoot_s)
begin
if nRST_p = '0' then
doBoot_s <= '1';
elsif rstStack_s = '1' then
doBoot_s <= '0';
else
doBoot_s <= doBoot_s;
end if;
end process;
--reset the doBoot flipflop
--original PBC resets on nWR_p during RST instruction
process( nRST_p, nWR_p, nCRTOE_p, endStack_s )
begin
if nRST_p = '0' then
rstStack_s <= '0';
else
case mode_g is
when 0 =>
rstStack_s <= not(nWR_p);
when 1 =>
rstStack_s <= not(nWR_p);
when 2 =>
rstStack_s <= endStack_s;
when others =>
rstStack_s <= '0';
end case;
end if;
end process;
--endStack_s only matters in mode_g = 2
process( nRST_p, nCRTOE_p, ADDR_p)
begin
if nRST_p = '0' then
endStack_s <= '0';
elsif (rising_edge(nCRTOE_p)) then
if ADDR_p = x"0e" then --read the reset instruction in BIOS
endStack_s <= '1';
end if;
end if;
end process;
--drive stack code (depends on mode_g)
process( nRST_p, ADDR_p, nRD_p, nCRTOE_p, doBoot_s)
begin
if nRST_p = '0' then
dataout_s <= (others=>'Z');
elsif doBoot_s = '1' then
if nRD_p = '0' and nCRTOE_p = '0' then
case mode_g is
when 0 =>
dataout_s <= (others=>'Z');
when 1 =>
dataout_s <= PCBBootROM(to_integer(unsigned(ADDR_p(2 downto 0))));
when 2 =>
dataout_s <= dbBootROM(to_integer(unsigned(ADDR_p(3 downto 0))));
when others =>
dataout_s <= (others=>'Z');
end case;
else
dataout_s <= (others=>'Z');
end if;
else
dataout_s <= (others=>'Z');
end if;
end process;
end PBCFM_a;
| gpl-3.0 | 5dabb6c5649b5a30f31e5c4a67cffa66 | 0.57851 | 2.831636 | false | false | false | false |
huukit/logicsynth | excercises/vhd/multi_port_adder.vhd | 1 | 3,718 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 04
-- Project :
-------------------------------------------------------------------------------
-- File : multi_port_adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 09.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fourth excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 09.11.2015 1.0 tuhu, nikulaj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity multi_port_adder is -- Multi port adder definition.
generic(
operand_width_g : integer := 16; -- Specify default value for both.
num_of_operands_g : integer := 4
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
operands_in : in std_logic_vector((operand_width_g * num_of_operands_g) - 1 downto 0); -- Operand inputs
sum_out : out std_logic_vector(operand_width_g - 1 downto 0) -- Calculation result.
);
end multi_port_adder;
architecture structural of multi_port_adder is -- Structural declaration utilizing the adder component.
component adder -- Declare component.
generic(
operand_width_g : integer
);
port( -- See component for definitions of signals.
clk : in std_logic;
rst_n : in std_logic;
a_in : in std_logic_vector(operand_width_g - 1 downto 0);
b_in : in std_logic_vector(operand_width_g - 1 downto 0);
sum_out : out std_logic_vector(operand_width_g downto 0)
);
end component;
type subtotal_arr is array (0 to (num_of_operands_g / 2) - 1) -- Declare new type for intermediate
of std_logic_vector(operand_width_g downto 0); -- result storage.
signal subtotal_r : subtotal_arr; -- Subtotals.
signal total_r : std_logic_vector(operand_width_g + 1 downto 0); -- Total addition.
begin -- structural
i_adder_1 : adder -- Adder instance 1
generic map(
operand_width_g => operand_width_g
)
port map(
clk => clk,
rst_n => rst_n,
a_in => operands_in((operand_width_g - 1) downto 0),
b_in => operands_in((operand_width_g * 2 - 1) downto operand_width_g),
sum_out => subtotal_r(0)
);
i_adder_2 : adder -- Adder instance 2
generic map(
operand_width_g => operand_width_g
)
port map(
clk => clk,
rst_n => rst_n,
a_in => operands_in((operand_width_g * 3 - 1) downto operand_width_g * 2),
b_in => operands_in((operand_width_g * 4 - 1) downto operand_width_g * 3),
sum_out => subtotal_r(1)
);
i_adder_3 : adder -- Adder instance 3
generic map(
operand_width_g => (operand_width_g + 1)
)
port map(
clk => clk,
rst_n => rst_n,
a_in => subtotal_r(0),
b_in => subtotal_r(1),
sum_out => total_r
);
sum_out <= total_r((operand_width_g - 1) downto 0); -- Assign total register to output, discarding msb.
assert (num_of_operands_g = 4) report -- Make sure the number of operands is 4.
"failure: num_of_operands_g is not 4" severity failure;
end structural;
| gpl-2.0 | 4e556e2486be74e7ea3b3fb133ed2c2c | 0.497848 | 3.864865 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/gcu_ic/ifetch.vhdl | 2 | 18,423 | -- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
use work.ffaccel_globals.all;
use work.ffaccel_gcu_opcodes.all;
use work.ffaccel_imem_mau.all;
use work.tce_util.all;
entity ffaccel_ifetch is
generic (
no_glock_loopback_g : std_logic := '0';
bypass_fetchblock_register : boolean := false;
bypass_pc_register : boolean := false;
bypass_decoder_registers : boolean := false;
extra_fetch_cycles : integer := 0;
sync_reset_g : boolean := false;
debug_logic_g : boolean := false;
enable_loop_buffer_g : boolean := false;
enable_infloop_buffer_g : boolean := false;
enable_irf_g : boolean := false;
irf_size_g : integer := 0;
pc_init_g : std_logic_vector(IMEMADDRWIDTH-1 downto 0) := (others => '0'));
port (
-- program counter in
pc_in : in std_logic_vector (IMEMADDRWIDTH-1 downto 0);
--return address out
ra_out : out std_logic_vector (IMEMADDRWIDTH-1 downto 0);
-- return address in
ra_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
-- ifetch control signals
pc_load : in std_logic;
ra_load : in std_logic;
pc_opcode : in std_logic_vector(0 downto 0);
--instruction memory interface
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_en_x : out std_logic;
fetchblock : out std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
busy : in std_logic;
-- global lock
glock : out std_logic;
-- external control interface
fetch_en : in std_logic; --fetch_enable
-- debugger signals
db_lockreq : in std_logic;
db_rstx : in std_logic;
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
db_cyclecnt : out std_logic_vector(64-1 downto 0);
db_lockcnt : out std_logic_vector(64-1 downto 0);
clk : in std_logic;
rstx : in std_logic);
end ffaccel_ifetch;
architecture rtl_andor of ffaccel_ifetch is
-- signals for program counter.
signal pc_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal pc_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal pc_prev_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal next_pc : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal increased_pc : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal return_addr_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
-- internal signals for initializing and locking execution.
signal lock : std_logic;
signal mem_en_lock_r : std_logic;
-- Delay/latency from retrieving instruction block from instruction memory.
constant IFETCH_DELAY : integer := 1 + extra_fetch_cycles;
-- Delay/latency from pc register to dispatching instruction.
constant PC_TO_DISPATCH_DELAY : integer :=
to_int(not bypass_fetchblock_register) +
IFETCH_DELAY;
-- Delay/latency from control flow operation to dispatching instruction.
constant NEXT_TO_DISPATCH_DELAY : integer :=
PC_TO_DISPATCH_DELAY + to_int(not bypass_pc_register);
signal reset_cntr : integer range 0 to IFETCH_DELAY;
signal reset_lock : std_logic;
-- Loopbuffer signals, or placeholders if lb is not enabled
-- Placeholder signals for loop buffer ports/constants
constant LBUFMAXITER : integer := 1;
constant LBUFMAXDEPTH : integer := 1;
constant IFE_LBUFS : integer := 1;
constant IFE_INFLOOP : integer := 1;
signal o1data : std_logic_vector(LBUFMAXITER-1 downto 0);
signal o1load : std_logic;
signal loop_start_out : std_logic;
signal loop_len_out : std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
signal loop_iter_out : std_logic_vector(LBUFMAXITER-1 downto 0);
signal iteration_count : std_logic_vector(LBUFMAXITER-1 downto 0);
signal pc_after_loop : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal lockcnt_r, cyclecnt_r : unsigned(64 - 1 downto 0);
signal db_pc_next : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
constant db_pc_start : std_logic_vector(IMEMADDRWIDTH-1 downto 0)
:= (others => '0');
begin
-- enable instruction memory.
imem_en_x <= '0' when (fetch_en = '1' and mem_en_lock_r = '0') else '1';
-- do not fetch new instruction when processor is locked.
imem_addr <= pc_wire;
-- propagate lock to global lock
glock <= busy or reset_lock or (not (fetch_en or no_glock_loopback_g));
ra_out <= return_addr_reg;
lock <= not fetch_en or busy or mem_en_lock_r;
pc_update_generate_0 : if not enable_irf_g generate
pc_update_proc : process (clk)
begin
if not sync_reset_g and rstx = '0' then
pc_reg <= pc_init_g;
pc_prev_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge.
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
pc_reg <= db_pc_start;
pc_prev_reg <= (others => '0');
elsif lock = '0' then
pc_reg <= next_pc;
if bypass_pc_register and bypass_fetchblock_register
and bypass_decoder_registers and pc_load = '1' then
pc_prev_reg <= pc_in;
else
pc_prev_reg <= pc_reg;
end if;
end if;
end if;
end process pc_update_proc;
end generate pc_update_generate_0;
-----------------------------------------------------------------------------
ra_block : block
signal ra_source : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
begin -- block ra_block
-- Default choice generate
ra_source_select_generate_0 : if not enable_irf_g and not bypass_pc_register generate
ra_source <= increased_pc;
end generate ra_source_select_generate_0;
-- Choice enabled by generic
ra_source_select_generate_1 : if not enable_irf_g and bypass_pc_register generate
ra_source <= pc_reg;
end generate ra_source_select_generate_1;
-- When using IRF
ra_source_select_generate_2 : if enable_irf_g generate
ra_source <= pc_prev_reg;
end generate ra_source_select_generate_2;
ra_update_proc : process (clk)
begin -- process ra_update_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
return_addr_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
return_addr_reg <= (others => '0');
elsif lock = '0' then
-- return address
if (ra_load = '1') then
return_addr_reg <= ra_in;
elsif (pc_load = '1' and unsigned(pc_opcode) = IFE_CALL) then
-- return address transformed to same form as all others addresses
-- provided as input
return_addr_reg <= ra_source;
end if;
end if;
end if;
end process ra_update_proc;
end block ra_block;
-----------------------------------------------------------------------------
-- Keeps memory enable inactive during reset
imem_lock_proc : process (clk)
begin
if not sync_reset_g and rstx = '0' then
mem_en_lock_r <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
mem_en_lock_r <= '1';
else
mem_en_lock_r <= '0';
end if;
end if;
end process imem_lock_proc;
-----------------------------------------------------------------------------
-- Default fetch implementation
fetch_block_registered_generate : if
not bypass_fetchblock_register generate
fetch_block : block
signal instruction_reg : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH*
(extra_fetch_cycles+1)-1 downto 0);
begin -- block fetch_block
fetch_block_proc : process (clk)
begin -- process fetch_block_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
instruction_reg <= (others => '0');
reset_cntr <= 0;
reset_lock <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
instruction_reg <= (others => '0');
reset_cntr <= 0;
reset_lock <= '1';
elsif lock = '0' then
if reset_cntr < IFETCH_DELAY then
reset_cntr <= reset_cntr + 1;
else
reset_lock <= '0';
end if;
if (extra_fetch_cycles > 0) then
instruction_reg(instruction_reg'length-fetchblock'length-1 downto 0)
<= instruction_reg(instruction_reg'length-1 downto fetchblock'length);
end if;
instruction_reg(instruction_reg'length-1
downto instruction_reg'length - fetchblock'length)
<= imem_data;
end if;
end if;
end process fetch_block_proc;
fetchblock <= instruction_reg(fetchblock'length-1 downto 0);
end block fetch_block;
end generate fetch_block_registered_generate;
-- Fetch implementation without fetch register.
fetch_block_bypassed_generate : if
not (not bypass_fetchblock_register) generate
fetch_block : block
begin -- block fetch_block
fetch_block_proc : process (clk)
begin -- process fetch_block_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
reset_lock <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
reset_lock <= '1';
elsif lock = '0' then
reset_lock <= '0';
end if;
end if;
end process fetch_block_proc;
fetchblock <= imem_data;
end block fetch_block;
end generate fetch_block_bypassed_generate;
-----------------------------------------------------------------------------
loopbuf_logic : if enable_loop_buffer_g generate
-- Loop buffer signals --
signal start_looping : std_logic;
signal start_looping_r : std_logic_vector(NEXT_TO_DISPATCH_DELAY-1
downto 0);
signal loop_length, loop_length_reg
: std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
signal loop_iter_reg : std_logic_vector(LBUFMAXITER-1 downto 0);
signal loop_iter_temp_reg : std_logic_vector(LBUFMAXITER-1 downto 0);
begin
assert not enable_irf_g
report "IRF is not supported with loop buffer!"
severity failure;
-- Loop buffer setup operation logic --
start_looping <= '1' when (pc_load = '1' and
unsigned(pc_opcode) = IFE_LBUFS) else
'0';
iteration_count <= o1data(LBUFMAXITER-1 downto 0)
when o1load = '1' else
loop_iter_temp_reg;
loop_length <= pc_in(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
process (clk)
begin
if not sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
loop_iter_reg <= (others => '0');
loop_iter_temp_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Loop buffer control --
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
loop_iter_reg <= (others => '0');
loop_iter_temp_reg <= (others => '0');
elsif lock = '0' then
if (start_looping = '1' and
unsigned(iteration_count) /= 0) then
loop_length_reg <= loop_length;
loop_iter_reg <= iteration_count;
start_looping_r(0) <= '1';
else
start_looping_r(0) <= '0';
end if;
if o1load = '1' then
loop_iter_temp_reg <= o1data(LBUFMAXITER-1 downto 0);
end if;
-- Delay slots for lbufs are introduced to avoid need of pipeline
-- flushing in case the loop is skipped with iteration count of zero.
start_looping_r(start_looping_r'left downto 1) <=
start_looping_r(start_looping_r'left-1 downto 0);
end if;
end if;
end process;
loop_start_out <= start_looping_r(start_looping_r'left);
loop_iter_out <= loop_iter_reg;
loop_len_out <= loop_length_reg;
pc_after_loop <= std_logic_vector(
unsigned(increased_pc) + unsigned(loop_length));
end generate;
infloop_logic : if enable_infloop_buffer_g generate
signal start_looping : std_logic;
signal start_looping_r
: std_logic_vector(NEXT_TO_DISPATCH_DELAY-1 downto 0);
signal loop_length, loop_length_reg
: std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
begin
-- infinity loop operation control logic --
start_looping <= '1' when (pc_load = '1' and
unsigned(pc_opcode) = IFE_INFLOOP) else
'0';
loop_length <= pc_in(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
process (clk)
begin
if not sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Loop buffer control --
if sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
elsif lock = '0' then
if (start_looping = '1' and to_uint(loop_length) /= 0) then
assert to_uint(loop_length) <= LBUFMAXDEPTH
report "The loop body size exceeds loop buffer capacity!"
severity failure;
loop_length_reg <= loop_length;
start_looping_r(0) <= '1';
else
start_looping_r(0) <= '0';
end if;
-- Delay slots for lbufs are introduced to avoid need of pipeline
-- flushing in case the loop is skipped with iteration count of
-- zero.
start_looping_r(start_looping_r'left downto 1) <=
start_looping_r(start_looping_r'left-1 downto 0);
end if;
end if;
end process;
loop_start_out <= start_looping_r(start_looping_r'left);
loop_len_out <= loop_length_reg;
end generate infloop_logic;
--------------------------------------------------------------------------------
default_pc_generate: if not bypass_pc_register generate
pc_wire <= pc_reg when (lock = '0') else pc_prev_reg;
-- increase program counter
increased_pc <= std_logic_vector(unsigned(pc_wire) + IMEMWIDTHINMAUS);
sel_next_pc : process (pc_load, pc_in, increased_pc, pc_opcode)
begin
if pc_load = '1' and (unsigned(pc_opcode) = IFE_CALL or unsigned(pc_opcode) = IFE_JUMP) then
next_pc <= pc_in;
else -- no branch
next_pc <= increased_pc;
end if;
end process sel_next_pc;
end generate default_pc_generate;
bypass_pc_register_generate: if bypass_pc_register generate
-- increase program counter
increased_pc <= std_logic_vector(unsigned(pc_wire) + IMEMWIDTHINMAUS);
sel_next_pc : process (pc_in, pc_reg, increased_pc ,
pc_load, pc_opcode)
begin
if pc_load = '1' and (unsigned(pc_opcode) = IFE_CALL or unsigned(pc_opcode) = IFE_JUMP) then
pc_wire <= pc_in;
next_pc <= increased_pc;
else -- no branch
pc_wire <= pc_reg;
next_pc <= increased_pc;
end if;
end process sel_next_pc;
end generate bypass_pc_register_generate;
-----------------------------------------------------------------------------
debug_counters : if debug_logic_g generate
-----------------------------------------------------------------------------
-- Debugger processes and signal assignments
-----------------------------------------------------------------------------
db_counters : process(clk)
begin
if not sync_reset_g and rstx = '0' then -- async reset (active low)
lockcnt_r <= (others => '0');
cyclecnt_r <= (others => '0');
elsif rising_edge(clk) then
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
lockcnt_r <= (others => '0');
cyclecnt_r <= (others => '0');
elsif db_lockreq = '0' then
if lock = '1' then
lockcnt_r <= lockcnt_r + 1;
else
cyclecnt_r <= cyclecnt_r + 1;
end if;
end if;
end if;
end process;
db_cyclecnt <= std_logic_vector(cyclecnt_r);
db_lockcnt <= std_logic_vector(lockcnt_r);
db_pc <= pc_reg;
db_pc_next <= next_pc;
end generate debug_counters;
end rtl_andor;
| mit | c3169956ebef895f0ade3d9307d58ddf | 0.576291 | 3.730107 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/rle.vhd | 13 | 7,423 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
| mit | 40bc49d5d805b70fafea98a7e7054921 | 0.590327 | 2.731052 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_timers.vhd | 1 | 6,104 | --
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
| mit | eafed5869b65f5eab0f80ba539696f8b | 0.611402 | 3.050475 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_intr.vhd | 1 | 10,645 | --
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 2ad974e5bd5d53bff590dc7b78e9f041 | 0.583091 | 3.796362 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_sim_netlist.vhdl | 1 | 84,107 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_sim_netlist.vhdl
-- Design : pikachu_down_pixel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
p_7_out : in STD_LOGIC_VECTOR ( 8 downto 0 );
ram_douta : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end pikachu_down_pixel_blk_mem_gen_mux;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(0),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(0),
O => douta(0)
);
\douta[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(1),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(1),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(2),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(2),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(3),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(3),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(4),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(4),
O => douta(4)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(5),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(5),
O => douta(5)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(6),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(6),
O => douta(6)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(7),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(7),
O => douta(7)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(8),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => ram_douta(8),
O => douta(8)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_prim_wrapper_init is
port (
ram_douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end pikachu_down_pixel_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000380000000000000000000400000000000000000000000000",
INITP_01 => X"0000000000000000003F0000000000000000003F8000000000000000000FA000",
INITP_02 => X"FFE000000000000000001FE0000000000000000007F8000000000000000000FA",
INITP_03 => X"1FFFF8000000000000000E0FF8000000000000000305FC000000000000000200",
INITP_04 => X"0001FFFE0000000000000001FFFFC000000000000000FFFFD000000000000000",
INITP_05 => X"000000821E00000000000000004E81E00000000000000011BF6C000000000000",
INITP_06 => X"000000005A023FFC0FF8000000001881BFFE0000000000000030F87000000000",
INITP_07 => X"FFFF00000023002C777FFFFC00000007801E3F83FFF9000000009C043FFBDFFC",
INITP_08 => X"FFFFFD3A0010C1800FFFFFFFFD7E0000009007C01FFFFFFC0000001000E00FFF",
INITP_09 => X"D3FFFFFFE4E8000E077FFBFFFFFFF07800830B0F95FFFFFFFC38001F8FFDFDFF",
INITP_0A => X"FBFF47FFFFFFE7F03FFFFD99B3FFFFFFE3FC07EFFDFFF9FFFFFF83F603EBFFFE",
INITP_0B => X"FFFFF3FEFFFFFFFFFF8FFFFFFFE71FFFFFFFFFC1FFFFF7FECFFFFFFFDFE0FFFF",
INITP_0C => X"F807FFFFFFEFFFFFFFFFFA79FFFFFFF7FFFFFFFFFF1CFFFFEFFBFFFFFFFFFF1E",
INITP_0D => X"FFFC803FFFFFFF8FFFFFFFFF001FFFFFFF8FFFFFFFFFE00FFFFFFFFFFFFFFFFF",
INITP_0E => X"FFFFFFF001FFFFFFFFBFFFFFFFFA00FFFFFFFE7FFFFFFFFE007FFFFFFF9FFFFF",
INITP_0F => X"FFFFFFFFFC000FFFFFFFFFFFFFFFFF0007FFFFFFFFFFFFFFFFC003FFFFFFFFFF",
INIT_00 => X"F0F0F00000000102F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_01 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_02 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_03 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F00000010080A0A0B02000F0F0F0F0F0F0F0F0",
INIT_04 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_05 => X"60E0F0F0B02000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_06 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000406061",
INIT_07 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_08 => X"F0F0F0F0F0F0F0F0F0F00120B0F0F0F0F0E0B000F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_09 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0A => X"9000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0B => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00101D0F0F0F0F0F0",
INIT_0C => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0D => X"F0F0F0F0F0F0F00000E0F0F0F0F0F09000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0E => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0F => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_10 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0042280F0F0F0F0F0A05000",
INIT_11 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_12 => X"F0F000012372F0F0F0F0F0F03000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_13 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000F0F0F0F0F0F0",
INIT_14 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_15 => X"F0F0F0F0F0F0F00000F0F0F0F0F0F0F000000190F0F0F0F0F0F0F04000F0F0F0",
INIT_16 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_17 => X"D0D0F0F0F0F0F0F0F03010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_18 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00251C00102F0F0F0F00020",
INIT_19 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_1A => X"F0F0F00060C0F090200000000150A0F0F0F0F0F0F0F0C06000F0F0F0F0F0F0F0",
INIT_1B => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_1C => X"F0F0F0F0F0A000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_1D => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000A0F0F0F08040404041B0F0F0F0",
INIT_1E => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_1F => X"F000A0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F09000F0F0F0F0F0F0F0F0F0F0",
INIT_20 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_21 => X"F0F06010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_22 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F00000D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_23 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_24 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F05000F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_25 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000010F0",
INIT_26 => X"4000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_27 => X"F0F0F0F0F0F0F0F0F0F00000000080D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A0",
INIT_28 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_29 => X"F0E0D0D0D0D0D0D0E0F0F0E0D0D00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2A => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000000010A0F0",
INIT_2B => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2C => X"F0F0F0F0F0F0F00000000000E0F0F0E01000000000000030F0F0700000F0F0F0",
INIT_2D => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2E => X"000000B0B0B09020200000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2F => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F010000000004040403000",
INIT_30 => X"F0F0F0F0F000000000000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_31 => X"F0F000002020000000000000000000003090F0F0F0E060606070707020000000",
INIT_32 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_33 => X"D0C0F0F0F0F0F0F0F0F0F0703030302000000000202020202020202020200000",
INIT_34 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010101000000000F0F00000002070",
INIT_35 => X"00000080F0F0F0F0F0F0F0F090000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_36 => X"10100000000000F0F0F0000000C0900000C0F0F0F0F0F0F0F0F0F0F0F0F04000",
INIT_37 => X"00F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000",
INIT_38 => X"2180F0F0F0F0F0F0F0F0B010100050D0D0D0E0F0F0F0F0F0F0F0F0F0D0D02000",
INIT_39 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F01000000000100000F0F0F0F00000C0F0C0C0",
INIT_3A => X"F0F0F0F0F0F0F0F0F0F0F0F0F0A0807000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_3B => X"0000000000F0000000000030B0F0F0A06180F0F0F0D050505060808080C0F0F0",
INIT_3C => X"01F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000000000",
INIT_3D => X"01B0B0B08030303181F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E040",
INIT_3E => X"F0F0F0F0F0F0F0F0F000000000000000000000000000000000403060B0B0C040",
INIT_3F => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F03101F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_40 => X"F0F0000000000020F0F090000000000001010241F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_41 => X"00F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000000000000000",
INIT_42 => X"E0E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E060",
INIT_43 => X"0000F0F0F0F0F010100000000000F0F0F0F0F0000050F0F0F0F0E0E0E0E0E0E0",
INIT_44 => X"F0F0F0F0F0F0C05040D0F0F0F0F07000F0F0F0F0F0F0F0F0F0F0F0F0F0000000",
INIT_45 => X"000000002070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_46 => X"F0F0F0F0F0F0F0F0F0F00010A0A0A0A0901000F0F02010000000000010000000",
INIT_47 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F090015782C0F0F0F0A05000",
INIT_48 => X"1000F000100000005000001000000010500000000090E0F0F0F0F0F0F0F0F0F0",
INIT_49 => X"F0F0F0F09011EE4761E0F0F0F0C000F0F0F0F0F0F0F0F0F0004080F0F0F0F0F0",
INIT_4A => X"300000000090E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_4B => X"F0F0F0F0F0F0F00070E0E0E0E0E0F01000000000000041F050000000000050F0",
INIT_4C => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0900000CD8920F0F0F0B000F0F0",
INIT_4D => X"0000010261F0F0F0700000000040F0F0500000000070F0F0F0F0F0F0F0F0F0F0",
INIT_4E => X"F0F0900000332220F0F0F0E0B0000000F0F0F0F0F00000000000000050F01000",
INIT_4F => X"000000807041F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_50 => X"F0F0F0F00080B0B0B0B0B08030A0B0B0B0B0B0D0F0F0F0800000000040F0F050",
INIT_51 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0C06000000030F0F0F0F0F080705000",
INIT_52 => X"F0F0F0F0F0F0700000000030F0F040000000D0C05180E0F0F0F0F0F0F0F0F0F0",
INIT_53 => X"F0F030000020F0F0F0F0F0F0F0B000F0F0F00060E0F0F0F0F0F0D060F0F0F0F0",
INIT_54 => X"00B0F0D001C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_55 => X"0040F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0902000001060F0F0701000",
INIT_56 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0300021F0F0F0F0F0F0F0A000F0F0",
INIT_57 => X"F0F0F0F0F0C0000090F0F0F0F0A00000B0F0C000C0F0F0F0F0F0F0F0F0F0F0F0",
INIT_58 => X"F0D0C0D0F0F0F0F0F0F0F0A000F00060F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_59 => X"F0D000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_5A => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0C0000090F0F0F0F0900000B0",
INIT_5B => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A0010080E0F0",
INIT_5C => X"F0F0F0E0800080F0F0F0F0D08080D0B06080E0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_5D => X"B0C0F0F0F0F0F0F0F0A00100B0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_5E => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0C0B0",
INIT_5F => X"D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01080F0F0F0F0F0F0F0F07000",
INIT_60 => X"F0F0F0F0F0F0F0F0F0F0F0F0D000000020F0F0F0F0F0F0F0A00000B0F0F0F0C0",
INIT_61 => X"F0F0F01080F0F0F0F0F0F0F0F08010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_62 => X"10D0F0F0F0F0F0B00000A0F0F0F02060F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_63 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A01000000000",
INIT_64 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0E0F0F0F0F0F0F0F0F08010F0F0",
INIT_65 => X"F0F0F0F0F0F0F0F0F090000000000000C0F0F0F0F0A05100F010101010A0E0F0",
INIT_66 => X"F0F0F0F0F0F0F0F0F0F0F08010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_67 => X"F0F0F0B03101F0F000000000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_68 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F090000000000000C0",
INIT_69 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F07010F0F0F0F0",
INIT_6A => X"F0F0F0F0F0F0F090000000000000C0F0F0D0110000F0F0F0F0F000C0F0F0F0F0",
INIT_6B => X"F0F0F0F0F0F0F0F0F08020E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_6C => X"01000000F0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_6D => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F090000000000000C0F0B0",
INIT_6E => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0C000C0F0F0F0F0",
INIT_6F => X"F0F0F0F0F0E09000000010B0F0F0E0A0100000F0F0F0F0F000C0F0F0F0F0F0F0",
INIT_70 => X"F0F0F0F0F0F0F0F0D000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_71 => X"00F0F0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_72 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070606080F0F0F0F0F020",
INIT_73 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E06070B0F0F0F0F0F0",
INIT_74 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0C01000F0F0F0F0F0F000C0F0F0F0F0F0F0F0F0",
INIT_75 => X"F0F0F0F0F0F0F0F03080F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_76 => X"F0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_77 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B000F0F0F0",
INIT_78 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_79 => X"F0F0F0F0F0F0F0F0F0902000F0F0F0F0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0",
INIT_7A => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_7B => X"F0F00000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_7C => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0904000F0F0F0F0F0F0",
INIT_7D => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_7E => X"F0F0F0F0F0F02000F0F0F0F0F0F0F0F0F0F00060B0F0F0F0F0F0F0F0F0F0F0F0",
INIT_7F => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => ram_douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => ram_douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
p_7_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"FFFFFFFFFFFE80005FFFFFFFFFFFFFFF88003FFFFFFFFFFFFFFFF8001FFFFFFF",
INITP_01 => X"FFFFFFFFF0FFFF8000013FFFFFFFFCFFFFE00000FFFFFFFFFBFFFFF800003FFF",
INITP_02 => X"00001FFFFFFFFFBFE84000006FFFFFFFFF1FFD000000BFFFFFFFE1FFFE800001",
INITP_03 => X"020000000FFFFF03FF4F3F0000001FFFFFFFFEA7FF8000001FFFFFFFFF0F8F80",
INITP_04 => X"20E200000000001FFF902FF80000000001FFFFF81FE00000000008FFFF040FE0",
INITP_05 => X"0000000000000000000000000000000000000000000001E40000000000100000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"F0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_01 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F02000F0F0F0F0F0F0F0F0F0",
INIT_02 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_03 => X"F0A0202010F0F0F0F0F0F0F0F0F0F0F0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_04 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_05 => X"F01040F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_06 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080300000F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_07 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_08 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00020F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_09 => X"F0F0F0F0F0C0B0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A02000",
INIT_0A => X"30F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0B => X"F0F0F0F0F0F0F0F0F0F0F0C00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000",
INIT_0C => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F05030E0E0F0F0F0F0F0F0F0F0",
INIT_0D => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F00030E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_0E => X"F0F0F0F0A00000A0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A000F0F0F0F0F0",
INIT_0F => X"1090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_10 => X"F0F0F0F0F0F0F0801000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010",
INIT_11 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0A0A0603050F0F0F0F0F0F0F0",
INIT_12 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F000003080F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_13 => X"F0F0F0F0F09050508080C0F0F0F0F0F0F0F0F0F0F09060300000F0F0F0F0F0F0",
INIT_14 => X"209090E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_15 => X"F0F0F0C010C0C0202010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000",
INIT_16 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0101060D0D0F0F0F0F0",
INIT_17 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000000080D0D0F0F0F0F0F0F0F0F0F0F0F0",
INIT_18 => X"F0F0F0F0F0F0F0F0800000C0F0F0F0F0F0A000E0F0F0F0F03000F0F0F0F0F0F0",
INIT_19 => X"F0000010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_1A => X"50D0F0F0F0F0F0D07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_1B => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E09000102060F0F070",
INIT_1C => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000303090F0F0F0F0F0F0F0F0F0F0",
INIT_1D => X"F0F0F0F0F0F0F0F08070200070701010808070B0F0F0F09000F0F0F0F0F0F0F0",
INIT_1E => X"F0F000003090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080606060606090F0",
INIT_1F => X"000040C0C0C07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_20 => X"F0F0F0F0F0F0F050202020202050C0C0C0C0C0C0F0F0F0F0F090302000000000",
INIT_21 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010C0C0C0D0F0F0F0F0F0F0F0",
INIT_22 => X"000000B0F0F0F0F0F0F0F0200000F0F0F00000000000F0F0F0F0F0F0F0F0F0F0",
INIT_23 => X"F0F0F0F000000030F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B0000000",
INIT_24 => X"F0F0F00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_25 => X"F0F0F0F0F0F0F0F0F04020100000000000001080F0F0F0F0F0F0D0D090000000",
INIT_26 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000002020202030F0F0F0F0",
INIT_27 => X"0000306060606080F0F0F0C0000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_28 => X"F0F0F0F0F0F0000000000050606060606060606060606060000000F0F0F000F0",
INIT_29 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2A => X"00000000000000F00000F0F0F0F0F0F0F0000000000020B0B0B070000000F0F0",
INIT_2B => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000000000",
INIT_2C => X"F0F0F0F0F0000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2D => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2E => X"0000000000000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1) => '0',
DIPADIP(0) => dina(8),
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => p_7_out(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => p_7_out(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(11),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 2 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 2 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2222222222222222222222222222222222200000222222222222222222222222",
INIT_01 => X"2222222222222200004555102222222222222222222222222222222222222222",
INIT_02 => X"3777510222222222222222222222222222222222222222222222222222222222",
INIT_03 => X"2222222222222222222222222222222222222222222222222222222222220233",
INIT_04 => X"2222222222222222222222222222222222222222220157777750222222222222",
INIT_05 => X"2222222222222222222222220067777740222222222222222222222222222222",
INIT_06 => X"2222222007777774022222222222222222222222222222222222222222222222",
INIT_07 => X"2222222222222222222222222222222222222222222222222222222222222222",
INIT_08 => X"2222222222222222222222222222222222222222222222222222201477777520",
INIT_09 => X"2222222222222222222222222022222222001377777710222222222222222222",
INIT_0A => X"2222222002222222000477777772022222222222222222222222222222222222",
INIT_0B => X"6677777771022222222222222222222222222222222222222222222222222222",
INIT_0C => X"2222222222222222222222222222222222222222222222222222202600222201",
INIT_0D => X"2222222222222222222222222222222222203674100002577777776302222222",
INIT_0E => X"2222222222222222220577742222577777777502222222222222222222222222",
INIT_0F => X"2057777777777777777740222222222222222222222222222222222222222222",
INIT_10 => X"7730222222222222222222222222222222222222222222222222222222222222",
INIT_11 => X"2222222222222222222222222222222222222222222222006777777777777777",
INIT_12 => X"2222222222222222222222222222000777777777777777777202222222222222",
INIT_13 => X"2222222222000267777777777777777520222222222222222222222222222222",
INIT_14 => X"7766666677776600222222222222222222222222222222222222222222222222",
INIT_15 => X"2222222222222222222222222222222222222222222222222222222220015577",
INIT_16 => X"2222222222222222222222222222222222222220025577770000000177300222",
INIT_17 => X"2222222222222222222222034556321000055541100000222222222222222222",
INIT_18 => X"2200004555400000147777333333100022222000000000022222222222222222",
INIT_19 => X"6677777777731111000011111111110022222222222222222222222222222222",
INIT_1A => X"0004777777774000222222222222222222222222222222222000045542200013",
INIT_1B => X"0222222222222222222222222222222001444542220006400677777777777720",
INIT_1C => X"2222222222222203455100222200676614777777775000266677777777776610",
INIT_1D => X"4200020000015775347776222344467777777777777775430222222222222222",
INIT_1E => X"0555411147777777777777777777777202222222222222222222222222200245",
INIT_1F => X"7777777777777771022222222222222222222222200255420000000002135562",
INIT_20 => X"0222222222222222222222220254520022000001774000000002777777777777",
INIT_21 => X"0022222015510022222002777777777777777777777777777777777777777773",
INIT_22 => X"0000037777777777777777777777777777777762267777302222222222222000",
INIT_23 => X"7777777777777777777774024677752022222222220055554002202441000000",
INIT_24 => X"7777407237777602222222220247777700201442211111002111147777777777",
INIT_25 => X"2222222037777770000442176555512755540477777777777777777777777777",
INIT_26 => X"0000377764444577544403777777777777777777777777777774006417775022",
INIT_27 => X"4455327777777777777777777777777777400111777750002222200000002700",
INIT_28 => X"7777777777777777763000177777432022220455555415555556777644445776",
INIT_29 => X"7710017777777502220377777763777777777764444577544475247777777777",
INIT_2A => X"0277777777777777777776544567765447760677777777777777777777777777",
INIT_2B => X"7777774467777644776067777777777777777777777777777710177777775022",
INIT_2C => X"7606777777777777777777777777777776667777777502037777777777777777",
INIT_2D => X"7777777777777777777777777750047777777777777777777777744677776447",
INIT_2E => X"7777777775005777777777777777777777776467777766753477777777777777",
INIT_2F => X"6777777777777777777756777777773077777777777777777777777777777777",
INIT_30 => X"7775677777777407777777777777777777777777777777777777777750057776",
INIT_31 => X"7777777777777777777777777777777777777775005777137777777777777777",
INIT_32 => X"7777777777777777777775202000057777777777777777777777777777774077",
INIT_33 => X"7775102200006777777777777777777777777777777407777777777777777777",
INIT_34 => X"7777777777777777777777777730777777777777777777777777777777777777",
INIT_35 => X"7777777774177777777777777777777777777777777777777600022222067777",
INIT_36 => X"7777777777777777777777777777777500002222206777777777777777777777",
INIT_37 => X"7777777777777775000222220677777777777777777777777777777776067777",
INIT_38 => X"0222222067777777777777777777777777777777606777777777777777777777",
INIT_39 => X"7777777777777777777777773357777777777777777777777777777777777771",
INIT_3A => X"7777777714777777777777777777777777777777777776002222220677777777",
INIT_3B => X"7777777777777777777777777775022222222067777777777777777777777777",
INIT_3C => X"7777777774102222222206777777777777777777777777777777777777777777",
INIT_3D => X"2200677777777777777777777777777777777777777777777777777777777777",
INIT_3E => X"7777777777777777777777777777777777777777777777777777777420222222",
INIT_3F => X"7777777777777777777777777777777777777710222222222203577777777777",
INIT_40 => X"7777777777777777777771022222222222037777777777777777777777777777",
INIT_41 => X"7511022222222222203777777777777777777777777777777777777777777777",
INIT_42 => X"2027777777777777777777777777777777777777777777777777777777777777",
INIT_43 => X"7777777777777777777777777777777777777777777777741002222222222222",
INIT_44 => X"7777765777777777777777777777751022222222222222220177777777777777",
INIT_45 => X"7777777777760022222222222222222017777777777777777777777777777777",
INIT_46 => X"2222222222222201777777777777777777777777777777777777217777777777",
INIT_47 => X"0477777777777777777777777777777777775005777777777777777775022222",
INIT_48 => X"7777777777777777777755312777777777777774002222222222222222222200",
INIT_49 => X"7777742244677777777774310022222222222222222222001477777777777777",
INIT_4A => X"7776066110222222222222222222222014477777777777777777777777777777",
INIT_4B => X"2222222222222220004667777777777777777777777777777777777003667777",
INIT_4C => X"2000777777777777777777777777777777777777400677777507777710222222",
INIT_4D => X"7777777777777777777777774001377326777776302222222222222222222222",
INIT_4E => X"7777777743103300443577740222222222222222222222222001147777777777",
INIT_4F => X"0026663022222222222222222222222222001477777777777777777743333347",
INIT_50 => X"2222222222222222222006666777777777777772111112666666777774110000",
INIT_51 => X"2222000177777777777777777777500000057777777100222000002222222222",
INIT_52 => X"7777777772100000000477777766400022200222222222222222222222222222",
INIT_53 => X"0013333477760002222222222222222222222222222222222220000111117777",
INIT_54 => X"2222222222222222222222222222222222222200000233333333333300022202",
INIT_55 => X"2222222222222222222222222200000000000002112222222000001555300022",
INIT_56 => X"2222222222222222222222222222222222222000000222222222222222222222",
INIT_57 => X"0000000000000000000000000000000000000000000222222222222222222222",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 3) => B"00000000000000000000000000000",
DIADI(2 downto 0) => dina(2 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49\,
DOADO(2 downto 0) => douta(2 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_prim_width is
port (
ram_douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end pikachu_down_pixel_blk_mem_gen_prim_width;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.pikachu_down_pixel_blk_mem_gen_prim_wrapper_init
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
ram_douta(8 downto 0) => ram_douta(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0\ is
port (
p_7_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
p_7_out(8 downto 0) => p_7_out(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 2 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 2 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(2 downto 0) => dina(2 downto 0),
douta(2 downto 0) => douta(2 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end pikachu_down_pixel_blk_mem_gen_generic_cstr;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_generic_cstr is
signal p_7_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal ram_douta : STD_LOGIC_VECTOR ( 8 downto 0 );
begin
\has_mux_a.A\: entity work.pikachu_down_pixel_blk_mem_gen_mux
port map (
addra(1 downto 0) => addra(12 downto 11),
clka => clka,
douta(8 downto 0) => douta(8 downto 0),
p_7_out(8 downto 0) => p_7_out(8 downto 0),
ram_douta(8 downto 0) => ram_douta(8 downto 0)
);
\ramloop[0].ram.r\: entity work.pikachu_down_pixel_blk_mem_gen_prim_width
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
ram_douta(8 downto 0) => ram_douta(8 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0\
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
p_7_out(8 downto 0) => p_7_out(8 downto 0),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1\
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(2 downto 0) => dina(11 downto 9),
douta(2 downto 0) => douta(11 downto 9),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_top : entity is "blk_mem_gen_top";
end pikachu_down_pixel_blk_mem_gen_top;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_top is
begin
\valid.cstr\: entity work.pikachu_down_pixel_blk_mem_gen_generic_cstr
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end pikachu_down_pixel_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.pikachu_down_pixel_blk_mem_gen_top
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 13;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 13;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 4.681258 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "pikachu_down_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "pikachu_down_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 5589;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 5589;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 5589;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 5589;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of pikachu_down_pixel_blk_mem_gen_v8_3_5 : entity is "yes";
end pikachu_down_pixel_blk_mem_gen_v8_3_5;
architecture STRUCTURE of pikachu_down_pixel_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.pikachu_down_pixel_blk_mem_gen_v8_3_5_synth
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_down_pixel is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of pikachu_down_pixel : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of pikachu_down_pixel : entity is "pikachu_down_pixel,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of pikachu_down_pixel : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of pikachu_down_pixel : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end pikachu_down_pixel;
architecture STRUCTURE of pikachu_down_pixel is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 13;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 13;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.681258 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "pikachu_down_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "pikachu_down_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 5589;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 5589;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 5589;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 5589;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.pikachu_down_pixel_blk_mem_gen_v8_3_5
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => B"0000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(12 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(12 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(12 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(12 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 258d654e5ca6c8396c069ac9ebd8ebe0 | 0.714518 | 2.64122 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/OV7670/ov7670_top.vhd | 1 | 4,553 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Top level for the OV7670 camera project.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ov7670_top is
Port (
clk100 : in STD_LOGIC;
OV7670_SIOC : out STD_LOGIC;
OV7670_SIOD : inout STD_LOGIC;
OV7670_RESET : out STD_LOGIC;
OV7670_PWDN : out STD_LOGIC;
OV7670_VSYNC : in STD_LOGIC;
OV7670_HREF : in STD_LOGIC;
OV7670_PCLK : in STD_LOGIC;
OV7670_XCLK : out STD_LOGIC;
OV7670_D : in STD_LOGIC_VECTOR(7 downto 0);
LED : out STD_LOGIC_VECTOR(7 downto 0);
vga_red : out STD_LOGIC_VECTOR(3 downto 0);
vga_green : out STD_LOGIC_VECTOR(3 downto 0);
vga_blue : out STD_LOGIC_VECTOR(3 downto 0);
vga_hsync : out STD_LOGIC;
vga_vsync : out STD_LOGIC;
btn : in STD_LOGIC
);
end ov7670_top;
architecture Behavioral of ov7670_top is
COMPONENT debounce
PORT(
clk : IN std_logic;
i : IN std_logic;
o : OUT std_logic
);
END COMPONENT;
component clocking
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_50 : out std_logic;
CLK_25 : out std_logic
);
end component;
COMPONENT ov7670_controller
PORT(
clk : IN std_logic;
resend: IN std_logic;
config_finished : out std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic;
reset : OUT std_logic;
pwdn : OUT std_logic;
xclk : OUT std_logic
);
END COMPONENT;
COMPONENT frame_buffer
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
COMPONENT ov7670_capture
PORT(
pclk : IN std_logic;
vsync : IN std_logic;
href : IN std_logic;
d : IN std_logic_vector(7 downto 0);
addr : OUT std_logic_vector(18 downto 0);
dout : OUT std_logic_vector(11 downto 0);
we : OUT std_logic
);
END COMPONENT;
COMPONENT vga
PORT(
clk25 : IN std_logic;
vga_red : OUT std_logic_vector(3 downto 0);
vga_green : OUT std_logic_vector(3 downto 0);
vga_blue : OUT std_logic_vector(3 downto 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
frame_addr : OUT std_logic_vector(18 downto 0);
frame_pixel : IN std_logic_vector(11 downto 0)
);
END COMPONENT;
signal frame_addr : std_logic_vector(18 downto 0);
signal frame_pixel : std_logic_vector(11 downto 0);
signal capture_addr : std_logic_vector(18 downto 0);
signal capture_data : std_logic_vector(11 downto 0);
signal capture_we : std_logic_vector(0 downto 0);
signal resend : std_logic;
signal config_finished : std_logic;
signal clk_feedback : std_logic;
signal clk50u : std_logic;
signal clk50 : std_logic;
signal clk25u : std_logic;
signal clk25 : std_logic;
signal buffered_pclk : std_logic;
begin
btn_debounce: debounce PORT MAP(
clk => clk50,
i => btn,
o => resend
);
Inst_vga: vga PORT MAP(
clk25 => clk25,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync,
frame_addr => frame_addr,
frame_pixel => frame_pixel
);
fb : frame_buffer
PORT MAP (
clka => OV7670_PCLK,
wea => capture_we,
addra => capture_addr,
dina => capture_data,
clkb => clk50,
addrb => frame_addr,
doutb => frame_pixel
);
led <= "0000000" & config_finished;
capture: ov7670_capture PORT MAP(
pclk => OV7670_PCLK,
vsync => OV7670_VSYNC,
href => OV7670_HREF,
d => OV7670_D,
addr => capture_addr,
dout => capture_data,
we => capture_we(0)
);
controller: ov7670_controller PORT MAP(
clk => clk50,
sioc => ov7670_sioc,
resend => resend,
config_finished => config_finished,
siod => ov7670_siod,
pwdn => OV7670_PWDN,
reset => OV7670_RESET,
xclk => OV7670_XCLK
);
your_instance_name : clocking
port map
(-- Clock in ports
CLK_100 => CLK100,
-- Clock out ports
CLK_50 => CLK50,
CLK_25 => CLK25);
end Behavioral; | mit | 47f69b557af8d72b516536206de4b299 | 0.585109 | 2.969993 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/win_1/synth/win.vhd | 1 | 14,245 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY win IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END win;
ARCHITECTURE win_arch OF win IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF win_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF win_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF win_arch : ARCHITECTURE IS "win,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF win_arch: ARCHITECTURE IS "win,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=win.mif,C_INIT_" &
"FILE=win.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=15120,C_READ_DEPTH_A=15120,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=15120,C_R" &
"EAD_DEPTH_B=15120,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RAN" &
"GE=0,C_COUNT_36K_BRAM=5,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.227751 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "win.mif",
C_INIT_FILE => "win.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 15120,
C_READ_DEPTH_A => 15120,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 15120,
C_READ_DEPTH_B => 15120,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "5",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.227751 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END win_arch;
| gpl-3.0 | dd6a2ae2347a813cbe6f90b83a686ac6 | 0.624149 | 3.010991 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/OV7670/ov7670_capture.vhd | 1 | 2,664 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Captures the pixels coming from the OV7670 camera and
-- Stores them in block RAM
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_capture is
Port ( pclk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (7 downto 0);
addr : out STD_LOGIC_VECTOR (18 downto 0);
dout : out STD_LOGIC_VECTOR (15 downto 0);
we : out STD_LOGIC);
end ov7670_capture;
architecture Behavioral of ov7670_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
signal address_next : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
signal wr_hold : std_logic_vector(1 downto 0) := (others => '0');
begin
addr <= address;
process(pclk)
begin
if rising_edge(pclk) then
-- This is a bit tricky href starts a pixel transfer that takes 3 cycles
-- Input | state after clock tick
-- href | wr_hold d_latch d we address address_next
-- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx x xxxx xxxx
-- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxxxxxx x xxxx addr
-- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxRRRRRGGG x addr addr
-- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRRGGGGGGBBBBB 1 addr addr+1
if vsync = '1' then
address <= (others => '0');
address_next <= (others => '0');
wr_hold <= (others => '0');
else
-- This should be a different order, but seems to be GRB!
-- dout <= d_latch(11 downto 10) & d_latch(11 downto 10) & d_latch(15 downto 12) & d_latch(9 downto 8) & d_latch(9 downto 8);
-- dout <= d_latch(15 downto 12) & d_latch(10 downto 7) & d_latch(4 downto 1);
dout <= d_latch;
address <= address_next;
we <= wr_hold(1);
wr_hold <= wr_hold(0) & (href and not wr_hold(0));
d_latch <= d_latch( 7 downto 0) & d;
if wr_hold(1) = '1' then
address_next <= std_logic_vector(unsigned(address_next)+1);
end if;
end if;
end if;
end process;
end Behavioral; | mit | ec2e7fe222a5c1c3424bea428c746e5f | 0.504129 | 3.731092 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/dualport_ram.vhd | 13 | 5,091 | --
-- ZPUINO memory
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library board;
use board.zpupkg.all;
--library UNISIM;
--use UNISIM.VCOMPONENTS.all;
entity dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end entity dualport_ram;
architecture behave of dualport_ram is
component prom_generic_dualport is
port (ADDRA: in std_logic_vector(maxbit downto 2);
CLK : in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
WEA: in std_logic; -- to avoid a bug in Xilinx ISE
DOA: out STD_LOGIC_VECTOR (31 downto 0);
ADDRB: in std_logic_vector(maxbit downto 2);
DIA: in STD_LOGIC_VECTOR (31 downto 0); -- to avoid a bug in Xilinx ISE
WEB: in std_logic;
MASKB: in std_logic_vector(3 downto 0);
ENB: in std_logic;
DOB: out STD_LOGIC_VECTOR (31 downto 0);
DIB: in STD_LOGIC_VECTOR (31 downto 0));
end component;
signal memAWriteEnable_i: std_logic;
signal memBWriteEnable_i: std_logic;
constant nullAddr: std_logic_vector(maxbit downto 12) := (others => '0');
constant protectionEnabled: std_logic := '0';
begin
-- Boot loader address: 000XXXXXXXXXX
-- Disallow any writes to bootloader protected code (first 4096 bytes, 0x1000 hex (0x000 to 0xFFF)
memAWriteEnable_i <= memAWriteEnable when ( memAAddr(maxbit downto 12)/=nullAddr or protectionEnabled='0') else '0';
memBWriteEnable_i <= memBWriteEnable when ( memBAddr(maxbit downto 12)/=nullAddr or protectionEnabled='0') else '0';
process(memAWriteEnable,memAAddr(maxbit downto 12),memBWriteEnable,memBAddr(maxbit downto 12))
begin
memErr <= '0';
if memAWriteEnable='1' and memAAddr(maxbit downto 12)="000" and protectionEnabled='1' then
memErr<='1';
end if;
if memBWriteEnable='1' and memBAddr(maxbit downto 12)="000" and protectionEnabled='1' then
memErr<='1';
end if;
end process;
-- Sanity checks for simulation
process(clk)
begin
if rising_edge(clk) then
if memAWriteEnable='1' and memAAddr(maxbit downto 12)="000" and protectionEnabled='1' then
report "Write to BOOTLOADER port A not allowed!!! " severity note;
end if;
end if;
end process;
-- Sanity checks for simulation
process(clk)
begin
if rising_edge(clk) then
if memBWriteEnable='1' and memBAddr(maxbit downto 12)="000" and protectionEnabled='1' then
report "Write to BOOTLOADER port B not allowed!!!" severity note;
end if;
end if;
end process;
ram: prom_generic_dualport
port map (
DOA => memARead,
ADDRA => memAAddr,
CLK => clk,
DIA => memAWrite,
ENA => memAEnable,
MASKA => "1111",
WEA => memAWriteEnable,
DOB => memBRead,
ADDRB => memBAddr,
DIB => memBWrite,
MASKB => "1111",
ENB => memBEnable,
WEB => memBWriteEnable
);
end behave;
| mit | 80db861e3caeb62ddc48770455f94e53 | 0.668042 | 3.675812 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_jump_pixel/synth/pikachu_jump_pixel.vhd | 1 | 14,462 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY pikachu_jump_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END pikachu_jump_pixel;
ARCHITECTURE pikachu_jump_pixel_arch OF pikachu_jump_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF pikachu_jump_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF pikachu_jump_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF pikachu_jump_pixel_arch : ARCHITECTURE IS "pikachu_jump_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF pikachu_jump_pixel_arch: ARCHITECTURE IS "pikachu_jump_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=" &
"pikachu_jump_pixel.mif,C_INIT_FILE=pikachu_jump_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=6804,C_READ_DEPTH_A=6804,C_ADDRA_WIDTH=13,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12," &
"C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=6804,C_READ_DEPTH_B=6804,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0" &
",C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=3,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.016775 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "pikachu_jump_pixel.mif",
C_INIT_FILE => "pikachu_jump_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 6804,
C_READ_DEPTH_A => 6804,
C_ADDRA_WIDTH => 13,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 6804,
C_READ_DEPTH_B => 6804,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "3",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.016775 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END pikachu_jump_pixel_arch;
| gpl-3.0 | aeea2c5be7a45a801987300ddf01cc6f | 0.627714 | 3.004779 | false | false | false | false |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/soc_design_inst.vhd | 2 | 2,278 | component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; -- cke
dram_cs_n : out std_logic; -- cs_n
dram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
dram_dqm : out std_logic_vector(1 downto 0); -- dqm
dram_ras_n : out std_logic; -- ras_n
dram_we_n : out std_logic; -- we_n
dram_clk_clk : out std_logic; -- clk
fpga_reset_n : in std_logic := 'X'; -- reset_n
ledr0_ledr : out std_logic; -- ledr
ref_clk : in std_logic := 'X'; -- clk
uart_RXD : in std_logic := 'X'; -- RXD
uart_TXD : out std_logic -- TXD
);
end component soc_design;
u0 : component soc_design
port map (
dram_addr => CONNECTED_TO_dram_addr, -- dram.addr
dram_ba => CONNECTED_TO_dram_ba, -- .ba
dram_cas_n => CONNECTED_TO_dram_cas_n, -- .cas_n
dram_cke => CONNECTED_TO_dram_cke, -- .cke
dram_cs_n => CONNECTED_TO_dram_cs_n, -- .cs_n
dram_dq => CONNECTED_TO_dram_dq, -- .dq
dram_dqm => CONNECTED_TO_dram_dqm, -- .dqm
dram_ras_n => CONNECTED_TO_dram_ras_n, -- .ras_n
dram_we_n => CONNECTED_TO_dram_we_n, -- .we_n
dram_clk_clk => CONNECTED_TO_dram_clk_clk, -- dram_clk.clk
fpga_reset_n => CONNECTED_TO_fpga_reset_n, -- fpga.reset_n
ledr0_ledr => CONNECTED_TO_ledr0_ledr, -- ledr0.ledr
ref_clk => CONNECTED_TO_ref_clk, -- ref.clk
uart_RXD => CONNECTED_TO_uart_RXD, -- uart.RXD
uart_TXD => CONNECTED_TO_uart_TXD -- .TXD
);
| gpl-2.0 | 0d3a4747439efdc64f0f59f8dc7352cb | 0.410448 | 3.354934 | false | false | false | false |
sh-chris110/chris | FPGA/chris/Qsys/soc_design/soc_design_inst.vhd | 3 | 1,992 | component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; -- cke
dram_cs_n : out std_logic; -- cs_n
dram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
dram_dqm : out std_logic_vector(1 downto 0); -- dqm
dram_ras_n : out std_logic; -- ras_n
dram_we_n : out std_logic; -- we_n
dram_clk_clk : out std_logic; -- clk
fpga_reset_n : in std_logic := 'X'; -- reset_n
ledr0_ledr : out std_logic; -- ledr
ref_clk : in std_logic := 'X' -- clk
);
end component soc_design;
u0 : component soc_design
port map (
dram_addr => CONNECTED_TO_dram_addr, -- dram.addr
dram_ba => CONNECTED_TO_dram_ba, -- .ba
dram_cas_n => CONNECTED_TO_dram_cas_n, -- .cas_n
dram_cke => CONNECTED_TO_dram_cke, -- .cke
dram_cs_n => CONNECTED_TO_dram_cs_n, -- .cs_n
dram_dq => CONNECTED_TO_dram_dq, -- .dq
dram_dqm => CONNECTED_TO_dram_dqm, -- .dqm
dram_ras_n => CONNECTED_TO_dram_ras_n, -- .ras_n
dram_we_n => CONNECTED_TO_dram_we_n, -- .we_n
dram_clk_clk => CONNECTED_TO_dram_clk_clk, -- dram_clk.clk
fpga_reset_n => CONNECTED_TO_fpga_reset_n, -- fpga.reset_n
ledr0_ledr => CONNECTED_TO_ledr0_ledr, -- ledr0.ledr
ref_clk => CONNECTED_TO_ref_clk -- ref.clk
);
| gpl-2.0 | c652e42bd75a937fcb66af34583ae692 | 0.418173 | 3.303483 | false | false | false | false |
mwswartwout/EECS318 | hw3/problem1/UPM4x4.vhd | 1 | 1,883 | entity UPM4x4 is
port ( X : in bit_vector (3 downto 0);
Y : in bit_vector (3 downto 0);
output : out bit_vector (7 downto 0));
end UPM4x4;
architecture UPM4x4_arch of UPM4x4 is
signal c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20 : bit;
signal s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20 : bit;
component CSA
port ( Sout : out bit;
Cout : out bit;
Sin : in bit;
A : in bit;
B : in bit;
Cin : in bit);
end component;
component CPA
port ( Sout : out bit;
Cout : out bit;
A : in bit;
B : in bit;
Cin : in bit);
end component;
begin
CSA1 : CSA port map (s1, c1, '0', y(0), x(0), '0');
CSA2 : CSA port map (s2, c2, '0', y(1), x(0), '0');
CSA3 : CSA port map (s3, c3, '0', y(2), x(0), '0');
CSA4 : CSA port map (s4, c4, '0', y(3), x(0), '0');
CSA5 : CSA port map (s5, c5, s2, y(0), x(1), c1);
CSA6 : CSA port map (s6, c6, s3, y(1), x(1), c2);
CSA7 : CSA port map (s7, c7, s4, y(2), x(1), c3);
CSA8 : CSA port map (s8, c8, '0', y(3), x(1), c4);
CSA9 : CSA port map (s9, c9, s6, y(0), x(2), c5);
CSA10 : CSA port map (s10, c10, s7, y(1), x(2), c6);
CSA11 : CSA port map (s11, c11, s8, y(2), x(2), c7);
CSA12 : CSA port map (s12, c12, '0', y(3), x(2), c8);
CSA13 : CSA port map (s13, c13, s10, y(0), x(3), c9);
CSA14 : CSA port map (s14, c14, s11, y(1), x(3), c10);
CSA15 : CSA port map (s15, c15, s12, y(2), x(3), c11);
CSA16 : CSA port map (s16, c16, '0', y(3), x(3), c12);
CPA1 : CPA port map (s17, c17, s14, c13, '0');
CPA2 : CPA port map (s18, c18, s15, c14, c17);
CPA3 : CPA port map (s19, c19, s16, c15, c18);
CPA4 : CPA port map (s20, c20, '0', c16, c19);
output(0) <= s1;
output(1) <= s5;
output(2) <= s9;
output(3) <= s13;
output(4) <= s17;
output(5) <= s18;
output(6) <= s19;
output(7) <= s20;
end UPM4x4_arch;
| mit | 161fc738666146b7331dd75d62e3dd7f | 0.545937 | 1.91947 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Arcade_MegaWing_Pinout.vhd | 13 | 12,521 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
entity Arcade_MegaWing_Pinout is
port (
--Audio
Audio_Left : in std_logic;
Audio_Right : in std_logic;
--Buttons
BTN_Left : in std_logic;
BTN_Right : in std_logic;
BTN_Up : in std_logic;
BTN_Down : in std_logic;
BTN_Reset : in std_logic;
--Joystick A
JOYA_Left : in std_logic;
JOYA_Right : in std_logic;
JOYA_Up : in std_logic;
JOYA_Down : in std_logic;
JOYA_Fire1 : in std_logic;
JOYA_Fire2 : in std_logic;
JOYA_GND : in std_logic;
--Joystick B
JOYB_Left : in std_logic;
JOYB_Right : in std_logic;
JOYB_Up : in std_logic;
JOYB_Down : in std_logic;
JOYB_Fire1 : in std_logic;
JOYB_Fire2 : in std_logic;
JOYB_GND : in std_logic;
--LED's
LED1 : in std_logic;
LED2 : in std_logic;
LED3 : in std_logic;
LED4 : in std_logic;
--PS2 A
PS2A_CLK : in std_logic;
PS2A_Data : out std_logic;
--PS2 B
PS2B_CLK : in std_logic;
PS2B_Data : out std_logic;
--VGA
VGA_Red : in std_logic_vector (2 downto 0);
VGA_Green : in std_logic_vector (2 downto 0);
VGA_Blue : in std_logic_vector (1 downto 0);
VGA_Hsync : in std_logic;
VGA_Vsync : in std_logic;
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Arcade_MegaWing_Pinout;
architecture BEHAVIORAL of Arcade_MegaWing_Pinout is
-- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
--Audio
WING_AH6 <= Audio_Left;
WING_AH7 <= Audio_Right;
--Buttons
WING_BH0 <= BTN_Left;
WING_BH3 <= BTN_Right;
WING_BH1 <= BTN_Up;
WING_BH2 <= BTN_Down;
WING_AH4 <= BTN_Reset;
--Joystick A
WING_CH3 <= JOYA_Left;
WING_CH5 <= JOYA_Right;
WING_CH0 <= JOYA_Up ;
WING_CH2 <= JOYA_Down;
WING_CH1 <= JOYA_Fire1;
WING_CH7 <= JOYA_Fire2;
WING_CH4 <= JOYA_GND;
--Joystick B
WING_BH7 <= JOYB_Left;
WING_AL1 <= JOYB_Right;
WING_BH4 <= JOYB_Up ;
WING_BH6 <= JOYB_Down;
WING_BH5 <= JOYB_Fire1;
WING_AL3 <= JOYB_Fire2;
WING_AL0 <= JOYB_GND;
--LED's
WING_AL7 <= LED1;
WING_AL6 <= LED2;
WING_AL5 <= LED3;
WING_AL4 <= LED4;
--PS2 A
WING_CL1 <= PS2A_CLK;
PS2A_Data <= WING_CL0;
--PS2 B
WING_AH5 <= PS2B_CLK;
PS2B_Data <= WING_AH4;
--VGA
WING_CL2 <= VGA_Vsync;
WING_CL3 <= VGA_Hsync;
WING_BL0 <= VGA_Blue(0);
WING_BL1 <= VGA_Blue(1);
--WING_BL2 <= VGA_Blue(2);
--WING_BL3 <= VGA_Blue(3);
WING_BL4 <= VGA_Green(0);
WING_BL5 <= VGA_Green(1);
WING_BL6 <= VGA_Green(2);
--WING_BL7 <= VGA_Green(3);
WING_CL4 <= VGA_Red(0);
WING_CL5 <= VGA_Red(1);
WING_CL6 <= VGA_Red(2);
--WING_CL7 <= VGA_Red(3);
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_spp_data <= (others => DontCareValue);
-- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
| mit | c4cdd7c6d6b885978a16950b7acbf428 | 0.558023 | 2.487286 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev7.vhd | 1 | 38,937 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev7 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev7 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
signal rcount: integer := 0;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2=WPAD2) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 80) then
wout <= std_logic_vector(mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))));
end if;
elsif (Opcode2 = WPAD2) then
if (rcount < 80) then
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
if (rcount < 80) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
elsif (Opcode2 = WPAD2) then
if (rcount < 80) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 80) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
end if;
elsif(Opcode3 = WPAD2) then
if (rcount < 80) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3 = WPAD2) then
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 3a0dc173eadb171bb101d4ae7012d6e0 | 0.645915 | 2.911395 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.b-ALU.vhd | 1 | 5,904 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
port(
-- inputs
alu_op : in std_logic_vector(4 downto 0); -- specifies alu operation to be performed (from CU in ID stage)
a : in std_logic_vector(31 downto 0); -- operand 1
b : in std_logic_vector(31 downto 0); -- operand 2
-- outputs
ovf : out std_logic; -- ovf of operation; to PSW
zero : out std_logic; -- zero when res is all 0s; to branch_circ
res : out std_logic_vector(31 downto 0) -- result of the arit-logic operation on a and b
);
end ALU;
architecture rtl of ALU is
signal res_i : std_logic_vector(31 downto 0);
-- ALU OPERATION
constant ALUOP_SLL : std_logic_vector(4 downto 0) := "00001";
constant ALUOP_SRL : std_logic_vector(4 downto 0) := "00010";
constant ALUOP_SRA : std_logic_vector(4 downto 0) := "00011";
constant ALUOP_ADD : std_logic_vector(4 downto 0) := "00100";
constant ALUOP_ADDU : std_logic_vector(4 downto 0) := "00101";
constant ALUOP_SUB : std_logic_vector(4 downto 0) := "00110";
constant ALUOP_SUBU : std_logic_vector(4 downto 0) := "00111";
constant ALUOP_AND : std_logic_vector(4 downto 0) := "01000";
constant ALUOP_OR : std_logic_vector(4 downto 0) := "01001";
constant ALUOP_XOR : std_logic_vector(4 downto 0) := "01010";
constant ALUOP_SEQ : std_logic_vector(4 downto 0) := "01011";
constant ALUOP_SNE : std_logic_vector(4 downto 0) := "01100";
constant ALUOP_SLT : std_logic_vector(4 downto 0) := "01101";
constant ALUOP_SGT : std_logic_vector(4 downto 0) := "01110";
constant ALUOP_SLE : std_logic_vector(4 downto 0) := "01111";
constant ALUOP_SGE : std_logic_vector(4 downto 0) := "10000";
constant ALUOP_MOVS2I : std_logic_vector(4 downto 0) := "00000";
constant ALUOP_SLTU : std_logic_vector(4 downto 0) := "10001";
constant ALUOP_SGTU : std_logic_vector(4 downto 0) := "10010";
constant ALUOP_SGEU : std_logic_vector(4 downto 0) := "10011";
begin
res <= res_i;
zero <= '1' when res_i = X"00000000" else '0';
process (alu_op, a, b)
-- complete all the requested functions (20 in total, some are shared b/n instructions)
variable tmp : std_logic_vector(32 downto 0);
begin
ovf <= '0';
case alu_op is
when ALUOP_SLL =>
res_i <= std_logic_vector(shift_left(unsigned(a), to_integer(unsigned(b(4 downto 0)))));
when ALUOP_SRL =>
res_i <= std_logic_vector(shift_right(unsigned(a), to_integer(unsigned(b(4 downto 0)))));
when ALUOP_SRA => -- the shift_right func from numeric_std with a signed number as arg will do SRA
res_i <= std_logic_vector(shift_right(signed(a), to_integer(unsigned(b(4 downto 0)))));
when ALUOP_ADD =>
tmp := std_logic_vector(resize(signed(a), 33) + resize(signed(b), 33));
res_i <= tmp(31 downto 0);
ovf <= (not a(31) and not b(31) and tmp(31)) or (a(31) and b(31) and not tmp(31));
when ALUOP_ADDU =>
tmp := std_logic_vector(resize(unsigned(a), 33) + resize(unsigned(b), 33));
res_i <= tmp(31 downto 0);
when ALUOP_SUB =>
tmp := std_logic_vector(resize(signed(a), 33) - resize(signed(b), 33));
res_i <= tmp(31 downto 0);
-- "ovf = 1 when operands have different sign and result has different sign wrt first operand"
if( (a(31) /= b(31)) and (tmp(31) /= a(31))) then
ovf <= '1';
else
ovf <= '0';
end if;
when ALUOP_SUBU =>
tmp := std_logic_vector(resize(unsigned(a), 33) - resize(unsigned(b), 33));
res_i <= tmp(31 downto 0);
when ALUOP_AND =>
res_i <= a and b;
when ALUOP_OR =>
res_i <= a or b;
when ALUOP_XOR =>
res_i <= a xor b;
when ALUOP_SEQ => -- if a = b then res = 1
if(signed(a) = signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SNE => -- if a /= b then res = 1
if(signed(a) /= signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SLT => -- if a < b then res = 1
if(signed(a) < signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGT => -- if a > b then res = 1
if(signed(a) > signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SLE => -- if a <= b then res = 1
if(signed(a) <= signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGE => -- if a >= b then res = 1
if(signed(a) >= signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_MOVS2I =>
res_i <= a;
when ALUOP_SLTU => -- if a < b then res = 1 (a, b unsigned)
if(unsigned(a) < unsigned(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGTU => -- if a > b then res = 1 (a, b unsigned)
if(unsigned(a) > unsigned(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGEU => -- if a >= b then res = 1 (a, b unsigned)
if(unsigned(a) >= unsigned(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when others => res_i <= (others => '0'); -- design decision, to avoid inferred latches during synthesis
end case;
end process ;
end rtl;
| mit | cff2a90f9c47d03517df74e540061a9f | 0.541836 | 3.393103 | false | false | false | false |
johnmurrayvi/misc-scripts-files | vhdl/FSMs/Kiss2Fsm.vhd | 1 | 3,262 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Jeppe M.
--
-- Create Date: 09:25:23 03/14/2008
-- Design Name:
-- Module Name: Kiss2Fsm - Behavioral
----------------------------------------------start of
--example of input file---------------------------
--..i 2
--..o 2
--..p 8
--..s 4
--01 s0 s1 11
--11 so s3 00
--01 s1 s0 11
--11 s1 s2 00
--1- s2 s3 01
--0- s2 s1 10
--11 s3 s0 10
--10 s3 s2 11
----------------------------------------------end of
--file---------------------------------
--i= # of inputs
--o= # of outputs
--p= # of transitions
--s= # of states
--01 so s1 11 = this is read as for input 01 and current state s0 the
--output is 11 and next state is s1.
--'-' means don't care
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Kiss2Fsm is
Port ( Clk : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC_VECTOR (1 downto 0));
end Kiss2Fsm;
architecture Behavioral of Kiss2Fsm is
type states is (S0,S1,S2,S3);
signal state: states := s0;
begin
-------------------- State transitions process -----------------------
process( Clk)
begin
if rising_edge(clk) then
case State is
when s0 => --============================================
if i="01" then
State <= S1;
end if;
if i="11" then
State <= S3;
end if;
when s1 => --============================================
if i="01" then
State <= S0;
end if;
if i="11" then
State <= S2;
end if;
when s2 => --============================================
if i(1)='1' then -- note single bit
State <= S3;
end if;
if i="0-" then -- note dont care signal
State <= S1;
end if;
when s3 => --==============================================
case i is -- alternative assignment
when "11" => State <= S0;
when "10" => State <= S2;
when others => State <= S3; -- Default needed here
end case;
end case;
end if;
end process;
-------------------------- Output process -----------------------
process( State, i)
begin
case state is
when s0 => --==========================================
case i is
when "01" => O <= "11";
when "11" => O <= "00";
when others => O <= "01";
end case;
when s1 => --==========================================
case i is
when "01" => O <= "11";
when "11" => O <= "00";
when others => O <= "01";
end case;
when s2 => --==========================================
case i is
when "1-" => O <= "01";
when "0-" => O <= "10";
when others => O <= "11";
end case;
when s3 => --==========================================
case i is
when "11" => O <= "10";
when "10" => O <= "11";
when others => O <= "--";
end case;
end case;
end process;
end Behavioral;
| gpl-3.0 | b528c22b72e8d4bc10310c9583553605 | 0.370938 | 3.779838 | false | false | false | false |
huukit/logicsynth | excercises/vhd/wave_gen_bonus.vhd | 1 | 3,160 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 06
-- Project :
-------------------------------------------------------------------------------
-- File : wave_gen_bonus.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 23.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sixth excercise (bonus).
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 25.11.2015 1.0 tuhu Created
-- 09.12.2015 1.1 nikulaj Tweak bonus
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_float_types.all;
use ieee.fixed_pkg.all;
entity wave_gen is -- Wave generator entity.
generic
(
width_g : integer := 16; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port
(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end wave_gen;
architecture rtl of wave_gen is
constant maxval_c : integer := (2**(width_g - 2) - 1); -- Maximum value for output.
constant minval_c : integer := -maxval_c; -- Minimun value for output.
constant decimals_c : integer := -width_g;
constant d_c : sfixed(width_g-1 downto decimals_c) := resize((2 * to_sfixed(3.141593, width_g-1, decimals_c)) / maxval_c, width_g-1, decimals_c);
signal count_r : sfixed(width_g-1 downto decimals_c);
signal sin_r : sfixed(width_g-1 downto decimals_c);
signal cos_r : sfixed(width_g-1 downto decimals_c);
signal result_r : sfixed(width_g-1 downto decimals_c);
begin -- rtl
value_out <= std_logic_vector(to_signed(result_r, width_g)); -- Assign register to output.
count : process (clk, rst_n) -- Process to increment or decrement counter value.
begin
if(rst_n = '0') then
count_r <= (others => '0'); -- Clear the output on reset ...
sin_r <= (others => '0');
cos_r <= to_sfixed(1.0, cos_r);
elsif(clk'event and clk = '1') then
sin_r <= resize(sin_r + cos_r * d_c, sin_r'high, sin_r'low);
cos_r <= resize(cos_r - sin_r * d_c, cos_r'high, cos_r'low);
result_r <= resize(sin_r * maxval_c, result_r'high, result_r'low);
count_r <= resize(count_r + to_sfixed(1.0, count_r), count_r'high, count_r'low);
if(count_r = maxval_c) then
count_r <= (others => '0');
sin_r <= (others => '0');
cos_r <= to_sfixed(1.0, cos_r);
end if;
end if; -- clk'event ...
end process count;
end rtl;
| gpl-2.0 | 50d4af6afce43ec7d47b5d4b8f010f78 | 0.486392 | 3.603193 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev3.vhd | 1 | 38,291 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev3 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev3 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmp1, tmp2, tmp3: unsigned(63 downto 0);
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WPAD : std_logic_vector(5 downto 0) := "011101";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal message0 : std_logic_vector(63 downto 0);
signal message1 : std_logic_vector(63 downto 0);
signal message2 : std_logic_vector(63 downto 0);
signal message3 : std_logic_vector(63 downto 0);
signal message4 : std_logic_vector(63 downto 0);
signal message5 : std_logic_vector(63 downto 0);
signal message6 : std_logic_vector(63 downto 0);
signal message7 : std_logic_vector(63 downto 0);
signal message8 : std_logic_vector(63 downto 0);
signal message9 : std_logic_vector(63 downto 0);
signal message10 : std_logic_vector(63 downto 0);
signal message11 : std_logic_vector(63 downto 0);
signal message12 : std_logic_vector(63 downto 0);
signal message13 : std_logic_vector(63 downto 0);
signal message14 : std_logic_vector(63 downto 0);
signal message15 : std_logic_vector(63 downto 0);
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2= MLOAD0) then
message0 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message1 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message2 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message3 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
message4 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message5 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message6 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message7 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
message8 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message9 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message10 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message11 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
message12 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message13 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message14 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message15 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = WPAD) then
w_80(0) := message0;
w_80(1) := message1;
w_80(2) := message2;
w_80(3) := message3;
w_80(4) := message4;
w_80(5) := message5;
w_80(6) := message6;
w_80(7) := message7;
w_80(8) := message8;
w_80(9) := message9;
w_80(10) := message10;
w_80(11) := message11;
w_80(12) := message12;
w_80(13) := message13;
w_80(14) := message14;
w_80(15) := message15;
for i in 16 to 79 loop
w_80(i) :=
std_logic_vector(
unsigned(rotate_right(unsigned(w_80(i-2)), 19)) xor unsigned(rotate_right(unsigned(w_80(i-2)), 61)) xor unsigned(shift_right(unsigned(w_80(i-2)), 6)) +
unsigned(w_80(i-7)) +
unsigned(rotate_right(unsigned(w_80(i-15)), 1)) xor unsigned(rotate_right(unsigned(w_80(i-15)), 8)) xor unsigned(rotate_right(unsigned(w_80(i-15)), 7))+
unsigned(w_80(i-16)));
end loop;
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
for i in 0 to 79 loop
for j in 0 to 1 loop
if (j = 0) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
unsigned(K_TABLE(0)) + unsigned(w_80(0)))
);
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
-- else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
end if;
end loop;
end loop;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3 = WPAD) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(message0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(message0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(message1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(message1))(31 downto 0);
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 7b63b36d224363f77b7e1f19cd2247a5 | 0.650649 | 2.936201 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_serialreset.vhd | 13 | 2,740 | --
-- Serial reset for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- This module causes a synchronous reset when we receive 0xFF at 300 baud.
-- Hopefully no other speed setting will cause this.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 100
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end entity zpuino_serialreset;
architecture behave of zpuino_serialreset is
constant rstcount_val: integer := ((SYSTEM_CLOCK_MHZ*1000000)/300)*8;
signal rstcount: integer;
signal rstcount_zero_q: std_logic;
begin
rstout<='1' when rstin='1' or rstcount_zero_q='1' else '0';
process(clk)
begin
if rising_edge(clk) then
if rstin='1' then
rstcount <= rstcount_val;
rstcount_zero_q <= '0';
else
if rx='1' then
rstcount <= rstcount_val;
else
if rstcount/=0 then
rstcount <= rstcount - 1;
rstcount_zero_q<='0';
else
rstcount_zero_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | d6f969292dd3448520bd2b67166159ae | 0.677007 | 3.677852 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/select2/synth/select2.vhd | 1 | 14,297 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY select2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END select2;
ARCHITECTURE select2_arch OF select2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF select2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF select2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF select2_arch : ARCHITECTURE IS "select2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF select2_arch: ARCHITECTURE IS "select2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=select2.mif" &
",C_INIT_FILE=select2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=2109,C_READ_DEPTH_A=2109,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B" &
"=2109,C_READ_DEPTH_B=2109,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN" &
"_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.822999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "select2.mif",
C_INIT_FILE => "select2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 2109,
C_READ_DEPTH_A => 2109,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 2109,
C_READ_DEPTH_B => 2109,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.822999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END select2_arch;
| gpl-3.0 | 26c3c221f4cca88cf6cb201d3a26a1e1 | 0.625516 | 3.020068 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/wbarb2_1.vhd | 13 | 3,656 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_stall_o: out std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end entity wbarb2_1;
architecture behave of wbarb2_1 is
signal current_master: std_logic;
signal next_master: std_logic;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
current_master <= '0';
else
current_master <= next_master;
end if;
end if;
end process;
process(current_master, m0_wb_cyc_i, m1_wb_cyc_i)
begin
next_master <= current_master;
case current_master is
when '0' =>
if m0_wb_cyc_i='0' then
if m1_wb_cyc_i='1' then
next_master <= '1';
end if;
end if;
when '1' =>
if m1_wb_cyc_i='0' then
if m0_wb_cyc_i='1' then
next_master <= '0';
end if;
end if;
when others =>
end case;
end process;
-- Muxers for slave
process(current_master,
m0_wb_dat_i, m0_wb_adr_i, m0_wb_sel_i, m0_wb_cti_i, m0_wb_we_i, m0_wb_cyc_i, m0_wb_stb_i,
m1_wb_dat_i, m1_wb_adr_i, m1_wb_sel_i, m1_wb_cti_i, m1_wb_we_i, m1_wb_cyc_i, m1_wb_stb_i)
begin
case current_master is
when '0' =>
s0_wb_dat_o <= m0_wb_dat_i;
s0_wb_adr_o <= m0_wb_adr_i;
s0_wb_sel_o <= m0_wb_sel_i;
s0_wb_cti_o <= m0_wb_cti_i;
s0_wb_we_o <= m0_wb_we_i;
s0_wb_cyc_o <= m0_wb_cyc_i;
s0_wb_stb_o <= m0_wb_stb_i;
when '1' =>
s0_wb_dat_o <= m1_wb_dat_i;
s0_wb_adr_o <= m1_wb_adr_i;
s0_wb_sel_o <= m1_wb_sel_i;
s0_wb_cti_o <= m1_wb_cti_i;
s0_wb_we_o <= m1_wb_we_i;
s0_wb_cyc_o <= m1_wb_cyc_i;
s0_wb_stb_o <= m1_wb_stb_i;
when others =>
null;
end case;
end process;
-- Muxers/sel for masters
m0_wb_dat_o <= s0_wb_dat_i;
m1_wb_dat_o <= s0_wb_dat_i;
-- Ack
m0_wb_ack_o <= s0_wb_ack_i when current_master='0' else '0';
m1_wb_ack_o <= s0_wb_ack_i when current_master='1' else '0';
m0_wb_stall_o <= s0_wb_stall_i when current_master='0' else '1';
m1_wb_stall_o <= s0_wb_stall_i when current_master='1' else '1';
end behave;
| mit | f42de23a5bee479d9291cea73bd52a10 | 0.596827 | 2.322745 | false | false | false | false |
algebrato/eldig | contatore_4_cifre/cont_1_cifra.vhd | 2 | 976 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Contatore_1_cifra is
port(Clock, Enable_in, UpDown, Reset, Preset : in std_logic;
N_preset : in std_logic_vector(3 downto 0);
N : out std_logic_vector(3 downto 0);
Enable_out : out std_logic);
end Contatore_1_cifra;
architecture V0 of Contatore_1_cifra is
signal C : unsigned(3 downto 0);
begin
p1:process(Clock)
begin
if rising_edge(Clock) then
if (Reset='1') then
C<=(others =>'0');
else
if (Preset='1') then
C<= unsigned(N_preset);
else
if (Enable_in='1') then
if (UpDown='1') then
if (C=9) then
C<=(others =>'0');
else
C<= C+1;
end if;
else
if (C=0) then
C<="1001";
else
C<= C-1;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
Enable_out <= '1' when Enable_in='1' and ((C=9 and UpDown='1') or (C=0 and UpDown='0')) else '0';
N<= std_logic_vector(C);
end V0; | gpl-3.0 | d1c4cb03889068cbc601031300ba5225 | 0.585041 | 2.616622 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.a-fetch.core/a.b.a.a-IRAM_block.vhd | 1 | 2,154 | ------------------------------------------------------------------------------
-- IRAM_block
-- This unit is the top-level entity which contains:
-- - MMU_in_IRAM
-- - MMU_out_IRAM
-- It is in charge for data exchange with the IRAM
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity iram_block is
port (
-- INPUTS
from_pc : in std_logic_vector(31 downto 0); -- address coming from the pc
flush : in std_logic; -- control signal for flushing the pipeline
from_iram : in std_logic_vector(31 downto 0); -- instruction from IRAM
-- OUTPUTS
to_iram : out std_logic_vector(31 downto 0); -- instruction address
to_if_id_reg : out std_logic_vector(31 downto 0) -- instruction to be decoded
);
end iram_block;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture structural of iram_block is
-- Components declaration
component mmu_in_iram is
port (
-- INPTUS
from_pc : in std_logic_vector(31 downto 0); -- address coming from the pc register
-- OUTPUTS
to_iram : out std_logic_vector(31 downto 0) -- address to the IRAM
);
end component;
component mmu_out_iram is
port (
-- INPTUS
from_iram : in std_logic_vector(31 downto 0); -- instruction to be decoded
flush : in std_logic; -- contorl singnal coming from MEM stage to fluhs the pipeline
-- OUTPUTS
to_if_id_reg : out std_logic_vector(31 downto 0) -- value propagated to the pipeline register
);
end component;
-- Internal Signals
begin
-- Components instantiation
mmu_in: mmu_in_iram port map ( from_pc => from_pc,
to_iram => to_iram);
mmu_out: mmu_out_iram port map ( from_iram => from_iram,
flush => flush,
to_if_id_reg => to_if_id_reg);
end structural;
| mit | 0507b75636335371d889284dd32e0d5c | 0.504643 | 3.867145 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/platform/almaif_axi_expander.vhdl | 2 | 10,295 | -- Copyright (c) 2016-2018 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : AlmaIF memory bus expander
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : almaif_expander.vhdl
-- Author : Aleksi Tervo <[email protected]>
-- Company : TUT/CPC
-- Created : 2016-11-22
-- Last update: 2016-11-22
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Acts as glue between one port of a dual-port memory and the
-- memory bus from AXI
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-22 1.0 tervoa Created
-- 2017-04-26 1.1 tervoa Sensitivity list fix
-- 2017-06-01 1.2 tervoa Converted to memory buses with handshaking
-- 2017-06-27 1.3 tervoa Split arbiter in two parts: between TTA cores
-- and between the multicore TTA and AXI
-- 2017-10-22 1.4 tervoa Changed to dual-port memory, no need for
-- arbiting
-- 2018-01-15 1.5 tervoa Fix typo in signal name
-- 2018-07-30 1.6 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tce_util.all;
entity almaif_axi_expander is
generic (
mem_dataw_g : integer;
mem_addrw_g : integer;
axi_dataw_g : integer;
axi_addrw_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
-- Bus to AXI if
axi_avalid_in : in std_logic;
axi_aready_out : out std_logic;
axi_aaddr_in : in std_logic_vector(axi_addrw_g-2-1 downto 0);
axi_awren_in : in std_logic;
axi_astrb_in : in std_logic_vector((axi_dataw_g+7)/8-1 downto 0);
axi_adata_in : in std_logic_vector(axi_dataw_g-1 downto 0);
axi_rvalid_out : out std_logic;
axi_rready_in : in std_logic;
axi_rdata_out : out std_logic_vector(axi_dataw_g-1 downto 0);
-- Bus to memory
mem_avalid_out : out std_logic;
mem_aready_in : in std_logic;
mem_aaddr_out : out std_logic_vector(mem_addrw_g-1 downto 0);
mem_awren_out : out std_logic;
mem_astrb_out : out std_logic_vector((mem_dataw_g+7)/8-1 downto 0);
mem_adata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
mem_rvalid_in : in std_logic;
mem_rready_out : out std_logic;
mem_rdata_in : in std_logic_vector(mem_dataw_g-1 downto 0)
);
end almaif_axi_expander;
architecture rtl of almaif_axi_expander is
constant sync_reset_c : boolean := sync_reset_g /= 0;
constant mem_word_width_c : integer := -- ceil(mem_dataw_g/axi_dataw_g)
(mem_dataw_g+axi_dataw_g-1)/axi_dataw_g;
constant mem_word_sel_c : integer := bit_width(mem_word_width_c);
constant axi_bytes_c : integer := (axi_dataw_g+7)/8;
constant mem_bytes_c : integer := (mem_dataw_g+7)/8;
constant fifo_depth_log2_c : integer := 2;
-- AXI signals padded to memory data width
signal axi_astrb_padded : std_logic_vector((mem_dataw_g+7)/8-1 downto 0);
signal axi_adata_padded : std_logic_vector(mem_dataw_g-1 downto 0);
signal axi_aaddr_stripped : std_logic_vector(mem_aaddr_out'range);
signal axi_word_sel : std_logic_vector(mem_word_sel_c-1 downto 0);
signal axi_rdata_padded : std_logic_vector(axi_dataw_g*mem_word_width_c-1
downto 0);
-- FIFO implemented as a shifted register array
type fifo_array_t is array (natural range <>)
of std_logic_vector(mem_word_sel_c-1 downto 0);
signal fifo_data_r : fifo_array_t(2**fifo_depth_log2_c-1 downto 0);
signal fifo_iter_r : unsigned(fifo_depth_log2_c-1 downto 0);
signal fifo_word_sel : std_logic_vector(mem_word_sel_c-1 downto 0);
begin
------------------------------------------------------------------------------
-- AXI signal glue: pad adata and astrb to memory width, strip aaddr to
-- meaninful width for memory
------------------------------------------------------------------------------
axi_expand : process(axi_adata_in, axi_astrb_in, axi_word_sel, mem_rdata_in,
axi_aaddr_in)
variable adata_pad_v : std_logic_vector(axi_dataw_g*mem_word_width_c-1
downto 0);
variable astrb_pad_v : std_logic_vector(axi_bytes_c*mem_word_width_c-1
downto 0);
variable rdata_pad_v : std_logic_vector(axi_dataw_g*mem_word_width_c-1
downto 0);
begin
adata_pad_v := (others => '0');
astrb_pad_v := (others => '0');
axi_word_sel <= axi_aaddr_in(mem_word_sel_c-1 downto 0);
for I in mem_word_width_c-1 downto 0 loop
adata_pad_v(axi_dataw_g*(I+1)-1 downto axi_dataw_g*I) := axi_adata_in;
if to_integer(unsigned(axi_word_sel)) = I or mem_word_width_c = 1 then
astrb_pad_v(axi_bytes_c*(I+1)-1 downto axi_bytes_c*I)
:= axi_astrb_in;
end if;
end loop;
axi_adata_padded <= adata_pad_v(axi_adata_padded'range);
axi_astrb_padded <= astrb_pad_v(axi_astrb_padded'range);
if mem_word_width_c = 1 then
axi_aaddr_stripped <= axi_aaddr_in(mem_addrw_g-1 downto 0);
else
axi_aaddr_stripped <= axi_aaddr_in(mem_addrw_g+mem_word_sel_c-1
downto mem_word_sel_c);
end if;
axi_rdata_padded <= (others => '0');
axi_rdata_padded(mem_rdata_in'range) <= mem_rdata_in;
end process;
------------------------------------------------------------------------------
-- Access channel:
------------------------------------------------------------------------------
mem_avalid_out <= axi_avalid_in;
axi_aready_out <= mem_aready_in;
mem_awren_out <= axi_awren_in;
mem_aaddr_out <= axi_aaddr_stripped;
mem_adata_out <= axi_adata_padded;
mem_astrb_out <= axi_astrb_padded;
----------------------------------------------------------------------------
-- FIFO to keep track of reads' destinations
-- TODO: Handle FIFO filling up (not an issue with current mem model/alu?)
----------------------------------------------------------------------------
fifo_sync : process(clk, rstx)
variable fifo_data_v : fifo_array_t(fifo_data_r'range);
variable fifo_iter_v : unsigned(fifo_iter_r'range);
begin
if not sync_reset_c and rstx = '0' then
fifo_data_r <= (others => (others => '0'));
fifo_iter_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
fifo_data_r <= (others => (others => '0'));
fifo_iter_r <= (others => '0');
else
fifo_data_v := fifo_data_r;
fifo_iter_v := fifo_iter_r;
if mem_rvalid_in = '1' and axi_rready_in = '1' and fifo_iter_r > 0 then
fifo_data_v(fifo_data_v'high-1 downto 0) :=
fifo_data_v(fifo_data_v'high downto 1);
fifo_data_v(fifo_data_v'high) := (others => '0');
fifo_iter_v := fifo_iter_v - 1;
end if;
if axi_avalid_in = '1' and mem_aready_in = '1' and axi_awren_in = '0' then
fifo_data_v(to_integer(fifo_iter_v)) := axi_word_sel;
fifo_iter_v := fifo_iter_v + 1;
end if;
fifo_iter_r <= fifo_iter_v;
fifo_data_r <= fifo_data_v;
end if;
end if;
end process fifo_sync;
fifo_word_sel <= fifo_data_r(0);
------------------------------------------------------------------------------
-- Response channel mux:
-- TODO: Handle reset better; works with local memory but will cause issues
-- w/ axi
------------------------------------------------------------------------------
rmux : process (fifo_word_sel, axi_rdata_padded)
variable dst_sel_int : integer;
begin
if mem_word_width_c = 1 then
axi_rdata_out <= axi_rdata_padded;
else
dst_sel_int := to_integer(unsigned(fifo_word_sel));
axi_rdata_out <= axi_rdata_padded(axi_dataw_g*(dst_sel_int+1)-1
downto axi_dataw_g*dst_sel_int);
end if;
end process rmux;
mem_rready_out <= axi_rready_in;
axi_rvalid_out <= mem_rvalid_in;
------------------------------------------------------------------------------
-- Design-wide checks:
------------------------------------------------------------------------------
-- coverage off
-- pragma translate_off
assert axi_addrw_g >= 2+mem_addrw_g+mem_word_sel_c
report "AXI address width is too short to encode all the addresses"
severity failure;
assert mem_dataw_g >= axi_dataw_g
report "Memory data width must be greater than or equal to AXI data width"
severity failure;
-- pragma translate_on
-- coverage on
end architecture rtl;
| mit | 17c4680df7fbc327375353b65e954c03 | 0.546382 | 3.55982 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/platform/xilinx_dp_blockram.vhdl | 2 | 9,101 | -- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx dual-port BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_do_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_dp_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- PORT A -------------------------------------------------------
-- Access channel
a_avalid_in : in std_logic;
a_aready_out : out std_logic;
a_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
a_awren_in : in std_logic;
a_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
a_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
a_rvalid_out : out std_logic;
a_rready_in : in std_logic;
a_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
-- PORT B -------------------------------------------------------
-- Access channel
b_avalid_in : in std_logic;
b_aready_out : out std_logic;
b_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
b_awren_in : in std_logic;
b_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
b_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
b_rvalid_out : out std_logic;
b_rready_in : in std_logic;
b_rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_dp_blockram;
architecture rtl of xilinx_dp_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
constant adata_padding_c : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal a_addr, b_addr : unsigned(addrw_g-1 downto 0);
signal a_wdata, b_wdata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_ram_rdata_r, b_ram_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_enable, b_enable : std_logic;
signal a_strb, b_strb : std_logic_vector(astrb_width_c-1 downto 0);
signal a_adata, b_adata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_aready_r, b_aready_r : std_logic;
signal a_live_read, b_live_read : std_logic;
signal a_live_read_r, b_live_read_r : std_logic;
signal a_rdata_r, b_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_rdata_valid_r, b_rdata_valid_r : std_logic;
signal a_rvalid, b_rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
shared variable RAM_ARR : ram_type;
begin
control_comb_a : process(a_aaddr_in, a_avalid_in, a_aready_r, a_awren_in,
a_astrb_in, a_live_read_r, a_rdata_valid_r)
begin
if a_avalid_in = '1' and a_aready_r = '1' then
a_enable <= '1';
if a_awren_in = '1' then
a_strb <= a_astrb_in;
a_live_read <= '0';
else
a_strb <= (others => '0');
a_live_read <= '1';
end if;
else
a_strb <= (others => '0');
a_enable <= '0';
a_live_read <= '0';
end if;
a_addr <= unsigned(a_aaddr_in);
a_rvalid <= a_live_read_r or a_rdata_valid_r;
end process;
control_comb_b : process(b_aaddr_in, b_avalid_in, b_aready_r, b_awren_in,
b_astrb_in, b_live_read_r, b_rdata_valid_r)
begin
if b_avalid_in = '1' and b_aready_r = '1' then
b_enable <= '1';
if b_awren_in = '1' then
b_strb <= b_astrb_in;
b_live_read <= '0';
else
b_strb <= (others => '0');
b_live_read <= '1';
end if;
else
b_strb <= (others => '0');
b_enable <= '0';
b_live_read <= '0';
end if;
b_addr <= unsigned(b_aaddr_in);
b_rvalid <= b_live_read_r or b_rdata_valid_r;
end process;
control_sync_a : process(clk, rstx)
begin
if rstx = '0' then
a_live_read_r <= '0';
a_aready_r <= '0';
a_rdata_valid_r <= '0';
a_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if a_rvalid = '1' and a_rready_in = '1' then
a_rdata_valid_r <= '0';
end if;
if a_rvalid = '1' and a_rready_in = '0' then
a_aready_r <= '0';
else
a_aready_r <= '1';
end if;
a_live_read_r <= a_live_read or a_live_read_r;
if a_live_read_r = '1' and (a_rready_in = '1' or a_rdata_valid_r = '0') then
a_live_read_r <= a_live_read;
if a_rready_in = '0' or a_rdata_valid_r = '1' then
a_rdata_valid_r <= '1';
a_rdata_r <= a_ram_rdata_r;
end if;
end if;
end if;
end process;
control_sync_b : process(clk, rstx)
begin
if rstx = '0' then
b_live_read_r <= '0';
b_aready_r <= '0';
b_rdata_valid_r <= '0';
b_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if b_rvalid = '1' and b_rready_in = '1' then
b_rdata_valid_r <= '0';
end if;
if b_rvalid = '1' and b_rready_in = '0' then
b_aready_r <= '0';
else
b_aready_r <= '1';
end if;
b_live_read_r <= b_live_read or b_live_read_r;
if b_live_read_r = '1' and (b_rready_in = '1' or b_rdata_valid_r = '0') then
b_live_read_r <= b_live_read;
if b_rready_in = '0' or b_rdata_valid_r = '1' then
b_rdata_valid_r <= '1';
b_rdata_r <= b_ram_rdata_r;
end if;
end if;
end if;
end process;
a_wdata <= adata_padding_c & a_adata_in;
b_wdata <= adata_padding_c & b_adata_in;
RAM_A : process(clk)
begin
if rising_edge(clk) then
if a_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if a_strb(i) = '1' then
RAM_ARR(to_integer(a_addr))((i+1)*8-1 downto i*8)
:= a_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
a_ram_rdata_r <= RAM_ARR(to_integer(a_addr));
end if;
end if;
end process;
RAM_B : process(clk)
begin
if rising_edge(clk) then
if b_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if b_strb(i) = '1' then
RAM_ARR(to_integer(b_addr))((i+1)*8-1 downto i*8)
:= b_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
b_ram_rdata_r <= RAM_ARR(to_integer(b_addr));
end if;
end if;
end process;
a_rdata_out <= a_ram_rdata_r(a_rdata_out'range) when a_rdata_valid_r = '0'
else a_rdata_r(a_rdata_out'range);
b_rdata_out <= b_ram_rdata_r(b_rdata_out'range) when b_rdata_valid_r = '0'
else b_rdata_r(b_rdata_out'range);
a_aready_out <= a_aready_r;
a_rvalid_out <= a_rvalid;
b_aready_out <= b_aready_r;
b_rvalid_out <= b_rvalid;
end architecture rtl; | mit | 6f5e9f097753825e0cfdebbe47dad30e | 0.523459 | 3.21363 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.d-IRAM.vhd | 1 | 1,544 | -- IRAM, not synth.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity IRAM is
generic (
RAM_DEPTH : integer := 128;
I_SIZE : integer := 32);
port (
Rst : in std_logic;
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end IRAM;
architecture IRam_Bhe of IRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0);
signal IRAM_mem : RAMtype;
begin -- IRam_Bhe
Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))),I_SIZE);
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: IRAM_mem
FILL_MEM_P: process (Rst)
file mem_fp: text;
variable file_line : line;
variable index : integer := 0;
variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(mem_fp,"test.asm.mem",READ_MODE);
while (not endfile(mem_fp)) loop
readline(mem_fp,file_line);
hread(file_line,tmp_data_u);
IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u));
index := index + 1;
end loop;
end if;
end process FILL_MEM_P;
end IRam_Bhe;
| mit | d597eee47cf002de869699b667d4e283 | 0.619171 | 3.236897 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/wbbootloadermux.vhd | 1 | 2,732 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end entity wbbootloadermux;
architecture behave of wbbootloadermux is
signal select_zero: std_logic;
begin
select_zero<='0' when sel='1' else '1';
s0_wb_dat_o <= m_wb_dat_i;
s0_wb_adr_o <= m_wb_adr_i;
s0_wb_stb_o <= m_wb_stb_i;
s0_wb_we_o <= m_wb_we_i;
s0_wb_cti_o <= m_wb_cti_i;
s0_wb_sel_o <= m_wb_sel_i;
s1_wb_dat_o <= m_wb_dat_i;
s1_wb_adr_o <= m_wb_adr_i(11 downto 2);
s1_wb_stb_o <= m_wb_stb_i;
s1_wb_we_o <= m_wb_we_i;
s1_wb_cti_o <= m_wb_cti_i;
s1_wb_sel_o <= m_wb_sel_i;
process(m_wb_cyc_i,select_zero)
begin
if m_wb_cyc_i='0' then
s0_wb_cyc_o<='0';
s1_wb_cyc_o<='0';
else
s0_wb_cyc_o<=select_zero;
s1_wb_cyc_o<=not select_zero;
end if;
end process;
process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i,s0_wb_stall_i,s1_wb_stall_i)
begin
if select_zero='0' then
m_wb_dat_o<=s1_wb_dat_i;
m_wb_ack_o<=s1_wb_ack_i;
m_wb_stall_o<=s1_wb_stall_i;
else
m_wb_dat_o<=s0_wb_dat_i;
m_wb_ack_o<=s0_wb_ack_i;
m_wb_stall_o<=s0_wb_stall_i;
end if;
end process;
end behave;
| mit | 2158f5d30b0a2897b0788d61d62e94ed | 0.621523 | 2.208569 | false | false | false | false |
kgugala/axi-coprocessor-interface-hw | project_1.srcs/sources_1/edk/module_1/pcores/coprocessor_v2_00_a/hdl/vhdl/coprocessor.vhd | 1 | 23,498 | ------------------------------------------------------------------------------
-- coprocessor.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: coprocessor.vhd
-- Version: 2.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Nov 23 17:12:23 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_slave_burst_v1_00_a;
use axi_slave_burst_v1_00_a.axi_slave_burst;
library coprocessor_v2_00_a;
use coprocessor_v2_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4 slave: Data Width
-- C_S_AXI_ADDR_WIDTH -- AXI4 slave: Address Width
-- C_S_AXI_ID_WIDTH -- AXI4 slave: ID Width
-- C_RDATA_FIFO_DEPTH -- AXI4 slave: FIFO Depth
-- C_INCLUDE_TIMEOUT_CNT -- AXI4 slave: Data Timeout Count
-- C_TIMEOUT_CNTR_VAL -- AXI4 slave: Timeout Counter Value
-- C_ALIGN_BE_RDADDR -- AXI4 slave: Align Byte Enable read Data Address
-- C_S_AXI_SUPPORTS_WRITE -- AXI4 slave: Support Write
-- C_S_AXI_SUPPORTS_READ -- AXI4 slave: Support Read
-- C_FAMILY -- FPGA Family
-- C_S_AXI_MEM0_BASEADDR -- User memory space 0 base address
-- C_S_AXI_MEM0_HIGHADDR -- User memory space 0 high address
-- C_S_AXI_MEM1_BASEADDR -- User memory space 1 base address
-- C_S_AXI_MEM1_HIGHADDR -- User memory space 1 high address
-- C_S_AXI_MEM2_BASEADDR -- User memory space 2 base address
-- C_S_AXI_MEM2_HIGHADDR -- User memory space 2 high address
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4 slave: Clock
-- S_AXI_ARESETN -- AXI4 slave: Reset
-- S_AXI_AWADDR -- AXI4 slave: Write address
-- S_AXI_AWVALID -- AXI4 slave: Write address valid
-- S_AXI_WDATA -- AXI4 slave: Write data
-- S_AXI_WSTRB -- AXI4 slave: Write strobe
-- S_AXI_WVALID -- AXI4 slave: Write data valid
-- S_AXI_BREADY -- AXI4 slave: read response ready
-- S_AXI_ARADDR -- AXI4 slave: read address
-- S_AXI_ARVALID -- AXI4 slave: read address valid
-- S_AXI_RREADY -- AXI4 slave: read data ready
-- S_AXI_ARREADY -- AXI4 slave: read address ready
-- S_AXI_RDATA -- AXI4 slave: read data
-- S_AXI_RRESP -- AXI4 slave: read data response
-- S_AXI_RVALID -- AXI4 slave: read data valid
-- S_AXI_WREADY -- AXI4 slave: write data ready
-- S_AXI_BRESP -- AXI4 slave: read response
-- S_AXI_BVALID -- AXI4 slave: read response valid
-- S_AXI_AWREADY -- AXI4 slave: write address ready
-- S_AXI_AWID -- AXI4 slave: write address ID
-- S_AXI_AWLEN -- AXI4 slave: write address Length
-- S_AXI_AWSIZE -- AXI4 slave: write address size
-- S_AXI_AWBURST -- AXI4 slave: write address burst
-- S_AXI_AWLOCK -- AXI4 slave: write address lock
-- S_AXI_AWCACHE -- AXI4 slave: write address cache
-- S_AXI_AWPROT -- AXI4 slave: write address protection
-- S_AXI_WLAST -- AXI4 slave: write data last
-- S_AXI_BID -- AXI4 slave: read response ID
-- S_AXI_ARID -- AXI4 slave: read address ID
-- S_AXI_ARLEN -- AXI4 slave: read address Length
-- S_AXI_ARSIZE -- AXI4 slave: read address size
-- S_AXI_ARBURST -- AXI4 slave: read address burst
-- S_AXI_ARLOCK -- AXI4 slave: read address lock
-- S_AXI_ARCACHE -- AXI4 slave: read address cache
-- S_AXI_ARPROT -- AXI4 slave: read address protection
-- S_AXI_RID -- AXI4 slave: read data ID
-- S_AXI_RLAST -- AXI4 slave: read data last
------------------------------------------------------------------------------
entity coprocessor is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_ID_WIDTH : integer := 4;
C_RDATA_FIFO_DEPTH : integer := 0;
C_INCLUDE_TIMEOUT_CNT : integer := 1;
C_TIMEOUT_CNTR_VAL : integer := 8;
C_ALIGN_BE_RDADDR : integer := 0;
C_S_AXI_SUPPORTS_WRITE : integer := 1;
C_S_AXI_SUPPORTS_READ : integer := 1;
C_FAMILY : string := "virtex6";
C_S_AXI_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_S_AXI_MEM0_HIGHADDR : std_logic_vector := X"00000000";
C_S_AXI_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_S_AXI_MEM1_HIGHADDR : std_logic_vector := X"00000000";
C_S_AXI_MEM2_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_S_AXI_MEM2_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
led_out : out std_logic_vector(7 downto 0);
sw_in : in std_logic_vector(7 downto 0);
btn_in : in std_logic_vector(4 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RLAST : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity coprocessor;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of coprocessor is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_S_AXI_MEM0_BASEADDR,-- user logic memory space 0 base address
ZERO_ADDR_PAD & C_S_AXI_MEM0_HIGHADDR,-- user logic memory space 0 high address
ZERO_ADDR_PAD & C_S_AXI_MEM1_BASEADDR,-- user logic memory space 1 base address
ZERO_ADDR_PAD & C_S_AXI_MEM1_HIGHADDR,-- user logic memory space 1 high address
ZERO_ADDR_PAD & C_S_AXI_MEM2_BASEADDR,-- user logic memory space 2 base address
ZERO_ADDR_PAD & C_S_AXI_MEM2_HIGHADDR -- user logic memory space 2 high address
);
constant USER_NUM_MEM : integer := 3;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
1 => 1, -- number of ce for user logic memory space 1 (always 1 chip enable)
2 => 1 -- number of ce for user logic memory space 2 (always 1 chip enable)
);
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_S_AXI_ADDR_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_MEM0_CS_INDEX : integer := 0;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Burst : std_logic;
signal ipif_Bus2IP_BurstLength : std_logic_vector(7 downto 0);
signal ipif_Bus2IP_WrReq : std_logic;
signal ipif_Bus2IP_RdReq : std_logic;
signal ipif_IP2Bus_AddrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Type_of_xfer : std_logic;
signal user_Bus2IP_BurstLength : std_logic_vector(7 downto 0) := (others => '0');
signal user_IP2Bus_AddrAck : std_logic;
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_slave_burst
------------------------------------------
AXI_SLAVE_BURST_I : entity axi_slave_burst_v1_00_a.axi_slave_burst
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH,
C_RDATA_FIFO_DEPTH => C_RDATA_FIFO_DEPTH,
C_INCLUDE_TIMEOUT_CNT => C_INCLUDE_TIMEOUT_CNT,
C_TIMEOUT_CNTR_VAL => C_TIMEOUT_CNTR_VAL,
C_ALIGN_BE_RDADDR => C_ALIGN_BE_RDADDR,
C_S_AXI_SUPPORTS_WRITE => C_S_AXI_SUPPORTS_WRITE,
C_S_AXI_SUPPORTS_READ => C_S_AXI_SUPPORTS_READ,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWLOCK => S_AXI_AWLOCK,
S_AXI_AWCACHE => S_AXI_AWCACHE,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_WLAST => S_AXI_WLAST,
S_AXI_BID => S_AXI_BID,
S_AXI_ARID => S_AXI_ARID,
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARLOCK => S_AXI_ARLOCK,
S_AXI_ARCACHE => S_AXI_ARCACHE,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_RID => S_AXI_RID,
S_AXI_RLAST => S_AXI_RLAST,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_Burst => ipif_Bus2IP_Burst,
Bus2IP_BurstLength => ipif_Bus2IP_BurstLength,
Bus2IP_WrReq => ipif_Bus2IP_WrReq,
Bus2IP_RdReq => ipif_Bus2IP_RdReq,
IP2Bus_AddrAck => ipif_IP2Bus_AddrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data,
Type_of_xfer => ipif_Type_of_xfer
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity coprocessor_v2_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_AWIDTH => USER_SLV_AWIDTH,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_MEM => USER_NUM_MEM
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
led_out => led_out,
sw_in => sw_in,
btn_in => btn_in,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS(USER_NUM_MEM-1 downto 0),
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Burst => ipif_Bus2IP_Burst,
Bus2IP_BurstLength => user_Bus2IP_BurstLength,
Bus2IP_RdReq => ipif_Bus2IP_RdReq,
Bus2IP_WrReq => ipif_Bus2IP_WrReq,
Type_of_xfer => ipif_Type_of_xfer,
IP2Bus_AddrAck => user_IP2Bus_AddrAck,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "100" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_AddrAck <= user_IP2Bus_AddrAck;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_BurstLength(7 downto 0)<= ipif_Bus2IP_BurstLength(7 downto 0);
end IMP;
| mit | fdd87b8a56bb0b0ae4924245097e1109 | 0.460167 | 3.95323 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Wing_Audio.vhd | 13 | 1,306 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_Audio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Audio is
port (
audio_left : in std_logic;
audio_right : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Audio;
architecture Behavioral of Wing_Audio is
begin
wt_miso(0) <= audio_right;
wt_miso(1) <= audio_left;
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= wt_mosi(5);
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= wt_mosi(7);
end Behavioral;
| mit | 49cd569e158105d48ebefd46e8b05931 | 0.578867 | 3.314721 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.h-EX-MEM_Reg.vhd | 2 | 2,186 | library ieee;
use ieee.std_logic_1164.all;
-- synchronous reset register
entity EX_MEM_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(10 downto 0); -- 11 control signals go from exe to mem stage
toPC1_in : in std_logic_vector(31 downto 0); -- from jreg controlled mux
toPC2_in : in std_logic_vector(31 downto 0); -- from adder2
takeBranch_in : in std_logic; -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in : in std_logic_vector(31 downto 0);
mem_writedata_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(10 downto 0);
toPC1_out : out std_logic_vector(31 downto 0);
toPC2_out : out std_logic_vector(31 downto 0);
takeBranch_out : out std_logic;
mem_addr_out : out std_logic_vector(31 downto 0);
mem_writedata_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end EX_MEM_Reg;
architecture rtl of EX_MEM_Reg is
begin
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
controls_out <= (others => '0');
toPC1_out <= (others => '0');
toPC2_out <= (others => '0');
takeBranch_out <= '0';
mem_addr_out <= (others => '0');
mem_writedata_out <= (others => '0');
regfile_addr_out <= (others => '0');
else
controls_out <= controls_in;
toPC1_out <= toPC1_in;
toPC2_out <= toPC2_in;
takeBranch_out <= takeBranch_in;
mem_addr_out <= mem_addr_in;
mem_writedata_out <= mem_writedata_in;
regfile_addr_out <= regfile_addr_in;
end if;
end if;
end process;
end rtl;
| mit | cc80c952fe371b8a07f5b69aae1be246 | 0.52699 | 3.589491 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/wbarb2_1.vhd | 1 | 3,654 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_stall_o: out std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end entity wbarb2_1;
architecture behave of wbarb2_1 is
signal current_master: std_logic;
signal next_master: std_logic;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
current_master <= '0';
else
current_master <= next_master;
end if;
end if;
end process;
process(current_master, m0_wb_cyc_i, m1_wb_cyc_i)
begin
next_master <= current_master;
case current_master is
when '0' =>
if m0_wb_cyc_i='0' then
if m1_wb_cyc_i='1' then
next_master <= '1';
end if;
end if;
when '1' =>
if m1_wb_cyc_i='0' then
if m0_wb_cyc_i='1' then
next_master <= '0';
end if;
end if;
when others =>
end case;
end process;
-- Muxers for slave
process(current_master,
m0_wb_dat_i, m0_wb_adr_i, m0_wb_sel_i, m0_wb_cti_i, m0_wb_we_i, m0_wb_cyc_i, m0_wb_stb_i,
m1_wb_dat_i, m1_wb_adr_i, m1_wb_sel_i, m1_wb_cti_i, m1_wb_we_i, m1_wb_cyc_i, m1_wb_stb_i)
begin
case current_master is
when '0' =>
s0_wb_dat_o <= m0_wb_dat_i;
s0_wb_adr_o <= m0_wb_adr_i;
s0_wb_sel_o <= m0_wb_sel_i;
s0_wb_cti_o <= m0_wb_cti_i;
s0_wb_we_o <= m0_wb_we_i;
s0_wb_cyc_o <= m0_wb_cyc_i;
s0_wb_stb_o <= m0_wb_stb_i;
when '1' =>
s0_wb_dat_o <= m1_wb_dat_i;
s0_wb_adr_o <= m1_wb_adr_i;
s0_wb_sel_o <= m1_wb_sel_i;
s0_wb_cti_o <= m1_wb_cti_i;
s0_wb_we_o <= m1_wb_we_i;
s0_wb_cyc_o <= m1_wb_cyc_i;
s0_wb_stb_o <= m1_wb_stb_i;
when others =>
null;
end case;
end process;
-- Muxers/sel for masters
m0_wb_dat_o <= s0_wb_dat_i;
m1_wb_dat_o <= s0_wb_dat_i;
-- Ack
m0_wb_ack_o <= s0_wb_ack_i when current_master='0' else '0';
m1_wb_ack_o <= s0_wb_ack_i when current_master='1' else '0';
m0_wb_stall_o <= s0_wb_stall_i when current_master='0' else '1';
m1_wb_stall_o <= s0_wb_stall_i when current_master='1' else '1';
end behave;
| mit | 3b0a56b3c1f0736cf0524339d269aea0 | 0.596606 | 2.321474 | false | false | false | false |
ordepmalo/matrizled | rtl/vhdl/matrizled.vhd | 1 | 2,102 | -------------------------------------------------------------------------------
-- Title : project top file
-- Project :
-------------------------------------------------------------------------------
-- File : matrizled.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created : 2015-04-28
-- Last update : 2015-04-29
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-28 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity matrizled is
port (
sysclk : in std_logic;
reset_n : in std_logic;
data_i : in std_logic_vector(17 downto 0);
serial_o : out std_logic;
clk_o : out std_logic;
stb_o : out std_logic);
end entity matrizled;
architecture matrizled_rtl of matrizled is
signal sel_int : std_logic_vector(4 downto 0);
signal enable_int : std_logic;
begin -- architecture matrizled_rtl
multiplexer_inst1 : entity work.multiplexer
generic map (
N_INPUTS => 18)
port map (
data_32_i => data_i,
sel_i => sel_int,
out_o => serial_o);
clk_divider_inst1 : entity work.clk_divider
generic map (
MAX_VALUE => 20)
port map (
sysclk => sysclk,
reset_n => reset_n,
clk_divider_o => enable_int);
interface_inst1 : entity work.interface
generic map (
MAX_VALUE => 18,
MAX_VALUE_BITS => 5)
port map (
sysclk => sysclk,
reset_n => reset_n,
en_i => enable_int,
ctrl_o => sel_int,
stb_o => stb_o,
clk => clk_o);
end architecture matrizled_rtl;
| mit | 2105d0e084aa8f092295562bf1bc7c81 | 0.436727 | 4.121569 | false | false | false | false |
purisc-group/purisc | Compute_Group/CORE/read_data_stage.vhd | 1 | 1,513 | library ieee;
use ieee.std_logic_1164.all;
entity read_data_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
noop_in : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 0);
a_out : out std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
ubranch_out : out std_logic;
noop_out : out std_logic;
r_addr_0 : out std_logic_vector(31 downto 0);
r_addr_1 : out std_logic_vector(31 downto 0);
pc_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture a1 of read_data_stage is
--signals
signal ubranch : std_logic;
--components
begin
ubranch_out <= ubranch;
process(clk, reset_n) begin
if (reset_n = '0') then
--on boot
noop_out <= '1';
ubranch <= '0';
r_addr_0 <= "00000000000000000000000000000000";
r_addr_1 <= "00000000000000000000000000000000";
elsif (rising_edge(clk)) then
if(stall = '0') then
--check for unconditional branch
if(a_in = b_in and not(pc = c_in) and not(ubranch = '1')) then
ubranch <= '1';
else
ubranch <= '0';
end if;
noop_out <= noop_in;
a_out <= a_in;
b_out <= b_in;
c_out <= c_in;
r_addr_0 <= a_in;
r_addr_1 <= b_in;
pc_out <= pc;
else
--hold previous outputs on stall (automatic)
end if;
end if;
end process;
end architecture; | gpl-2.0 | a936b0524b03e122d6426657b17c3453 | 0.621943 | 2.649737 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.d-memory.core/a.b.d.a-DRAM_block.core/a.b.d.a.a-DRAM.vhd | 1 | 3,186 | -----------------------------------------------------------------------------------------------------------------
-- Data RAM
-- This block implements a Data RAM. The address are not aligned, in contrast with the CPU which provides
-- word-aligned addresses and half-word-aligned addresses. Thus a MMU is needed (MMU_in and MMU_out).
-- Read/Write Operation are controlled by the control signal write and read.
-- Note bytes are stored according to the Big Edian format in case of a store of a one single byte
-----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
---------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------
entity ram_block is
generic (
width : integer := 32; -- data size 8 bit
depth : integer := 256; -- number of cells is 256
addr : integer := 32);
port (
read_op : in std_logic;
write_op : in std_logic;
rst : in std_logic;
nibble : in std_logic_vector(1 downto 0);
write_byte : in std_logic; --write operation on a single byte
Address : in std_logic_vector(addr - 1 downto 0);
Data_in : in std_logic_vector(width-1 downto 0);
Data_out : out std_logic_vector(width-1 downto 0)
);
end ram_block;
--------------------------------------------------------------------
--------------------------------------------------------------------
architecture Behavioral of ram_block is
type RAM_type is array(0 to depth-1) of std_logic_vector(width-1 downto 0);
signal tmp_ram : RAM_type; -- memory element, shared between processes, don't use a variable!
begin
-- Read functional section
process(read_op, Address)
begin
if(read_op = '1') then
Data_out <= tmp_ram(to_integer(unsigned(Address)));
end if;
end process;
-- Write functional section
process(write_op, rst, nibble, Data_in, Address, write_byte)
begin
if (rst = '1') then
tmp_ram <= (others => (others => '0'));
elsif (write_op = '1') then
if (write_byte = '1') then
case nibble is
when "00" =>
tmp_ram(to_integer(unsigned(Address)))(31 downto 24) <= Data_in(7 downto 0);
when "01" =>
tmp_ram(to_integer(unsigned(Address)))(23 downto 16) <= Data_in(7 downto 0);
when "10" =>
tmp_ram(to_integer(unsigned(Address)))(15 downto 8) <= Data_in(7 downto 0);
when "11" =>
tmp_ram(to_integer(unsigned(Address)))(7 downto 0) <= Data_in(7 downto 0);
when others =>
tmp_ram(to_integer(unsigned(Address))) <= Data_in;
end case;
else
tmp_ram(to_integer(unsigned(Address))) <= Data_in;
end if;
end if;
end process;
end Behavioral;
| mit | 2a3baf171cade28bda775f8bc959aeda | 0.470182 | 4.437326 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/Wishbone_Empty_Slot.vhd | 13 | 3,505 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library zpuino;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
entity Wishbone_Empty_Slot is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity Wishbone_Empty_Slot;
architecture behave of Wishbone_Empty_Slot is
-- signal wishbone_in_record : wishbone_bus_in_type;
-- signal wishbone_out_record : wishbone_bus_out_type;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Actual code for the module
-- wishbone_out_record.wb_ack_o <= wishbone_in_record.wb_cyc_i and wishbone_in_record.wb_stb_i;
wishbone_out(1) <= wishbone_in(1) and wishbone_in(0);
-- wishbone_out_record.wb_inta_o <= '0';
wishbone_out(0) <= '0';
-- wishbone_out_record.wb_dat_o <= (others => DontCareValue);
wishbone_out(33 downto 2) <= (others => DontCareValue);
end behave;
| mit | f5a8becdef0c217f4d1ad96dbe15514c | 0.650499 | 2.975382 | false | false | false | false |
purisc-group/purisc | Global_memory/MAGIC_global/create_opcode_global.vhd | 2 | 17,379 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity create_opcode_global is
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
W_EN : IN STD_LOGIC;
--OUTPUTS OF READS
OPCODE_0 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_1 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_2 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_3 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_4 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_5 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_6 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_7 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end;
architecture gen of create_opcode_global is
begin
OPCODE_0(5) <= not(COL_A(2)) and not(COL_A(1)) and not(COL_A(0));
OPCODE_1(5) <= not(COL_A(2)) and not(COL_A(1)) and (COL_A(0));
OPCODE_2(5) <= not(COL_A(2)) and (COL_A(1)) and not(COL_A(0));
OPCODE_3(5) <= not(COL_A(2)) and (COL_A(1)) and (COL_A(0));
OPCODE_4(5) <= (COL_A(2)) and not(COL_A(1)) and not(COL_A(0));
OPCODE_5(5) <= (COL_A(2)) and not(COL_A(1)) and (COL_A(0));
OPCODE_6(5) <= (COL_A(2)) and (COL_A(1)) and not(COL_A(0));
OPCODE_7(5) <= (COL_A(2)) and (COL_A(1)) and (COL_A(0));
OPCODE_0(4) <= not(COL_B(2)) and not(COL_B(1)) and not(COL_B(0));
OPCODE_1(4) <= not(COL_B(2)) and not(COL_B(1)) and (COL_B(0));
OPCODE_2(4) <= not(COL_B(2)) and (COL_B(1)) and not(COL_B(0));
OPCODE_3(4) <= not(COL_B(2)) and (COL_B(1)) and (COL_B(0));
OPCODE_4(4) <= (COL_B(2)) and not(COL_B(1)) and not(COL_B(0));
OPCODE_5(4) <= (COL_B(2)) and not(COL_B(1)) and (COL_B(0));
OPCODE_6(4) <= (COL_B(2)) and (COL_B(1)) and not(COL_B(0));
OPCODE_7(4) <= (COL_B(2)) and (COL_B(1)) and (COL_B(0));
OPCODE_0(3) <= not(COL_C(2)) and not(COL_C(1)) and not(COL_C(0));
OPCODE_1(3) <= not(COL_C(2)) and not(COL_C(1)) and (COL_C(0));
OPCODE_2(3) <= not(COL_C(2)) and (COL_C(1)) and not(COL_C(0));
OPCODE_3(3) <= not(COL_C(2)) and (COL_C(1)) and (COL_C(0));
OPCODE_4(3) <= (COL_C(2)) and not(COL_C(1)) and not(COL_C(0));
OPCODE_5(3) <= (COL_C(2)) and not(COL_C(1)) and (COL_C(0));
OPCODE_6(3) <= (COL_C(2)) and (COL_C(1)) and not(COL_C(0));
OPCODE_7(3) <= (COL_C(2)) and (COL_C(1)) and (COL_C(0));
OPCODE_0(2) <= not(COL_D(2)) and not(COL_D(1)) and not(COL_D(0));
OPCODE_1(2) <= not(COL_D(2)) and not(COL_D(1)) and (COL_D(0));
OPCODE_2(2) <= not(COL_D(2)) and (COL_D(1)) and not(COL_D(0));
OPCODE_3(2) <= not(COL_D(2)) and (COL_D(1)) and (COL_D(0));
OPCODE_4(2) <= (COL_D(2)) and not(COL_D(1)) and not(COL_D(0));
OPCODE_5(2) <= (COL_D(2)) and not(COL_D(1)) and (COL_D(0));
OPCODE_6(2) <= (COL_D(2)) and (COL_D(1)) and not(COL_D(0));
OPCODE_7(2) <= (COL_D(2)) and (COL_D(1)) and (COL_D(0));
OPCODE_0(1) <= not(COL_E(2)) and not(COL_E(1)) and not(COL_E(0));
OPCODE_1(1) <= not(COL_E(2)) and not(COL_E(1)) and (COL_E(0));
OPCODE_2(1) <= not(COL_E(2)) and (COL_E(1)) and not(COL_E(0));
OPCODE_3(1) <= not(COL_E(2)) and (COL_E(1)) and (COL_E(0));
OPCODE_4(1) <= (COL_E(2)) and not(COL_E(1)) and not(COL_E(0));
OPCODE_5(1) <= (COL_E(2)) and not(COL_E(1)) and (COL_E(0));
OPCODE_6(1) <= (COL_E(2)) and (COL_E(1)) and not(COL_E(0));
OPCODE_7(1) <= (COL_E(2)) and (COL_E(1)) and (COL_E(0));
OPCODE_0(0) <= (not(COL_W(2)) and not(COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_1(0) <= (not(COL_W(2)) and not(COL_W(1)) and (COL_W(0))) and W_EN;
OPCODE_2(0) <= (not(COL_W(2)) and (COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_3(0) <= (not(COL_W(2)) and (COL_W(1)) and (COL_W(0))) and W_EN;
OPCODE_4(0) <= ((COL_W(2)) and not(COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_5(0) <= ((COL_W(2)) and not(COL_W(1)) and (COL_W(0))) and W_EN;
OPCODE_6(0) <= ((COL_W(2)) and (COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_7(0) <= ((COL_W(2)) and (COL_W(1)) and (COL_W(0))) and W_EN;
-- process (COL_A, COL_B, COL_C, COL_D, COL_E, COL_W, W_EN) begin
-- --assigning address A to column
-- if (COL_A = 0) then
-- OPCODE_0(5) <= '1';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 1) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '1';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 2) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '1';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 3) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '1';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 4) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '1';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 5) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '1';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 6) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '1';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 7) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '1';
-- else
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- end if;
--
-- --assigning address B to column
-- if (COL_B = 0) then
-- OPCODE_0(4) <= '1';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 1) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '1';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 2) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '1';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 3) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '1';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 4) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '1';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 5) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '1';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 6) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '1';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 7) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '1';
-- else
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- end if;
--
-- --assigning address C to column
-- if (COL_C = 0) then
-- OPCODE_0(3) <= '1';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 1) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '1';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 2) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '1';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 3) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '1';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 4) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '1';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 5) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '1';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 6) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '1';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 7) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '1';
-- else
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- end if;
-- --assigning address D to column
-- if (COL_D = 0) then
-- OPCODE_0(2) <= '1';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 1) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '1';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 2) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '1';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 3) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '1';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 4) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '1';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 5) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '1';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 6) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '1';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 7) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '1';
-- else
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- end if;
-- --assigning address E to column
-- if (COL_E = 0) then
-- OPCODE_0(1) <= '1';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 1) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '1';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 2) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '1';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 3) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '1';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 4) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '1';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 5) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '1';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 6) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '1';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 7) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '1';
-- else
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- end if;
-- --assigning address W to column
-- if (COL_W = 0) then
-- OPCODE_0(0) <= '1' and W_EN;
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 1) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '1' and W_EN;
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 2) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '1' and W_EN;
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 3) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '1' and W_EN;
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 4) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '1' and W_EN;
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 5) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '1' and W_EN;
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 6) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '1' and W_EN;
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 7) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '1' and W_EN;
-- else
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- end if;
-- end process;
end gen; | gpl-2.0 | 39c428e9003539f096d290d6b6e3843d | 0.407618 | 1.913355 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_low_1/bg_low_sim_netlist.vhdl | 1 | 48,093 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_sim_netlist.vhdl
-- Design : bg_low
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_low_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_low_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"1C001C001C001C0024001C001C001C001C001C001C001C001C001C001C001C00",
INIT_01 => X"1D041D041D041D041D041D041C001C0024001C001C001C001C001C001C001C00",
INIT_02 => X"1D041D041D041D041D041D041D041D041D041D041D041D041D041D041D041D04",
INIT_03 => X"2C001D041D0434001D041D0434001D041D0434001D041D041D041D041D041D04",
INIT_04 => X"353735371D041D042C001D041D0434001D041D0434001D041D0434001D041D04",
INIT_05 => X"3E0835373E083E0835373537353735373E083E0835373E083E0835373E083E08",
INIT_06 => X"1D373E081D373E081D371D371D373E0835373537353735373E083E0835373E08",
INIT_07 => X"35373E081D371D371D373E081D373E081D371D371D373E0835373E081D371D37",
INIT_08 => X"35371D373E081D37353735373537261935373E081D37353735371D371D373E08",
INIT_09 => X"353700002619353735371D373E081D37353735373537261935373E081D373537",
INIT_0A => X"1D371D3735373537353700002619353704011D3735371D371D371D3735373537",
INIT_0B => X"2619261926193E0826192619261926193E0826192619353704011D3735371D37",
INIT_0C => X"3E08261926193E082619261926193E0826192619261926193E08261926193E08",
INIT_0D => X"3E083E0826192E3B3E0826192E3B3E0826193E082E3B26193E083E0826192E3B",
INIT_0E => X"2E3B2E3B2E3B2E3B2E3B2E3B26192E3B3E0826192E3B3E0826193E082E3B2619",
INIT_0F => X"2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B",
INIT_10 => X"2E3B2E3B3F382E3B0C002E3B2E3B2E3B2E3B2E3B2E3B04002E3B2E3B2E3B2E3B",
INIT_11 => X"3F382E3B2E3B04002E3B2E3B3F382E3B0C002E3B2E3B2E3B2E3B2E3B2E3B0400",
INIT_12 => X"3E0804002E3B2E3B3F382E3B2E3B3E08371D2E3B2E3B2E3B3E0804002E3B2E3B",
INIT_13 => X"2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F382E3B2E3B3E08371D2E3B2E3B2E3B",
INIT_14 => X"2E3B2E3B3F383E082E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F383E08",
INIT_15 => X"3F3F3F3F3F3F040026192619261926192619261926192619261926192E3B2E3B",
INIT_16 => X"371D0400371D371D3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F",
INIT_17 => X"2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F3F3F3F0400371D371D371D371D",
INIT_18 => X"3F3F3F3F371D3F38371D371D371D371D371D371D2E3B2E3B2E3B2E3B2E3B2E3B",
INIT_19 => X"371D371D371D0400371D371D371D371D371D371D371D371D371D371D371D0000",
INIT_1A => X"371D371D371D371D371D371D00003F3F00003F3800003F3800003F383F381400",
INIT_1B => X"3F383F383F383F383F383F38371D371D371D371D371D371D371D371D371D371D",
INIT_1C => X"3E083E083F383F383F383E083F383E083F383F383F383F383F3800003F3F0001",
INIT_1D => X"3E083F383F383F3800003F3F3F3F3F383F383F383F383F383F383F383F383E08",
INIT_1E => X"3E083F383F383F383E083F383F383E083E083F383F383F383F383F383F383F38",
INIT_1F => X"3E0800013E083E083F383F383E083F383F383E083F3800003F3F00013F380001",
INIT_20 => X"3F383F3800003F3F00013F303F383F383F383F383E083F383E083F383F383E08",
INIT_21 => X"3F383F3F3F383F383F3F3F383F383F383F383F383F3F3F383F383F383F3F3F38",
INIT_22 => X"3F383F383F303E083F303F383F383E083F383F3F3F3F000114003F383F3F3F38",
INIT_23 => X"00003F3F00003F383F383F383F303E083F303F383F303F383F383E083F383F38",
INIT_24 => X"3F383F383F303F303F383F303F303F383F303F303F303F383F303F383F303F38",
INIT_25 => X"000100000001000000000000000000003F3F00003F303F383F303F303F383F38",
INIT_26 => X"0001000000000000000000000000000000000000000000000001000000000000",
INIT_27 => X"3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F",
INIT_28 => X"3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F",
INIT_29 => X"3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F",
INIT_2A => X"3E083F3F3E083F383E083F383F383F383E083F3F3F3F3F383F3F3F3F3F3F3F3F",
INIT_2B => X"3F3F3F383F3F3F383E083F3F3E083F383E083F383F383F383E083F3F3F3F3F38",
INIT_2C => X"3F383F383F383F383F3F3F383F383F383F383F383F3F3F383F383F383F383F38",
INIT_2D => X"3F383F3F3F383F383F3F3F383E083F383F3F3F383F383F383F383F383F3F3F38",
INIT_2E => X"3F383F383F383F383F383F3F3F383F383F3F3F383E083F383F383F383F383F38",
INIT_2F => X"3F3F3F383F383F383F383F3F3F383F3F3F383E083F3814003F3F3F383E083F38",
INIT_30 => X"3E083F3F3E083F383F3F3F383F383F383F383F3F3F383F3F3F383E083F381400",
INIT_31 => X"3F3F3F383F383F383E083F3F3E083F383E083F383F383F383F3F3F383F383F38",
INIT_32 => X"3F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3E083F383E083F383F383F38",
INIT_33 => X"3F383F3F3F383E083F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3F383E08",
INIT_34 => X"3F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F3F383F383F3F1400",
INIT_35 => X"3E083F3F3F383F383F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F",
INIT_36 => X"3E083F383F383F383E083F3F3F383F383F383F383F3F3F383E083F383F383F38",
INIT_37 => X"3F383F3F3F3F3F383F3F3F383F383F383F383F3F3F383F3F3F383F383F3F3F38",
INIT_38 => X"3F383F3F3F3F3F3F3F383F3F3F3F3F3F3F3F3F383F383F3F3F383F3F3F3F3F3F",
INIT_39 => X"3F383F3F000D3F383F38000D3F383F3F3F3F3F3F3F3F3F3F3F383F3F3F3F3F38",
INIT_3A => X"3F3F3F3F3F3F3F3F3F3F3F383F3F3F383F38000D3F383F3F3F3F3F3F3F3F3F3F",
INIT_3B => X"3E083F3F3F38000D371D3F3F3F3F3F3F3F3F1D373F3F3F383E083E083F383F3F",
INIT_3C => X"3F383F3F3F383F383F3F3F3F3F3F3F3F3F383F3F000D3F383F38000D3F3F3F38",
INIT_3D => X"3F3F3E083F383F3F3F383F3F3F383F38233F3F3F3F3F000D3F383F3F3F3F3F38",
INIT_3E => X"3F38233F3E083E08233F3E083F38233F3F383E08233F3F3F3F38000D3E083E08",
INIT_3F => X"3E08233F3E083F38233F3F383E08233F233F3F383F38233F3F383E08000D3F3F",
INIT_40 => X"3F3F3F383F3F233F3E08233F371D3F38000D1D373E08000D3F3F3F383F3F3F3F",
INIT_41 => X"233F3F383F3F371D3F383F38000D3F383F3F233F3F383F38233F3F383F3F233F",
INIT_42 => X"000D1D373F3F000D3E083F383F3F371D3F383F38000D3F383F3F233F3F383F38",
INIT_43 => X"3F38233F3F383F3F3F3F220F220F233F233F3F38371D233F3F38233F371D3F3F",
INIT_44 => X"000000000000000000000000000000000000000000000000233F3F38371D233F",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 14) => B"000000000000000000",
DIADI(13 downto 8) => dina(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13 downto 8) => douta(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_low_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_low_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_low_blk_mem_gen_prim_wrapper_init
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_low_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_low_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bg_low_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_low_blk_mem_gen_top;
architecture STRUCTURE of bg_low_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_low_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_low_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_low_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_low_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_low_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_low_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_low_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_low_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_low_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.5912999999999999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_low_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_low_blk_mem_gen_v8_3_5 : entity is "bg_low.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_low_blk_mem_gen_v8_3_5 : entity is "bg_low.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_low_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_low_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_low_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_low_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_low_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_low_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_low_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_low_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_low_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_low_blk_mem_gen_v8_3_5_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_low : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_low : entity is "bg_low,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_low : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_low : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_low;
architecture STRUCTURE of bg_low is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.5912999999999999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_low.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_low.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1092;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1092;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1092;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1092;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_low_blk_mem_gen_v8_3_5
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => B"00000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | bd4e86a26de160cf77402663bd103fc4 | 0.70189 | 2.983807 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/vhdl/util_pkg.vhdl | 2 | 5,022 | -- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
package util is
function flip_bits(in_vec : std_logic_vector) -- make unconstrained
return std_logic_vector;
function int_to_str (InputInt : integer)
return string;
function bit_width (num : integer)
return integer;
component util_inverter is
port (
data_in : in std_logic;
data_out : out std_logic);
end component;
end package util;
package body util is
function flip_bits(in_vec : std_logic_vector) -- make unconstrained
return std_logic_vector is
variable flipped_vec : std_logic_vector(in_vec'reverse_range);
begin
for i in in_vec'range loop
flipped_vec(i) := in_vec(i);
end loop;
return flipped_vec;
end flip_bits;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: Int_To_Str
--
-- PARAMETERS : InputInt - Integer to be converted to String.
-- ResultStr - String buffer for converted Integer
-- AppendPos - Position in buffer to place result
--
-- DESCRIPTION : This procedure is used to convert an input integer
-- into a string representation. The converted string
-- may be placed at a specific position in the result
-- buffer.
--
-- ------------------------------------------------------------------------
function int_to_str (InputInt : integer)
return string is
-- Look-up table. Given an int, we can get the character.
type integer_table_type is array (0 to 9) of character;
constant integer_table : integer_table_type :=
(
'0', '1', '2', '3', '4',
'5', '6', '7', '8', '9'
) ;
-- Local variables used in this function.
variable inpVal : integer := inputInt;
variable divisor : integer := 10;
variable tmpStrIndex : integer := 1;
variable tmpStr : string (1 to 256);
variable ResultStr : string (1 to 256);
variable appendPos : integer := 1;
begin
if (inpVal = 0) then
tmpStr(tmpStrIndex) := integer_table (0);
tmpStrIndex := tmpStrIndex + 1;
else
while (inpVal > 0) loop
tmpStr(tmpStrIndex) := integer_table (inpVal mod divisor);
tmpStrIndex := tmpStrIndex + 1;
inpVal := inpVal / divisor;
end loop;
end if;
if (appendPos /= 1) then
resultStr(appendPos) := ',';
appendPos := appendPos + 1;
end if;
for i in tmpStrIndex-1 downto 1 loop
resultStr(appendPos) := tmpStr(i);
appendPos := appendPos + 1;
end loop;
return ResultStr;
end int_to_str;
function bit_width (num : integer) return integer is
variable count : integer;
begin
count := 1;
if (num <= 0) then return 0;
elsif (num <= 2**10) then
for i in 1 to 10 loop
if (2**count >= num) then
return i;
end if;
count := count + 1;
end loop;
elsif (num <= 2**20) then
for i in 1 to 20 loop
if (2**count >= num) then
return i;
end if;
count := count + 1;
end loop;
elsif (num <= 2**30) then
for i in 1 to 30 loop
if (2**count >= num) then
return i;
end if;
count := count + 1;
end loop;
else
for i in 1 to num loop
if (2**i >= num) then
return i;
end if;
end loop;
end if;
end bit_width;
end package body util;
library ieee;
use ieee.std_logic_1164.all;
entity util_inverter is
port (
data_in : in std_logic;
data_out : out std_logic);
end util_inverter;
architecture rtl of util_inverter is
begin -- rtl
data_out <= not data_in;
end rtl;
| mit | 74238a3fdb29a4f98322dad69b6a8285 | 0.593986 | 4.053269 | false | false | false | false |
sh-chris110/chris | FPGA/chris.uart.ok/Qsys/soc_design/soc_design_inst.vhd | 2 | 541 | component soc_design is
port (
fpga_reset_n : in std_logic := 'X'; -- reset_n
ref_clk : in std_logic := 'X'; -- clk
uart_RXD : in std_logic := 'X'; -- RXD
uart_TXD : out std_logic -- TXD
);
end component soc_design;
u0 : component soc_design
port map (
fpga_reset_n => CONNECTED_TO_fpga_reset_n, -- fpga.reset_n
ref_clk => CONNECTED_TO_ref_clk, -- ref.clk
uart_RXD => CONNECTED_TO_uart_RXD, -- uart.RXD
uart_TXD => CONNECTED_TO_uart_TXD -- .TXD
);
| gpl-2.0 | 74ad71d47f8fd607936979d9cdf02337 | 0.537893 | 2.78866 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag.vhd | 13 | 7,125 | ----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
| mit | ba9077ada206bbaec7996d7c6b029dbb | 0.628351 | 3.063199 | false | false | false | false |
F3CDG/Embedded-System-Documentation | Doc_esterna/Esercitazione_1_GPIO/design/my_gpio_v1_0_S00_AXI.vhd | 1 | 21,700 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity my_gpio_v1_0_S00_AXI is
generic (
-- Users to add parameters here
gpio_size : natural := 8;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
pad : inout std_logic_vector(gpio_size-1 downto 0);
irq : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end my_gpio_v1_0_S00_AXI;
architecture arch_imp of my_gpio_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal reg_pad_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --pad_out register
signal reg_pad_rw_n :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --read write_n register
signal reg_pad_en :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --pad_en register
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --inutilizzato
signal reg_im :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --interrupt mask register
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --inutilizzato
signal reg_ack :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --interrupt ack register
signal reg_gie :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --global interrupt register
signal status_register :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- interrupt status register
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
component gpio_array is
generic(gpio_size : natural := gpio_size);
Port ( pad_out : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_rw_n : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_en : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_in : out STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad : inout STD_LOGIC_VECTOR (gpio_size-1 downto 0));
end component;
signal periph_pad_in : std_logic_vector(gpio_size-1 downto 0):=(others=>'0');
signal pad_intr_temp : std_logic_vector(gpio_size-1 downto 0):=(others=>'0');
signal new_intr : std_logic_vector(gpio_size-1 downto 0):=(others=>'0');
signal one_bit_status : std_logic:='0';
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_pad_out <= (others => '0');
reg_pad_rw_n <= (others => '0');
reg_pad_en <= (others => '0');
slv_reg3 <= (others => '0');
reg_im <= (others => '0');
slv_reg5 <= (others => '0');
reg_ack <= (others => '0');
reg_gie <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
reg_ack <= (others => '0');
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
reg_pad_out(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
reg_pad_rw_n(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
reg_pad_en(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3 (not used)
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
reg_im(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5 (not used)
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
reg_ack(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
reg_gie(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
reg_pad_out <= reg_pad_out;
reg_pad_rw_n <= reg_pad_rw_n;
reg_pad_en <= reg_pad_en;
slv_reg3 <= slv_reg3;
reg_im <= reg_im;
slv_reg5 <= slv_reg5;
reg_ack <= (others=>'0');
reg_gie <= reg_gie;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (reg_pad_out, reg_pad_rw_n, reg_pad_en, periph_pad_in, reg_im, status_register, reg_ack, reg_gie, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= reg_pad_out;
when b"001" =>
reg_data_out <= reg_pad_rw_n;
when b"010" =>
reg_data_out <= reg_pad_en;
when b"011" =>
--reg_data_out <= slv_reg3;
reg_data_out <= (others => '0');
reg_data_out(gpio_size-1 downto 0) <= periph_pad_in;
when b"100" =>
reg_data_out <= reg_im;
when b"101" =>
--reg_data_out <= slv_reg5
reg_data_out <= (others=>'0');
reg_data_out(gpio_size-1 downto 0) <= status_register(gpio_size-1 downto 0);
when b"110" =>
reg_data_out <= reg_ack;
when b"111" =>
reg_data_out <= reg_gie;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--istanza gpio
GPIO_ARRAY_INST: gpio_array port map(
pad_out => reg_pad_out(gpio_size-1 downto 0),
pad_rw_n => reg_pad_rw_n(gpio_size-1 downto 0),
pad_en => reg_pad_en(gpio_size-1 downto 0),
pad_in => periph_pad_in,
pad => pad);
--Implementazione della logica di interrupt
--il segnale di interrupt deve essere ottenuto solo mediante una and bit a bit tra il segnale in ingresso (pad) e il registro delle interrupt mascherate (reg_im),
--inoltre poiché un interrupt è desiderabile solo se esso avviene mediante una periferica di input è necessario eseguire un'altra and bit a bit col registro di
--read_write_n (reg_pad_rw_n)
pad_intr_temp <= (pad and reg_im(gpio_size-1 downto 0)) and reg_pad_rw_n(gpio_size-1 downto 0);
--il segnale di output (irq) è alto se esiste almeno una interrupt pendente e la global interrupt è attiva (reg_gie)
irq <= or_reduce(status_register(gpio_size-1 downto 0)) and reg_gie(0);
--logica di scrittura all'interno dello statur register:
--se vi è almeno un bit alto di ack (reg_ack) allora si pulisce tutto il registro di stato, se invece non è arrivato alcun ack ma la global interrupt è attiva,
--allora voglio salvare nello status ulteriori bit di pending altrimenti voglio tener memoria del valore precedente.
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
status_register <= (others => '0');
else
if(or_reduce(reg_ack(gpio_size-1 downto 0))='1')then
status_register(gpio_size-1 downto 0) <= status_register(gpio_size-1 downto 0) xor (reg_ack(gpio_size-1 downto 0)and status_register(gpio_size-1 downto 0));
else
if(reg_gie(0)='1')then
new_intr <= pad_intr_temp;
else
new_intr <= (others => '0');
end if;
status_register(gpio_size-1 downto 0) <= status_register(gpio_size -1 downto 0) or new_intr;
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
| agpl-3.0 | b852d2e855b4d02824666faaa690763f | 0.59031 | 3.511737 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/sdram_wrap.vhd | 1 | 4,107 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpuinopkg.all;
use work.zpupkg.all;
use work.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
| mit | a24c459bc329d2b5e0585c7c5294fdb2 | 0.591429 | 2.868017 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/stack.vhd | 13 | 1,500 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_b_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(3 downto 0) := (others => '0');
begin
stack: RAMB16_S36_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
DOA => stack_a_read,
DOB => stack_b_read,
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr,
ADDRB => stack_b_addr,
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write,
DIB => stack_b_write,
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable,
WEB => stack_b_writeenable
);
end behave;
| mit | 195db5f9f8c01b0d9de5df18c52d708a | 0.629333 | 2.901354 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/generic_dp_ram.vhd | 15 | 3,032 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end entity generic_dp_ram;
architecture behave of generic_dp_ram is
subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE;
begin
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dia;
end if;
doa <= RAM(conv_integer(addra)) ;
end if;
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if enb='1' then
if web='1' then
RAM( conv_integer(addrb) ) := dib;
end if;
dob <= RAM(conv_integer(addrb)) ;
end if;
end if;
end process;
end behave;
| mit | 8322ff73f56b5d95ae7c85e914af00f2 | 0.64248 | 3.738594 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev10.vhd | 1 | 38,449 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev10 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev10 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : integer;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= 0;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(std_logic_vector(mvect(rcount))))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)))))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 8f9b2b74534654036105076d8ea2ccc4 | 0.645713 | 2.914128 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/ball_small/ball_small_sim_netlist.vhdl | 1 | 40,141 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Dec 25 17:16:48 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_small/ball_small_sim_netlist.vhdl
-- Design : ball_small
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end ball_small_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of ball_small_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000013301330133013301330133013301330",
INIT_01 => X"1330133013301330133013301330133013301330133013300000000000000000",
INIT_02 => X"3C003C003C003C003C003C003C003C003C000000000013301330133013301330",
INIT_03 => X"133013301330133013301330133013301330133013301330000000001C001C00",
INIT_04 => X"00001C0000003C003C003C003C003C003C003C003C003C003C00000013301330",
INIT_05 => X"0000000013301330133013301330133013301330133013300000000026190000",
INIT_06 => X"2619261900001C0000003C003C003C003C003C003C003C003C003C003C003C00",
INIT_07 => X"3C003C003C00000000001330133013301330133013301330133000002E3B2619",
INIT_08 => X"261926192E3B2E3B00001C001C0000003C003C003C003C003C003C003C003C00",
INIT_09 => X"3C003C003C003C003C003C000000133013301330133013301330133000002619",
INIT_0A => X"261926192E3B261926192619261900001C0000003C003C003C003C003C003C00",
INIT_0B => X"3C003C003C003C003C003C003C003C003C000000000013301330133013300000",
INIT_0C => X"000026192E3B26192E3B261926192619261900001C001C0000003C003C003C00",
INIT_0D => X"3C003C003C003C003C003C003C003C003C003C003C0000000000133013301330",
INIT_0E => X"1330000000002E3B26192619261926192E3B26192E3B26191C001C0000003C00",
INIT_0F => X"00003C003C003C003C003C003C003C003C003C003C003C003C003C0000001330",
INIT_10 => X"0000000013300000261926192E3B26192E3B26192619261926192E3B1C001C00",
INIT_11 => X"00001C001C001C001C0000003C003C003C003C003C003C003C003C003C003C00",
INIT_12 => X"3C003C003C000000133000002E3B26192E3B26192E3B26192619261926192E3B",
INIT_13 => X"2E3B000000001C001C001C001C001C003C003C003C003C003C003C003C003C00",
INIT_14 => X"3C003C003C003C003C0000000000261926192E3B26192619261926192E3B2619",
INIT_15 => X"26192E3B26191C001C001C001C001C001C001C001C0000003C003C003C003C00",
INIT_16 => X"3C003C003C003C003C003C003C00000000002E3B2619261926192E3B26192E3B",
INIT_17 => X"26192E3B26192E3B00001C001C001C003F3F3F3F3F3F1C001C0000003C003C00",
INIT_18 => X"00003C003C003C003C003C003C003C003C00000000002E3B2619261926192E3B",
INIT_19 => X"2E3B26192E3B26192619261900001C001C003F3F3F3F00003F3F3F3F1C001C00",
INIT_1A => X"1C001C0000003C003C003C003C003C003C003C003C0000000000261926192619",
INIT_1B => X"2619261926192E3B26192E3B261900001C001C001C003F3F00003F3F00003F3F",
INIT_1C => X"3F3F3F3F1C001C0000003C003C003C003C003C003C003C003C00000000002E3B",
INIT_1D => X"00002E3B2619261926192E3B261926192E3B261900001C0000003F3F3F3F0000",
INIT_1E => X"3F3F3F3F3F3F1C001C001C0000003C003C003C003C003C003C003C003C000000",
INIT_1F => X"3C00000000002619261926192E3B26192E3B26192619261900001C001C001C00",
INIT_20 => X"1C001C001C00000000001C001C0000003C003C003C003C003C003C003C003C00",
INIT_21 => X"3C003C003C00000000002E3B2619261926192E3B26192E3B26192E3B26190000",
INIT_22 => X"2E3B26191C001C001C001C001C001C00000000003C003C003C003C003C003C00",
INIT_23 => X"3C003C003C003C003C000000000000002E3B26192E3B26192E3B261926192619",
INIT_24 => X"2E3B261926192E3B261900001C0000001C001C003C003C003C003C003C003C00",
INIT_25 => X"3C003C003C003C003C003C00000000000000000026192E3B2619261926192619",
INIT_26 => X"2E3B2619261926192619261926192619000000001C001C003C003C003C003C00",
INIT_27 => X"3C003C003C003C003C003C003C003C0000001330133000002E3B26192E3B2619",
INIT_28 => X"2E3B26192E3B261926192619261926192E3B26192619261900001C0000003C00",
INIT_29 => X"00003C003C003C003C003C003C003C003C000000133013301330000000002619",
INIT_2A => X"00002E3B26192619261926192E3B26192E3B2619261926192E3B2E3B00001C00",
INIT_2B => X"261900001C0000003C003C003C003C003C003C003C0000001330133013301330",
INIT_2C => X"13301330000026192E3B26192E3B261926192619261926192E3B261926192619",
INIT_2D => X"26192619261900001C0000003C003C003C003C003C003C000000133013301330",
INIT_2E => X"13301330133013301330000000002619261926192E3B26192E3B26192E3B2619",
INIT_2F => X"261926192E3B26192E3B26191C001C0000003C003C003C003C00000013301330",
INIT_30 => X"133013301330133013301330133013300000000026192E3B26192E3B26192619",
INIT_31 => X"2E3B26192E3B26192619261926192E3B1C001C0000003C003C003C0000001330",
INIT_32 => X"133013301330133013301330133013301330133013300000000026192E3B2619",
INIT_33 => X"000026192E3B26192E3B26192619261926192E3B00001C001C00000000000000",
INIT_34 => X"0000133013301330133013301330133013301330133013301330133000000000",
INIT_35 => X"133013300000000000002619261926192E3B26192E3B26190000000000000000",
INIT_36 => X"0000133013301330133013301330133013301330133013301330133013301330",
INIT_37 => X"1330133013301330133013300000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000001330133013301330",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => addra(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => dina(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_1\,
DOADO(13 downto 8) => douta(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\,
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end ball_small_blk_mem_gen_prim_width;
architecture STRUCTURE of ball_small_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.ball_small_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end ball_small_blk_mem_gen_generic_cstr;
architecture STRUCTURE of ball_small_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.ball_small_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_top : entity is "blk_mem_gen_top";
end ball_small_blk_mem_gen_top;
architecture STRUCTURE of ball_small_blk_mem_gen_top is
begin
\valid.cstr\: entity work.ball_small_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end ball_small_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of ball_small_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.ball_small_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of ball_small_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of ball_small_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of ball_small_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of ball_small_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of ball_small_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 1.43485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of ball_small_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of ball_small_blk_mem_gen_v8_3_5 : entity is "ball_small.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of ball_small_blk_mem_gen_v8_3_5 : entity is "ball_small.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of ball_small_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of ball_small_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of ball_small_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of ball_small_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of ball_small_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of ball_small_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_small_blk_mem_gen_v8_3_5 : entity is "yes";
end ball_small_blk_mem_gen_v8_3_5;
architecture STRUCTURE of ball_small_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.ball_small_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ball_small : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ball_small : entity is "ball_small,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_small : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ball_small : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end ball_small;
architecture STRUCTURE of ball_small is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 1.43485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "ball_small.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "ball_small.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 900;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 900;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 900;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 900;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.ball_small_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 4f504d40b0d03a064b33cff26094b2c6 | 0.685558 | 2.981358 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_adc.vhd | 1 | 9,393 | --
-- ADC interface
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity zpuino_adc is
generic (
fifo_width_bits: integer := 16;
upper_offset: integer := 15;
lower_offset: integer := 4
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic; -- External trigger
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end entity zpuino_adc;
architecture behave of zpuino_adc is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
constant fifo_lower_bit: integer := fifo_width_bits/8;
signal request_samples_q: unsigned(11-fifo_lower_bit downto 0); -- Maximum 4K samples
signal current_sample_q: unsigned(11-fifo_lower_bit downto 0); -- Current sample
signal read_fifo_ptr_q: unsigned(10 downto 2);
-- signal dly_interval_q: unsigned(31 downto 0); -- Additional clock delay between samples
signal fifo_read: std_logic_vector(31 downto 0);
signal fifo_read_address: std_logic_vector(10 downto 2);
signal fifo_write_address: std_logic_vector(11-fifo_lower_bit downto 0);
signal fifo_write: std_logic_vector(fifo_width_bits-1 downto 0);
signal fifo_wr: std_logic;
signal spi_dout: std_logic_vector(31 downto 0);
signal spi_enable: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
-- Configuration registers
signal adc_enabled_q: std_logic;
signal adc_source_external_q: std_logic;
signal run_spi: std_logic;
signal do_sample: std_logic;
begin
enabled <= adc_enabled_q;
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
process(spi_enable,spi_ready)
begin
seln<='1';
if spi_enable='1' or spi_ready='0' then
seln<='0';
end if;
end process;
adcspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => (others => '0'), -- Change to channel number
dout => spi_dout,
en => spi_enable,
ready => spi_ready,
transfersize => "01", -- Fixed 16-bit transfers
miso => miso,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => '1'
);
acdclkgen: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
cpol => '1',
pres => "010", -- Fixed
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck
);
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_fifo_ptr_q <= (others => '0');
else
if wb_we_i='1' and wb_adr_i(4 downto 2)="100" then
read_fifo_ptr_q <= unsigned(wb_dat_i(10 downto 2));
else
if wb_cyc_i='1' and wb_we_i='0' and wb_stb_i='1' and wb_adr_i(4 downto 2)="101" then
-- FIFO wb_dat_o, increment wb_adr_i
read_fifo_ptr_q <= read_fifo_ptr_q+1;
end if;
end if;
end if;
end if;
end process;
-- READ muxer
process(wb_adr_i,fifo_read,request_samples_q,current_sample_q)
begin
wb_dat_o <= (others => DontCareValue);
case wb_adr_i(4 downto 2) is
when "000" =>
if (request_samples_q /= current_sample_q) then
wb_dat_o(0) <= '0';
else
wb_dat_o(0) <= '1';
end if;
when "101" =>
wb_dat_o <= fifo_read;
when others =>
end case;
end process;
fifo_write_address <= std_logic_vector(current_sample_q);
fifo_read_address <= std_logic_vector(read_fifo_ptr_q);
process(spi_dout)
begin
fifo_write <= (others => '0');
fifo_write(upper_offset-lower_offset downto 0) <= spi_dout(upper_offset downto lower_offset); -- Data from SPI
end process;
ram8: if fifo_width_bits=8 generate
ram: RAMB16_S9_S36
port map (
DOA => open,
DOB => fifo_read,
DOPA => open,
DOPB => open,
ADDRA => fifo_write_address,
ADDRB => fifo_read_address,
CLKA => wb_clk_i,
CLKB => wb_clk_i,
DIA => fifo_write,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => '0',
SSRB => '0',
WEA => fifo_wr,
WEB => '0'
);
end generate;
ram16: if fifo_width_bits=16 generate
ram: RAMB16_S18_S36
port map (
DOA => open,
DOB => fifo_read,
DOPA => open,
DOPB => open,
ADDRA => fifo_write_address,
ADDRB => fifo_read_address,
CLKA => wb_clk_i,
CLKB => wb_clk_i,
DIA => fifo_write,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => '0',
SSRB => '0',
WEA => fifo_wr,
WEB => '0'
);
end generate;
spi_enable <= '1' when run_spi='1' and spi_ready='1' and do_sample='1' else '0';
do_sample <= sample when adc_source_external_q='1' else '1';
-- Main process
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
request_samples_q <= (others => '0');
current_sample_q <= (others => '0');
run_spi <= '0';
fifo_wr <= '0';
adc_source_external_q <= '0';
adc_enabled_q<='0';
else
fifo_wr <= '0';
if wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
-- Write configuration
adc_enabled_q <= wb_dat_i(0);
adc_source_external_q <= wb_dat_i(1);
when "001" =>
-- Write request samples
request_samples_q <= unsigned(wb_dat_i(11-fifo_lower_bit downto 0));
current_sample_q <= (others => '1'); -- WARNING - this will overwrite last value on RAM
run_spi <= '1';
when others =>
end case;
else
-- Normal run.
if (request_samples_q /= current_sample_q) then
-- Sampling right now.
if spi_ready='1' then
-- Add delay here.
if do_sample='1' then
fifo_wr <= '1';
run_spi <= '1';
end if;
end if;
else
run_spi <= '0';
end if;
if fifo_wr='1' then
current_sample_q <= current_sample_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 3adfbba1140c33b2166f1b4c987be63d | 0.565102 | 3.34747 | false | false | false | false |
huukit/logicsynth | excercises/vhd/audio_ctrl.vhd | 1 | 4,812 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 08
-- Project :
-------------------------------------------------------------------------------
-- File : audio_ctrl.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 11.1.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Controller for Wolfson WM8731 -audio codec
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 11.01.2016 1.0 nikulaj Created
-- 12.01.2016 1.1 huukit Drafting functionality.
-- 15.01.2016 1.2 huukit Fixed a bug where the snapshot was incorrectly updated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Define the entity.
entity audio_ctrl is
generic(
ref_clk_freq_g : integer := 18432000; -- Reference clock.
sample_rate_g : integer := 48000; -- Sample clock fs.
data_width_g : integer := 16 -- Data width.
);
port(
clk : in std_logic; -- Main clock.
rst_n : in std_logic; -- Reset, active low.
left_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, left.
right_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, right.
aud_bclk_out : out std_logic; -- Audio bitclock.
aud_data_out : out std_logic; -- Audio data.
aud_lrclk_out : out std_logic -- Audio bitclock L/R select.
);
end audio_ctrl;
architecture rtl of audio_ctrl is
-- Calculate contants for clock generation counters.
constant fs_c : integer := (((ref_clk_freq_g / sample_rate_g) / data_width_g) / 4) - 1;
constant lr_c : integer := (data_width_g * 2) - 1;
-- Define the width of the counters used.
constant clk_c_width_c : integer := 16;
-- Clock counters.
signal bclk_count_r : unsigned(clk_c_width_c - 1 downto 0);
signal lr_count_r : unsigned(clk_c_width_c - 1 downto 0);
-- Data and control registers.
signal left_data_ss_r : std_logic_vector(data_width_g - 1 downto 0);
signal right_data_ss_r : std_logic_vector(data_width_g - 1 downto 0);
signal aud_data_r : std_logic;
signal bclk_r : std_logic;
signal lr_r : std_logic;
begin --rtl
-- Assign registers to outputs.
aud_bclk_out <= bclk_r;
aud_lrclk_out <= lr_r;
aud_data_out <= aud_data_r;
bclock : process (clk, rst_n) -- Generates the bit and lr clocks.
begin
if(rst_n = '0') then
bclk_count_r <= to_unsigned(fs_c, bclk_count_r'length);
lr_count_r <= to_unsigned(lr_c, lr_count_r'length);
bclk_r <= '0';
lr_r <= '1';
elsif(clk'event and clk = '1') then
if(bclk_count_r = 0) then -- Handle bclk.
bclk_r <= not bclk_r; -- bclk Invert on compare.
bclk_count_r <= to_unsigned(fs_c, bclk_count_r'length); -- bclk Reset counter.
if(lr_count_r = 0) then -- Handle L/R selection.
lr_r <= not lr_r; -- L/R invert on compare.
lr_count_r <= to_unsigned(lr_c, lr_count_r'length); -- L/R reset counter.
else
lr_count_r <= lr_count_r - 1; -- L/R count down.
end if;
else
bclk_count_r <= bclk_count_r - 1; -- bclk Count down.
end if;
end if;
end process bclock;
dataload : process (clk, rst_n) -- Load and serialize the input data.
begin
if(rst_n = '0') then -- Reset clears dataregisters.
left_data_ss_r <= (others => '0');
right_data_ss_r <= (others => '0');
aud_data_r <= '0';
elsif(clk'event and clk = '1') then
if(lr_count_r = 0 and bclk_count_r = 0) then -- Store and load.
if(lr_r = '0') then -- Only store snapshot on SOF.
left_data_ss_r <= left_data_in; -- Store snapshots.
right_data_ss_r <= right_data_in;
aud_data_r <= left_data_in(lr_c / 2); -- Load first bit.
else
aud_data_r <= right_data_ss_r(lr_c/ 2); -- Load first bit.
end if;
elsif(bclk_count_r = 0 and bclk_r = '1') then -- Load next byte on falling clock.
if(lr_r = '1') then
aud_data_r <= left_data_ss_r(to_integer((lr_count_r -1 )/ 2));
else
aud_data_r <= right_data_ss_r(to_integer((lr_count_r -1)/ 2));
end if;
end if;
end if;
end process dataload;
end rtl;
| gpl-2.0 | f1f18ef4f6e84ee34004c28ef0376161 | 0.505403 | 3.449462 | false | false | false | false |
sh-chris110/chris | FPGA/uCos/system/system_inst.vhd | 1 | 1,835 | component system is
port (
ref_clk : in std_logic := 'X'; -- clk
fpga_reset_n : in std_logic := 'X'; -- reset_n
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; -- cke
dram_cs_n : out std_logic; -- cs_n
dram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
dram_dqm : out std_logic_vector(1 downto 0); -- dqm
dram_ras_n : out std_logic; -- ras_n
dram_we_n : out std_logic; -- we_n
dram_clk_clk : out std_logic -- clk
);
end component system;
u0 : component system
port map (
ref_clk => CONNECTED_TO_ref_clk, -- ref.clk
fpga_reset_n => CONNECTED_TO_fpga_reset_n, -- fpga.reset_n
dram_addr => CONNECTED_TO_dram_addr, -- dram.addr
dram_ba => CONNECTED_TO_dram_ba, -- .ba
dram_cas_n => CONNECTED_TO_dram_cas_n, -- .cas_n
dram_cke => CONNECTED_TO_dram_cke, -- .cke
dram_cs_n => CONNECTED_TO_dram_cs_n, -- .cs_n
dram_dq => CONNECTED_TO_dram_dq, -- .dq
dram_dqm => CONNECTED_TO_dram_dqm, -- .dqm
dram_ras_n => CONNECTED_TO_dram_ras_n, -- .ras_n
dram_we_n => CONNECTED_TO_dram_we_n, -- .we_n
dram_clk_clk => CONNECTED_TO_dram_clk_clk -- dram_clk.clk
);
| gpl-2.0 | 303ccb68fa2117745d8c4a2513dfff06 | 0.415259 | 3.30036 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/zpuinopkg.vhd | 13 | 22,276 | --
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg; | mit | af114fa7abe7faf00fc6475eaae473c0 | 0.629108 | 2.830136 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.vhd | 1 | 32,235 | --------------------------------------------------------------------------------
-- Datapath made of the following stages:
-- fetch
-- decode
-- execute
-- memory
-- writeback
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity DataPath is
port(
-- INPUTS
clk : in std_logic;
rst : in std_logic;
fromIRAM : in std_logic_vector(31 downto 0); -- data coming from IRAM
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- Control Word + ALU operation for the current instruction decoded
-- OUTPUTS
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
Addr : out std_logic_vector(31 downto 0) -- address coming from PC (goes to IRAM)
);
end DataPath;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture struct of DataPath is
-- component declarations
component fetch is
port (
--INPTUS
jump_address : in std_logic_vector(31 downto 0);
branch_target : in std_logic_vector(31 downto 0);
from_iram : in std_logic_vector(31 downto 0);
flush : in std_logic;
clk : in std_logic;
rst : in std_logic;
pcsrc : in std_logic;
jump : in std_logic;
pcwrite : in std_logic;
--OUTPUTS
to_iram : out std_logic_vector(31 downto 0);
pc_4 : out std_logic_vector(31 downto 0);
instruction_fetch : out std_logic_vector(31 downto 0)
);
end component;
component decode_unit is
port (
-- INPUTS
address_write : in std_logic_vector(4 downto 0); -- register address that should be written
data_write : in std_logic_vector(31 downto 0); -- data to be written in the reg file
pc_4_from_dec : in std_logic_vector(31 downto 0); -- Program counter incremented by 4
instruction : in std_logic_vector(31 downto 0); -- instruction fetched
idex_rt : in std_logic_vector(4 downto 0); -- Rt register coming from the ex stage
clk : in std_logic; -- global clock
rst : in std_logic; -- global reset signal
reg_write : in std_logic; -- Reg Write signal to enable the write operation
idex_mem_read : in std_logic_vector(3 downto 0); -- control signals for Mem Read (lb,lhu, lw, lbu)
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address : out std_logic_vector(31 downto 0); -- jump address sign-extended
pc_4_to_ex : out std_logic_vector(31 downto 0); -- Program counter incremented by 4 directed to the ex stage
data_read_1 : out std_logic_vector(31 downto 0); -- Output of read port 1 of reg file
data_read_2 : out std_logic_vector(31 downto 0); -- Output of read port 2 of reg file
immediate_ext : out std_logic_vector(31 downto 0); -- Immediate field signe-exntended
immediate : out std_logic_vector(15 downto 0); -- Immediate filed not sign extended (for LUI instruction)
rt : out std_logic_Vector(4 downto 0); -- rt address (instruction 20-16)
rd : out std_logic_vector(4 downto 0); -- rd address (instruction 15-11)
rs : out std_logic_vector(4 downto 0); -- rs address (instruction 25-21)
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode for the CU, instruction (31-26)
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field of instruction (10-0) to the CU
pcwrite : out std_logic; -- write enable generated by the Hazard Detection Unit for the PC
ifid_write : out std_logic -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline register
);
end component;
component execute is
port(
clk : in std_logic;
rst : in std_logic;
-- inputs from IDEX pipeline reg
controls_in : in std_logic_vector(21 downto 0); -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) is already exhausted in the DECODE stage
ext25_0 : in std_logic_vector(31 downto 0); -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC : in std_logic_vector(31 downto 0);
op_A : in std_logic_vector(31 downto 0);
op_B : in std_logic_vector(31 downto 0);
ext15_0 : in std_logic_vector(31 downto 0); -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 : in std_logic_vector(15 downto 0); -- bits 15_0 of instr.
rt_inst : in std_logic_vector(4 downto 0);
rd_inst : in std_logic_vector(4 downto 0);
rs_inst : in std_logic_vector(4 downto 0);
-- inputs from other sources
unaligned : in std_logic; -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB : in std_logic_vector(31 downto 0); -- data from WB stage that is used if forwarding needed
forw_dataMEM : in std_logic_vector(31 downto 0); -- data from MEM stage that is used if forwarding needed
RFaddr_WB : in std_logic_vector(4 downto 0); -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM : in std_logic_vector(4 downto 0); -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB : in std_logic; -- reg_write ctrl signal from WB stage
regwriteMEM : in std_logic; -- reg_write ctrl signal from MEM stage
-- outputs
controls_out : out std_logic_vector(10 downto 0); -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 : out std_logic_vector(31 downto 0);
toPC2 : out std_logic_vector(31 downto 0);
branchTaken : out std_logic;
addrMem : out std_logic_vector(31 downto 0);
writeData : out std_logic_vector(31 downto 0);
addrRF : out std_logic_vector(4 downto 0);
IDEX_rt : out std_logic_vector(4 downto 0); -- goes to hazard unit
IDEX_memread : out std_logic_vector(3 downto 0) -- goes to hazard unit
);
end component;
component memory is
port(
-- inputs
rst : in std_logic;
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0) -- goes to EXE stage and is used if forwarding detected by forwarding unit
);
end component;
component writeback is
port(
-- inputs
from_mem_data : in std_logic_vector(31 downto 0);
from_alu_data : in std_logic_vector(31 downto 0); -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in : in std_logic_vector(4 downto 0); -- address of register to write
regwrite_in : in std_logic; -- control signal (1 -> write in reg file)
link : in std_logic; -- control signal (1 -> link the instruction, save IP in R31)
memtoreg : in std_logic;
-- outputs
regwrite_out : out std_logic; -- control signal (send regwrite signal back to other stages)
regfile_data : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
component ifid_reg is
port (
-- INPUTS
pc_4 : in std_logic_vector(31 downto 0); -- PC + 4 coming from the fetch stage
instruction_fetch : in std_logic_vector(31 downto 0); -- Instruction to be decoded
flush : in std_logic; -- flush control signal
ifid_write : in std_logic; -- write enable
clk : in std_logic; -- clock signal
rst : in std_logic; -- reset signal
-- OUTPUTS
instruction_decode : out std_logic_vector(31 downto 0); -- Instruction for the decode stage
new_pc : out std_logic_vector(31 downto 0) -- PC + 4 directed to the next pipeline register
);
end component;
component idex_reg is
port (
-- INPUTS
cw_to_ex_dec : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec : in std_logic_vector(31 downto 0); -- jump address extended
pc_4_dec : in std_logic_vector(31 downto 0); -- PC incremented by 4 from decode
read_data_1_dec : in std_logic_vector(31 downto 0); -- reg 1 read from decode
read_data_2_dec : in std_logic_vector(31 downto 0); -- reg 2 read from decode
immediate_ext_dec : in std_logic_vector(31 downto 0); -- immediate sign extended from decode
immediate_dec : in std_logic_vector(15 downto 0); -- immediate for lui instrucion from decode
rt_dec : in std_logic_vector(4 downto 0); -- rt address from decode
rd_dec : in std_logic_vector(4 downto 0); -- rs address from decode
rs_dec : in std_logic_vector(4 downto 0); -- rd address from decode
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word for ex stage
jump_address : out std_logic_vector(31 downto 0); -- jump address to ex stage
pc_4 : out std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0);
immediate_ext : out std_logic_vector(31 downto 0);
immediate : out std_logic_vector(15 downto 0);
rt : out std_logic_vector(4 downto 0);
rd : out std_logic_vector(4 downto 0);
rs : out std_logic_vector(4 downto 0)
);
end component;
component EX_MEM_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(10 downto 0); -- 11 control signals go from exe to mem stage
toPC1_in : in std_logic_vector(31 downto 0); -- from jreg controlled mux
toPC2_in : in std_logic_vector(31 downto 0); -- from adder2
takeBranch_in : in std_logic; -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in : in std_logic_vector(31 downto 0);
mem_writedata_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(10 downto 0);
toPC1_out : out std_logic_vector(31 downto 0);
toPC2_out : out std_logic_vector(31 downto 0);
takeBranch_out : out std_logic;
mem_addr_out : out std_logic_vector(31 downto 0);
mem_writedata_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
component MEM_WB_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(2 downto 0); -- in order, from MSB to LSB : regwrite, link, memtoreg
from_mem_data_in : in std_logic_vector(31 downto 0);
from_alu_data_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(2 downto 0);
from_mem_data_out : out std_logic_vector(31 downto 0);
from_alu_data_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
-- signal declarations
signal jump_address_i : std_logic_vector(31 downto 0);
signal branch_target_i : std_logic_vector(31 downto 0);
signal flush_i : std_logic;
signal pcsrc_i : std_logic;
signal jump_i : std_logic;
signal pcwrite_i : std_logic;
signal pc_4_i : std_logic_vector(31 downto 0);
signal instruction_fetch_i : std_logic_vector(31 downto 0);
signal instruction_decode_i : std_logic_vector(31 downto 0);
signal new_pc_i : std_logic_vector(31 downto 0);
signal ifid_write_i : std_logic;
signal address_write_i : std_logic_vector(4 downto 0);
signal data_write_i : std_logic_vector(31 downto 0);
signal idex_rt_i : std_logic_vector(4 downto 0);
signal reg_write_i : std_logic;
signal idex_mem_read_i : std_logic_vector(3 downto 0);
signal jaddr_i : std_logic_vector(31 downto 0);
signal pc4_to_idexreg_i : std_logic_vector(31 downto 0);
signal data_read_dec_1_i : std_logic_vector(31 downto 0);
signal data_read_dec_2_i : std_logic_vector(31 downto 0);
signal immediate_ext_dec_i : std_logic_vector(31 downto 0);
signal immediate_dec_i : std_logic_vector(15 downto 0);
signal rt_dec_i : std_logic_vector(4 downto 0);
signal rd_dec_i : std_logic_vector(4 downto 0);
signal rs_dec_i : std_logic_vector(4 downto 0);
signal cw_to_idex_i : std_logic_vector(21 downto 0);
signal cw_to_ex_i : std_logic_vector(21 downto 0);
signal jump_address_toex_i : std_logic_vector(31 downto 0);
signal pc_4_to_ex_i : std_logic_vector(31 downto 0);
signal data_read_ex_1_i : std_logic_vector(31 downto 0);
signal data_read_ex_2_i : std_logic_vector(31 downto 0);
signal immediate_ext_ex_i : std_logic_vector(31 downto 0);
signal immediate_ex_i : std_logic_vector(15 downto 0);
signal rt_ex_i : std_logic_vector(4 downto 0);
signal rd_ex_i : std_logic_vector(4 downto 0);
signal rs_ex_i : std_logic_vector(4 downto 0);
signal unaligned_i : std_logic;
signal forw_dataMEM_i : std_logic_vector(31 downto 0);
signal RFaddr_MEM_i : std_logic_vector(4 downto 0);
signal regwriteMEM_i : std_logic;
signal cw_exmem_i : std_logic_vector(10 downto 0);
signal toPC1_i : std_logic_vector(31 downto 0);
signal toPC2_i : std_logic_vector(31 downto 0);
signal branchTaken_i : std_logic;
signal addrMem_exmem_i : std_logic_vector(31 downto 0);
signal writeData_exmem_i : std_logic_vector(31 downto 0);
signal addrRF_exmem_i : std_logic_vector(4 downto 0);
signal cw_tomem_i : std_logic_vector(10 downto 0);
signal PC1_tomem_i : std_logic_vector(31 downto 0);
signal PC2_tomem_i : std_logic_vector(31 downto 0);
signal takeBranch_out_i : std_logic;
signal mem_addr_out_i : std_logic_vector(31 downto 0);
signal mem_writedata_out_i : std_logic_vector(31 downto 0);
signal regfile_addr_out_tomem_i : std_logic_vector(4 downto 0);
signal cw_memwb_i : std_logic_vector(2 downto 0);
signal dataOut_mem_i : std_logic_vector(31 downto 0);
signal dataOut_exe_i : std_logic_vector(31 downto 0);
signal RFaddr_out_memwb_i : std_logic_vector(4 downto 0);
signal cw_towb_i : std_logic_vector(2 downto 0);
signal from_mem_data_out_i : std_logic_vector(31 downto 0);
signal from_alu_data_out_i : std_logic_vector(31 downto 0);
signal regfile_addr_out_towb_i : std_logic_vector(4 downto 0);
begin
-- component instantiations
u_fetch: fetch
port map (
--INPTUS
jump_address => jump_address_i,
branch_target => branch_target_i,
from_iram => fromIRAM,
flush => flush_i,
clk => clk,
rst => rst,
pcsrc => pcsrc_i,
jump => jump_i,
pcwrite => pcwrite_i,
--OUTPUTS
to_iram => Addr,
pc_4 => pc_4_i,
instruction_fetch => instruction_fetch_i
);
u_ifidreg : ifid_reg port map(
-- INPUTS
pc_4 => pc_4_i, -- PC + 4 coming from the fetch stage
instruction_fetch => instruction_fetch_i, -- Instruction to be decoded
flush => flush_i, -- flush control signal
ifid_write => ifid_write_i, -- write enable
clk => clk, -- clock signal
rst => rst, -- reset signal
-- OUTPUTS
instruction_decode => instruction_decode_i, -- Instruction for the decode stage
new_pc => new_pc_i -- PC + 4 directed to the next pipeline register
);
u_decode_unit: decode_unit
port map (
-- INPUTS
address_write => address_write_i, -- regter address that should be written
data_write => data_write_i, -- data to be written in the reg file
pc_4_from_dec => new_pc_i, -- Program counter incremented by 4
instruction => instruction_decode_i, -- instruction fetched
idex_rt => idex_rt_i, -- Rt regter coming from the ex stage
clk => clk, -- global clock
rst => rst, -- global reset signal
reg_write => reg_write_i, -- Reg Write signal to enable the write operation
idex_mem_read => idex_mem_read_i, -- control signals for Mem Read (lb,lhu, lw, lbu)
cw => cw, -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex => cw_to_idex_i, -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address => jaddr_i, -- jump address sign-extended
pc_4_to_ex => pc4_to_idexreg_i, -- Program counter incremented by 4 directed to the ex stage
data_read_1 => data_read_dec_1_i, -- Output of read port 1 of reg file
data_read_2 => data_read_dec_2_i, -- Output of read port 2 of reg file
immediate_ext => immediate_ext_dec_i, -- Immediate field signe-exntended
immediate => immediate_dec_i, -- Immediate filed not sign extended (for LUI instruction)
rt => rt_dec_i, -- rt address (instruction 20-16)
rd => rd_dec_i, -- rd address (instruction 15-11)
rs => rs_dec_i, -- rs address (instruction 25-21)
opcode => opcode, -- opcode for the CU, instruction (31-26)
func => func, -- func field of instruction (10-0) to the CU
pcwrite => pcwrite_i, -- write enable generated by the Hazard Detection Unit for the PC
ifid_write => ifid_write_i -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline regter
);
u_idexreg: idex_reg port map(
-- INPUTS
cw_to_ex_dec => cw_to_idex_i, -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec => jaddr_i, -- jump address extended
pc_4_dec => pc4_to_idexreg_i, -- PC incremented by 4 from decode
read_data_1_dec => data_read_dec_1_i, -- reg 1 read from decode
read_data_2_dec => data_read_dec_2_i, -- reg 2 read from decode
immediate_ext_dec => immediate_ext_dec_i, -- immediate sign extended from decode
immediate_dec => immediate_dec_i, -- immediate for lui instrucion from decode
rt_dec => rt_dec_i, -- rt address from decode
rd_dec => rd_dec_i, -- rs address from decode
rs_dec => rs_dec_i, -- rd address from decode
clk => clk, -- global clock signal
rst => rst, -- global reset signal
-- OUTPUTS
cw_to_ex => cw_to_ex_i, -- control word for ex stage
jump_address => jump_address_toex_i, -- jump address to ex stage
pc_4 => pc_4_to_ex_i,
read_data_1 => data_read_ex_1_i,
read_data_2 => data_read_ex_2_i,
immediate_ext => immediate_ext_ex_i,
immediate => immediate_ex_i,
rt => rt_ex_i,
rd => rd_ex_i,
rs => rs_ex_i
);
u_execute: execute
port map (
clk => clk,
rst => rst,
-- inputs from IDEX pipeline reg
controls_in => cw_to_ex_i, -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) already exhausted in the DECODE stage
ext25_0 => jump_address_toex_i, -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC => pc_4_to_ex_i,
op_A => data_read_ex_1_i,
op_B => data_read_ex_2_i,
ext15_0 => immediate_ext_ex_i, -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 => immediate_ex_i, -- bits 15_0 of instr.
rt_inst => rt_ex_i,
rd_inst => rd_ex_i,
rs_inst => rs_ex_i,
-- inputs from other sources
unaligned => unaligned_i, -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB => data_write_i, -- data from WB stage that used if forwarding needed
forw_dataMEM => forw_dataMEM_i, -- data from MEM stage that used if forwarding needed
RFaddr_WB => address_write_i, -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM => RFaddr_MEM_i, -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB => reg_write_i, -- reg_write ctrl signal from WB stage
regwriteMEM => regwriteMEM_i, -- reg_write ctrl signal from MEM stage
-- outputs
controls_out => cw_exmem_i, -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 => toPC1_i,
toPC2 => toPC2_i,
branchTaken => branchTaken_i,
addrMem => addrMem_exmem_i,
writeData => writeData_exmem_i,
addrRF => addrRF_exmem_i,
IDEX_rt => idex_rt_i, -- goes to hazard unit
IDEX_memread => idex_mem_read_i -- goes to hazard unit
);
u_exmemreg: EX_MEM_Reg port map (
-- input signals
clk => clk, -- clock source
rst => rst, -- reset signal
controls_in => cw_exmem_i, -- 11 control signals go from exe to mem stage
toPC1_in => toPC1_i, -- from jreg controlled mux
toPC2_in => toPC2_i, -- from adder2
takeBranch_in => branchTaken_i, -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in => addrMem_exmem_i,
mem_writedata_in => writeData_exmem_i,
regfile_addr_in => addrRF_exmem_i,
-- output signals
controls_out => cw_tomem_i,
toPC1_out => PC1_tomem_i,
toPC2_out => PC2_tomem_i,
takeBranch_out => takeBranch_out_i,
mem_addr_out => mem_addr_out_i,
mem_writedata_out => mem_writedata_out_i,
regfile_addr_out => regfile_addr_out_tomem_i
);
u_memory: memory
port map (
-- inputs
rst => rst,
controls_in => cw_tomem_i,
PC1_in => PC1_tomem_i,
PC2_in => PC2_tomem_i,
takeBranch => takeBranch_out_i,
addrMem => mem_addr_out_i,
writeData => mem_writedata_out_i,
RFaddr_in => regfile_addr_out_tomem_i,
-- outputs
controls_out => cw_memwb_i,
dataOut_mem => dataOut_mem_i, -- data that has been read directly from memory
dataOut_exe => dataOut_exe_i, -- data that has been produced in exe stage
RFaddr_out => RFaddr_out_memwb_i,
unaligned => unaligned_i,
PCsrc => pcsrc_i,
flush => flush_i,
jump => jump_i,
PC1_out => jump_address_i,
PC2_out => branch_target_i,
regwrite_MEM => regwriteMEM_i, -- goes to forwarding unit
RFaddr_MEM => RFaddr_MEM_i, -- goes to forwarding unit
forw_addr_MEM => forw_dataMEM_i -- goes to EXE stage and used if forwarding detected by forwarding unit
);
u_memwbreg: MEM_WB_Reg port map (
clk => clk, -- clock source
rst => rst, -- reset signal
controls_in => cw_memwb_i, -- in order, from MSB to LSB : regwrite, link, memtoreg
from_mem_data_in => dataOut_mem_i,
from_alu_data_in => dataOut_exe_i,
regfile_addr_in => RFaddr_out_memwb_i,
-- output signals
controls_out => cw_towb_i,
from_mem_data_out => from_mem_data_out_i,
from_alu_data_out => from_alu_data_out_i,
regfile_addr_out => regfile_addr_out_towb_i
);
u_writeback: writeback
port map (
-- inputs
from_mem_data => from_mem_data_out_i,
from_alu_data => from_alu_data_out_i, -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in => regfile_addr_out_towb_i, -- address of regter to write
regwrite_in => cw_towb_i(2), -- control signal (1 -> write in reg file)
link => cw_towb_i(1), -- control signal (1 -> link the instruction, save IP in R31)
memtoreg => cw_towb_i(0),
-- outputs
regwrite_out => reg_write_i, -- control signal (send regwrite signal back to other stages)
regfile_data => data_write_i,
regfile_addr_out => address_write_i
);
end struct;
| mit | 802e2f5a2592796c8a749f086436af17 | 0.493904 | 4.190173 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/vhdl/ffaccel.vhdl | 2 | 46,193 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tce_util.all;
use work.ffaccel_globals.all;
use work.ffaccel_imem_mau.all;
use work.ffaccel_params.all;
entity ffaccel is
generic (
core_id : integer := 0);
port (
clk : in std_logic;
rstx : in std_logic;
busy : in std_logic;
imem_en_x : out std_logic;
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
locked : out std_logic;
fu_DATA_LSU_avalid_out : out std_logic_vector(0 downto 0);
fu_DATA_LSU_aready_in : in std_logic_vector(0 downto 0);
fu_DATA_LSU_aaddr_out : out std_logic_vector(fu_DATA_LSU_addrw_g-2-1 downto 0);
fu_DATA_LSU_awren_out : out std_logic_vector(0 downto 0);
fu_DATA_LSU_astrb_out : out std_logic_vector(3 downto 0);
fu_DATA_LSU_adata_out : out std_logic_vector(31 downto 0);
fu_DATA_LSU_rvalid_in : in std_logic_vector(0 downto 0);
fu_DATA_LSU_rready_out : out std_logic_vector(0 downto 0);
fu_DATA_LSU_rdata_in : in std_logic_vector(31 downto 0);
fu_PARAM_LSU_avalid_out : out std_logic_vector(0 downto 0);
fu_PARAM_LSU_aready_in : in std_logic_vector(0 downto 0);
fu_PARAM_LSU_aaddr_out : out std_logic_vector(fu_PARAM_LSU_addrw_g-2-1 downto 0);
fu_PARAM_LSU_awren_out : out std_logic_vector(0 downto 0);
fu_PARAM_LSU_astrb_out : out std_logic_vector(3 downto 0);
fu_PARAM_LSU_adata_out : out std_logic_vector(31 downto 0);
fu_PARAM_LSU_rvalid_in : in std_logic_vector(0 downto 0);
fu_PARAM_LSU_rready_out : out std_logic_vector(0 downto 0);
fu_PARAM_LSU_rdata_in : in std_logic_vector(31 downto 0);
fu_SP_LSU_avalid_out : out std_logic_vector(0 downto 0);
fu_SP_LSU_aready_in : in std_logic_vector(0 downto 0);
fu_SP_LSU_aaddr_out : out std_logic_vector(fu_SP_LSU_addrw_g-2-1 downto 0);
fu_SP_LSU_awren_out : out std_logic_vector(0 downto 0);
fu_SP_LSU_astrb_out : out std_logic_vector(3 downto 0);
fu_SP_LSU_adata_out : out std_logic_vector(31 downto 0);
fu_SP_LSU_rvalid_in : in std_logic_vector(0 downto 0);
fu_SP_LSU_rready_out : out std_logic_vector(0 downto 0);
fu_SP_LSU_rdata_in : in std_logic_vector(31 downto 0);
fu_AQL_FU_read_idx_out : out std_logic_vector(63 downto 0);
fu_AQL_FU_read_idx_clear_in : in std_logic_vector(0 downto 0);
db_tta_nreset : in std_logic;
db_lockcnt : out std_logic_vector(63 downto 0);
db_cyclecnt : out std_logic_vector(63 downto 0);
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
db_lockrq : in std_logic);
end ffaccel;
architecture structural of ffaccel is
signal decomp_fetch_en_wire : std_logic;
signal decomp_lock_wire : std_logic;
signal decomp_fetchblock_wire : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
signal decomp_instructionword_wire : std_logic_vector(INSTRUCTIONWIDTH-1 downto 0);
signal decomp_glock_wire : std_logic;
signal decomp_lock_r_wire : std_logic;
signal fu_AQL_FU_t1_data_in_wire : std_logic_vector(31 downto 0);
signal fu_AQL_FU_t1_load_in_wire : std_logic;
signal fu_AQL_FU_r1_data_out_wire : std_logic_vector(31 downto 0);
signal fu_AQL_FU_t1_opcode_in_wire : std_logic_vector(0 downto 0);
signal fu_AQL_FU_glock_wire : std_logic;
signal fu_DATA_LSU_t1_address_in_wire : std_logic_vector(11 downto 0);
signal fu_DATA_LSU_t1_load_in_wire : std_logic;
signal fu_DATA_LSU_r1_data_out_wire : std_logic_vector(31 downto 0);
signal fu_DATA_LSU_o1_data_in_wire : std_logic_vector(31 downto 0);
signal fu_DATA_LSU_o1_load_in_wire : std_logic;
signal fu_DATA_LSU_t1_opcode_in_wire : std_logic_vector(2 downto 0);
signal fu_DATA_LSU_glock_in_wire : std_logic;
signal fu_DATA_LSU_glockreq_out_wire : std_logic;
signal fu_PARAM_LSU_t1_address_in_wire : std_logic_vector(31 downto 0);
signal fu_PARAM_LSU_t1_load_in_wire : std_logic;
signal fu_PARAM_LSU_r1_data_out_wire : std_logic_vector(31 downto 0);
signal fu_PARAM_LSU_o1_data_in_wire : std_logic_vector(31 downto 0);
signal fu_PARAM_LSU_o1_load_in_wire : std_logic;
signal fu_PARAM_LSU_t1_opcode_in_wire : std_logic_vector(2 downto 0);
signal fu_PARAM_LSU_glock_in_wire : std_logic;
signal fu_PARAM_LSU_glockreq_out_wire : std_logic;
signal fu_SP_LSU_t1_address_in_wire : std_logic_vector(9 downto 0);
signal fu_SP_LSU_t1_load_in_wire : std_logic;
signal fu_SP_LSU_r1_data_out_wire : std_logic_vector(31 downto 0);
signal fu_SP_LSU_o1_data_in_wire : std_logic_vector(31 downto 0);
signal fu_SP_LSU_o1_load_in_wire : std_logic;
signal fu_SP_LSU_t1_opcode_in_wire : std_logic_vector(2 downto 0);
signal fu_SP_LSU_glock_in_wire : std_logic;
signal fu_SP_LSU_glockreq_out_wire : std_logic;
signal fu_alu_comp_generated_glock_in_wire : std_logic;
signal fu_alu_comp_generated_operation_in_wire : std_logic_vector(4-1 downto 0);
signal fu_alu_comp_generated_glockreq_out_wire : std_logic;
signal fu_alu_comp_generated_data_in1t_in_wire : std_logic_vector(32-1 downto 0);
signal fu_alu_comp_generated_load_in1t_in_wire : std_logic;
signal fu_alu_comp_generated_data_in2_in_wire : std_logic_vector(32-1 downto 0);
signal fu_alu_comp_generated_load_in2_in_wire : std_logic;
signal fu_alu_comp_generated_data_out1_out_wire : std_logic_vector(32-1 downto 0);
signal fu_alu_comp_generated_data_out2_out_wire : std_logic_vector(32-1 downto 0);
signal fu_alu_comp_generated_data_out3_out_wire : std_logic_vector(32-1 downto 0);
signal ic_glock_wire : std_logic;
signal ic_socket_lsu_i1_data_wire : std_logic_vector(11 downto 0);
signal ic_socket_lsu_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_lsu_i2_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_lsu_i2_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_alu_comp_i1_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_alu_comp_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_alu_comp_i2_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_alu_comp_i2_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_RF_i1_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_RF_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_bool_i1_data_wire : std_logic_vector(0 downto 0);
signal ic_socket_bool_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_gcu_i1_data_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal ic_socket_gcu_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_gcu_i2_data_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal ic_socket_gcu_i2_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_lsu_i1_1_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_lsu_i1_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_lsu_i2_1_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_lsu_i2_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_lsu_i2_1_1_data_wire : std_logic_vector(9 downto 0);
signal ic_socket_lsu_i2_1_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_lsu_i1_1_1_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_lsu_i1_1_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_socket_lsu_i2_1_1_2_1_data_wire : std_logic_vector(31 downto 0);
signal ic_socket_lsu_i2_1_1_2_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal ic_B1_mux_ctrl_in_wire : std_logic_vector(3 downto 0);
signal ic_B1_data_0_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_data_1_in_wire : std_logic_vector(32-1 downto 0);
signal ic_B1_data_2_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_data_3_in_wire : std_logic_vector(0 downto 0);
signal ic_B1_data_4_in_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal ic_B1_data_5_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_data_6_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_data_7_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_data_8_in_wire : std_logic_vector(32-1 downto 0);
signal ic_B1_data_9_in_wire : std_logic_vector(32-1 downto 0);
signal ic_B1_data_10_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_1_mux_ctrl_in_wire : std_logic_vector(3 downto 0);
signal ic_B1_1_data_0_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_1_data_1_in_wire : std_logic_vector(32-1 downto 0);
signal ic_B1_1_data_2_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_1_data_3_in_wire : std_logic_vector(0 downto 0);
signal ic_B1_1_data_4_in_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal ic_B1_1_data_5_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_1_data_6_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_1_data_7_in_wire : std_logic_vector(31 downto 0);
signal ic_B1_1_data_8_in_wire : std_logic_vector(32-1 downto 0);
signal ic_B1_1_data_9_in_wire : std_logic_vector(32-1 downto 0);
signal ic_B1_1_data_10_in_wire : std_logic_vector(31 downto 0);
signal ic_simm_B1_wire : std_logic_vector(31 downto 0);
signal ic_simm_cntrl_B1_wire : std_logic_vector(0 downto 0);
signal ic_simm_B1_1_wire : std_logic_vector(31 downto 0);
signal ic_simm_cntrl_B1_1_wire : std_logic_vector(0 downto 0);
signal inst_decoder_instructionword_wire : std_logic_vector(INSTRUCTIONWIDTH-1 downto 0);
signal inst_decoder_pc_load_wire : std_logic;
signal inst_decoder_ra_load_wire : std_logic;
signal inst_decoder_pc_opcode_wire : std_logic_vector(0 downto 0);
signal inst_decoder_lock_wire : std_logic;
signal inst_decoder_lock_r_wire : std_logic;
signal inst_decoder_simm_B1_wire : std_logic_vector(31 downto 0);
signal inst_decoder_simm_B1_1_wire : std_logic_vector(31 downto 0);
signal inst_decoder_socket_lsu_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_lsu_i2_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_alu_comp_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_alu_comp_i2_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_RF_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_bool_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_gcu_i1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_gcu_i2_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_lsu_i1_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_lsu_i2_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_lsu_i2_1_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_lsu_i1_1_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_socket_lsu_i2_1_1_2_1_bus_cntrl_wire : std_logic_vector(0 downto 0);
signal inst_decoder_B1_src_sel_wire : std_logic_vector(3 downto 0);
signal inst_decoder_B1_1_src_sel_wire : std_logic_vector(3 downto 0);
signal inst_decoder_fu_DATA_LSU_in1t_load_wire : std_logic;
signal inst_decoder_fu_DATA_LSU_in2_load_wire : std_logic;
signal inst_decoder_fu_DATA_LSU_opc_wire : std_logic_vector(2 downto 0);
signal inst_decoder_fu_alu_comp_in1t_load_wire : std_logic;
signal inst_decoder_fu_alu_comp_in2_load_wire : std_logic;
signal inst_decoder_fu_alu_comp_opc_wire : std_logic_vector(3 downto 0);
signal inst_decoder_fu_PARAM_LSU_in1t_load_wire : std_logic;
signal inst_decoder_fu_PARAM_LSU_in2_load_wire : std_logic;
signal inst_decoder_fu_PARAM_LSU_opc_wire : std_logic_vector(2 downto 0);
signal inst_decoder_fu_SP_LSU_in1t_load_wire : std_logic;
signal inst_decoder_fu_SP_LSU_in2_load_wire : std_logic;
signal inst_decoder_fu_SP_LSU_opc_wire : std_logic_vector(2 downto 0);
signal inst_decoder_fu_AQL_FU_t1_in_load_wire : std_logic;
signal inst_decoder_fu_AQL_FU_opc_wire : std_logic_vector(0 downto 0);
signal inst_decoder_rf_RF_wr_load_wire : std_logic;
signal inst_decoder_rf_RF_wr_opc_wire : std_logic_vector(4 downto 0);
signal inst_decoder_rf_RF_rd_load_wire : std_logic;
signal inst_decoder_rf_RF_rd_opc_wire : std_logic_vector(4 downto 0);
signal inst_decoder_rf_bool_wr_load_wire : std_logic;
signal inst_decoder_rf_bool_wr_opc_wire : std_logic_vector(0 downto 0);
signal inst_decoder_rf_bool_rd_load_wire : std_logic;
signal inst_decoder_rf_bool_rd_opc_wire : std_logic_vector(0 downto 0);
signal inst_decoder_iu_IMM_P1_read_load_wire : std_logic;
signal inst_decoder_iu_IMM_P1_read_opc_wire : std_logic_vector(0 downto 0);
signal inst_decoder_iu_IMM_write_wire : std_logic_vector(31 downto 0);
signal inst_decoder_iu_IMM_write_load_wire : std_logic;
signal inst_decoder_iu_IMM_write_opc_wire : std_logic_vector(0 downto 0);
signal inst_decoder_rf_guard_bool_0_wire : std_logic;
signal inst_decoder_rf_guard_bool_1_wire : std_logic;
signal inst_decoder_lock_req_wire : std_logic_vector(4 downto 0);
signal inst_decoder_glock_wire : std_logic_vector(8 downto 0);
signal inst_fetch_ra_out_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal inst_fetch_ra_in_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal inst_fetch_pc_in_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal inst_fetch_pc_load_wire : std_logic;
signal inst_fetch_ra_load_wire : std_logic;
signal inst_fetch_pc_opcode_wire : std_logic_vector(0 downto 0);
signal inst_fetch_fetch_en_wire : std_logic;
signal inst_fetch_glock_wire : std_logic;
signal inst_fetch_fetchblock_wire : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
signal iu_IMM_data_rd_out_wire : std_logic_vector(31 downto 0);
signal iu_IMM_load_rd_in_wire : std_logic;
signal iu_IMM_addr_rd_in_wire : std_logic_vector(0 downto 0);
signal iu_IMM_data_wr_in_wire : std_logic_vector(31 downto 0);
signal iu_IMM_load_wr_in_wire : std_logic;
signal iu_IMM_addr_wr_in_wire : std_logic_vector(0 downto 0);
signal iu_IMM_glock_in_wire : std_logic;
signal rf_RF_data_rd_out_wire : std_logic_vector(31 downto 0);
signal rf_RF_load_rd_in_wire : std_logic;
signal rf_RF_addr_rd_in_wire : std_logic_vector(4 downto 0);
signal rf_RF_data_wr_in_wire : std_logic_vector(31 downto 0);
signal rf_RF_load_wr_in_wire : std_logic;
signal rf_RF_addr_wr_in_wire : std_logic_vector(4 downto 0);
signal rf_RF_glock_in_wire : std_logic;
signal rf_bool_t1data_wire : std_logic_vector(0 downto 0);
signal rf_bool_t1load_wire : std_logic;
signal rf_bool_t1opcode_wire : std_logic_vector(0 downto 0);
signal rf_bool_r1data_wire : std_logic_vector(0 downto 0);
signal rf_bool_r1load_wire : std_logic;
signal rf_bool_r1opcode_wire : std_logic_vector(0 downto 0);
signal rf_bool_guard_wire : std_logic_vector(1 downto 0);
signal rf_bool_glock_wire : std_logic;
signal ground_signal : std_logic_vector(0 downto 0);
component ffaccel_ifetch
generic (
sync_reset_g : boolean;
debug_logic_g : boolean);
port (
clk : in std_logic;
rstx : in std_logic;
ra_out : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
ra_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
busy : in std_logic;
imem_en_x : out std_logic;
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
pc_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
pc_load : in std_logic;
ra_load : in std_logic;
pc_opcode : in std_logic_vector(1-1 downto 0);
fetch_en : in std_logic;
glock : out std_logic;
fetchblock : out std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
db_rstx : in std_logic;
db_lockreq : in std_logic;
db_cyclecnt : out std_logic_vector(64-1 downto 0);
db_lockcnt : out std_logic_vector(64-1 downto 0);
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0));
end component;
component ffaccel_decompressor
port (
fetch_en : out std_logic;
lock : in std_logic;
fetchblock : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
clk : in std_logic;
rstx : in std_logic;
instructionword : out std_logic_vector(INSTRUCTIONWIDTH-1 downto 0);
glock : out std_logic;
lock_r : in std_logic);
end component;
component ffaccel_decoder
port (
instructionword : in std_logic_vector(INSTRUCTIONWIDTH-1 downto 0);
pc_load : out std_logic;
ra_load : out std_logic;
pc_opcode : out std_logic_vector(1-1 downto 0);
lock : in std_logic;
lock_r : out std_logic;
clk : in std_logic;
rstx : in std_logic;
locked : out std_logic;
simm_B1 : out std_logic_vector(32-1 downto 0);
simm_B1_1 : out std_logic_vector(32-1 downto 0);
socket_lsu_i1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_lsu_i2_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_alu_comp_i1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_alu_comp_i2_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_RF_i1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_bool_i1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_gcu_i1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_gcu_i2_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_lsu_i1_1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_lsu_i2_1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_lsu_i2_1_1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_lsu_i1_1_1_bus_cntrl : out std_logic_vector(1-1 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl : out std_logic_vector(1-1 downto 0);
B1_src_sel : out std_logic_vector(4-1 downto 0);
B1_1_src_sel : out std_logic_vector(4-1 downto 0);
fu_DATA_LSU_in1t_load : out std_logic;
fu_DATA_LSU_in2_load : out std_logic;
fu_DATA_LSU_opc : out std_logic_vector(3-1 downto 0);
fu_alu_comp_in1t_load : out std_logic;
fu_alu_comp_in2_load : out std_logic;
fu_alu_comp_opc : out std_logic_vector(4-1 downto 0);
fu_PARAM_LSU_in1t_load : out std_logic;
fu_PARAM_LSU_in2_load : out std_logic;
fu_PARAM_LSU_opc : out std_logic_vector(3-1 downto 0);
fu_SP_LSU_in1t_load : out std_logic;
fu_SP_LSU_in2_load : out std_logic;
fu_SP_LSU_opc : out std_logic_vector(3-1 downto 0);
fu_AQL_FU_t1_in_load : out std_logic;
fu_AQL_FU_opc : out std_logic_vector(1-1 downto 0);
rf_RF_wr_load : out std_logic;
rf_RF_wr_opc : out std_logic_vector(5-1 downto 0);
rf_RF_rd_load : out std_logic;
rf_RF_rd_opc : out std_logic_vector(5-1 downto 0);
rf_bool_wr_load : out std_logic;
rf_bool_wr_opc : out std_logic_vector(1-1 downto 0);
rf_bool_rd_load : out std_logic;
rf_bool_rd_opc : out std_logic_vector(1-1 downto 0);
iu_IMM_P1_read_load : out std_logic;
iu_IMM_P1_read_opc : out std_logic_vector(0 downto 0);
iu_IMM_write : out std_logic_vector(32-1 downto 0);
iu_IMM_write_load : out std_logic;
iu_IMM_write_opc : out std_logic_vector(0 downto 0);
rf_guard_bool_0 : in std_logic;
rf_guard_bool_1 : in std_logic;
lock_req : in std_logic_vector(5-1 downto 0);
glock : out std_logic_vector(9-1 downto 0);
db_tta_nreset : in std_logic);
end component;
component fu_alu_comp
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
operation_in : in std_logic_vector(4-1 downto 0);
glockreq_out : out std_logic;
data_in1t_in : in std_logic_vector(32-1 downto 0);
load_in1t_in : in std_logic;
data_in2_in : in std_logic_vector(32-1 downto 0);
load_in2_in : in std_logic;
data_out1_out : out std_logic_vector(32-1 downto 0);
data_out2_out : out std_logic_vector(32-1 downto 0);
data_out3_out : out std_logic_vector(32-1 downto 0));
end component;
component fu_lsu_32b_slim
generic (
addrw_g : integer;
register_bypass_g : integer;
little_endian_g : integer);
port (
t1_address_in : in std_logic_vector(addrw_g-1 downto 0);
t1_load_in : in std_logic;
r1_data_out : out std_logic_vector(32-1 downto 0);
o1_data_in : in std_logic_vector(32-1 downto 0);
o1_load_in : in std_logic;
t1_opcode_in : in std_logic_vector(3-1 downto 0);
avalid_out : out std_logic_vector(1-1 downto 0);
aready_in : in std_logic_vector(1-1 downto 0);
aaddr_out : out std_logic_vector(addrw_g-2-1 downto 0);
awren_out : out std_logic_vector(1-1 downto 0);
astrb_out : out std_logic_vector(4-1 downto 0);
adata_out : out std_logic_vector(32-1 downto 0);
rvalid_in : in std_logic_vector(1-1 downto 0);
rready_out : out std_logic_vector(1-1 downto 0);
rdata_in : in std_logic_vector(32-1 downto 0);
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
glockreq_out : out std_logic);
end component;
component fu_aql_minimal
port (
t1_data_in : in std_logic_vector(32-1 downto 0);
t1_load_in : in std_logic;
r1_data_out : out std_logic_vector(32-1 downto 0);
t1_opcode_in : in std_logic_vector(1-1 downto 0);
read_idx_out : out std_logic_vector(64-1 downto 0);
read_idx_clear_in : in std_logic_vector(1-1 downto 0);
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic);
end component;
component s7_rf_1wr_1rd
generic (
width_g : integer;
depth_g : integer);
port (
data_rd_out : out std_logic_vector(width_g-1 downto 0);
load_rd_in : in std_logic;
addr_rd_in : in std_logic_vector(bit_width(depth_g)-1 downto 0);
data_wr_in : in std_logic_vector(width_g-1 downto 0);
load_wr_in : in std_logic;
addr_wr_in : in std_logic_vector(bit_width(depth_g)-1 downto 0);
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic);
end component;
component rf_1wr_1rd_always_1_guarded_0
generic (
dataw : integer;
rf_size : integer);
port (
t1data : in std_logic_vector(dataw-1 downto 0);
t1load : in std_logic;
t1opcode : in std_logic_vector(bit_width(rf_size)-1 downto 0);
r1data : out std_logic_vector(dataw-1 downto 0);
r1load : in std_logic;
r1opcode : in std_logic_vector(bit_width(rf_size)-1 downto 0);
guard : out std_logic_vector(rf_size-1 downto 0);
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic);
end component;
component ffaccel_interconn
port (
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic;
socket_lsu_i1_data : out std_logic_vector(12-1 downto 0);
socket_lsu_i1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_lsu_i2_data : out std_logic_vector(32-1 downto 0);
socket_lsu_i2_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_alu_comp_i1_data : out std_logic_vector(32-1 downto 0);
socket_alu_comp_i1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_alu_comp_i2_data : out std_logic_vector(32-1 downto 0);
socket_alu_comp_i2_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_RF_i1_data : out std_logic_vector(32-1 downto 0);
socket_RF_i1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_bool_i1_data : out std_logic_vector(1-1 downto 0);
socket_bool_i1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_gcu_i1_data : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
socket_gcu_i1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_gcu_i2_data : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
socket_gcu_i2_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_lsu_i1_1_data : out std_logic_vector(32-1 downto 0);
socket_lsu_i1_1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_lsu_i2_1_data : out std_logic_vector(32-1 downto 0);
socket_lsu_i2_1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_lsu_i2_1_1_data : out std_logic_vector(10-1 downto 0);
socket_lsu_i2_1_1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_lsu_i1_1_1_data : out std_logic_vector(32-1 downto 0);
socket_lsu_i1_1_1_bus_cntrl : in std_logic_vector(1-1 downto 0);
socket_lsu_i2_1_1_2_1_data : out std_logic_vector(32-1 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl : in std_logic_vector(1-1 downto 0);
B1_mux_ctrl_in : in std_logic_vector(4-1 downto 0);
B1_data_0_in : in std_logic_vector(32-1 downto 0);
B1_data_1_in : in std_logic_vector(32-1 downto 0);
B1_data_2_in : in std_logic_vector(32-1 downto 0);
B1_data_3_in : in std_logic_vector(1-1 downto 0);
B1_data_4_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
B1_data_5_in : in std_logic_vector(32-1 downto 0);
B1_data_6_in : in std_logic_vector(32-1 downto 0);
B1_data_7_in : in std_logic_vector(32-1 downto 0);
B1_data_8_in : in std_logic_vector(32-1 downto 0);
B1_data_9_in : in std_logic_vector(32-1 downto 0);
B1_data_10_in : in std_logic_vector(32-1 downto 0);
B1_1_mux_ctrl_in : in std_logic_vector(4-1 downto 0);
B1_1_data_0_in : in std_logic_vector(32-1 downto 0);
B1_1_data_1_in : in std_logic_vector(32-1 downto 0);
B1_1_data_2_in : in std_logic_vector(32-1 downto 0);
B1_1_data_3_in : in std_logic_vector(1-1 downto 0);
B1_1_data_4_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
B1_1_data_5_in : in std_logic_vector(32-1 downto 0);
B1_1_data_6_in : in std_logic_vector(32-1 downto 0);
B1_1_data_7_in : in std_logic_vector(32-1 downto 0);
B1_1_data_8_in : in std_logic_vector(32-1 downto 0);
B1_1_data_9_in : in std_logic_vector(32-1 downto 0);
B1_1_data_10_in : in std_logic_vector(32-1 downto 0);
simm_B1 : in std_logic_vector(32-1 downto 0);
simm_cntrl_B1 : in std_logic_vector(1-1 downto 0);
simm_B1_1 : in std_logic_vector(32-1 downto 0);
simm_cntrl_B1_1 : in std_logic_vector(1-1 downto 0));
end component;
begin
ic_B1_data_4_in_wire <= inst_fetch_ra_out_wire;
ic_B1_1_data_4_in_wire <= inst_fetch_ra_out_wire;
inst_fetch_ra_in_wire <= ic_socket_gcu_i2_data_wire;
inst_fetch_pc_in_wire <= ic_socket_gcu_i1_data_wire;
inst_fetch_pc_load_wire <= inst_decoder_pc_load_wire;
inst_fetch_ra_load_wire <= inst_decoder_ra_load_wire;
inst_fetch_pc_opcode_wire <= inst_decoder_pc_opcode_wire;
inst_fetch_fetch_en_wire <= decomp_fetch_en_wire;
decomp_lock_wire <= inst_fetch_glock_wire;
decomp_fetchblock_wire <= inst_fetch_fetchblock_wire;
inst_decoder_instructionword_wire <= decomp_instructionword_wire;
inst_decoder_lock_wire <= decomp_glock_wire;
decomp_lock_r_wire <= inst_decoder_lock_r_wire;
ic_simm_B1_wire <= inst_decoder_simm_B1_wire;
ic_simm_B1_1_wire <= inst_decoder_simm_B1_1_wire;
ic_socket_lsu_i1_bus_cntrl_wire <= inst_decoder_socket_lsu_i1_bus_cntrl_wire;
ic_socket_lsu_i2_bus_cntrl_wire <= inst_decoder_socket_lsu_i2_bus_cntrl_wire;
ic_socket_alu_comp_i1_bus_cntrl_wire <= inst_decoder_socket_alu_comp_i1_bus_cntrl_wire;
ic_socket_alu_comp_i2_bus_cntrl_wire <= inst_decoder_socket_alu_comp_i2_bus_cntrl_wire;
ic_socket_RF_i1_bus_cntrl_wire <= inst_decoder_socket_RF_i1_bus_cntrl_wire;
ic_socket_bool_i1_bus_cntrl_wire <= inst_decoder_socket_bool_i1_bus_cntrl_wire;
ic_socket_gcu_i1_bus_cntrl_wire <= inst_decoder_socket_gcu_i1_bus_cntrl_wire;
ic_socket_gcu_i2_bus_cntrl_wire <= inst_decoder_socket_gcu_i2_bus_cntrl_wire;
ic_socket_lsu_i1_1_bus_cntrl_wire <= inst_decoder_socket_lsu_i1_1_bus_cntrl_wire;
ic_socket_lsu_i2_1_bus_cntrl_wire <= inst_decoder_socket_lsu_i2_1_bus_cntrl_wire;
ic_socket_lsu_i2_1_1_bus_cntrl_wire <= inst_decoder_socket_lsu_i2_1_1_bus_cntrl_wire;
ic_socket_lsu_i1_1_1_bus_cntrl_wire <= inst_decoder_socket_lsu_i1_1_1_bus_cntrl_wire;
ic_socket_lsu_i2_1_1_2_1_bus_cntrl_wire <= inst_decoder_socket_lsu_i2_1_1_2_1_bus_cntrl_wire;
ic_B1_mux_ctrl_in_wire <= inst_decoder_B1_src_sel_wire;
ic_B1_1_mux_ctrl_in_wire <= inst_decoder_B1_1_src_sel_wire;
fu_DATA_LSU_t1_load_in_wire <= inst_decoder_fu_DATA_LSU_in1t_load_wire;
fu_DATA_LSU_o1_load_in_wire <= inst_decoder_fu_DATA_LSU_in2_load_wire;
fu_DATA_LSU_t1_opcode_in_wire <= inst_decoder_fu_DATA_LSU_opc_wire;
fu_alu_comp_generated_load_in1t_in_wire <= inst_decoder_fu_alu_comp_in1t_load_wire;
fu_alu_comp_generated_load_in2_in_wire <= inst_decoder_fu_alu_comp_in2_load_wire;
fu_alu_comp_generated_operation_in_wire <= inst_decoder_fu_alu_comp_opc_wire;
fu_PARAM_LSU_t1_load_in_wire <= inst_decoder_fu_PARAM_LSU_in1t_load_wire;
fu_PARAM_LSU_o1_load_in_wire <= inst_decoder_fu_PARAM_LSU_in2_load_wire;
fu_PARAM_LSU_t1_opcode_in_wire <= inst_decoder_fu_PARAM_LSU_opc_wire;
fu_SP_LSU_t1_load_in_wire <= inst_decoder_fu_SP_LSU_in1t_load_wire;
fu_SP_LSU_o1_load_in_wire <= inst_decoder_fu_SP_LSU_in2_load_wire;
fu_SP_LSU_t1_opcode_in_wire <= inst_decoder_fu_SP_LSU_opc_wire;
fu_AQL_FU_t1_load_in_wire <= inst_decoder_fu_AQL_FU_t1_in_load_wire;
fu_AQL_FU_t1_opcode_in_wire <= inst_decoder_fu_AQL_FU_opc_wire;
rf_RF_load_wr_in_wire <= inst_decoder_rf_RF_wr_load_wire;
rf_RF_addr_wr_in_wire <= inst_decoder_rf_RF_wr_opc_wire;
rf_RF_load_rd_in_wire <= inst_decoder_rf_RF_rd_load_wire;
rf_RF_addr_rd_in_wire <= inst_decoder_rf_RF_rd_opc_wire;
rf_bool_t1load_wire <= inst_decoder_rf_bool_wr_load_wire;
rf_bool_t1opcode_wire <= inst_decoder_rf_bool_wr_opc_wire;
rf_bool_r1load_wire <= inst_decoder_rf_bool_rd_load_wire;
rf_bool_r1opcode_wire <= inst_decoder_rf_bool_rd_opc_wire;
iu_IMM_load_rd_in_wire <= inst_decoder_iu_IMM_P1_read_load_wire;
iu_IMM_addr_rd_in_wire <= inst_decoder_iu_IMM_P1_read_opc_wire;
iu_IMM_data_wr_in_wire <= inst_decoder_iu_IMM_write_wire;
iu_IMM_load_wr_in_wire <= inst_decoder_iu_IMM_write_load_wire;
iu_IMM_addr_wr_in_wire <= inst_decoder_iu_IMM_write_opc_wire;
inst_decoder_rf_guard_bool_0_wire <= rf_bool_guard_wire(0);
inst_decoder_rf_guard_bool_1_wire <= rf_bool_guard_wire(1);
inst_decoder_lock_req_wire(0) <= fu_DATA_LSU_glockreq_out_wire;
inst_decoder_lock_req_wire(1) <= fu_alu_comp_generated_glockreq_out_wire;
inst_decoder_lock_req_wire(2) <= fu_PARAM_LSU_glockreq_out_wire;
inst_decoder_lock_req_wire(3) <= fu_SP_LSU_glockreq_out_wire;
inst_decoder_lock_req_wire(4) <= db_lockrq;
fu_DATA_LSU_glock_in_wire <= inst_decoder_glock_wire(0);
fu_alu_comp_generated_glock_in_wire <= inst_decoder_glock_wire(1);
fu_PARAM_LSU_glock_in_wire <= inst_decoder_glock_wire(2);
fu_SP_LSU_glock_in_wire <= inst_decoder_glock_wire(3);
fu_AQL_FU_glock_wire <= inst_decoder_glock_wire(4);
rf_RF_glock_in_wire <= inst_decoder_glock_wire(5);
rf_bool_glock_wire <= inst_decoder_glock_wire(6);
iu_IMM_glock_in_wire <= inst_decoder_glock_wire(7);
ic_glock_wire <= inst_decoder_glock_wire(8);
fu_alu_comp_generated_data_in1t_in_wire <= ic_socket_alu_comp_i1_data_wire;
fu_alu_comp_generated_data_in2_in_wire <= ic_socket_alu_comp_i2_data_wire;
ic_B1_data_1_in_wire <= fu_alu_comp_generated_data_out1_out_wire;
ic_B1_1_data_1_in_wire <= fu_alu_comp_generated_data_out1_out_wire;
ic_B1_data_8_in_wire <= fu_alu_comp_generated_data_out2_out_wire;
ic_B1_1_data_8_in_wire <= fu_alu_comp_generated_data_out2_out_wire;
ic_B1_data_9_in_wire <= fu_alu_comp_generated_data_out3_out_wire;
ic_B1_1_data_9_in_wire <= fu_alu_comp_generated_data_out3_out_wire;
fu_DATA_LSU_t1_address_in_wire <= ic_socket_lsu_i1_data_wire;
ic_B1_data_0_in_wire <= fu_DATA_LSU_r1_data_out_wire;
ic_B1_1_data_0_in_wire <= fu_DATA_LSU_r1_data_out_wire;
fu_DATA_LSU_o1_data_in_wire <= ic_socket_lsu_i2_data_wire;
fu_PARAM_LSU_t1_address_in_wire <= ic_socket_lsu_i1_1_data_wire;
ic_B1_data_5_in_wire <= fu_PARAM_LSU_r1_data_out_wire;
ic_B1_1_data_5_in_wire <= fu_PARAM_LSU_r1_data_out_wire;
fu_PARAM_LSU_o1_data_in_wire <= ic_socket_lsu_i2_1_data_wire;
fu_SP_LSU_t1_address_in_wire <= ic_socket_lsu_i2_1_1_data_wire;
ic_B1_data_7_in_wire <= fu_SP_LSU_r1_data_out_wire;
ic_B1_1_data_7_in_wire <= fu_SP_LSU_r1_data_out_wire;
fu_SP_LSU_o1_data_in_wire <= ic_socket_lsu_i1_1_1_data_wire;
fu_AQL_FU_t1_data_in_wire <= ic_socket_lsu_i2_1_1_2_1_data_wire;
ic_B1_data_10_in_wire <= fu_AQL_FU_r1_data_out_wire;
ic_B1_1_data_10_in_wire <= fu_AQL_FU_r1_data_out_wire;
ic_B1_data_2_in_wire <= rf_RF_data_rd_out_wire;
ic_B1_1_data_2_in_wire <= rf_RF_data_rd_out_wire;
rf_RF_data_wr_in_wire <= ic_socket_RF_i1_data_wire;
rf_bool_t1data_wire <= ic_socket_bool_i1_data_wire;
ic_B1_data_3_in_wire <= rf_bool_r1data_wire;
ic_B1_1_data_3_in_wire <= rf_bool_r1data_wire;
ic_B1_data_6_in_wire <= iu_IMM_data_rd_out_wire;
ic_B1_1_data_6_in_wire <= iu_IMM_data_rd_out_wire;
ground_signal <= (others => '0');
inst_fetch : ffaccel_ifetch
generic map (
sync_reset_g => true,
debug_logic_g => true)
port map (
clk => clk,
rstx => rstx,
ra_out => inst_fetch_ra_out_wire,
ra_in => inst_fetch_ra_in_wire,
busy => busy,
imem_en_x => imem_en_x,
imem_addr => imem_addr,
imem_data => imem_data,
pc_in => inst_fetch_pc_in_wire,
pc_load => inst_fetch_pc_load_wire,
ra_load => inst_fetch_ra_load_wire,
pc_opcode => inst_fetch_pc_opcode_wire,
fetch_en => inst_fetch_fetch_en_wire,
glock => inst_fetch_glock_wire,
fetchblock => inst_fetch_fetchblock_wire,
db_rstx => db_tta_nreset,
db_lockreq => db_lockrq,
db_cyclecnt => db_cyclecnt,
db_lockcnt => db_lockcnt,
db_pc => db_pc);
decomp : ffaccel_decompressor
port map (
fetch_en => decomp_fetch_en_wire,
lock => decomp_lock_wire,
fetchblock => decomp_fetchblock_wire,
clk => clk,
rstx => rstx,
instructionword => decomp_instructionword_wire,
glock => decomp_glock_wire,
lock_r => decomp_lock_r_wire);
inst_decoder : ffaccel_decoder
port map (
instructionword => inst_decoder_instructionword_wire,
pc_load => inst_decoder_pc_load_wire,
ra_load => inst_decoder_ra_load_wire,
pc_opcode => inst_decoder_pc_opcode_wire,
lock => inst_decoder_lock_wire,
lock_r => inst_decoder_lock_r_wire,
clk => clk,
rstx => rstx,
locked => locked,
simm_B1 => inst_decoder_simm_B1_wire,
simm_B1_1 => inst_decoder_simm_B1_1_wire,
socket_lsu_i1_bus_cntrl => inst_decoder_socket_lsu_i1_bus_cntrl_wire,
socket_lsu_i2_bus_cntrl => inst_decoder_socket_lsu_i2_bus_cntrl_wire,
socket_alu_comp_i1_bus_cntrl => inst_decoder_socket_alu_comp_i1_bus_cntrl_wire,
socket_alu_comp_i2_bus_cntrl => inst_decoder_socket_alu_comp_i2_bus_cntrl_wire,
socket_RF_i1_bus_cntrl => inst_decoder_socket_RF_i1_bus_cntrl_wire,
socket_bool_i1_bus_cntrl => inst_decoder_socket_bool_i1_bus_cntrl_wire,
socket_gcu_i1_bus_cntrl => inst_decoder_socket_gcu_i1_bus_cntrl_wire,
socket_gcu_i2_bus_cntrl => inst_decoder_socket_gcu_i2_bus_cntrl_wire,
socket_lsu_i1_1_bus_cntrl => inst_decoder_socket_lsu_i1_1_bus_cntrl_wire,
socket_lsu_i2_1_bus_cntrl => inst_decoder_socket_lsu_i2_1_bus_cntrl_wire,
socket_lsu_i2_1_1_bus_cntrl => inst_decoder_socket_lsu_i2_1_1_bus_cntrl_wire,
socket_lsu_i1_1_1_bus_cntrl => inst_decoder_socket_lsu_i1_1_1_bus_cntrl_wire,
socket_lsu_i2_1_1_2_1_bus_cntrl => inst_decoder_socket_lsu_i2_1_1_2_1_bus_cntrl_wire,
B1_src_sel => inst_decoder_B1_src_sel_wire,
B1_1_src_sel => inst_decoder_B1_1_src_sel_wire,
fu_DATA_LSU_in1t_load => inst_decoder_fu_DATA_LSU_in1t_load_wire,
fu_DATA_LSU_in2_load => inst_decoder_fu_DATA_LSU_in2_load_wire,
fu_DATA_LSU_opc => inst_decoder_fu_DATA_LSU_opc_wire,
fu_alu_comp_in1t_load => inst_decoder_fu_alu_comp_in1t_load_wire,
fu_alu_comp_in2_load => inst_decoder_fu_alu_comp_in2_load_wire,
fu_alu_comp_opc => inst_decoder_fu_alu_comp_opc_wire,
fu_PARAM_LSU_in1t_load => inst_decoder_fu_PARAM_LSU_in1t_load_wire,
fu_PARAM_LSU_in2_load => inst_decoder_fu_PARAM_LSU_in2_load_wire,
fu_PARAM_LSU_opc => inst_decoder_fu_PARAM_LSU_opc_wire,
fu_SP_LSU_in1t_load => inst_decoder_fu_SP_LSU_in1t_load_wire,
fu_SP_LSU_in2_load => inst_decoder_fu_SP_LSU_in2_load_wire,
fu_SP_LSU_opc => inst_decoder_fu_SP_LSU_opc_wire,
fu_AQL_FU_t1_in_load => inst_decoder_fu_AQL_FU_t1_in_load_wire,
fu_AQL_FU_opc => inst_decoder_fu_AQL_FU_opc_wire,
rf_RF_wr_load => inst_decoder_rf_RF_wr_load_wire,
rf_RF_wr_opc => inst_decoder_rf_RF_wr_opc_wire,
rf_RF_rd_load => inst_decoder_rf_RF_rd_load_wire,
rf_RF_rd_opc => inst_decoder_rf_RF_rd_opc_wire,
rf_bool_wr_load => inst_decoder_rf_bool_wr_load_wire,
rf_bool_wr_opc => inst_decoder_rf_bool_wr_opc_wire,
rf_bool_rd_load => inst_decoder_rf_bool_rd_load_wire,
rf_bool_rd_opc => inst_decoder_rf_bool_rd_opc_wire,
iu_IMM_P1_read_load => inst_decoder_iu_IMM_P1_read_load_wire,
iu_IMM_P1_read_opc => inst_decoder_iu_IMM_P1_read_opc_wire,
iu_IMM_write => inst_decoder_iu_IMM_write_wire,
iu_IMM_write_load => inst_decoder_iu_IMM_write_load_wire,
iu_IMM_write_opc => inst_decoder_iu_IMM_write_opc_wire,
rf_guard_bool_0 => inst_decoder_rf_guard_bool_0_wire,
rf_guard_bool_1 => inst_decoder_rf_guard_bool_1_wire,
lock_req => inst_decoder_lock_req_wire,
glock => inst_decoder_glock_wire,
db_tta_nreset => db_tta_nreset);
fu_alu_comp_generated : fu_alu_comp
port map (
clk => clk,
rstx => rstx,
glock_in => fu_alu_comp_generated_glock_in_wire,
operation_in => fu_alu_comp_generated_operation_in_wire,
glockreq_out => fu_alu_comp_generated_glockreq_out_wire,
data_in1t_in => fu_alu_comp_generated_data_in1t_in_wire,
load_in1t_in => fu_alu_comp_generated_load_in1t_in_wire,
data_in2_in => fu_alu_comp_generated_data_in2_in_wire,
load_in2_in => fu_alu_comp_generated_load_in2_in_wire,
data_out1_out => fu_alu_comp_generated_data_out1_out_wire,
data_out2_out => fu_alu_comp_generated_data_out2_out_wire,
data_out3_out => fu_alu_comp_generated_data_out3_out_wire);
fu_DATA_LSU : fu_lsu_32b_slim
generic map (
addrw_g => fu_DATA_LSU_addrw_g,
register_bypass_g => 2,
little_endian_g => 1)
port map (
t1_address_in => fu_DATA_LSU_t1_address_in_wire,
t1_load_in => fu_DATA_LSU_t1_load_in_wire,
r1_data_out => fu_DATA_LSU_r1_data_out_wire,
o1_data_in => fu_DATA_LSU_o1_data_in_wire,
o1_load_in => fu_DATA_LSU_o1_load_in_wire,
t1_opcode_in => fu_DATA_LSU_t1_opcode_in_wire,
avalid_out => fu_DATA_LSU_avalid_out,
aready_in => fu_DATA_LSU_aready_in,
aaddr_out => fu_DATA_LSU_aaddr_out,
awren_out => fu_DATA_LSU_awren_out,
astrb_out => fu_DATA_LSU_astrb_out,
adata_out => fu_DATA_LSU_adata_out,
rvalid_in => fu_DATA_LSU_rvalid_in,
rready_out => fu_DATA_LSU_rready_out,
rdata_in => fu_DATA_LSU_rdata_in,
clk => clk,
rstx => rstx,
glock_in => fu_DATA_LSU_glock_in_wire,
glockreq_out => fu_DATA_LSU_glockreq_out_wire);
fu_PARAM_LSU : fu_lsu_32b_slim
generic map (
addrw_g => fu_PARAM_LSU_addrw_g,
register_bypass_g => 2,
little_endian_g => 1)
port map (
t1_address_in => fu_PARAM_LSU_t1_address_in_wire,
t1_load_in => fu_PARAM_LSU_t1_load_in_wire,
r1_data_out => fu_PARAM_LSU_r1_data_out_wire,
o1_data_in => fu_PARAM_LSU_o1_data_in_wire,
o1_load_in => fu_PARAM_LSU_o1_load_in_wire,
t1_opcode_in => fu_PARAM_LSU_t1_opcode_in_wire,
avalid_out => fu_PARAM_LSU_avalid_out,
aready_in => fu_PARAM_LSU_aready_in,
aaddr_out => fu_PARAM_LSU_aaddr_out,
awren_out => fu_PARAM_LSU_awren_out,
astrb_out => fu_PARAM_LSU_astrb_out,
adata_out => fu_PARAM_LSU_adata_out,
rvalid_in => fu_PARAM_LSU_rvalid_in,
rready_out => fu_PARAM_LSU_rready_out,
rdata_in => fu_PARAM_LSU_rdata_in,
clk => clk,
rstx => rstx,
glock_in => fu_PARAM_LSU_glock_in_wire,
glockreq_out => fu_PARAM_LSU_glockreq_out_wire);
fu_SP_LSU : fu_lsu_32b_slim
generic map (
addrw_g => fu_SP_LSU_addrw_g,
register_bypass_g => 2,
little_endian_g => 1)
port map (
t1_address_in => fu_SP_LSU_t1_address_in_wire,
t1_load_in => fu_SP_LSU_t1_load_in_wire,
r1_data_out => fu_SP_LSU_r1_data_out_wire,
o1_data_in => fu_SP_LSU_o1_data_in_wire,
o1_load_in => fu_SP_LSU_o1_load_in_wire,
t1_opcode_in => fu_SP_LSU_t1_opcode_in_wire,
avalid_out => fu_SP_LSU_avalid_out,
aready_in => fu_SP_LSU_aready_in,
aaddr_out => fu_SP_LSU_aaddr_out,
awren_out => fu_SP_LSU_awren_out,
astrb_out => fu_SP_LSU_astrb_out,
adata_out => fu_SP_LSU_adata_out,
rvalid_in => fu_SP_LSU_rvalid_in,
rready_out => fu_SP_LSU_rready_out,
rdata_in => fu_SP_LSU_rdata_in,
clk => clk,
rstx => rstx,
glock_in => fu_SP_LSU_glock_in_wire,
glockreq_out => fu_SP_LSU_glockreq_out_wire);
fu_AQL_FU : fu_aql_minimal
port map (
t1_data_in => fu_AQL_FU_t1_data_in_wire,
t1_load_in => fu_AQL_FU_t1_load_in_wire,
r1_data_out => fu_AQL_FU_r1_data_out_wire,
t1_opcode_in => fu_AQL_FU_t1_opcode_in_wire,
read_idx_out => fu_AQL_FU_read_idx_out,
read_idx_clear_in => fu_AQL_FU_read_idx_clear_in,
clk => clk,
rstx => rstx,
glock => fu_AQL_FU_glock_wire);
rf_RF : s7_rf_1wr_1rd
generic map (
width_g => 32,
depth_g => 32)
port map (
data_rd_out => rf_RF_data_rd_out_wire,
load_rd_in => rf_RF_load_rd_in_wire,
addr_rd_in => rf_RF_addr_rd_in_wire,
data_wr_in => rf_RF_data_wr_in_wire,
load_wr_in => rf_RF_load_wr_in_wire,
addr_wr_in => rf_RF_addr_wr_in_wire,
clk => clk,
rstx => rstx,
glock_in => rf_RF_glock_in_wire);
rf_bool : rf_1wr_1rd_always_1_guarded_0
generic map (
dataw => 1,
rf_size => 2)
port map (
t1data => rf_bool_t1data_wire,
t1load => rf_bool_t1load_wire,
t1opcode => rf_bool_t1opcode_wire,
r1data => rf_bool_r1data_wire,
r1load => rf_bool_r1load_wire,
r1opcode => rf_bool_r1opcode_wire,
guard => rf_bool_guard_wire,
clk => clk,
rstx => rstx,
glock => rf_bool_glock_wire);
iu_IMM : s7_rf_1wr_1rd
generic map (
width_g => 32,
depth_g => 1)
port map (
data_rd_out => iu_IMM_data_rd_out_wire,
load_rd_in => iu_IMM_load_rd_in_wire,
addr_rd_in => iu_IMM_addr_rd_in_wire,
data_wr_in => iu_IMM_data_wr_in_wire,
load_wr_in => iu_IMM_load_wr_in_wire,
addr_wr_in => iu_IMM_addr_wr_in_wire,
clk => clk,
rstx => rstx,
glock_in => iu_IMM_glock_in_wire);
ic : ffaccel_interconn
port map (
clk => clk,
rstx => rstx,
glock => ic_glock_wire,
socket_lsu_i1_data => ic_socket_lsu_i1_data_wire,
socket_lsu_i1_bus_cntrl => ic_socket_lsu_i1_bus_cntrl_wire,
socket_lsu_i2_data => ic_socket_lsu_i2_data_wire,
socket_lsu_i2_bus_cntrl => ic_socket_lsu_i2_bus_cntrl_wire,
socket_alu_comp_i1_data => ic_socket_alu_comp_i1_data_wire,
socket_alu_comp_i1_bus_cntrl => ic_socket_alu_comp_i1_bus_cntrl_wire,
socket_alu_comp_i2_data => ic_socket_alu_comp_i2_data_wire,
socket_alu_comp_i2_bus_cntrl => ic_socket_alu_comp_i2_bus_cntrl_wire,
socket_RF_i1_data => ic_socket_RF_i1_data_wire,
socket_RF_i1_bus_cntrl => ic_socket_RF_i1_bus_cntrl_wire,
socket_bool_i1_data => ic_socket_bool_i1_data_wire,
socket_bool_i1_bus_cntrl => ic_socket_bool_i1_bus_cntrl_wire,
socket_gcu_i1_data => ic_socket_gcu_i1_data_wire,
socket_gcu_i1_bus_cntrl => ic_socket_gcu_i1_bus_cntrl_wire,
socket_gcu_i2_data => ic_socket_gcu_i2_data_wire,
socket_gcu_i2_bus_cntrl => ic_socket_gcu_i2_bus_cntrl_wire,
socket_lsu_i1_1_data => ic_socket_lsu_i1_1_data_wire,
socket_lsu_i1_1_bus_cntrl => ic_socket_lsu_i1_1_bus_cntrl_wire,
socket_lsu_i2_1_data => ic_socket_lsu_i2_1_data_wire,
socket_lsu_i2_1_bus_cntrl => ic_socket_lsu_i2_1_bus_cntrl_wire,
socket_lsu_i2_1_1_data => ic_socket_lsu_i2_1_1_data_wire,
socket_lsu_i2_1_1_bus_cntrl => ic_socket_lsu_i2_1_1_bus_cntrl_wire,
socket_lsu_i1_1_1_data => ic_socket_lsu_i1_1_1_data_wire,
socket_lsu_i1_1_1_bus_cntrl => ic_socket_lsu_i1_1_1_bus_cntrl_wire,
socket_lsu_i2_1_1_2_1_data => ic_socket_lsu_i2_1_1_2_1_data_wire,
socket_lsu_i2_1_1_2_1_bus_cntrl => ic_socket_lsu_i2_1_1_2_1_bus_cntrl_wire,
B1_mux_ctrl_in => ic_B1_mux_ctrl_in_wire,
B1_data_0_in => ic_B1_data_0_in_wire,
B1_data_1_in => ic_B1_data_1_in_wire,
B1_data_2_in => ic_B1_data_2_in_wire,
B1_data_3_in => ic_B1_data_3_in_wire,
B1_data_4_in => ic_B1_data_4_in_wire,
B1_data_5_in => ic_B1_data_5_in_wire,
B1_data_6_in => ic_B1_data_6_in_wire,
B1_data_7_in => ic_B1_data_7_in_wire,
B1_data_8_in => ic_B1_data_8_in_wire,
B1_data_9_in => ic_B1_data_9_in_wire,
B1_data_10_in => ic_B1_data_10_in_wire,
B1_1_mux_ctrl_in => ic_B1_1_mux_ctrl_in_wire,
B1_1_data_0_in => ic_B1_1_data_0_in_wire,
B1_1_data_1_in => ic_B1_1_data_1_in_wire,
B1_1_data_2_in => ic_B1_1_data_2_in_wire,
B1_1_data_3_in => ic_B1_1_data_3_in_wire,
B1_1_data_4_in => ic_B1_1_data_4_in_wire,
B1_1_data_5_in => ic_B1_1_data_5_in_wire,
B1_1_data_6_in => ic_B1_1_data_6_in_wire,
B1_1_data_7_in => ic_B1_1_data_7_in_wire,
B1_1_data_8_in => ic_B1_1_data_8_in_wire,
B1_1_data_9_in => ic_B1_1_data_9_in_wire,
B1_1_data_10_in => ic_B1_1_data_10_in_wire,
simm_B1 => ic_simm_B1_wire,
simm_cntrl_B1 => ic_simm_cntrl_B1_wire,
simm_B1_1 => ic_simm_B1_1_wire,
simm_cntrl_B1_1 => ic_simm_cntrl_B1_1_wire);
end structural;
| mit | 413a7e85eca984dd907db11fb6b79f82 | 0.660511 | 2.585526 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/timer.vhd | 1 | 9,953 | --
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end entity timer;
architecture behave of timer is
component prescaler is
port (
clk: in std_logic;
rst: in std_logic;
prescale: in std_logic_vector(2 downto 0);
event: out std_logic
);
end component prescaler;
type singlepwmregs is record
cmplow: unsigned(WIDTH-1 downto 0);
cmphigh: unsigned(WIDTH-1 downto 0);
en: std_logic;
end record;
type pwmregs is array(PWMCOUNT-1 downto 0) of singlepwmregs;
type timerregs is record
cnt: unsigned(WIDTH-1 downto 0); -- current timer counter value
cmp: unsigned(WIDTH-1 downto 0); -- top timer compare value
ccm: std_logic; -- clear on compare match
en: std_logic; -- enable
dir: std_logic; -- direction
ien: std_logic; -- interrupt enable
intr: std_logic; -- interrupt
pres: std_logic_vector(2 downto 0); -- Prescaler
updp: std_logic_vector(1 downto 0);
presrst: std_logic;
pwmr: pwmregs;
pwmrb:pwmregs;
end record;
constant UPDATE_NOW: std_logic_vector(1 downto 0) := "00";
constant UPDATE_ZERO_SYNC: std_logic_vector(1 downto 0) := "01";
constant UPDATE_LATER: std_logic_vector(1 downto 0) := "10";
signal tmr0_prescale_rst: std_logic;
--signal tmr0_prescale: std_logic_vector(2 downto 0);
signal tmr0_prescale_event: std_logic;
signal TSC_q: unsigned(wordSize-1 downto 0);
signal tmrr: timerregs;
function eq(a:std_logic_vector; b:std_logic_vector) return std_logic is
begin
if a=b then
return '1';
else
return '0';
end if;
end function;
signal do_interrupt: std_logic;
begin
wb_inta_o <= tmrr.intr;
-- comp <= tmrr.cout;
wb_ack_o <= wb_cyc_i and wb_stb_i;
pr: if PRESCALER_ENABLED generate
tmr0prescale_inst: prescaler
port map (
clk => wb_clk_i,
rst => tmrr.presrst,
prescale=> tmrr.pres,
event => tmr0_prescale_event
);
end generate;
npr: if not PRESCALER_ENABLED generate
tmr0_prescale_event<='1';
end generate;
tsc_process: if TSCENABLED generate
TSCgen: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
TSC_q <= (others => '0');
else
TSC_q <= TSC_q + 1;
end if;
end if;
end process;
end generate;
-- Read
process(wb_adr_i, tmrr,TSC_q)
begin
case wb_adr_i(1 downto 0) is
when "00" =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= tmrr.en;
wb_dat_o(1) <= tmrr.ccm;
wb_dat_o(2) <= tmrr.dir;
wb_dat_o(3) <= tmrr.ien;
wb_dat_o(6 downto 4) <= tmrr.pres;
wb_dat_o(7) <= tmrr.intr;
wb_dat_o(10 downto 9) <= tmrr.updp;
when "01" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cnt);
when "10" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cmp);
when others =>
if TSCENABLED then
wb_dat_o <= (others => '0');
wb_dat_o <= std_logic_vector(TSC_q);
else
wb_dat_o <= (others => DontCareValue );
end if;
end case;
end process;
process(wb_clk_i, tmrr, wb_rst_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,wb_dat_i,tmrr,do_interrupt,tmr0_prescale_event)
variable w: timerregs;
variable write_ctrl: std_logic;
variable write_cmp: std_logic;
variable write_cnt: std_logic;
variable write_pwm: std_logic;
variable ovf: std_logic;
variable pwmindex: integer;
begin
w := tmrr;
-- These are just helpers
write_ctrl := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000000");
write_cnt := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000001");
write_cmp := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000010");
write_pwm := wb_cyc_i and wb_stb_i and wb_we_i and wb_adr_i(5);
ovf:='0';
if tmrr.cnt = tmrr.cmp then
ovf:='1';
end if;
do_interrupt <= '0';
if wb_rst_i='1' then
w.en := '0';
w.ccm := '0';
w.dir := '0';
w.ien := '0';
w.pres := (others => '0');
w.presrst := '1';
w.updp := UPDATE_ZERO_SYNC;
for i in 0 to PWMCOUNT-1 loop
w.pwmrb(i).en :='0';
w.pwmr(i).en :='0';
end loop;
else
if do_interrupt='1' then
w.intr := '1';
end if;
w.presrst := '0';
-- Wishbone access
if write_ctrl='1' then
w.en := wb_dat_i(0);
w.ccm := wb_dat_i(1);
w.dir := wb_dat_i(2);
w.ien := wb_dat_i(3);
w.pres:= wb_dat_i(6 downto 4);
w.updp := wb_dat_i(10 downto 9);
if wb_dat_i(7)='0' then
w.intr:='0';
end if;
end if;
if write_cmp='1' then
w.cmp := unsigned(wb_dat_i(WIDTH-1 downto 0));
end if;
if write_cnt='1' then
w.cnt := unsigned(wb_dat_i(WIDTH-1 downto 0));
else
if tmrr.en='1' and tmr0_prescale_event='1' then
-- If output matches, set interrupt
if ovf='1' then
if tmrr.ien='1' then
do_interrupt<='1';
end if;
end if;
-- CCM
if tmrr.ccm='1' and ovf='1' then
w.cnt := (others => '0');
else
if tmrr.dir='1' then
w.cnt := tmrr.cnt + 1;
else
w.cnt := tmrr.cnt - 1;
end if;
end if;
end if;
end if;
end if;
if write_pwm='1' then
for i in 0 to PWMCOUNT-1 loop
if wb_adr_i(4 downto 2) = std_logic_vector(to_unsigned(i,3)) then
if BUFFERS then
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmrb(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmrb(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmrb(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
else
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmr(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmr(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmr(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
end if;
end if;
end loop;
end if;
if BUFFERS then
for i in 0 to PWMCOUNT-1 loop
case tmrr.updp is
when UPDATE_NOW =>
w.pwmr(i) := tmrr.pwmrb(i);
when UPDATE_ZERO_SYNC =>
if ovf='1' then
w.pwmr(i) := tmrr.pwmrb(i);
end if;
when UPDATE_LATER =>
--if wb_adr_i(3 downto 2) = std_logic_vector(to_unsigned(i,2)) then
-- if wb_adr_i(1 downto 0)="11" then
-- w.pwmr(i) := tmrr.pwmrb(i);
-- end if;
-- end if;
when others =>
--w.pwmr(i) := tmrr.pwmrb(i);
end case;
end loop;
end if;
if rising_edge(wb_clk_i) then
tmrr <= w;
for i in 0 to PWMCOUNT-1 loop
if tmrr.pwmr(i).en='1' then
if tmrr.cnt >= tmrr.pwmr(i).cmplow and tmrr.cnt<tmrr.pwmr(i).cmphigh then
pwm_out(i) <= '1';
else
pwm_out(i) <= '0';
end if;
else
pwm_out(i)<='0';
end if;
end loop;
end if;
end process;
end behave;
| mit | 643bf2ef778f054c0417f3a4e98700b8 | 0.563147 | 3.16672 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/simulation/bmg_stim_gen.vhd | 1 | 12,292 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((15 <= 15),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((15 <= 15),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(14 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(14 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 20000 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 20000,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
| mit | 30541205d64e1b49c34ecb072c8a0205 | 0.543036 | 3.548499 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_adc_test.vhd | 1 | 3,362 | --
-- ADC for ZPUINO
--
--
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
entity zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
AD_CS_o : out std_logic;
AD_SCLK_o: out std_logic;
AD_DIN_o : out std_logic;
AD_OUT_i : in std_logic
);
end entity zpuino_adc;
architecture behave of zpuino_adc is
signal adc_data_0: std_logic_vector(15 downto 0);
signal adc_data_1: std_logic_vector(15 downto 0);
signal adc_data_2: std_logic_vector(15 downto 0);
signal adc_data_3: std_logic_vector(15 downto 0);
signal adc_data_4: std_logic_vector(15 downto 0);
signal adc_data_5: std_logic_vector(15 downto 0);
signal adc_data_6: std_logic_vector(15 downto 0);
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
AD_CS_o <= '1';
AD_SCLK_o <= '1';
AD_DIN_o <= '1';
-- Read
--
process(wb_adr_i)
begin
case wb_adr_i(5 downto 2) is
when X"0" =>
wb_dat_o <= (others=>'0');
wb_dat_o( 7 downto 0 ) <= X"01";
when X"1" =>
wb_dat_o <= (others=>'0');
wb_dat_o( 7 downto 0 ) <= X"03";
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
-- Write
--
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(5 downto 2) is
when X"2" =>
when X"3" =>
--<= wb_dat_i;
when others =>
end case;
end if;
end if;
end process;
end behave;
| mit | acdeaac7347435fd86d0a44e9a11d4aa | 0.658834 | 2.977857 | false | false | false | false |
purisc-group/purisc | Global_memory/MAGIC_global/SELECTOR_global.vhd | 2 | 4,533 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SELECTOR_global is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end;
architecture input_select of SELECTOR_global is
signal opcode_sig : std_logic_vector (5 downto 0) := "000000";
signal serviced_vector : std_logic_vector (5 downto 0) := "000000";
signal equality_vector : std_logic_vector (5 downto 0) := "111111";
signal equality_extend : std_logic_vector (5 downto 0) := "111111";
signal equality_signal : std_logic := '1';
signal equality_buff : std_logic;
signal to_service_next : std_logic_vector (5 downto 0) := "000000";
signal hazard_to_mask : std_logic_vector (5 downto 0) := "111111";
signal hazard_mask : std_logic_vector (5 downto 0) := "111111";
signal SEL_A_0_sig : std_logic;
signal SEL_B_0_sig : std_logic;
signal SEL_C_0_sig : std_logic;
signal SEL_D_0_sig : std_logic;
signal SEL_E_0_sig : std_logic;
signal SEL_W_0_sig : std_logic;
signal SEL_A_1_sig : std_logic;
signal SEL_B_1_sig : std_logic;
signal SEL_C_1_sig : std_logic;
signal SEL_D_1_sig : std_logic;
signal SEL_E_1_sig : std_logic;
signal SEL_W_1_sig : std_logic;
begin
sel_A_0_sig <= opcode_sig(5) and RESET_n;
sel_B_0_sig <= opcode_sig(4) and (not opcode_sig(5)) and RESET_n;
sel_C_0_sig <= opcode_sig(3) and (not (opcode_sig(5) or opcode_sig(4))) and RESET_n;
sel_D_0_sig <= opcode_sig(2) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3))) and RESET_n;
sel_E_0_sig <= opcode_sig(1) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3) or opcode_sig(2))) and RESET_n;
sel_W_0_sig <= opcode_sig(0) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3) or opcode_sig(2) or opcode_sig(1))) and RESET_n;
sel_W_1_sig <= opcode_sig(0) and RESET_n;
sel_E_1_sig <= opcode_sig(1) and (not opcode_sig(0)) and RESET_n;
sel_D_1_sig <= opcode_sig(2) and (not (opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_C_1_sig <= opcode_sig(3) and (not (opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_B_1_sig <= opcode_sig(4) and (not (opcode_sig(3) or opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_A_1_sig <= opcode_sig(5) and (not (opcode_sig(4) or opcode_sig(3) or opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
-- opcode_sig <= OPCODE and hazard_mask;
-- opcode_sig <= OPCODE;
opcode_sig <= (OPCODE(5) and hazard_mask(5)) & (OPCODE(4) and hazard_mask(4)) & (OPCODE(3) and hazard_mask(3)) &
(OPCODE(2) and hazard_mask(2)) & (OPCODE(1) and hazard_mask(1)) & (OPCODE(0) and hazard_mask(0));
serviced_vector <= (sel_A_0_sig or sel_A_1_sig ) &
(sel_B_0_sig or sel_B_1_sig ) &
(sel_C_0_sig or sel_C_1_sig ) &
(sel_D_0_sig or sel_D_1_sig ) &
(sel_E_0_sig or sel_E_1_sig ) &
(sel_W_0_sig or sel_W_1_sig );
to_service_next <= serviced_vector xor opcode_sig;
equality_vector <= opcode_sig xor (not serviced_vector);
hazard_to_mask <= to_service_next xor equality_extend;
hazard_latching : process (CLK, RESET_n) begin
if (RESET_n = '0') then
hazard_mask <= "111111";
elsif (rising_edge(CLK)) then
hazard_mask <= hazard_to_mask;
end if;
end process;
equality_extend <= equality_signal & equality_signal & equality_signal & equality_signal & equality_signal & equality_signal;
equality_signal <= equality_vector(5) and equality_vector(4) and equality_vector(3) and equality_vector(2) and equality_vector(1) and equality_vector(0);
-- derp : process (CLK) begin
-- if (falling_edge(CLK)) then
-- equality_buff <= equality_signal;
-- end if;
-- end process;
EQUALITY <= equality_signal; --used to be equality_signal
SEL_A_0 <= SEL_A_0_sig;
SEL_B_0 <= SEL_B_0_sig;
SEL_C_0 <= SEL_C_0_sig;
SEL_D_0 <= SEL_D_0_sig;
SEL_E_0 <= SEL_E_0_sig;
SEL_W_0 <= SEL_W_0_sig;
SEL_A_1 <= SEL_A_1_sig;
SEL_B_1 <= SEL_B_1_sig;
SEL_C_1 <= SEL_C_1_sig;
SEL_D_1 <= SEL_D_1_sig;
SEL_E_1 <= SEL_E_1_sig;
SEL_W_1 <= SEL_W_1_sig;
end; | gpl-2.0 | ee790a05531dd556ef0106846b03ab7d | 0.62034 | 2.490659 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to400_pll.vhd | 13 | 5,860 | -- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
| mit | 3e8aa9e11a106bd5ced6b3ee7ce1fdf8 | 0.606826 | 4.234104 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/sdram_wrap.vhd | 13 | 4,114 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
| mit | 490a569595b21683e8b3d663cd1c1c0c | 0.591881 | 2.872905 | false | false | false | false |
purisc-group/purisc | Compute_Group/MAGIC_clocked/ROUTE.vhd | 2 | 13,498 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
OUTPUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture control of ROUTE is
--******************************************PROTOTYPE FOR REFERENCE************************************************
-- RAM 0 -----> ram_0_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 1 -----> ram_1_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 2 -----> ram_2_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 3 -----> ram_3_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 4 -----> ram_4_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 5 -----> ram_5_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 6 -----> ram_6_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 7 -----> ram_7_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
component ROUTE_SIGNAL
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal select_a : std_logic_vector (15 downto 0);
signal select_b : std_logic_vector (15 downto 0);
signal select_c : std_logic_vector (15 downto 0);
signal select_0 : std_logic_vector (15 downto 0);
signal select_1 : std_logic_vector (15 downto 0);
signal select_a_1hot : std_logic_vector (15 downto 0);
signal select_b_1hot : std_logic_vector (15 downto 0);
signal select_c_1hot : std_logic_vector (15 downto 0);
signal select_0_1hot : std_logic_vector (15 downto 0);
signal select_1_1hot : std_logic_vector (15 downto 0);
begin
select_a <= ram_0_sel_vector(9 downto 8) & ram_1_sel_vector(9 downto 8) &
ram_2_sel_vector(9 downto 8) & ram_3_sel_vector(9 downto 8) &
ram_4_sel_vector(9 downto 8) & ram_5_sel_vector(9 downto 8) &
ram_6_sel_vector(9 downto 8) & ram_7_sel_vector(9 downto 8);
select_b <= ram_0_sel_vector(7 downto 6) & ram_1_sel_vector(7 downto 6) &
ram_2_sel_vector(7 downto 6) & ram_3_sel_vector(7 downto 6) &
ram_4_sel_vector(7 downto 6) & ram_5_sel_vector(7 downto 6) &
ram_6_sel_vector(7 downto 6) & ram_7_sel_vector(7 downto 6);
select_c <= ram_0_sel_vector(5 downto 4) & ram_1_sel_vector(5 downto 4) &
ram_2_sel_vector(5 downto 4) & ram_3_sel_vector(5 downto 4) &
ram_4_sel_vector(5 downto 4) & ram_5_sel_vector(5 downto 4) &
ram_6_sel_vector(5 downto 4) & ram_7_sel_vector(5 downto 4);
select_0 <= ram_0_sel_vector(3 downto 2) & ram_1_sel_vector(3 downto 2) &
ram_2_sel_vector(3 downto 2) & ram_3_sel_vector(3 downto 2) &
ram_4_sel_vector(3 downto 2) & ram_5_sel_vector(3 downto 2) &
ram_6_sel_vector(3 downto 2) & ram_7_sel_vector(3 downto 2);
select_1 <= ram_0_sel_vector(1 downto 0) & ram_1_sel_vector(1 downto 0) &
ram_2_sel_vector(1 downto 0) & ram_3_sel_vector(1 downto 0) &
ram_4_sel_vector(1 downto 0) & ram_5_sel_vector(1 downto 0) &
ram_6_sel_vector(1 downto 0) & ram_7_sel_vector(1 downto 0);
select_a_1hot <= select_a(15) & (not(select_a(15) and select_a(14)) and select_a(14)) &
select_a(13) & (not(select_a(13) and select_a(12)) and select_a(12)) &
select_a(11) & (not(select_a(11) and select_a(10)) and select_a(10)) &
select_a(9) & (not(select_a(9) and select_a(8)) and select_a(8)) &
select_a(7) & (not(select_a(7) and select_a(6)) and select_a(6)) &
select_a(5) & (not(select_a(5) and select_a(4)) and select_a(4)) &
select_a(3) & (not(select_a(3) and select_a(2)) and select_a(2)) &
select_a(1) & (not(select_a(1) and select_a(0)) and select_a(0));
select_b_1hot <= select_b(15) & (not(select_b(15) and select_b(14)) and select_b(14)) &
select_b(13) & (not(select_b(13) and select_b(12)) and select_b(12)) &
select_b(11) & (not(select_b(11) and select_b(10)) and select_b(10)) &
select_b(9) & (not(select_b(9) and select_b(8)) and select_b(8)) &
select_b(7) & (not(select_b(7) and select_b(6)) and select_b(6)) &
select_b(5) & (not(select_b(5) and select_b(4)) and select_b(4)) &
select_b(3) & (not(select_b(3) and select_b(2)) and select_b(2)) &
select_b(1) & (not(select_b(1) and select_b(0)) and select_b(0));
select_c_1hot <= select_c(15) & (not(select_c(15) and select_c(14)) and select_c(14)) &
select_c(13) & (not(select_c(13) and select_c(12)) and select_c(12)) &
select_c(11) & (not(select_c(11) and select_c(10)) and select_c(10)) &
select_c(9) & (not(select_c(9) and select_c(8)) and select_c(8)) &
select_c(7) & (not(select_c(7) and select_c(6)) and select_c(6)) &
select_c(5) & (not(select_c(5) and select_c(4)) and select_c(4)) &
select_c(3) & (not(select_c(3) and select_c(2)) and select_c(2)) &
select_c(1) & (not(select_c(1) and select_c(0)) and select_c(0));
select_0_1hot <= select_0(15) & (not(select_0(15) and select_0(14)) and select_0(14)) &
select_0(13) & (not(select_0(13) and select_0(12)) and select_0(12)) &
select_0(11) & (not(select_0(11) and select_0(10)) and select_0(10)) &
select_0(9) & (not(select_0(9) and select_0(8)) and select_0(8)) &
select_0(7) & (not(select_0(7) and select_0(6)) and select_0(6)) &
select_0(5) & (not(select_0(5) and select_0(4)) and select_0(4)) &
select_0(3) & (not(select_0(3) and select_0(2)) and select_0(2)) &
select_0(1) & (not(select_0(1) and select_0(0)) and select_0(0));
select_1_1hot <= select_1(15) & (not(select_1(15) and select_1(14)) and select_1(14)) &
select_1(13) & (not(select_1(13) and select_1(12)) and select_1(12)) &
select_1(11) & (not(select_1(11) and select_1(10)) and select_1(10)) &
select_1(9) & (not(select_1(9) and select_1(8)) and select_1(8)) &
select_1(7) & (not(select_1(7) and select_1(6)) and select_1(6)) &
select_1(5) & (not(select_1(5) and select_1(4)) and select_1(4)) &
select_1(3) & (not(select_1(3) and select_1(2)) and select_1(2)) &
select_1(1) & (not(select_1(1) and select_1(0)) and select_1(0));
route_a : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_a_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_A
);
route_b : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_b_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_B
);
route_c : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_c_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_C
);
route_0 : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_0_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_0
);
route_1 : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_1_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_1
);
end; | gpl-2.0 | 16fa924d0df33f69a8dcaef961a4b0c5 | 0.523485 | 2.557408 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/zpuino_uart_mv_filter.vhd | 13 | 2,522 | --
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity zpuino_uart_mv_filter;
architecture behave of zpuino_uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 00ead75edf5c02692fa5c7198020916d | 0.660983 | 3.649783 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/vhdl/ffaccel_globals_pkg.vhdl | 2 | 627 | library work;
use work.ffaccel_imem_mau.all;
package ffaccel_globals is
-- address width of the instruction memory
constant IMEMADDRWIDTH : positive := 12;
-- width of the instruction memory in MAUs
constant IMEMWIDTHINMAUS : positive := 1;
-- width of instruction fetch block.
constant IMEMDATAWIDTH : positive := IMEMWIDTHINMAUS*IMEMMAUWIDTH;
-- clock period
constant PERIOD : time := 10 ns;
-- number of busses.
constant BUSTRACE_WIDTH : positive := 64;
-- number of cores
constant CORECOUNT : positive := 1;
-- instruction width
constant INSTRUCTIONWIDTH : positive := 43;
end ffaccel_globals;
| mit | 3ac2b1866a04c63e641d814251c6556a | 0.727273 | 4.071429 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.e-writeback.vhd | 1 | 1,804 | library ieee;
use ieee.std_logic_1164.all;
entity writeback is
port(
-- inputs
from_mem_data : in std_logic_vector(31 downto 0);
from_alu_data : in std_logic_vector(31 downto 0); -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in : in std_logic_vector(4 downto 0); -- address of register to write
regwrite_in : in std_logic; -- control signal (1 -> write in reg file)
link : in std_logic; -- control signal (1 -> link the instruction, save IP in R31)
memtoreg : in std_logic;
-- outputs
regwrite_out : out std_logic; -- control signal (send regwrite signal back to other stages)
regfile_data : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end writeback;
architecture rtl of writeback is
constant reg31 : std_logic_vector(4 downto 0) := "11111";
-- a goes through when s='1', b with s='0'
component mux21 is
generic(
NBIT : integer := 32
);
port (
A : in std_logic_vector(NBIT - 1 downto 0);
B : in std_logic_vector(NBIT - 1 downto 0);
S : in std_logic;
Y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
begin
regwrite_out <= regwrite_in;
-- component instantiations
-- NOTE:
-- if memtoreg == 1 then out <= from_mem_data
-- else out <= from_alu_data
memtoreg_mux21 : mux21 generic map (32) port map (from_mem_data, from_alu_data, memtoreg, regfile_data);
link_mux21 : mux21 generic map (5) port map (reg31, regfile_addr_in, link, regfile_addr_out);
end rtl;
| mit | cb8f727792fd6c7b485e18596931fc7e | 0.577051 | 3.651822 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to100_pll.vhd | 13 | 5,098 | -- file: clk_32to100_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to100_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to100_pll;
architecture xilinx of clk_32to100_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to100_pll,clk_wiz_v3_6,{component_name=clk_32to100_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
| mit | 461a52840ea6f27c258fec9834ee2385 | 0.668301 | 3.979703 | false | false | false | false |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/hps_design_inst.vhd | 1 | 3,438 | component hps_design is
port (
clk_clk : in std_logic := 'X'; -- clk
pll_0_sdram_clk : out std_logic; -- clk
ledr_export : out std_logic; -- export
hps_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_ddr_mem_ck : out std_logic; -- mem_ck
hps_ddr_mem_ck_n : out std_logic; -- mem_ck_n
hps_ddr_mem_cke : out std_logic; -- mem_cke
hps_ddr_mem_cs_n : out std_logic; -- mem_cs_n
hps_ddr_mem_ras_n : out std_logic; -- mem_ras_n
hps_ddr_mem_cas_n : out std_logic; -- mem_cas_n
hps_ddr_mem_we_n : out std_logic; -- mem_we_n
hps_ddr_mem_reset_n : out std_logic; -- mem_reset_n
hps_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_ddr_mem_odt : out std_logic; -- mem_odt
hps_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_ddr_oct_rzqin : in std_logic := 'X' -- oct_rzqin
);
end component hps_design;
u0 : component hps_design
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pll_0_sdram_clk => CONNECTED_TO_pll_0_sdram_clk, -- pll_0_sdram.clk
ledr_export => CONNECTED_TO_ledr_export, -- ledr.export
hps_ddr_mem_a => CONNECTED_TO_hps_ddr_mem_a, -- hps_ddr.mem_a
hps_ddr_mem_ba => CONNECTED_TO_hps_ddr_mem_ba, -- .mem_ba
hps_ddr_mem_ck => CONNECTED_TO_hps_ddr_mem_ck, -- .mem_ck
hps_ddr_mem_ck_n => CONNECTED_TO_hps_ddr_mem_ck_n, -- .mem_ck_n
hps_ddr_mem_cke => CONNECTED_TO_hps_ddr_mem_cke, -- .mem_cke
hps_ddr_mem_cs_n => CONNECTED_TO_hps_ddr_mem_cs_n, -- .mem_cs_n
hps_ddr_mem_ras_n => CONNECTED_TO_hps_ddr_mem_ras_n, -- .mem_ras_n
hps_ddr_mem_cas_n => CONNECTED_TO_hps_ddr_mem_cas_n, -- .mem_cas_n
hps_ddr_mem_we_n => CONNECTED_TO_hps_ddr_mem_we_n, -- .mem_we_n
hps_ddr_mem_reset_n => CONNECTED_TO_hps_ddr_mem_reset_n, -- .mem_reset_n
hps_ddr_mem_dq => CONNECTED_TO_hps_ddr_mem_dq, -- .mem_dq
hps_ddr_mem_dqs => CONNECTED_TO_hps_ddr_mem_dqs, -- .mem_dqs
hps_ddr_mem_dqs_n => CONNECTED_TO_hps_ddr_mem_dqs_n, -- .mem_dqs_n
hps_ddr_mem_odt => CONNECTED_TO_hps_ddr_mem_odt, -- .mem_odt
hps_ddr_mem_dm => CONNECTED_TO_hps_ddr_mem_dm, -- .mem_dm
hps_ddr_oct_rzqin => CONNECTED_TO_hps_ddr_oct_rzqin -- .oct_rzqin
);
| gpl-2.0 | 48d8e411ab493a068d585e0685644f7b | 0.4395 | 3.050577 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.d-memory.vhd | 1 | 3,263 | --------------------------------------------------------------------------------
-- Memory stage
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity memory is
port(
-- inputs
rst : in std_logic;
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0) -- goes to EXE stage and is used if forwarding detected by forwarding unit
);
end memory;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture struct of memory is
-- component declarations
component dram_block is
port(
-- inputs
address : in std_logic_vector(31 downto 0);
data_write : in std_logic_vector(31 downto 0);
mem_op : in std_logic_vector(5 downto 0);
rst : in std_logic;
-- outputs
unaligned : out std_logic;
data_read : out std_logic_vector(31 downto 0)
);
end component;
-- internal signals
signal PCsrc_i : std_logic;
signal jump_i : std_logic;
begin
-- concurrent signal assignments
jump_i <= controls_in(1); -- MV
PCsrc_i <= controls_in(0) and takeBranch; -- MV Branch and takeBranch
PCsrc <= PCsrc_i;
jump <= jump_i;
flush <= PCsrc_i or jump_i;
regwrite_MEM <= controls_in(10); -- to forwarding unit
RFaddr_MEM <= RFaddr_in; -- to forwarding unit
forw_addr_MEM <= addrMem; -- to forwarding unit
controls_out <= controls_in(10) & controls_in (9) & controls_in(2); -- pass regwrite, link, memtoreg to WB stage
dataOut_exe <= addrMem;
RFaddr_out <= RFaddr_in;
PC1_out <= PC1_in;
PC2_out <= PC2_in;
-- component instantiations
dram : dram_block port map (addrMem, writeData, controls_in(8 downto 3),rst, unaligned, dataOut_mem);
end struct;
| mit | 8c46d155262075738ebf8e1d3920cbe6 | 0.504444 | 4.053416 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/uart_brgen.vhd | 15 | 2,186 | --
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end entity uart_brgen;
architecture behave of uart_brgen is
signal cnt: integer range 0 to 65535;
begin
process (clk)
begin
if rising_edge(clk) then
clkout <= '0';
if rst='1' then
cnt <= conv_integer(count);
elsif en='1' then
if cnt=0 then
clkout <= '1';
cnt <= conv_integer(count);
else
cnt <= cnt - 1;
end if;
end if;
end if;
end process;
end behave;
| mit | 112bb8a54ff47a9116bf349141ed8d45 | 0.675206 | 3.862191 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/zpuinopkg.vhd | 26 | 21,269 | --
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg; | mit | 291b77a9d313844c44a0c50329db587f | 0.628614 | 2.829453 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_250k/stack.vhd | 13 | 1,535 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_b_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(3 downto 0) := (others => '0');
begin
stack: RAMB16_S36_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read,
DOB => stack_b_read,
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr,
ADDRB => stack_b_addr,
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write,
DIB => stack_b_write,
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable,
WEB => stack_b_writeenable
);
end behave;
| mit | 20a0eb940fbbdf190b9571a7fc77c379 | 0.628664 | 2.912713 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/dualport_ram_hyperion.vhd | 13 | 5,145 | --
-- ZPUINO memory
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library board;
use board.zpupkg_hyperion.all;
--library UNISIM;
--use UNISIM.VCOMPONENTS.all;
entity dualport_ram_hyperion is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end entity dualport_ram_hyperion;
architecture behave of dualport_ram_hyperion is
component prom_generic_dualport_hyperion is
port (ADDRA: in std_logic_vector(maxbit downto 2);
CLK : in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
WEA: in std_logic; -- to avoid a bug in Xilinx ISE
DOA: out STD_LOGIC_VECTOR (31 downto 0);
ADDRB: in std_logic_vector(maxbit downto 2);
DIA: in STD_LOGIC_VECTOR (31 downto 0); -- to avoid a bug in Xilinx ISE
WEB: in std_logic;
MASKB: in std_logic_vector(3 downto 0);
ENB: in std_logic;
DOB: out STD_LOGIC_VECTOR (31 downto 0);
DIB: in STD_LOGIC_VECTOR (31 downto 0));
end component;
signal memAWriteEnable_i: std_logic;
signal memBWriteEnable_i: std_logic;
constant nullAddr: std_logic_vector(maxbit downto 12) := (others => '0');
constant protectionEnabled: std_logic := '0';
begin
-- Boot loader address: 000XXXXXXXXXX
-- Disallow any writes to bootloader protected code (first 4096 bytes, 0x1000 hex (0x000 to 0xFFF)
memAWriteEnable_i <= memAWriteEnable when ( memAAddr(maxbit downto 12)/=nullAddr or protectionEnabled='0') else '0';
memBWriteEnable_i <= memBWriteEnable when ( memBAddr(maxbit downto 12)/=nullAddr or protectionEnabled='0') else '0';
process(memAWriteEnable,memAAddr(maxbit downto 12),memBWriteEnable,memBAddr(maxbit downto 12))
begin
memErr <= '0';
if memAWriteEnable='1' and memAAddr(maxbit downto 12)="000" and protectionEnabled='1' then
memErr<='1';
end if;
if memBWriteEnable='1' and memBAddr(maxbit downto 12)="000" and protectionEnabled='1' then
memErr<='1';
end if;
end process;
-- Sanity checks for simulation
process(clk)
begin
if rising_edge(clk) then
if memAWriteEnable='1' and memAAddr(maxbit downto 12)="000" and protectionEnabled='1' then
report "Write to BOOTLOADER port A not allowed!!! " severity note;
end if;
end if;
end process;
-- Sanity checks for simulation
process(clk)
begin
if rising_edge(clk) then
if memBWriteEnable='1' and memBAddr(maxbit downto 12)="000" and protectionEnabled='1' then
report "Write to BOOTLOADER port B not allowed!!!" severity note;
end if;
end if;
end process;
ram: prom_generic_dualport_hyperion
port map (
DOA => memARead,
ADDRA => memAAddr,
CLK => clk,
DIA => memAWrite,
ENA => memAEnable,
MASKA => "1111",
WEA => memAWriteEnable,
DOB => memBRead,
ADDRB => memBAddr,
DIB => memBWrite,
MASKB => "1111",
ENB => memBEnable,
WEB => memBWriteEnable
);
end behave;
| mit | 31e454fe41b6ab04be91074eeeeb73b3 | 0.67036 | 3.651526 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_uart_rx.vhd | 1 | 4,933 | --
-- UART for ZPUINO - Receiver unit
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end entity zpuino_uart_rx;
architecture behave of zpuino_uart_rx is
component zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end component zpuino_uart_mv_filter;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
signal rxf: std_logic;
signal baudtick: std_logic;
signal rxd: std_logic_vector(7 downto 0);
signal datacount: unsigned(2 downto 0);
signal baudreset: std_logic;
signal filterreset: std_logic;
signal datao: std_logic_vector(7 downto 0);
signal dataready: std_logic;
signal start: std_logic;
signal debug_synctick_q: std_logic;
signal debug_baudreset_q: std_logic;
-- State
type uartrxstate is (
rx_idle,
rx_start,
rx_data,
rx_end
);
signal state: uartrxstate;
begin
data <= datao;
data_av <= dataready;
rxmvfilter: zpuino_uart_mv_filter
generic map (
bits => 4,
threshold => 10
)
port map (
clk => clk,
rst => rst,
sin => rx,
sout => rxf,
clear => filterreset,
enable => rxclk
);
filterreset <= baudreset or baudtick;
--istart <= start;
baudgen: uart_brgen
port map (
clk => clk,
rst => baudreset,
en => rxclk,
count => x"000f",
clkout => baudtick
);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
state <= rx_idle;
dataready <= '0';
baudreset <= '0';
start<='0';
else
baudreset <= '0';
start<='0';
if read='1' then
dataready <= '0';
end if;
case state is
when rx_idle =>
if rx='0' then -- Start bit
state <= rx_start;
baudreset <= '1';
start <='1';
end if;
when rx_start =>
if baudtick='1' then
-- Check filtered output.
if rxf='0' then
datacount <= b"111";
state <= rx_data; -- Valid start bit.
else
state <= rx_idle;
end if;
end if;
when rx_data =>
if baudtick='1' then
rxd(7) <= rxf;
rxd(6 downto 0) <= rxd(7 downto 1);
datacount <= datacount - 1;
if datacount=0 then
state <= rx_end;
end if;
end if;
when rx_end =>
-- Check for framing errors ?
-- Do fast recovery here.
if rxf='1' then
dataready<='1';
datao <= rxd;
state <= rx_idle;
end if;
if baudtick='1' then
-- Framing error.
state <= rx_idle;
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
| mit | e7d79110b49690b767255b9d5a2d2d89 | 0.588486 | 3.654074 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_ov7670.vhd | 1 | 4,535 | --
-- ADC for ZPUINO
--
--
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
entity zpuino_ov7670 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
CLK50 : in STD_LOGIC;
OV7670_VSYNC : in STD_LOGIC;
OV7670_HREF : in STD_LOGIC;
OV7670_PCLK : in STD_LOGIC;
OV7670_XCLK : out STD_LOGIC;
OV7670_D : in STD_LOGIC_VECTOR(7 downto 0)
);
end entity zpuino_ov7670;
architecture behave of zpuino_ov7670 is
COMPONENT ov7670_capture
PORT(
pclk : IN std_logic;
vsync : IN std_logic;
href : IN std_logic;
d : IN std_logic_vector(7 downto 0);
addr : OUT std_logic_vector(18 downto 0);
dout : OUT std_logic_vector(15 downto 0);
we : OUT std_logic
);
END COMPONENT;
COMPONENT frame_buffer
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
signal capture_addr : std_logic_vector(18 downto 0);
signal capture_data : std_logic_vector(15 downto 0);
signal capture_we : std_logic_vector(0 downto 0);
signal frame_addr : std_logic_vector(18 downto 0);
signal frame_pixel : std_logic_vector(15 downto 0);
signal ov7670_sys_clk : std_logic := '0';
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
process(CLK50)
begin
if rising_edge(CLK50) then
ov7670_sys_clk <= not ov7670_sys_clk;
end if;
end process;
OV7670_XCLK <= ov7670_sys_clk;
-- Read
--
process(wb_adr_i)
begin
case wb_adr_i(5 downto 2) is
when X"0" =>
wb_dat_o <= (others=>'0');
wb_dat_o( 15 downto 0 ) <= frame_pixel;
when X"1" =>
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
-- Write
--
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(5 downto 2) is
when X"0" =>
frame_addr <= wb_dat_i( 18 downto 0 );
when X"1" =>
when others =>
end case;
end if;
end if;
end process;
capture: ov7670_capture
PORT MAP(
pclk => OV7670_PCLK,
vsync => OV7670_VSYNC,
href => OV7670_HREF,
d => OV7670_D,
addr => capture_addr,
dout => capture_data,
we => capture_we(0)
);
fb : frame_buffer
PORT MAP (
clka => OV7670_PCLK,
wea => capture_we,
addra => capture_addr( 14 downto 0 ),
dina => capture_data,
clkb => wb_clk_i,
addrb => frame_addr( 14 downto 0 ),
doutb => frame_pixel
);
end behave;
| mit | 25114e4327cbccabe740040c5947a0db | 0.654686 | 2.922036 | false | false | false | false |
purisc-group/purisc | Compute_Group/CORE/purisc_core.vhd | 1 | 4,532 | library ieee;
use ieee.std_logic_1164.all;
entity purisc_core is
port(
clk, reset_n : in std_logic;
r_addr_0, r_addr_1, r_addr_inst : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
flags : in std_logic_vector(7 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end entity;
architecture arch of purisc_core is
--ri output signals
signal ri_a : std_logic_vector(31 downto 0);
signal ri_next_pc : std_logic_vector(31 downto 0);
--rd output signals
signal rd_a : std_logic_vector(31 downto 0);
signal rd_b : std_logic_vector(31 downto 0);
signal rd_c : std_logic_vector(31 downto 0);
signal rd_next_pc : std_logic_vector(31 downto 0);
signal rd_ubranch : std_logic;
signal rd_noop : std_logic;
--ex output signals
signal ex_b : std_logic_vector(31 downto 0);
signal ex_c : std_logic_vector(31 downto 0);
signal ex_db : std_logic_vector(31 downto 0);
signal ex_cbranch : std_logic;
signal ex_noop : std_logic;
--ex input signals
signal ex_da_in, ex_db_in : std_logic_vector(31 downto 0);
--wd output signals
signal wd_data, wd_addr : std_logic_vector(31 downto 0);
--ri stage
component read_instruction_stage
port(
--inputs
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
cbranch : in std_logic;
cbranch_address : in std_logic_vector(31 downto 0);
ubranch : in std_logic;
ubranch_address : in std_logic_vector(31 downto 0);
--outputs
next_pc : out std_logic_vector(31 downto 0);
--memory
r_addr_inst : out std_logic_vector(31 downto 0)
);
end component;
--rd stage
component read_data_stage
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
noop_in : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 0);
a_out : out std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
ubranch_out : out std_logic;
noop_out : out std_logic;
r_addr_0 : out std_logic_vector(31 downto 0);
r_addr_1 : out std_logic_vector(31 downto 0);
pc_out : out std_logic_vector(31 downto 0)
);
end component;
--ex stage
component execute_stage
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
da_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
noop_in : in std_logic;
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
db_out : out std_logic_vector(31 downto 0);
cbranch : out std_logic;
noop_out : out std_logic
);
end component;
--wd stage
component write_data_stage
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
b_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
noop_in : in std_logic;
w_data : out std_logic_vector(31 downto 0);
w_addr : out std_logic_vector(31 downto 0);
we : out std_logic
);
end component;
begin
ri : read_instruction_stage port map (
--in
clk, reset_n, stall,
ex_cbranch,ex_c,
rd_ubranch,rd_c,
ri_next_pc,
ri_a
);
rd : read_data_stage port map (
--inputs
clk, reset_n, stall, rd_ubranch or ex_cbranch,
r_data_a, r_data_b, r_data_c,
ri_next_pc,
--outputs
rd_a, rd_b, rd_c,
rd_ubranch, rd_noop,
r_addr_0, r_addr_1,
rd_next_pc
);
ex : execute_stage port map (
--inputs
clk, reset_n, stall,
rd_a, rd_b, rd_c, ex_da_in, ex_db_in,
rd_next_pc,
rd_noop or ex_cbranch,
--outputs
ex_b, ex_c, ex_db, ex_cbranch, ex_noop
);
wd : write_data_stage port map (
--inputs
clk, reset_n, stall,
ex_b, ex_db, ex_noop,
--memory
wd_data, wd_addr, we
);
--data forwarding
ex_da_in <= ex_db when rd_a=ex_b else
wd_data when rd_a=wd_addr else
r_data_0;
ex_db_in <= ex_db when rd_b=ex_b else
wd_data when rd_b=wd_addr else
r_data_1;
w_data <= wd_data;
w_addr <= wd_addr;
r_addr_inst <= ri_a;
end architecture; | gpl-2.0 | 832b05fa88d6caba55436a2720a8494e | 0.620697 | 2.573538 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_mid/synth/bg_mid.vhd | 1 | 14,310 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bg_mid IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END bg_mid;
ARCHITECTURE bg_mid_arch OF bg_mid IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bg_mid_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bg_mid_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bg_mid_arch : ARCHITECTURE IS "bg_mid,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bg_mid_arch: ARCHITECTURE IS "bg_mid,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bg_mid.mif,C" &
"_INIT_FILE=bg_mid.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=18560,C_READ_DEPTH_A=18560,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=" &
"18560,C_READ_DEPTH_B=18560,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WAR" &
"N_BHV_RANGE=0,C_COUNT_36K_BRAM=5,C_COUNT_18K_BRAM=5,C_EST_POWER_SUMMARY=Estimated Power for IP _ 7.0707579999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bg_mid.mif",
C_INIT_FILE => "bg_mid.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 18560,
C_READ_DEPTH_A => 18560,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 18560,
C_READ_DEPTH_B => 18560,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "5",
C_COUNT_18K_BRAM => "5",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 7.0707579999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bg_mid_arch;
| gpl-3.0 | 9dbbffb98e2fcd50b2edbb3ac24ad6d7 | 0.624808 | 3.004409 | false | false | false | false |
huukit/logicsynth | excercises/syn/audio_pll.vhd | 1 | 15,491 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: audio_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY audio_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END audio_pll;
ARCHITECTURE SYN OF audio_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=audio_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "audio_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL audio_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL audio_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL audio_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL audio_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL audio_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL audio_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | dd677674e59b2f22bc37a73f4b979a3d | 0.699374 | 3.355936 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_intr.vhd | 13 | 10,649 | --
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | d9f08925b6828a8941a3fd698d9d268b | 0.583247 | 3.797789 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/papilio_stepper.vhd | 13 | 7,399 | --**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget Factory (www.gadgetfactory.net)
-- This work is licensed under the Creative Commons Attribution 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
-- use work.zpuino_config.all;
-- use work.zpu_config.all;
-- use work.zpupkg.all;
entity papilio_stepper is
Generic (
timebase_g : std_logic_vector(15 downto 0) := (others => '0');
period_g : std_logic_vector(15 downto 0) := (others => '0')
);
port (
wb_clk_i: in std_logic; -- Wishbone clock
wb_rst_i: in std_logic; -- Wishbone reset (synchronous)
wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: in std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: in std_logic; -- Wishbone write enable signal
wb_cyc_i: in std_logic; -- Wishbone cycle signal
wb_stb_i: in std_logic; -- Wishbone strobe signal
wb_ack_o: out std_logic; -- Wishbone acknowledge out signal
-- External connections
st_home : in std_logic;
st_dir : out std_logic;
st_ms2 : out std_logic;
st_ms1 : out std_logic;
st_rst : out std_logic;
st_step : out std_logic;
st_enable : out std_logic;
st_sleep : out std_logic;
-- IRQ
st_irq : out std_logic
);
end entity papilio_stepper;
architecture rtl of papilio_stepper is
signal prescale_o : std_logic;
signal halfperiod_o : std_logic;
signal step_o : std_logic;
signal irq_o : std_logic;
signal Control_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Timebase_reg : std_logic_vector(15 downto 0) := timebase_g;
signal Period_reg : std_logic_vector(15 downto 0) := period_g;
signal StepCnt_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Steps_reg : std_logic_vector(15 downto 0) := (others => '0');
signal PrescaleCnt : std_logic_vector(15 downto 0);
signal HalfPeriodCnt : std_logic_vector(15 downto 0);
signal ack_i: std_logic; -- Internal ACK signal (flip flop)
begin
-- This example uses fully synchronous outputs.
-- General Output signals
st_dir <= Control_reg(3);
st_ms2 <= Control_reg(1);
st_ms1 <= Control_reg(0);
st_rst <= Control_reg(4);
st_step <= step_o;
st_sleep <= Control_reg(7);
st_enable <= not Control_reg(8);
st_irq <= irq_o;
wb_ack_o <= ack_i; -- Tie ACK output to our flip flop
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
-- Always set output data on rising edge, even if reset is set.
Control_reg(14) <= st_home;
Control_reg(15) <= irq_o;
wb_dat_o <= (others => 'X'); -- Return undefined by omission
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(Control_reg'RANGE) <= Control_reg;
when "001" =>
wb_dat_o(Timebase_reg'RANGE) <= Timebase_reg;
when "010" =>
wb_dat_o(Period_reg'RANGE) <= Period_reg;
when "011" =>
wb_dat_o(StepCnt_reg'RANGE) <= StepCnt_reg;
when "100" =>
wb_dat_o(Steps_reg'RANGE) <= Steps_reg;
when others =>
end case;
ack_i <= '0'; -- Reset ACK value by default
if wb_rst_i='1' then
Control_reg <= "0000000010010000";
Timebase_reg <= timebase_g;
Period_reg <= period_g;
StepCnt_reg <= (others => '0');
else -- Not reset
-- See if we did not acknowledged a cycle, otherwise we need to ignore
-- the apparent request, because wishbone signals are still set
if ack_i='0' then
-- Check if someone is accessing
if wb_cyc_i='1' and wb_stb_i='1' then
ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above.
if wb_we_i='1' then
-- It's a write. See for which register based on address
case wb_adr_i(4 downto 2) is
when "000" =>
Control_reg(8 downto 0) <= wb_dat_i(8 downto 0); -- Set register
when "001" =>
Timebase_reg <= wb_dat_i(Timebase_reg'RANGE);
when "010" =>
Period_reg <= wb_dat_i(Period_reg'RANGE);
when "011" =>
StepCnt_reg <= wb_dat_i(StepCnt_reg'RANGE);
when others =>
null; -- Nothing to do for other addresses
end case;
end if; -- if wb_we_i='1'
end if; -- if wb_cyc_i='1' and wb_stb_i='1'
end if; -- if ack_i='0'
end if; -- if wb_rst_i='1'
end if; -- if rising_edge(wb_clk_i)
end process;
-- Prescaler
Prescaler:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if(wb_rst_i='1') then
PrescaleCnt <= (others => '0');
else
if (Control_reg(8)='1') then
if (PrescaleCnt=Timebase_reg) then
PrescaleCnt <= "0000000000000001";
else
PrescaleCnt <= PrescaleCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Half period counter
Halfperiod:process(wb_clk_i,prescale_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
HalfPeriodCnt <= (others => '0');
elsif (PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
if (HalfPeriodCnt=('0'&Period_reg(15 downto 1))) then
HalfPeriodCnt <= "0000000000000001";
else
HalfPeriodCnt <= HalfPeriodCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Step output
Step_out:process(wb_clk_i,halfperiod_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
step_o <= '1';
Steps_reg <= (others => '0');
elsif (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
step_o <= not step_o;
if (step_o = '1') then
Steps_reg <= Steps_reg+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Stepper interrupt
Int_out:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
irq_o <= '0';
if (wb_rst_i='1') then
irq_o <= '0';
else
--elsif (wb_clk_i='1' and wb_clk_i'event) then
case (Control_reg(6 downto 5)) is
when "01" =>
--if (halfperiod_o='1') then
if (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
irq_o <= '1';
end if;
when "10" =>
if (Control_reg(14)='1') then
irq_o <= '1';
end if;
when "11" =>
if (Steps_reg = StepCnt_reg) then
irq_o <= '1';
end if;
when others =>
--irq_o <= '0';
end case;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
end rtl;
| mit | de6aa90a99da37be40748dd83fd638f8 | 0.606028 | 2.941948 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to25_dcm.vhd | 13 | 6,302 | -- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to25_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to25_dcm;
architecture xilinx of clk_32to25_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to25_dcm,clk_wiz_v3_6,{component_name=clk_32to25_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit | 932b5f88d50a68183a1af15cbc6fa962 | 0.574738 | 4.240915 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/wb_master_np_to_slave_p.vhd | 1 | 2,101 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end entity wb_master_np_to_slave_p;
architecture behave of wb_master_np_to_slave_p is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= idle;
else
case state is
when idle =>
if m_wb_cyc_i='1' and m_wb_stb_i='1' and s_wb_stall_i='0' then
state <= wait_for_ack;
end if;
when wait_for_ack =>
if s_wb_ack_i='1' then
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
s_wb_stb_o <= m_wb_stb_i when state=idle else '0';
s_wb_dat_o <= m_wb_dat_i;
s_wb_adr_o <= m_wb_adr_i;
s_wb_sel_o <= m_wb_sel_i;
s_wb_cti_o <= m_wb_cti_i;
s_wb_we_o <= m_wb_we_i;
s_wb_cyc_o <= m_wb_cyc_i;
m_wb_dat_o <= s_wb_dat_i;
m_wb_ack_o <= s_wb_ack_i;
end behave;
| mit | f1aad06b770ab1e12be25278b20a8494 | 0.600666 | 2.495249 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Wing_Analog.vhd | 13 | 1,476 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
| mit | 58e411e94f51508ad20400b5ab14822a | 0.581301 | 3.1606 | false | false | false | false |
algebrato/eldig | Component_Contatore/Component_Contatore.vhd | 1 | 1,894 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Component_Contatore is
Port (
enable_in : in STD_LOGIC ;
SEG : out STD_LOGIC_VECTOR(0 to 6);
N_out : out STD_LOGIC_VECTOR(3 downto 0);
enable_out : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR(3 downto 0);
CLK100M : in STD_LOGIC;
CLK_1K_O : out STD_LOGIC
);
end Component_Contatore;
architecture Behavioral of Component_Contatore is
signal N: UNSIGNED(3 downto 0);
signal NN: UNSIGNED(15 downto 0);
signal clk_1k: STD_LOGIC;
begin
CLK_1K_O <= clk_1k; --collego le varie scatole con i segnali
SEG(0)<='0' when N=0 or N=2 or N=3 or N>4 else '1';
SEG(1)<='0' when N=0 or N=1 or N=2 or N=3 or N=4 or N=7 or N=8 or N=9 else '1';
SEG(2)<='0' when N=0 or N=1 or N=3 or N=4 or N=5 or N=6 or N=7 or N=8 or N=9 else '1';
SEG(3)<='0' when N=0 or N=2 or N=3 or N=5 or N=6 or N=8 or N>9 else '1';
SEG(4)<='0' when N=0 or N=2 or N=6 or N=8 or N>9 else '1';
SEG(5)<='0' when N=0 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
SEG(6)<='0' when N=2 or N=3 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
AN <= "0000";
mod_freq:process(CLK100M)
begin
if rising_edge(CLK100M) then
if NN=49999 then
NN<=(others => '0');
clk_1k <= not clk_1k;
else
NN<=NN+1;
end if;
end if;
end process mod_freq;
contatore_1_cifra:process(clk_1k)
begin
if rising_edge(contatore_1_cifra) then
if(reset = '1') then
C <=(others => '0');
else
if(preset ='1') then
C<= C_preset;
else
if(enable_in='1')then
if(up_down='1')then
if C = 9 then
C <=(others=>'0');
else
C<=C+1;
end if;
else
if C=0 then
C <= "1001";
else
C<=C-1;
end if;
end if;
end if;
end process contatore_1_cifra;
enable_out <= '1' when(((C=9) and up_down='1') or (C=0 and up_down='0')) and else '0';
end Behavioral;
| gpl-3.0 | a4b70e9ae4c7da55a8385b6a5ccd0578 | 0.595565 | 2.321078 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/spi_slave.vhd | 13 | 2,650 | ----------------------------------------------------------------------------------
-- spi_slave.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- spi_slave
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_slave is
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end spi_slave;
architecture behavioral of spi_slave is
component spi_receiver
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end component;
component spi_transmitter
port(
data : in std_logic_vector(31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic;
cs : in std_logic;
busy : out std_logic;
reset : in std_logic;
dataReady : out std_logic
);
end component;
begin
Inst_spi_receiver: spi_receiver
port map(
rx => mosi,
clock => clock,
sclk => sclk,
cmd => cmd,
execute => execute,
reset => reset,
cs => cs
);
Inst_spi_transmitter: spi_transmitter
port map(
data => data,
tx_bytes => tx_bytes,
send => send,
clock => clock,
sclk => sclk,
tx => miso,
cs => cs,
busy => busy,
reset => reset,
dataReady => dataReady
);
end behavioral;
| mit | 69198190b974eb229a90681a9e44b5aa | 0.60566 | 3.446034 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.b-ALU.vhd | 1 | 5,444 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
port(
-- inputs
alu_op : in std_logic_vector(4 downto 0); -- specifies alu operation to be performed (from CU in ID stage)
a : in std_logic_vector(31 downto 0); -- operand 1
b : in std_logic_vector(31 downto 0); -- operand 2
-- outputs
-- cout : out std_logic; -- cout of operation; to PSW
ovf : out std_logic; -- ovf of operation; to PSW
zero : out std_logic; -- zero when res is all 0s; to branch_circ
res : out std_logic_vector(31 downto 0) -- result of the arit-logic operation on a and b
);
end ALU;
architecture rtl of ALU is
signal res_i : std_logic_vector(31 downto 0);
-- ALU OPERATION
constant ALUOP_SLL : std_logic_vector(4 downto 0) := "00001";
constant ALUOP_SRL : std_logic_vector(4 downto 0) := "00010";
constant ALUOP_SRA : std_logic_vector(4 downto 0) := "00011";
constant ALUOP_ADD : std_logic_vector(4 downto 0) := "00100";
constant ALUOP_ADDU : std_logic_vector(4 downto 0) := "00101";
constant ALUOP_SUB : std_logic_vector(4 downto 0) := "00110";
constant ALUOP_SUBU : std_logic_vector(4 downto 0) := "00111";
constant ALUOP_AND : std_logic_vector(4 downto 0) := "01000";
constant ALUOP_OR : std_logic_vector(4 downto 0) := "01001";
constant ALUOP_XOR : std_logic_vector(4 downto 0) := "01010";
constant ALUOP_SEQ : std_logic_vector(4 downto 0) := "01011";
constant ALUOP_SNE : std_logic_vector(4 downto 0) := "01100";
constant ALUOP_SLT : std_logic_vector(4 downto 0) := "01101";
constant ALUOP_SGT : std_logic_vector(4 downto 0) := "01110";
constant ALUOP_SLE : std_logic_vector(4 downto 0) := "01111";
constant ALUOP_SGE : std_logic_vector(4 downto 0) := "10000";
constant ALUOP_MOVS2I : std_logic_vector(4 downto 0) := "00000";
constant ALUOP_SLTU : std_logic_vector(4 downto 0) := "10001";
constant ALUOP_SGTU : std_logic_vector(4 downto 0) := "10010";
constant ALUOP_SGEU : std_logic_vector(4 downto 0) := "10011";
begin
res <= res_i;
zero <= '1' when res_i = X"00000000" else '0';
process (alu_op, a, b)
-- complete all the requested functions (20 in total, some are shared b/n instructions)
variable tmp : std_logic_vector(32 downto 0);
begin
ovf <= '0';
case alu_op is
when ALUOP_SLL =>
res_i <= std_logic_vector(shift_left(unsigned(a), to_integer(unsigned(b(4 downto 0)))));
when ALUOP_SRL =>
res_i <= std_logic_vector(shift_right(unsigned(a), to_integer(unsigned(b(4 downto 0)))));
when ALUOP_SRA => -- the shift_right func from numeric_std with a signed number as arg will do SRA
res_i <= std_logic_vector(shift_right(signed(a), to_integer(unsigned(b(4 downto 0)))));
when ALUOP_ADD =>
tmp := std_logic_vector(resize(signed(a), 33) + resize(signed(b), 33));
res_i <= tmp(31 downto 0);
ovf <= (not a(31) and not b(31) and tmp(31)) or (a(31) and b(31) and not tmp(31));
when ALUOP_ADDU =>
tmp := std_logic_vector(resize(unsigned(a), 33) + resize(unsigned(b), 33));
res_i <= tmp(31 downto 0);
when ALUOP_SUB =>
tmp := std_logic_vector(resize(signed(a), 33) - resize(signed(b), 33));
res_i <= tmp(31 downto 0);
-- "ovf = 1 when operands have different sign and result has different sign wrt first operand"
if( (a(31) /= b(31)) and (tmp(31) /= a(31))) then
ovf <= '1';
else
ovf <= '0';
end if;
when ALUOP_SUBU =>
tmp := std_logic_vector(resize(unsigned(a), 33) - resize(unsigned(b), 33));
res_i <= tmp(31 downto 0);
when ALUOP_AND =>
res_i <= a and b;
when ALUOP_OR =>
res_i <= a or b;
when ALUOP_XOR =>
res_i <= a xor b;
when ALUOP_SEQ => -- if a = b then res = 1
if(signed(a) = signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SNE => -- if a /= b then res = 1
if(signed(a) /= signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SLT => -- if a < b then res = 1
if(signed(a) < signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGT => -- if a > b then res = 1
if(signed(a) > signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SLE => -- if a <= b then res = 1
if(signed(a) <= signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGE => -- if a >= b then res = 1
if(signed(a) >= signed(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_MOVS2I =>
res_i <= a;
when ALUOP_SLTU => -- if a < b then res = 1 (a, b unsigned)
if(unsigned(a) < unsigned(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGTU => -- if a > b then res = 1 (a, b unsigned)
if(unsigned(a) > unsigned(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when ALUOP_SGEU => -- if a >= b then res = 1 (a, b unsigned)
if(unsigned(a) >= unsigned(b)) then
res_i <= X"0000000"&"0001";
else
res_i <= X"00000000";
end if;
when others => res_i <= (others => '0'); -- design decision, to avoid inferred latches during synthesis
end case;
end process ;
end rtl;
| mit | bf2e34ec1499f6d012c31ec8348caaef | 0.594048 | 2.989566 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.b-decode.core/a.b.b.b-Extender.vhd | 1 | 2,068 | -------------------------------------------------------------------------------------------------------------
-- Extender
-- This unit recieves as input the immediate filed in the instruction(15-0). Depending on the value of the
-- control signal Unsigned_value it performs and unsigned sing-extension or a signed sign-extension(in two's
-- complement. The block is fully combinational.
-------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
entity extender is
port (
-- INPUTS
immediate : in std_logic_vector(15 downto 0); -- immediate filed (instruction 15 -0)
unsigned_value : in std_logic; -- control signal generated by the CU
-- OUTPUTS
extended : out std_logic_vector(31 downto 0) -- extended value
);
end extender;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
architecture behavioral of extender is
begin
--------------------------------------------------
-- Extend Process
-- Type: Combinational
-- Implemnents the
-- sign-extensionl
-- logic
-----------------------i--------------------------
extend_process:process(immediate, unsigned_value)
begin
if (unsigned_value = '1') then
extended <= "0000000000000000" & immediate;
else
if (immediate(15) = '1') then
extended(31 downto 16) <= (others => '1');
extended(15 downto 0) <= immediate;
else
extended(31 downto 16) <= (others => '0');
extended(15 downto 0) <= immediate;
end if;
end if;
end process;
end behavioral;
| mit | a6a7aca930cab546778c0f572cacdc80 | 0.404255 | 5.385417 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Papilio_Default_Pinout.vhd | 13 | 13,239 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
| mit | 730d38bafc221edd0b87bc41a425a22a | 0.585769 | 2.564207 | false | false | false | false |
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