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chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/lsu.vhd | 13 | 2,970 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
| mit | 2127ff8ea0aad27fd90bd34b6776fc0a | 0.508081 | 3.046154 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.g-mux41.vhd | 1 | 680 | library ieee;
use ieee.std_logic_1164.all;
-- s = 00 -> out = a
-- s = 01 -> out = b
-- s = 10 -> out = c
-- else -> out = 0
entity mux41 is
generic(
NBIT : integer := 32
);
Port (
a: in std_logic_vector(NBIT-1 downto 0);
b: in std_logic_vector(NBIT-1 downto 0);
c: in std_logic_vector(NBIT-1 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic_vector(NBIT-1 downto 0)
);
end mux41;
architecture beh of mux41 is
begin
process (a, b, c, s)
begin
case s is
when "00" =>
y <= a;
when "01" =>
y <= b;
when "10" =>
y <= c;
when others => -- case s = "11"
y <= (others => '0');
end case;
end process;
end beh;
| mit | 891609216638004ef6570332a8a0e6d2 | 0.548529 | 2.446043 | false | false | false | false |
purisc-group/purisc | Compute_Group/BIST_core.vhd | 2 | 3,082 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BIST_core is
PORT (
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end;
architecture BIST of BIST_core is
signal start_address : std_logic_vector(31 downto 0);
signal error_a : std_logic;
signal error_b : std_logic;
signal error_c : std_logic;
signal error_0 : std_logic;
signal error_1 : std_logic;
signal address_a : std_logic_vector(31 downto 0);
signal address_b : std_logic_vector(31 downto 0);
signal address_c : std_logic_vector(31 downto 0);
signal address_0 : std_logic_vector(31 downto 0);
signal address_1 : std_logic_vector(31 downto 0);
begin
process (start_address, id) begin
if (id(0) = '1') then
address_a <= start_address;
address_b <= std_logic_vector(unsigned(start_address) + 1);
address_c <= std_logic_vector(unsigned(start_address) + 2);
address_0 <= std_logic_vector(unsigned(start_address) + 3);
address_1 <= std_logic_vector(unsigned(start_address) + 4);
else
address_a <= start_address;
address_b <= std_logic_vector(unsigned(start_address) + 1);
address_c <= std_logic_vector(unsigned(start_address) + 2);
address_0 <= std_logic_vector(unsigned(start_address) + 3);
address_1 <= std_logic_vector(unsigned(start_address) + 4);
end if;
end process;
w_addr <= "00000000000000000000000000000000";
w_data <= "00000000000000000000000000000000";
we <= '0';
r_addr_a <= address_a;
r_addr_b <= address_b;
r_addr_c <= address_c;
r_addr_0 <= address_0;
r_addr_1 <= address_1;
process (reset_n, clk) begin
if (reset_n = '0') then
if (id(0) = '0') then
start_address <= "00000000000000000000000000010000";
else
start_address <= "00000000000000000000000000010000";
end if;
elsif (rising_edge(clk)) then
if (stall = '0') then
start_address <= std_logic_vector(unsigned(start_address) + 5);
end if;
end if;
end process;
process (reset_n, clk) begin
if (reset_n = '0') then
error_a <= '0';
error_b <= '0';
error_c <= '0';
error_0 <= '0';
error_1 <= '0';
elsif(rising_edge(clk)) then
if (stall = '0') then
if (r_data_a = address_a) then
error_a <= '0';
else
error_a <= '1';
end if;
if (r_data_b = address_b) then
error_b <= '0';
else
error_b <= '1';
end if;
if (r_data_c = address_c) then
error_c <= '0';
else
error_c <= '1';
end if;
if (r_data_a = address_a) then
error_0 <= '0';
else
error_0 <= '1';
end if;
if (r_data_a = address_a) then
error_1 <= '0';
else
error_1 <= '1';
end if;
end if;
end if;
end process;
end; | gpl-2.0 | 2787f88f58c239b682ef889fb5c281b6 | 0.591823 | 2.754245 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/flags.vhd | 13 | 2,535 | ----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
| mit | fda4949b230785299c90e6fc3a5f2989 | 0.601578 | 3.421053 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_passthrough.vhd | 13 | 4,021 | --
-- Audio Passthrough
--
-- Copyright 2008,2009,2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.1: First version, adapted from sigma-delta.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpupkg.all;
use board.zpu_config.all;
use board.zpuinopkg.all;
entity AUDIO_zpuino_wb_passthrough is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_passthrough;
architecture behave of AUDIO_zpuino_wb_passthrough is
signal dat_q1: unsigned(17 downto 0);
signal dat_q2: unsigned(17 downto 0);
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o <= (others => '0');
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
raw_out(17 downto 2) <= std_logic_vector(dat_q1(15 downto 0));
raw_out(1 downto 0)<=(others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dat_q1 <= (others =>'0');
dat_q1(15) <= '1';
dat_q2 <= (others =>'0');
dat_q2(15) <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(2) is
when '1' =>
dat_q1(15 downto 0) <= unsigned(wb_dat_i(15 downto 0));
dat_q2(15 downto 0) <= unsigned(wb_dat_i(31 downto 16));
when others =>
end case;
end if;
end if;
end if;
end process;
end behave;
| mit | 609f30ccc6236a14980a71e4489b07c4 | 0.653071 | 3.348043 | false | false | false | false |
sh-chris110/chris | FPGA/HPS.bak/hps_design/hps_design_inst.vhd | 1 | 3,210 | component hps_design is
port (
clk_clk : in std_logic := 'X'; -- clk
ddr3_mem_a : out std_logic_vector(12 downto 0); -- mem_a
ddr3_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
ddr3_mem_ck : out std_logic; -- mem_ck
ddr3_mem_ck_n : out std_logic; -- mem_ck_n
ddr3_mem_cke : out std_logic; -- mem_cke
ddr3_mem_cs_n : out std_logic; -- mem_cs_n
ddr3_mem_ras_n : out std_logic; -- mem_ras_n
ddr3_mem_cas_n : out std_logic; -- mem_cas_n
ddr3_mem_we_n : out std_logic; -- mem_we_n
ddr3_mem_reset_n : out std_logic; -- mem_reset_n
ddr3_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
ddr3_mem_dqs : inout std_logic := 'X'; -- mem_dqs
ddr3_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
ddr3_mem_odt : out std_logic; -- mem_odt
ddr3_mem_dm : out std_logic; -- mem_dm
ddr3_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
ledr_export : out std_logic; -- export
ddr3_clk_clk : out std_logic -- clk
);
end component hps_design;
u0 : component hps_design
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
ddr3_mem_a => CONNECTED_TO_ddr3_mem_a, -- ddr3.mem_a
ddr3_mem_ba => CONNECTED_TO_ddr3_mem_ba, -- .mem_ba
ddr3_mem_ck => CONNECTED_TO_ddr3_mem_ck, -- .mem_ck
ddr3_mem_ck_n => CONNECTED_TO_ddr3_mem_ck_n, -- .mem_ck_n
ddr3_mem_cke => CONNECTED_TO_ddr3_mem_cke, -- .mem_cke
ddr3_mem_cs_n => CONNECTED_TO_ddr3_mem_cs_n, -- .mem_cs_n
ddr3_mem_ras_n => CONNECTED_TO_ddr3_mem_ras_n, -- .mem_ras_n
ddr3_mem_cas_n => CONNECTED_TO_ddr3_mem_cas_n, -- .mem_cas_n
ddr3_mem_we_n => CONNECTED_TO_ddr3_mem_we_n, -- .mem_we_n
ddr3_mem_reset_n => CONNECTED_TO_ddr3_mem_reset_n, -- .mem_reset_n
ddr3_mem_dq => CONNECTED_TO_ddr3_mem_dq, -- .mem_dq
ddr3_mem_dqs => CONNECTED_TO_ddr3_mem_dqs, -- .mem_dqs
ddr3_mem_dqs_n => CONNECTED_TO_ddr3_mem_dqs_n, -- .mem_dqs_n
ddr3_mem_odt => CONNECTED_TO_ddr3_mem_odt, -- .mem_odt
ddr3_mem_dm => CONNECTED_TO_ddr3_mem_dm, -- .mem_dm
ddr3_oct_rzqin => CONNECTED_TO_ddr3_oct_rzqin, -- .oct_rzqin
ledr_export => CONNECTED_TO_ledr_export, -- ledr.export
ddr3_clk_clk => CONNECTED_TO_ddr3_clk_clk -- ddr3_clk.clk
);
| gpl-2.0 | b30ad7b696817c3764bbe119c14901ad | 0.420561 | 3.057143 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.d-memory.vhd | 1 | 4,932 | ------------------------------------------------------------------------------------------------
-- MEM Stage
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity memory is
port(
-- inputs
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
--
Data_out_fromRAM : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0); -- goes to EXE stage and is used if forwarding detected by forwarding unit
--
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end memory;
architecture struct of memory is
-- component declarations
component dram_block is
port(
-- INPUTS
address : in std_logic_vector(31 downto 0); -- address to the memory
data_write : in std_logic_vector(31 downto 0); -- data to be written in memory
mem_op : in std_logic_vector(5 downto 0); -- control signals for mem operations (sb, sw, lbu, lw, lhu, lb)
-- for protocol: external DRAM communication
Data_out : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- OUTPUTS
unaligned : out std_logic; -- control signal asserted in case of unaligned access
data_read : out std_logic_vector(31 downto 0); -- data read from memory
-- for protocol: external DRAM communication
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end component;
-- internal signals
signal PCsrc_i : std_logic;
signal jump_i : std_logic;
begin
-- concurrent signal assignments
jump_i <= controls_in(1); -- MV
PCsrc_i <= controls_in(0) and takeBranch; -- MV Branch and takeBranch
PCsrc <= PCsrc_i;
jump <= jump_i;
flush <= PCsrc_i or jump_i;
regwrite_MEM <= controls_in(10); -- to forwarding unit
RFaddr_MEM <= RFaddr_in; -- to forwarding unit
forw_addr_MEM <= addrMem; -- to forwarding unit
controls_out <= controls_in(10) & controls_in (9) & controls_in(2); -- pass regwrite, link, memtoreg to WB stage
dataOut_exe <= addrMem;
RFaddr_out <= RFaddr_in;
PC1_out <= PC1_in;
PC2_out <= PC2_in;
-- component instantiations
dram : dram_block port map (addrMem, writeData, controls_in(8 downto 3), Data_out_fromRAM , unaligned, dataOut_mem,
read_op, write_op, nibble, write_byte, Address_toRAM, Data_in);
end struct;
| mit | bf7d18f211862894494f13fc797c5ad1 | 0.536902 | 4.029412 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/sampler.vhd | 13 | 3,330 | ----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from la_input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sampler is
port(
la_input : in std_logic_vector(31 downto 0); -- 32 la_input channels
clock : in std_logic; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in std_logic_vector(23 downto 0); -- configuration data
wrDivider : in std_logic; -- write divider register
sample : out std_logic_vector(31 downto 0); -- sampled data
ready : out std_logic; -- new sample ready
trig_delay : out std_logic_vector(1 downto 0);
num_scheme : in std_logic
);
end sampler;
architecture behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
signal la_input_i : std_logic_vector(31 downto 0);
begin
trig_delay <=
"01" when divider = 0 else
"10" when divider = 1 else
"00";
process(la_input, num_scheme)
begin
if num_scheme = '1' then
for i in 31 downto 0 loop
la_input_i(i) <= la_input(31 - i);
end loop;
else
la_input_i <= la_input;
end if;
end process;
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
ready <= '1';
else
sample <= la_input_i;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= la_input_i;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
end behavioral;
| mit | 9080a8f69c1e539d33466e938d9a94ee | 0.617417 | 3.6 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/wbmux2.vhd | 13 | 2,538 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end entity wbmux2;
architecture behave of wbmux2 is
signal select_zero: std_logic;
begin
select_zero<='1' when m_wb_adr_i(select_line)='0' else '0';
s0_wb_dat_o <= m_wb_dat_i;
s0_wb_adr_o <= m_wb_adr_i;
s0_wb_stb_o <= m_wb_stb_i;
s0_wb_we_o <= m_wb_we_i;
s0_wb_cti_o <= m_wb_cti_i;
s0_wb_sel_o <= m_wb_sel_i;
s1_wb_dat_o <= m_wb_dat_i;
s1_wb_adr_o <= m_wb_adr_i;
s1_wb_stb_o <= m_wb_stb_i;
s1_wb_we_o <= m_wb_we_i;
s1_wb_cti_o <= m_wb_cti_i;
s1_wb_sel_o <= m_wb_sel_i;
process(m_wb_cyc_i,select_zero)
begin
if m_wb_cyc_i='0' then
s0_wb_cyc_o<='0';
s1_wb_cyc_o<='0';
else
s0_wb_cyc_o<=select_zero;
s1_wb_cyc_o<=not select_zero;
end if;
end process;
process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i)
begin
if select_zero='0' then
m_wb_dat_o<=s1_wb_dat_i;
m_wb_ack_o<=s1_wb_ack_i;
else
m_wb_dat_o<=s0_wb_dat_i;
m_wb_ack_o<=s0_wb_ack_i;
end if;
end process;
end behave;
| mit | 24af5d1c4785c2fd2e7b11004111fca2 | 0.623325 | 2.218531 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpu_core_extreme_hyperion.vhd | 13 | 42,758 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg_hyperion.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_hyperion;
architecture behave of zpu_core_extreme_hyperion is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_Store,
State_StoreB,
State_StoreB2,
State_Load,
State_LoadMemory,
State_LoadStack,
State_Loadb,
State_Resync1,
State_Resync2,
State_LoadSP,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := 10;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
dbg_out.stacka <= std_logic_vector(exr.tos);
dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(rom_wb_dat_i, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(rom_wb_dat_i(31 downto 24));
when 1 => tOpcode := std_logic_vector(rom_wb_dat_i(23 downto 16));
when 2 => tOpcode := std_logic_vector(rom_wb_dat_i(15 downto 8));
when 3 => tOpcode := std_logic_vector(rom_wb_dat_i(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
sampledOpWillFreeze<='1';
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
rom_wb_stb_o <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, rom_wb_ack_i, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, rom_wb_stall_i
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
rom_wb_adr_o <= std_logic_vector(pc_to_memaddr(decr.fetchpc));
rom_wb_cti_o <= CTI_CYCLE_INCRADDR;
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
rom_wb_cyc_o <= '0';
else
rom_wb_cyc_o <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and rom_wb_stall_i='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o <='0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
w.valid := rom_wb_ack_i;
end if;
if rom_wb_ack_i='1' then
w.im := sampledOpcode(7);
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and rom_wb_stall_i='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
if rom_wb_stall_i='0' then
w.opcode := sampledOpcode;
end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
w.valid := decr.valid;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
| Decoded_Load
| Decoded_Store
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(10 downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(10 downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
wb_adr_o(maxAddrBitIncIO downto 0) <= std_logic_vector(exr.tos_save(maxAddrBitIncIO downto 0));
wb_cyc_o <= exr.wb_cyc;
wb_stb_o <= exr.wb_stb;
wb_we_o <= exr.wb_we;
wb_dat_o <= std_logic_vector( exr.nos_save );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= '0';
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= '0';
wroteback := wroteback_q;
stack_b_writeenable <= '0';
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
case exr.state is
when State_Resync1 =>
exu_busy <= '1';
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(10 downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<='1';
wroteback:='1';
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= '1';
when Decoded_StoreSP =>
stack_a_writeenable <= '1';
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<='1';
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store =>
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(nos);
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_StoreB =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(10 downto 2));
stack_a_enable<='1';
w.state := State_LoadStack;
else
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
w.wb_we :='0';
w.wb_cyc :='1';
w.wb_stb :='1';
w.state := State_Load;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Store =>
exu_busy <= '1';
-- Keep writeback flag
wroteback := wroteback_q;
if wb_ack_i='1' then
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
stack_b_enable<='1';
wroteback := '0';
--exu_busy <= '1';
w.wb_cyc := '0';
w.state := State_Resync2;
else
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_enable<='0';
stack_b_enable<='0';
end if;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Load =>
if wb_ack_i='0' then
exu_busy<='1';
else
w.tos := unsigned(wb_dat_i);
w.wb_cyc := '0';
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state := State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state := State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
end if;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state:=State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when State_StoreB =>
exu_busy <= '1';
--
-- At this point, we have loaded the 32-bit, and it's in TOS
-- The IO address is still saved in save_TOS.
-- The original write value is still at save_NOS
--
-- So we mangle the write value, and update save_NOS, and restore
-- the IO address to TOS
--
-- This is still buggy - don't use. Problems arise when writing to stack.
--
w.nos_save := exr.tos;
case exr.tos_save(1 downto 0) is
when "00" =>
w.nos_save(31 downto 24) := exr.nos_save(7 downto 0);
when "01" =>
w.nos_save(23 downto 16) := exr.nos_save(7 downto 0);
when "10" =>
w.nos_save(15 downto 8) := exr.nos_save(7 downto 0);
when "11" =>
w.nos_save(7 downto 0) := exr.nos_save(7 downto 0);
when others =>
null;
end case;
w.tos := exr.tos_save;
w.state := State_StoreB2;
when State_StoreB2 =>
exu_busy <= '1';
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(exr.nos_save); -- hmm I don't like this
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
| mit | cbb89afb50b434dcc31a26404585684c | 0.555615 | 3.600977 | false | false | false | false |
huukit/logicsynth | excercises/vhd/wave_gen.vhd | 1 | 3,613 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 06
-- Project :
-------------------------------------------------------------------------------
-- File : wave_gen.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 23.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sixth excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 23.11.2015 1.0 tuhu Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wave_gen is -- Wave generator entity.
generic (
width_g : integer; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end wave_gen;
architecture rtl of wave_gen is
type dir_type is (up, down); -- Definition for counter direction type.
constant maxval_c : integer := (2**(width_g - 1) - 1)/step_g * step_g; -- Maximum value for counter.
constant minval_c : integer := -maxval_c; -- Minimun value for counter.
signal dir_r : dir_type; -- Counter direction.
signal count_r : signed(width_g - 1 downto 0); -- Counter count register.
begin -- rtl
value_out <= std_logic_vector(count_r); -- Assign register to output.
count : process (clk, rst_n) -- Process to increment or decrement counter value.
begin
if(rst_n = '0') then
count_r <= (others => '0'); -- Clear the output on reset ...
elsif(clk'event and clk = '1') then
if(sync_clear_in = '1') then
count_r <= (others => '0'); -- ... or if the sync bit is active.
else
case (dir_r) is -- Check the direction and step the counter up or down.
when up =>
count_r <= count_r + step_g; -- Step counter up.
when down =>
count_r <= count_r - step_g; -- Step counter down.
end case; -- dir_r
end if; -- sync_clear_in
end if; -- clk'event ...
end process count;
compare : process (clk, rst_n) -- Process to do compare and change direction.
begin
if(rst_n = '0') then
dir_r <= up; -- Set the default direction of the counter on reset ...
elsif(clk'event and clk = '1') then
if(sync_clear_in = '1') then
dir_r <= up; -- ... and also set the counter direction on sync bit active.
else
if((count_r + step_g) = maxval_c) then -- If we are on the limit on the next round ...
dir_r <= down; -- ... change the direction of the counter.
elsif((count_r - step_g) = minval_c) then -- Note, as assignments take place after the block
dir_r <= up; -- has been executed, we need to change the direction
end if; -- count_r -- before hitting the actual limit.
end if; -- sync_clear_in
end if; -- clk'event ...
end process compare;
end rtl; | gpl-2.0 | aae31a4792465c8a41f919df3c42ca9e | 0.486576 | 4.133867 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/wbbootloadermux.vhd | 13 | 2,734 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end entity wbbootloadermux;
architecture behave of wbbootloadermux is
signal select_zero: std_logic;
begin
select_zero<='0' when sel='1' else '1';
s0_wb_dat_o <= m_wb_dat_i;
s0_wb_adr_o <= m_wb_adr_i;
s0_wb_stb_o <= m_wb_stb_i;
s0_wb_we_o <= m_wb_we_i;
s0_wb_cti_o <= m_wb_cti_i;
s0_wb_sel_o <= m_wb_sel_i;
s1_wb_dat_o <= m_wb_dat_i;
s1_wb_adr_o <= m_wb_adr_i(11 downto 2);
s1_wb_stb_o <= m_wb_stb_i;
s1_wb_we_o <= m_wb_we_i;
s1_wb_cti_o <= m_wb_cti_i;
s1_wb_sel_o <= m_wb_sel_i;
process(m_wb_cyc_i,select_zero)
begin
if m_wb_cyc_i='0' then
s0_wb_cyc_o<='0';
s1_wb_cyc_o<='0';
else
s0_wb_cyc_o<=select_zero;
s1_wb_cyc_o<=not select_zero;
end if;
end process;
process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i,s0_wb_stall_i,s1_wb_stall_i)
begin
if select_zero='0' then
m_wb_dat_o<=s1_wb_dat_i;
m_wb_ack_o<=s1_wb_ack_i;
m_wb_stall_o<=s1_wb_stall_i;
else
m_wb_dat_o<=s0_wb_dat_i;
m_wb_ack_o<=s0_wb_ack_i;
m_wb_stall_o<=s0_wb_stall_i;
end if;
end process;
end behave;
| mit | 297f76f20ed1249ecb92421eac4b9d97 | 0.6218 | 2.210186 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_debug_core.vhd | 13 | 5,367 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
| mit | a73f6ec48b157f81dc4f3b92b165de03 | 0.53829 | 3.192742 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_io.vhd | 1 | 8,214 | --
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0')
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
| mit | 1e0da7222caa9c440be806d1cb152dda | 0.615656 | 3.135115 | false | false | false | false |
algebrato/eldig | Lez12/num.vhd | 1 | 3,849 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:31 04/21/2016
-- Design Name:
-- Module Name: num - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--Tutto quello che entra in SEZIONE LOGICA CONCORRENTE -- e` tutto in parallelo (non conta l'ordine)
--non ho un prima o un dopo (solo logica combinatoria -> le uscite al tempo t sono una funzione al tempo t).
--Ma posso aver bisogno di un ordine (logica sequenziale) out(t)=f(I(t))_{t<=t_0} quindi gli ingressi dipenderanno anche
--da quello che e` successo nel passato. Uguale a scrivere a out(t_0) = g(I(t_0), stati(t_0)), gli stati sono informazioni
--interne alal scatola.
--Un contatore e` un oggetto di logica sequenziale. L'ingresso e` un segnale di tipo "enable" se passo da 0 a 1 allora incrementa di 1
--passo da uno stato all'altro da una certa regola
entity num is
Port ( SW : in STD_LOGIC_VECTOR(7 downto 0);
N_OUT : out UNSIGNED(3 downto 0);
SEG : out STD_LOGIC_VECTOR(0 to 6)
);
end num;
architecture Behavioral of num is
signal N: UNSIGNED(2 downto 0);
begin
--flipflop di tipo D
contatore_3bit:process(enable)
begin
if rising_edge(enable) then
--N <= N+1; --sfrutto algebra di bool (perdo il riporto)
--oppure, in modo diverso
if N=7 then N<= "000";
else N<=N+1
end if
end if
end process contatore_3bit;
--possibili rappresentazioni della stessa cosa (porta AND)
C <= A and B;
C <= '1' when A='1' and B='1' else '0';
porta_and:process(A,B)
begin
if A='1' and B='1' then
C <='1';
else
C <= '0';
end if;
end process porta_and;
--possibili interpretazioni del multiplexer
with sel select
C <= A when '1',
B when '0';
--implementazione della porta AND col multiplexer
with sel select
C <= '1' when '11',
'0' when others;
--N_OUT(0)<='0' when SW(0)='1' else '1';
--N_OUT(1)<='0' when SW(1)='1' else '1';
--N_OUT(2)<='0' when SW(2)='1' else '1';
--N_OUT(3)<='0' when SW(3)='1' else '1';
--N<=UNSIGNED(SW(7 downto 4));
--SEG(0)<='0' when N=0 or N=2 or N=3 or N>4 else '1';
--SEG(1)<='0' when N=0 or N=1 or N=2 or N=3 or N=4 or N=7 or N=8 or N=9 else '1';
--SEG(2)<='0' when N=0 or N=1 or N=3 or N=4 or N=5 or N=6 or N=7 or N=8 or N=9 else '1';
--SEG(3)<='0' when N=0 or N=2 or N=3 or N=5 or N=6 or N=8 or N>9 else '1';
--SEG(4)<='0' when N=0 or N=2 or N=6 or N=8 or N>9 else '1';
--SEG(5)<='0' when N=0 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
--SEG(6)<='0' when N=2 or N=3 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
--processi--
--P1:process(A,B,C) --sensivity list
--parte dichiarativa
--parte implementativa --dentro una entity posso avere tanti processi quanti ne voglio
--la struttura del processo, come blocco, sono all'interno della sezione concorrente.
--stanno tutte parallelamente nella entity. I processi, sono tra loro concorrenti (agiscono in modo indipendente)
--ma all'interno di un processo c'e` un "prima" e un "dopo" c'e` una certa idea di sequenzialita`
--i processi parlano tra loro tramite i segnali! Oppure posso usare le VARIABILI. Sono piu` astratte
--end process P1;
end Behavioral;
| gpl-3.0 | e6ce8e3c1055846903c5db30fd9ae483 | 0.618862 | 2.791153 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/BRAM8k36bit.vhd | 13 | 2,520 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BRAM8k36bit is
generic (
address_bits: integer := 13;
data_bits: integer := 36
);
port (
clka: in std_logic;
-- ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dina: in std_logic_vector(data_bits-1 downto 0);
douta: out std_logic_vector(data_bits-1 downto 0)
);
end entity BRAM8k36bit;
architecture behave of BRAM8k36bit is
subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE;
signal ena : std_logic;
begin
ena <= '1';
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dina;
end if;
douta <= RAM(conv_integer(addra)) ;
end if;
end if;
end process;
end behave;
| mit | b21c243cdc3ca66d2b6c25d99564f7f5 | 0.673413 | 3.75 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/simulation/frame_buffer_tb.vhd | 1 | 4,541 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: frame_buffer_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY frame_buffer_tb IS
END ENTITY;
ARCHITECTURE frame_buffer_tb_ARCH OF frame_buffer_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
frame_buffer_synth_inst:ENTITY work.frame_buffer_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | b8b71515e1c624f352a8a3a2befc5dbb | 0.617265 | 4.605477 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15,356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity COMM_zpuino_wb_i2c is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity COMM_zpuino_wb_i2c;
architecture structural of COMM_zpuino_wb_i2c is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
| mit | 45a115cc9f0ddb53dab8a0f3695a3103 | 0.45982 | 4.094933 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/bootloader.vhd | 13 | 13,706 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(11 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity bootloader_dp_32;
architecture behave of bootloader_dp_32 is
subtype RAM_WORD is STD_LOGIC_VECTOR (31 downto 0);
type RAM_TABLE is array (0 to 1023) of RAM_WORD;
shared variable RAM: RAM_TABLE := RAM_TABLE'(
x"0b0b0b98",x"c0040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b98",x"a1040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fd0608",x"72830609",x"81058205",x"832b2a83",x"ffff0652",x"04000000",x"00000000",x"00000000",x"71fd0608",x"83ffff73",x"83060981",x"05820583",x"2b2b0906",x"7383ffff",x"0b0b0b0b",x"83a70400",x"72098105",x"72057373",x"09060906",x"73097306",x"070a8106",x"53510400",x"00000000",x"00000000",x"72722473",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71737109",x"71068106",x"30720a10",x"0a720a10",x"0a31050a",x"81065151",x"53510400",x"00000000",x"72722673",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"cc040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"720a722b",x"0a535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72729f06",x"0981050b",x"0b0b88af",x"05040000",x"00000000",x"00000000",x"00000000",x"00000000",x"72722aff",x"739f062a",x"0974090a",x"8106ff05",x"06075351",x"04000000",x"00000000",x"00000000",x"71715351",x"020d0406",x"73830609",x"81058205",x"832b0b2b",x"0772fc06",x"0c515104",x"00000000",x"72098105",x"72050970",x"81050906",x"0a810653",x"51040000",x"00000000",x"00000000",x"00000000",x"72098105",x"72050970",x"81050906",x"0a098106",x"53510400",x"00000000",x"00000000",x"00000000",x"71098105",x"52040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72720981",x"05055351",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097206",x"73730906",x"07535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fc0608",x"72830609",x"81058305",x"1010102a",x"81ff0652",x"04000000",x"00000000",x"00000000",x"71fc0608",x"0b0b0b9e",x"ec738306",x"10100508",x"060b0b0b",x"88b20400",x"00000000",x"00000000",x"0b0b0b89",x"80040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"e8040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097081",x"0509060a",x"8106ff05",x"70547106",x"73097274",x"05ff0506",x"07515151",x"04000000",x"72097081",x"0509060a",x"098106ff",x"05705471",x"06730972",x"7405ff05",x"06075151",x"51040000",x"05ff0504",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"810b0b0b",x"0b9fb40c",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71810552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"02840572",x"10100552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"717105ff",x"05715351",x"020d0400",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"81dd3f96",x"ba3f0400",x"00000000",x"00000000",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101053",x"51047381",x"ff067383",x"06098105",x"83051010",x"102b0772",x"fc060c51",x"51043c04",x"72728072",x"8106ff05",x"09720605",x"71105272",x"0a100a53",x"72ed3851",x"51535104",x"88088c08",x"90087575",x"99ed2d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90087575",x"99a92d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90088dff",x"2d900c8c",x"0c880c04",x"ff3d0d0b",x"0b0b9fc4",x"335170a6",x"389fc008",x"70085252",x"70802e92",x"3884129f",x"c00c702d",x"9fc00870",x"08525270",x"f038810b",x"0b0b0b9f",x"c434833d",x"0d040480",x"3d0d0b0b",x"0b9ff008",x"802e8e38",x"0b0b0b0b",x"800b802e",x"09810685",x"38823d0d",x"040b0b0b",x"9ff0510b",x"0b0bf5f8",x"3f823d0d",x"0404ff3d",x"0d80c480",x"80845271",x"0870822a",x"70810651",x"515170f3",x"38833d0d",x"04ff3d0d",x"80c48080",x"84527108",x"70812a70",x"81065151",x"5170f338",x"7382900a",x"0c833d0d",x"04fe3d0d",x"747080dc",x"8080880c",x"7081ff06",x"ff831154",x"51537181",x"268d3880",x"fd518aa9",x"2d72a032",x"51833972",x"518aa92d",x"843d0d04",x"803d0d83",x"ffff0b83",x"d00a0c80",x"fe518aa9",x"2d823d0d",x"04ff3d0d",x"83d00a08",x"70882a52",x"528ac92d",x"7181ff06",x"518ac92d",x"80fe518a",x"a92d833d",x"0d0482f6",x"ff0b80cc",x"8080880c",x"800b80cc",x"8080840c",x"9f0b8390",x"0a0c04ff",x"3d0d7370",x"08515180",x"c8808084",x"70087084",x"80800772",x"0c525283",x"3d0d04ff",x"3d0d80c8",x"80808470",x"0870fbff",x"ff06720c",x"5252833d",x"0d04a090",x"0ba0800c",x"9fc80ba0",x"840c98d9",x"2dff3d0d",x"73518b71",x"0c901152",x"98808072",x"0c80720c",x"700883ff",x"ff06880c",x"833d0d04",x"fa3d0d78",x"7a7dff1e",x"57575853",x"73ff2ea7",x"38805684",x"5275730c",x"72088818",x"0cff1252",x"71f33874",x"84167408",x"720cff16",x"56565273",x"ff2e0981",x"06dd3888",x"3d0d04f8",x"3d0d80c0",x"80808457",x"83d00a59",x"8be32d76",x"518c892d",x"9fc87088",x"08101098",x"80840571",x"70840553",x"0c5656fb",x"8084a1ad",x"750c9fa4",x"0b88170c",x"8070780c",x"770c7608",x"83ffff06",x"5683ffdf",x"800b8808",x"278338ff",x"3983ffff",x"790ca080",x"54880853",x"78527651",x"8ca82d76",x"518bc72d",x"78085574",x"762e8938",x"80c3518a",x"a92dff39",x"a0840855",x"74faa090",x"ae802e89",x"3880c251",x"8aa92dff",x"39900a70",x"0870ffbf",x"06720c56",x"568a8e2d",x"8bfa2dff",x"3d0d9fd4",x"0881119f",x"d40c5183",x"900a7008",x"70feff06",x"720c5252",x"833d0d04",x"803d0d8a",x"f82d7281",x"8007518a",x"c92d8b8d",x"2d823d0d",x"04fe3d0d",x"80c08080",x"84538be3",x"2d85730c",x"80730c72",x"087081ff",x"06745351",x"528bc72d",x"71880c84",x"3d0d04fc",x"3d0d7681",x"11338212",x"33718180",x"0a297184",x"80802905",x"83143370",x"82802912",x"84163352",x"7105a080",x"05861685",x"17335752",x"53535557",x"5553ff13",x"5372ff2e",x"91387370",x"81055533",x"52717570",x"81055734",x"e9398951",x"8e9c2d86",x"3d0d04f9",x"3d0d7957",x"80c08080",x"84568be3",x"2d811733",x"82183371",x"82802905",x"53537180",x"2e943885",x"17725553",x"72708105",x"5433760c",x"ff145473",x"f3388317",x"33841833",x"71828029",x"05565280",x"54737527",x"97387358",x"77760c73",x"17760853",x"53717334",x"81145474",x"7426ed38",x"75518bc7",x"2d8af82d",x"8184518a",x"c92d7488",x"2a518ac9",x"2d74518a",x"c92d8054",x"7375278f",x"38731770",x"3352528a",x"c92d8114",x"54ee398b",x"8d2d893d",x"0d04f93d",x"0d795680",x"c0808084",x"558be32d",x"86750c74",x"518bc72d",x"8be32d81",x"ad70760c",x"81173382",x"18337182",x"80290583",x"1933780c",x"84193378",x"0c851933",x"780c5953",x"53805473",x"7727b338",x"72587380",x"2e87388b",x"e32d7775",x"0c731686",x"1133760c",x"87113376",x"0c527451",x"8bc72d8e",x"b12d8808",x"81065271",x"f6388214",x"54767426",x"d1388be3",x"2d84750c",x"74518bc7",x"2d8af82d",x"8187518a",x"c92d8b8d",x"2d893d0d",x"04fc3d0d",x"76811133",x"82123371",x"902b7188",x"2b078314",x"33707207",x"882b8416",x"33710751",x"52535757",x"54528851",x"8e9c2d81",x"ff518aa9",x"2d80c480",x"80845372",x"0870812a",x"70810651",x"515271f3",x"38738480",x"800780c4",x"8080840c",x"863d0d04",x"fe3d0d8e",x"b12d8808",x"88088106",x"535371f3",x"388af82d",x"8183518a",x"c92d7251",x"8ac92d8b",x"8d2d843d",x"0d04fe3d",x"0d800b9f",x"d40c8af8",x"2d818151",x"8ac92d9f",x"a4538f52",x"72708105",x"5433518a",x"c92dff12",x"5271ff2e",x"098106ec",x"388b8d2d",x"843d0d04",x"fe3d0d80",x"0b9fd40c",x"8af82d81",x"82518ac9",x"2d80c080",x"8084528b",x"e32d81f9",x"0a0b80c0",x"80809c0c",x"71087252",x"538bc72d",x"729fdc0c",x"72902a51",x"8ac92d9f",x"dc08882a",x"518ac92d",x"9fdc0851",x"8ac92d8e",x"b12d8808",x"518ac92d",x"8b8d2d84",x"3d0d0480",x"3d0d810b",x"9fd80c80",x"0b83900a",x"0c85518e",x"9c2d823d",x"0d04803d",x"0d800b9f",x"d80c8bae",x"2d86518e",x"9c2d823d",x"0d04fd3d",x"0d80c080",x"8084548a",x"518e9c2d",x"8be32d9f",x"c8745253",x"8c892d72",x"88081010",x"98808405",x"71708405",x"530c52fb",x"8084a1ad",x"720c9fa4",x"0b88140c",x"73518bc7",x"2d8a8e2d",x"8bfa2dfc",x"3d0d80c0",x"80808470",x"52558bc7",x"2d8be32d",x"8b750c76",x"80c08080",x"940c8075",x"0ca08054",x"775383d0",x"0a527451",x"8ca82d74",x"518bc72d",x"8a8e2d8b",x"fa2dffab",x"3d0d800b",x"9fd80c80",x"0b9fd40c",x"800b8dff",x"0ba0800c",x"5780c480",x"80845584",x"80b3750c",x"80c88080",x"a453fbff",x"ff730870",x"7206750c",x"535480c8",x"80809470",x"08707606",x"720c5353",x"a8709aa5",x"71708405",x"530c9b82",x"710c539c",x"9b0b8812",x"0c9daa0b",x"8c120c94",x"bb0b9012",x"0c53880b",x"80d08080",x"840c80d0",x"0a538173",x"0c8bae2d",x"8288880b",x"80dc8080",x"840c81f2",x"0b900a0c",x"80c08080",x"84705252",x"8bc72d8b",x"e32d7151",x"8bc72d8b",x"e32d8472",x"0c71518b",x"c72d7677",x"7675933d",x"41415b5b",x"5b83d00a",x"5c780870",x"81065152",x"719d389f",x"d8085372",x"f0389fd4",x"085287e8",x"7227e638",x"727e0c72",x"83900a0c",x"98d12d82",x"900a0853",x"79802e81",x"b4387280",x"fe2e0981",x"0680f438",x"76802ec1",x"38807d78",x"58565a82",x"7727ffb5",x"3883ffff",x"7c0c79fe",x"18535379",x"72279838",x"80dc8080",x"88725558",x"72157033",x"790c5281",x"13537373",x"26f238ff",x"16751154",x"7505ff05",x"70337433",x"7072882b",x"077f0853",x"51555152",x"71732e09",x"8106feed",x"38743353",x"728a26fe",x"e4387210",x"109ef805",x"75527008",x"5152712d",x"fed33972",x"80fd2e09",x"81068638",x"815bfec5",x"3976829f",x"269e387a",x"802e8738",x"8073a032",x"545b80d7",x"3d7705fd",x"e0055272",x"72348117",x"57fea239",x"805afe9d",x"397280fe",x"2e098106",x"fe933879",x"5783ffff",x"7c0c8177",x"5c5afe85",x"39803d0d",x"88088c08",x"9008a080",x"0851702d",x"900c8c0c",x"8a0c810b",x"80d00a0c",x"823d0d04",x"ff3d0d98",x"fd2d8052",x"805194f2",x"2d833d0d",x"0483ffff",x"f80d8ce3",x"0483ffff",x"f80da088",x"04000000",x"00000000",x"00000000",x"00000000",x"820b80d0",x"8080900c",x"0b0b0b04",x"0083f00a",x"0b800ba0",x"80721208",x"720c8412",x"5271712e",x"ff05f238",x"028c050d",x"98f00400",x"00000000",x"00000000",x"00000000",x"00fb3d0d",x"77795555",x"80567575",x"24ab3880",x"74249d38",x"80537352",x"745180e1",x"3f880854",x"75802e85",x"38880830",x"5473880c",x"873d0d04",x"73307681",x"325754dc",x"39743055",x"81567380",x"25d238ec",x"39fa3d0d",x"787a5755",x"80577675",x"24a43875",x"9f2c5481",x"53757432",x"74315274",x"519b3f88",x"08547680",x"2e853888",x"08305473",x"880c883d",x"0d047430",x"558157d7",x"39fc3d0d",x"76785354",x"81538074",x"73265255",x"72802e98",x"3870802e",x"a9388072",x"24a43871",x"10731075",x"72265354",x"5272ea38",x"73517883",x"38745170",x"880c863d",x"0d047281",x"2a72812a",x"53537280",x"2ee63871",x"7426ef38",x"73723175",x"74077481",x"2a74812a",x"55555654",x"e539fc3d",x"0d767079",x"7b555555",x"558f7227",x"8c387275",x"07830651",x"70802ea7",x"38ff1252",x"71ff2e98",x"38727081",x"05543374",x"70810556",x"34ff1252",x"71ff2e09",x"8106ea38",x"74880c86",x"3d0d0474",x"51727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0cf01252",x"718f26c9",x"38837227",x"95387270",x"84055408",x"71708405",x"530cfc12",x"52718326",x"ed387054",x"ff8339fc",x"3d0d7679",x"71028c05",x"9f053357",x"55535583",x"72278a38",x"74830651",x"70802ea2",x"38ff1252",x"71ff2e93",x"38737370",x"81055534",x"ff125271",x"ff2e0981",x"06ef3874",x"880c863d",x"0d047474",x"882b7507",x"7071902b",x"07515451",x"8f7227a5",x"38727170",x"8405530c",x"72717084",x"05530c72",x"71708405",x"530c7271",x"70840553",x"0cf01252",x"718f26dd",x"38837227",x"90387271",x"70840553",x"0cfc1252",x"718326f2",x"387053ff",x"9039fb3d",x"0d777970",x"72078306",x"53545270",x"93387173",x"73085456",x"54717308",x"2e80c438",x"73755452",x"71337081",x"ff065254",x"70802e9d",x"38723355",x"70752e09",x"81069538",x"81128114",x"71337081",x"ff065456",x"545270e5",x"38723355",x"7381ff06",x"7581ff06",x"71713188",x"0c525287",x"3d0d0471",x"0970f7fb",x"fdff1406",x"70f88482",x"81800651",x"51517097",x"38841484",x"16710854",x"56547175",x"082edc38",x"73755452",x"ff963980",x"0b880c87",x"3d0d04ff",x"3d0d9fe4",x"0bfc0570",x"08525270",x"ff2e9138",x"702dfc12",x"70085252",x"70ff2e09",x"8106f138",x"833d0d04",x"04eac13f",x"04000000",x"00ffffff",x"ff00ffff",x"ffff00ff",x"ffffff00",x"00000946",x"00000978",x"00000920",x"000007ab",x"000009cf",x"000009e6",x"0000083e",x"000008cd",x"00000757",x"000009fa",x"01090600",x"007fef80",x"05b8d800",x"a4041700",x"00000000",x"00000000",x"00000000",x"00000fec",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"ffffffff",x"00000000",x"ffffffff",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if WEA='1' then
RAM(conv_integer(ADDRA) ) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if WEB='1' then
RAM( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave; | mit | 4231124d5f5571156edba6ccf5438ce5 | 0.732818 | 1.966992 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Wing_VGA8.vhd | 13 | 1,470 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
| mit | ca816664d4f8d54d64f5c738852ffacb | 0.585034 | 3.252212 | false | false | false | false |
sh-chris110/chris | FPGA/HPS.bak/demo/DE1_SoC_demo/hw/hdl/DE1_SoC_top_level.vhd | 2 | 20,120 | -- #############################################################################
-- DE1_SoC_top_level.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.4
-- Creation date : 04/02/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_top_level is
port(
-- ADC
-- ADC_CS_n : out std_logic;
-- ADC_DIN : out std_logic;
-- ADC_DOUT : in std_logic;
-- ADC_SCLK : out std_logic;
-- Audio
-- AUD_ADCDAT : in std_logic;
-- AUD_ADCLRCK : inout std_logic;
-- AUD_BCLK : inout std_logic;
-- AUD_DACDAT : out std_logic;
-- AUD_DACLRCK : inout std_logic;
-- AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
-- CLOCK2_50 : in std_logic;
-- CLOCK3_50 : in std_logic;
-- CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
-- FPGA_I2C_SCLK : out std_logic;
-- FPGA_I2C_SDAT : inout std_logic;
-- SEG7
-- HEX0_N : out std_logic_vector(6 downto 0);
-- HEX1_N : out std_logic_vector(6 downto 0);
-- HEX2_N : out std_logic_vector(6 downto 0);
-- HEX3_N : out std_logic_vector(6 downto 0);
-- HEX4_N : out std_logic_vector(6 downto 0);
-- HEX5_N : out std_logic_vector(6 downto 0);
-- IR
-- IRDA_RXD : in std_logic;
-- IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
-- PS2_CLK : inout std_logic;
-- PS2_CLK2 : inout std_logic;
-- PS2_DAT : inout std_logic;
-- PS2_DAT2 : inout std_logic;
-- SW
-- SW : in std_logic_vector(9 downto 0);
-- Video-In
-- TD_CLK27 : inout std_logic;
-- TD_DATA : out std_logic_vector(7 downto 0);
-- TD_HS : out std_logic;
-- TD_RESET_N : out std_logic;
-- TD_VS : out std_logic;
-- VGA
-- VGA_B : out std_logic_vector(7 downto 0);
-- VGA_BLANK_N : out std_logic;
-- VGA_CLK : out std_logic;
-- VGA_G : out std_logic_vector(7 downto 0);
-- VGA_HS : out std_logic;
-- VGA_R : out std_logic_vector(7 downto 0);
-- VGA_SYNC_N : out std_logic;
-- VGA_VS : out std_logic;
-- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_top_level;
architecture rtl of DE1_SoC_top_level is
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0);
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0);
hps_0_ddr_mem_ck : out std_logic;
hps_0_ddr_mem_ck_n : out std_logic;
hps_0_ddr_mem_cke : out std_logic;
hps_0_ddr_mem_cs_n : out std_logic;
hps_0_ddr_mem_ras_n : out std_logic;
hps_0_ddr_mem_cas_n : out std_logic;
hps_0_ddr_mem_we_n : out std_logic;
hps_0_ddr_mem_reset_n : out std_logic;
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_odt : out std_logic;
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0);
hps_0_ddr_oct_rzqin : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_qspi_inst_CLK : out std_logic;
hps_0_io_hps_io_qspi_inst_SS0 : out std_logic;
hps_0_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
pll_0_sdram_clk : out std_logic;
reset_reset_n : in std_logic := 'X';
sdram_controller_0_wire_addr : out std_logic_vector(12 downto 0);
sdram_controller_0_wire_ba : out std_logic_vector(1 downto 0);
sdram_controller_0_wire_cas_n : out std_logic;
sdram_controller_0_wire_cke : out std_logic;
sdram_controller_0_wire_cs_n : out std_logic;
sdram_controller_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_0_wire_dqm : out std_logic_vector(1 downto 0);
sdram_controller_0_wire_ras_n : out std_logic;
sdram_controller_0_wire_we_n : out std_logic;
nios_leds_external_connection_export : out std_logic_vector(4 downto 0);
hps_fpga_leds_external_connection_export : out std_logic_vector(4 downto 0)
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => CLOCK_50,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_0_io_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_0_io_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_0_io_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_0_io_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_0_io_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
pll_0_sdram_clk => DRAM_CLK,
reset_reset_n => KEY_N(0),
sdram_controller_0_wire_addr => DRAM_ADDR,
sdram_controller_0_wire_ba => DRAM_BA,
sdram_controller_0_wire_cas_n => DRAM_CAS_N,
sdram_controller_0_wire_cke => DRAM_CKE,
sdram_controller_0_wire_cs_n => DRAM_CS_N,
sdram_controller_0_wire_dq => DRAM_DQ,
sdram_controller_0_wire_dqm(1) => DRAM_UDQM,
sdram_controller_0_wire_dqm(0) => DRAM_LDQM,
sdram_controller_0_wire_ras_n => DRAM_RAS_N,
sdram_controller_0_wire_we_n => DRAM_WE_N,
nios_leds_external_connection_export => LEDR(4 downto 0),
hps_fpga_leds_external_connection_export => LEDR(9 downto 5)
);
end;
| gpl-2.0 | 133fa742965a487d4c01ecd5e3300aaa | 0.436978 | 3.206886 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.d-memory.core/a.b.d.a-DRAM_block.core/a.b.d.a.b-MMU_in_DRAM.vhd | 1 | 5,610 | ---------------------------------------------------------------------------------------------------------
-- MMU in
-- This block handles input values for the DRAM, to perform read/write operation.
-- It is in charge for translating virtual aligned address in physical uniligned addresses and feed
-- the DRAM with the correct data. In case of unaligned access to memory unaligned control signal is
-- asserted
---------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
---------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------
entity mmu_in_dram is
port (
--INPUTS
mem_op : in std_logic_vector(5 downto 0); -- control signal which groups the control signals directed to the memory (sb, sw, lbu, lw, lhu, lb)
aligned_address : in std_logic_vector(31 downto 0); -- aligned access to be translated
data : in std_logic_vector(31 downto 0); -- data to be written at the address specified in aligned address
--OUTPUTS
unaligned : out std_logic; -- signal directed to the PSW, asserted in case of unaligned access to the memory
nibble : out std_logic_vector(1 downto 0); -- last two bit of the incoming address in case of lb, sb, lbu, lhu
write_op : out std_logic; -- write signal to the memory
read_op : out std_logic; -- read signal to the memory
mem_address : out std_logic_vector(31 downto 0); -- physical address to memory
mem_data : out std_logic_vector(31 downto 0); -- data to written in the right format
write_byte : out std_logic -- Inform DRAM that we want to write a byte
);
end mmu_in_dram;
------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------
architecture behavioral of mmu_in_dram is
begin
-----------------------
-- Name: Comb Logic
-- Type: Combinational
-- Purpose: Implement
-- the combinational
-- logic of the MMU
-----------------------
comb_logic:process(mem_op, aligned_address, data)
begin
case mem_op is
when "000100" => -- lw
-- check address alignement
if (aligned_address(1 downto 0) = "00") then
unaligned <= '0';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0'); -- not used here
else
-- raise exception
unaligned <= '1';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
end if;
when "000010" => -- lhu2
-- check address alignement
if (aligned_address(0) = '0') then
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
write_byte <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0'); -- not used here
else
unaligned <= '1';
nibble <= "00";
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
end if;
when "000001" => -- lb
-- unaligned access are allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
when "001000" => -- lbu
-- unaligned access are allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
when "010000" => -- sw
-- check for alignement
if (aligned_address(1 downto 0) = "00") then
unaligned <= '0';
nibble <= "00";
write_op <= '1';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= data;
write_byte <= '0';
else
-- raise exception, write is not performed
unaligned <= '1';
nibble <= "00";
write_op <= '0';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
end if;
when "100000" => -- sb
-- unaligned access is allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '1';
write_byte <= '1';
read_op <= '0';
mem_data(7 downto 0) <= data(7 downto 0);
mem_data(31 downto 8) <= (others => '0');
mem_address <= "00" & aligned_address(31 downto 2);
when others =>
unaligned <= '0';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '0';
mem_data <= (others => '0');
mem_address <= (others => '0');
end case;
end process;
end architecture;
| mit | 662a984e1e6e1c19879e49da66662f63 | 0.466132 | 3.495327 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/menu_bg/menu_bg_sim_netlist.vhdl | 1 | 126,982 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:26 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/menu_bg/menu_bg_sim_netlist.vhdl
-- Design : menu_bg
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_bindec : entity is "bindec";
end menu_bg_bindec;
architecture STRUCTURE of menu_bg_bindec is
begin
\/i_\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end menu_bg_blk_mem_gen_mux;
architecture STRUCTURE of menu_bg_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I4 => sel_pipe_d1(0),
O => douta(7)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I4 => sel_pipe_d1(0),
O => douta(8)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I4 => sel_pipe_d1(0),
O => douta(0)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I4 => sel_pipe_d1(0),
O => douta(1)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I4 => sel_pipe_d1(0),
O => douta(2)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I4 => sel_pipe_d1(0),
O => douta(3)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I4 => sel_pipe_d1(0),
O => douta(4)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I4 => sel_pipe_d1(0),
O => douta(5)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I4 => sel_pipe_d1(0),
O => douta(6)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end menu_bg_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of menu_bg_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0200000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"1000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"000000000E000000000000000000000000000000000000000000000000000000",
INIT_0D => X"00000000000000000000300000000000000000000000001C0000000000000000",
INIT_0E => X"0C00000000000000000000000000000400000000000000000000000000000000",
INIT_0F => X"0000000000007000000000000000000000000038000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000040000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"8000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000028000000000000000000000008000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000004000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000040000",
INIT_19 => X"0800000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0080200000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000040000000000020000000000000000000000000000000000000",
INIT_1C => X"00000000000080000000000000008004000000000000000000000A0000000000",
INIT_1D => X"0000000000000200000000000000000000000000000000001000000000000001",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000002000",
INIT_1F => X"0000000008000000010000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000004000040000000000000000000000000000000000000",
INIT_21 => X"000000A000000000001000000000000000000000000000000000000000080000",
INIT_22 => X"0000000000000000000000000000000000000000000000020000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000040000",
INIT_24 => X"0000000000000000000400020000000000000000000000000000000000000000",
INIT_25 => X"0000000001400000000000000000000000010000000000000000000004000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0080000000000000000000000000000000000000000000000000800000000000",
INIT_28 => X"0000000000000800000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"00000000000000000000000000000000000000C3000000080001000000000000",
INIT_4A => X"0000040200000000000000000000000000000000000000000020000000030300",
INIT_4B => X"0000003000000000000120000000000000000000000000000000000000020001",
INIT_4C => X"000000000000000C000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000003000000000000000000000000000000000000",
INIT_4E => X"000000000000000000000000000000000000000C100004000000000000000000",
INIT_4F => X"0000400000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000040000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000010000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000010000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"00000000000000000000000C0000000000000000000000000200000000000000",
INITP_05 => X"00000007E0000000000000000000000000F00000000000000000000000003800",
INITP_06 => X"0000F0000000000001FF8000000000700000000000003FC00000000020000000",
INITP_07 => X"FFFBF80000000003F8000001FFFFFFFE0000000001F00000000FFF07FF000000",
INITP_08 => X"1FFE0000FFFFFFF9C0000000000FFE00003FFFFFF3F00000000007F8000007FF",
INITP_09 => X"F800000000007FFF801FFFFFFFF800000000003FFF0007FFFFFFF90000000000",
INITP_0A => X"F0FFFFFFFFFFF00000000001FFFE03FFFFFFFFF80000000000FFFF807FFFFFFF",
INITP_0B => X"0000000007F87FFFFFFFFFFFE00000000007FF0FFFFFFFFFFFF00000000003FF",
INITP_0C => X"FFFFFFFFC40000000000021FFFFFFFFFFFF1800000000007C3FFFFFFFFFFFFC0",
INITP_0D => X"000000001FFFFFFFFFFE020000000000001FFFFFFFFFFF190000000000001FFF",
INITP_0E => X"81FFF8300000000000003FFFFFE1FFF8080000000000001FFFFFFFFFFC040000",
INITP_0F => X"000007FFBFFC23FFFFE00000000000074047FE11FFF8E00000000000040FC0FF",
INIT_00 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_01 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_02 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_03 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_04 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_05 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_06 => X"1A161A161A161A161A161A161616161616161616161616161616161616161616",
INIT_07 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_08 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_09 => X"1616161616161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_0A => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0B => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0D => X"161616161616161616161616161616161616161616161616161A161616161616",
INIT_0E => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0F => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_10 => X"1A161A161A161A161A161A161A161A1616161616161616161616161616161616",
INIT_11 => X"1A161A161A161A161A161A161A161A161A161A161A0020161A161A161A161A16",
INIT_12 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_13 => X"1616161616161616161616161A161A161A161A161A161A161A161A161A161A16",
INIT_14 => X"1616161616161616161616060000161616161616161616161616161616161616",
INIT_15 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_16 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_17 => X"16160000201616161616161616161616161616161616161616161616161A1616",
INIT_18 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_19 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_1A => X"1A161A161A161A161A161A161A161A161A161A1616161616161A161616161616",
INIT_1B => X"1A161A161A161A161A161A161A161A161A161A161A161A160000000016161A16",
INIT_1C => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_1D => X"1616161616161616161616161A161616161616161A161A161A161A161A161A16",
INIT_1E => X"161616161616161616161616161600000000001A161616161616161616161616",
INIT_1F => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_20 => X"1616161616161616161A16161616161616161616161616161616161616161616",
INIT_21 => X"1616161600007600000016161616161616161616161616161616161616161616",
INIT_22 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_23 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_24 => X"0016161A161A161A161A161A161A161A161A161A161A161A161616161616161A",
INIT_25 => X"161A161A161A161A161A161A161A161A161A161A161A161A161A000076760000",
INIT_26 => X"161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A",
INIT_27 => X"16161616161616161616161616161616161A161A16161616161A161A161A161A",
INIT_28 => X"1616161616161616161616161616160000007676760000001616161616161616",
INIT_29 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_2A => X"1616161616161A161616161A1616161616161616161616161616161616161616",
INIT_2B => X"16161616000000EE7676BA76000020161A161616161616161616161616161616",
INIT_2C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_2D => X"161616161A161A16161600001616161616161616161616161616161616161616",
INIT_2E => X"7676760000001616161A161A161A161A161A161A161A161A161A161616161616",
INIT_2F => X"161A161A161A161A161A161A161A161A161A161A161A161A161A0000EE767676",
INIT_30 => X"16007600001A161A161A161A161A161A161A161A161A161A161A161A161A161A",
INIT_31 => X"1616161616161616161616161616161616161A16161A1616161616161616161A",
INIT_32 => X"1616161616161616161616161616161600007676BA76BA767676000016161616",
INIT_33 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_34 => X"1616161616161616161616161616161616161616161616160076767600161616",
INIT_35 => X"001616161600007676767676767676BA76000016161A16161616161616161616",
INIT_36 => X"1616161616161616161616161616161616161616160000000000000000000000",
INIT_37 => X"161A16161A161616161A161A1616160076BA7676001616161616161616161616",
INIT_38 => X"76BA76767676767600001A1616161A161A161A161A161A161A161A161A161A16",
INIT_39 => X"161A161A161A161A000000007676767676767676767676760000000000767676",
INIT_3A => X"16161616161A0076763276760002161A161A161A161A161A161A161A161A161A",
INIT_3B => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_3C => X"767676BA7676BA7676BA7676BA76767676767676BA76BA767676BA7676767600",
INIT_3D => X"BA76767676000016461A16161616161616161616161616161616161616160076",
INIT_3E => X"161616161616161616161616161A16161A16161616161A161616161A16007676",
INIT_3F => X"7676767676BA76BA76BA767676EE7676327676BA76EE0016161A161616161616",
INIT_40 => X"1616161616161616161616161616161616161600007676767676767676767676",
INIT_41 => X"1A161A16161616161A1616161616161A161616160076767676BA767676EE0202",
INIT_42 => X"76767676AA003276767676760216161616161A161A161A161A161A161A161A16",
INIT_43 => X"1A161A161A161A161A0076767676BA76BA7676BA7676BA7676BA767676767676",
INIT_44 => X"161616161616161A1616160076BA7676767676BA7676760000161A161A161A16",
INIT_45 => X"BA76461616161A1616161616161616161616161616161616161616161A161616",
INIT_46 => X"767676BA7676767676767676767676767676BA76767676767676BA7676006676",
INIT_47 => X"1A16007676767676BA7676763276760000161616161616161616161616160000",
INIT_48 => X"1616161616161616161616161616161616161616161616161A16161A16161616",
INIT_49 => X"7676BA7676BA7676767676BA76BA76BA767676767620AA766620161616161616",
INIT_4A => X"7676BA76BA76767600001616161616161616161600767676BA767676767676BA",
INIT_4B => X"161A161A161A161A16161A161A161616161616161616161616007676BA767676",
INIT_4C => X"767676767676767676BA76BA7622002016161A16161A161A161A161A161A161A",
INIT_4D => X"BA0000AA1A161A161A16007676BA76767676BA76BA767676767676767676BA76",
INIT_4E => X"161616161616161616161A16161A161600BA767676BA76767676767676BA7676",
INIT_4F => X"7676767632006606161616161616161616161616161616161616161616161616",
INIT_50 => X"0076BA767676767676767676767676BA7676BA76767676BA7676767676767676",
INIT_51 => X"161616161616160076767676767676BA7676767676767676764600AA16161600",
INIT_52 => X"16161A16161616161616161616161616161616161616161A161616161A161616",
INIT_53 => X"76767676BA7676767676767676767676BA76BA76BA76BA767676BA767600161A",
INIT_54 => X"76BA7676BA76767676BA767676BA76EE64000000000076767676767676BA76BA",
INIT_55 => X"161A161A161A161A161A161A16161616161A161616161616161A16161A160032",
INIT_56 => X"76BA76BA76767676767676767676767676767676001616161616161A161A161A",
INIT_57 => X"7676762A640000AA327676767676BA767676BA7676767676BA7676767676BA76",
INIT_58 => X"161616161A1616161616161616161A16161616161600327676767676767676BA",
INIT_59 => X"7676767676BA767676BA767600161A1616161616161616161616161616161616",
INIT_5A => X"BA7676BA767676BA767676767676767676BA76767676767676767676BA767676",
INIT_5B => X"161A1616161616161A1616160032BA7676BA7676BA767676A06600AA32BA7676",
INIT_5C => X"767632001616161A1616161616161616161616161616161616161616161A1616",
INIT_5D => X"76BA7676BA767676767676BA7676BA76767676767676BA76BA76BA767676BA76",
INIT_5E => X"16161A16007676767676767676600200EE767676767676767676767676767676",
INIT_5F => X"161A161A161A161A161A161A161A161A161A161616161A161616161616161616",
INIT_60 => X"BA76767676767676BA7676BA76767676767676767676767676BA001616161616",
INIT_61 => X"7632460022EE76BA7676BA7676BA7676BA767676BA7676767676767676BA7676",
INIT_62 => X"16161616161616161616161616161616161616161A16161A16161600007676BA",
INIT_63 => X"76767676767676767676BA32000000767600161A1616161A1616161616161616",
INIT_64 => X"767676767676767676BA767676BA767676BA7676767676767676BA767676BA76",
INIT_65 => X"1A161A1616161A16161616161616161616168E1600AA76460000007676BA7676",
INIT_66 => X"76760000EE33EEEEEE0016161A16161616161616161616161616161616161616",
INIT_67 => X"767676767676BA7676767676BA7676BA767676BA76767676BA7676BA76BA76BA",
INIT_68 => X"161A16161A16161A161A16002000000000006676767676BA7676BA7676BA7676",
INIT_69 => X"0016161616161616161A161A161A161A161A161A161A16161616161A16161616",
INIT_6A => X"76BA767676767676767676767676767676767676767676760000007777AA0076",
INIT_6B => X"16160000000000000000667676767676767676767676767676BA767676767676",
INIT_6C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_6D => X"7676BA7676BA7676BA76767676767600000066EE460076001A16161A16161A16",
INIT_6E => X"00000076BA3276BA767676BA7676BA767676BA767676BA76767676BA767676BA",
INIT_6F => X"16161616161A161A1616161A16161616161A16161A1616161616000000000000",
INIT_70 => X"76BA76BA76760000000000000076001616161616161616161616161616161616",
INIT_71 => X"BA76767676767676767676BA7676767676767676BA7676767676767676767676",
INIT_72 => X"1A1616161616161A16161616161A161A16161600000000000000007676767676",
INIT_73 => X"00000000760016161A16161A16161A161A161A161A161A161A161A1616161616",
INIT_74 => X"7676767676BA76BA767676000000007676BA767676BA767676767676BA000000",
INIT_75 => X"161A1616161616161A1616000000000000007676BA7676767676BA7676BA7676",
INIT_76 => X"1616161616161616161616161616161616161616161616161616161A16161616",
INIT_77 => X"7600004666AA00767676BA767676767676767676760000000000767600161616",
INIT_78 => X"161616000076AA00000000EE7676767676760000000000007676767676767676",
INIT_79 => X"161616161616161616161A161A1616161A16161A161616161616161616161616",
INIT_7A => X"7676767676BA76BA76BA7676760000007676BAEE001A16161A16161A16161616",
INIT_7B => X"EE76000000000000007600EEEE767676BA76BA76767676000000EEBBEE000076",
INIT_7C => X"16161616161A161616161616161A161A16161A161A1616161A16161600767632",
INIT_7D => X"76767676767676767676760000161616161616161A161A161A161A161A161A16",
INIT_7E => X"76007676BA767676767676BA76BA000000AA77EE000076BA767676BA76767676",
INIT_7F => X"161616161616161616161616161A1616161A16160076BA767676767676767676",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"E1F9E0000000000007FEFFF00FFFFC40000000000007FF7FF807FFFF00000000",
INITP_01 => X"000FF7FFC1FF8FCFC0000000000007FBFFE07FC3E7E0000000000007FDFFE01F",
INITP_02 => X"3E0000000000003FDFFFFFFFF99F0000000000001FEFFFFFFFFF9F8000000000",
INITP_03 => X"F07C7C7F0F7F00000000000001FC7F1C7FE0BF38000000000000FF3FC07FFF07",
INITP_04 => X"00000000001F81F3FDFFCDFF0000000000000FE0F9FEFFCEFFC0000000000007",
INITP_05 => X"DFCFFFFFF00000000000002C01CFF7FFCFF80000000000001C01E7FBFF8BFE00",
INITP_06 => X"000000007801C07FFFFFF00000000000003003CF1FFFFFD00000000000003801",
INITP_07 => X"FFFFFFC0000000000000B81E7FFFFFFFE00000000000007C0CC3FFFFFFE00000",
INITP_08 => X"00000FA1FFFFFFFFFF80000000000003D87FFFFFFFFFC0000000000001F81F3F",
INITP_09 => X"FFFE0000000000007607FFFFFFFFFF0000000000003F83FFFFFFFFFF80000000",
INITP_0A => X"01603FFF7FFFEFFC000000000000F01FFFFFFFF7FE000000000000FC0FFFFFFF",
INITP_0B => X"60000000000003807FFEFFFFBFB0000000000003403FFEFFFFDFD80000000000",
INITP_0C => X"C0FFFDFFFDFB8000000000000782FFFDFFFEFEC0000000000007827FFDFFFF7E",
INITP_0D => X"00000000001F31FFFBFFEFEF8000000000000F90FFFBFFFBF780000000000002",
INITP_0E => X"1FF3FF1EFF8000000000001CFFFFE9FF3F7FC000000000001E7FFFF3FF9FBF80",
INITP_0F => X"0000000031FFCFCFFF07FE00000000000039FF9FE7FE2DFF00000000000018FE",
INIT_00 => X"4600000000161A16161A161616161616161616161616161A1616161616161616",
INIT_01 => X"76767676760000000000000000767676BA76767676767676BA76BA767676BA76",
INIT_02 => X"16161616161616161616161A007676BA76BA76BA76BA76760076767676BA7676",
INIT_03 => X"16161616161616161616161616161616161A1616161A1616161A161616161A16",
INIT_04 => X"00000000767676767676767676BA7676767676BA767600206060600000161616",
INIT_05 => X"1A161616003276767676767676BA760076BA7676767676BA7676767600000000",
INIT_06 => X"161A161A16161A1616161A161616161616161A161616161A161A1616161A1616",
INIT_07 => X"7676BAEE6600AA76767676763200A0606060600016161A16161A161A161A161A",
INIT_08 => X"767676767676007676767676BA76767676BA76000000000000000076BA7676BA",
INIT_09 => X"16161616161616161616161A1616161616161A16161616161616161600767676",
INIT_0A => X"767676EE00606060A06060001616161616161616161616161616161616161616",
INIT_0B => X"BA767676767676BA767676000000000000767676767676767676000000AABA76",
INIT_0C => X"161616161616161616161616161A16161A16161602BA76BA7676BA7676007676",
INIT_0D => X"60600016161A1616161616161616161616161A1616161A1616161A1616161A16",
INIT_0E => X"7676EE000000007676BA7676BA7676BA76AA4620767676BA7676AA0060A06060",
INIT_0F => X"16161A1616161616161A1600767676767676767600BA767676BA7676BA767676",
INIT_10 => X"161A161A161A161A1616161A1616161A161616161616161A16161A161A161A16",
INIT_11 => X"76767676767676767676BA76767632BA76EE0060606060A0600016161616161A",
INIT_12 => X"161600767676BA7676BA7600767676767676767676767676BA76767676767676",
INIT_13 => X"16161616161616161616161616161616161616161616161A161616161A161616",
INIT_14 => X"767676BA7600AA76BA00206060206060001A16161A1616161616161616161616",
INIT_15 => X"767600767676BA7676BA7676767632327676BA7676BA7676BA767676BA7676BA",
INIT_16 => X"1616161A1616161A16161616161616161616161616161A16160076BA76767676",
INIT_17 => X"AA2060A0606060001616161616161616161616161616161A1616161A1616161A",
INIT_18 => X"7676AA2000200020EE7676767676767676BA7676767676760000000000767676",
INIT_19 => X"1A161A161616161A161616161A161600767676767676BA76000076BA76767676",
INIT_1A => X"161A16161A161A161A161A161A1616161A1616161A161616161616161A161616",
INIT_1B => X"66BA3276BA7676767676760000000060600076767676767666006060A0001616",
INIT_1C => X"1A161616161600767676BA76767600160076767676BA3276000060606020A000",
INIT_1D => X"1616161616161616161616161616161616161616161616161616161A16161616",
INIT_1E => X"EE0000006060A02000767676BA76BA76AA000000000616161616161616161616",
INIT_1F => X"7676767600161616007676767676AA00E060A06060A0A6206676767676BA7676",
INIT_20 => X"1A1616161A1616161A1616161A1616161616161A161616161A161616003276BA",
INIT_21 => X"76BA3276767676BA7676001616161A16161A161616161616161616161A161616",
INIT_22 => X"76BA7676BA6400A0606020606060200076BA7676767676BA7676000020606000",
INIT_23 => X"161A1616161A161A161616161A161616161A1600BA76767676BA7600161A1600",
INIT_24 => X"EE00161A1616161616161A161A161A161A161616161A1616161A161616161616",
INIT_25 => X"60A06060606000327676767676BA767676760060606000767676767676767676",
INIT_26 => X"1616161616161616161600767676763276001616161600767676767600A06060",
INIT_27 => X"1616161616161616161A16161616161616161616161616161616161616161616",
INIT_28 => X"BA76BA76767676BA76EE00A060007676BA76BA767676760016161616161A1616",
INIT_29 => X"16160076BA32E82000161A1616160076BA767620606020606060A02020003276",
INIT_2A => X"16161616161A1616161A1616161A1616161A161616161A16161A16161A161616",
INIT_2B => X"7676000076BA767676763276BA00161A1616161616161A161616161616161616",
INIT_2C => X"1616161A1600EE7676764660A060A060606060200032767676767676767676BA",
INIT_2D => X"1616161616161A161616161A1616161616161616161A161A1600BAE820326000",
INIT_2E => X"76BA7676001616161A161A161616161A161A161A161A161A16161A1616161A16",
INIT_2F => X"BA7620602060606060A0E00076BA7676767676BA76767676BA76767676767676",
INIT_30 => X"1A16161616161A16161A1616161616161600207660E00000161616161600EE76",
INIT_31 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_32 => X"6420AA767676BA76BA767676767676767676BA7676BA76767676007600161616",
INIT_33 => X"161616161616161600EE2032E8AA200016161A160A00767676BA206060A06060",
INIT_34 => X"1616161616161A16161A1616161A161616161A16161616161616161A16161616",
INIT_35 => X"7676BA7676BA7676767676767676BA767676763200161616161A161A16161616",
INIT_36 => X"0032603260A622001616161A000000767676A0A0E020E0606076BA7676767676",
INIT_37 => X"16161616161616161616161A16161A161A161616161A16161A161A161A161616",
INIT_38 => X"76BA76767676767676BA760000161A1616161616161A161A161A161A16161616",
INIT_39 => X"161616007676000076766000A0A076767676767676767676767676767676BA76",
INIT_3A => X"1616161616161616161616161616161616161616161A16120020326032202000",
INIT_3B => X"767676001616161616161A16161616161616161616161A16161A16161A161616",
INIT_3C => X"007676BA76BA3276BA7676BA76BA76BA7676BA76767676767676BA767676BA76",
INIT_3D => X"1A161A16161A1616161616161616160032AA203260EE001A1600EE76BA767600",
INIT_3E => X"16161616161616161616161A16161616161616161616161A1616161A16161616",
INIT_3F => X"76327676767676767676767676BA7676767676BA76767676BA76001616161A16",
INIT_40 => X"1A1616161A1600206032203220A6001600EEEE7676BA76760000767676767676",
INIT_41 => X"1A161616161A16161A161616161616161A161616161A16161616161616161A16",
INIT_42 => X"76BA76767676BA767676767676BA76767676001A1616161A16161A161A161A16",
INIT_43 => X"3220EE7620001600EE3276767676767676BA7676BA7676BA767676767676BA76",
INIT_44 => X"1A1616161616161616161A1616161616161A161616161616161A161616003220",
INIT_45 => X"76767676767676BA760016161616161616161616161616161616161616161616",
INIT_46 => X"76767676BA76BA76767676767676767676BA76BA7676767676BA7676767676BA",
INIT_47 => X"16161616161A161616161A1616161616161616003220322076E0200016160076",
INIT_48 => X"7600161A1616161A1616161616161616161A16161A161616161616161A161616",
INIT_49 => X"BA7676BA7676BA767676767676BA76767676BA7676767676BA76BA7676767676",
INIT_4A => X"161616161A161A161600322032603220324600161600767676BA767676767676",
INIT_4B => X"1A161A161A161A1616161616161616161A161616161A161A16161A1616161A16",
INIT_4C => X"7676767676767676767676BA76763276767676BA767676BA001616161A161616",
INIT_4D => X"00207620EE2032A00016161A0076BA7676767676767676767676767676767676",
INIT_4E => X"1A16161A161A16161616161616161616161616161616161616161A161616161A",
INIT_4F => X"76767676BA76327676767676BA76760016161616161616161616161616161616",
INIT_50 => X"1616160076767676BA76BA76BA767676BA3276BA7676BA76BA767676BA7676BA",
INIT_51 => X"161A161616161A16161A1616161A161A16161616161616003220322076600016",
INIT_52 => X"76767676767676001A1616161A16161616161616161616161616161616161616",
INIT_53 => X"7676767676BA7676767676767676767676BA7676767676767676767600BA76BA",
INIT_54 => X"16161A16161616161616161A1616160032203220A016161A1616007676767676",
INIT_55 => X"161A1616161A161A161A161A161A16161A161616161616161616161A16161616",
INIT_56 => X"007676BA7676767676767676BA767676BA76320076767676BA76767676760016",
INIT_57 => X"1A1616161A160060A66032001A16161616002ABA76BA7676767676767676BA76",
INIT_58 => X"1616161616161616161A16161A1616161A16161616161A161616161616161616",
INIT_59 => X"76BA767676BA7676763200767676767676760076BA0016161616161616161616",
INIT_5A => X"EE20001616161A0060AA76767676BA76BA7676767676320076767676BA767676",
INIT_5B => X"16161616161616161616161A1616161616161A161A1616161616161616163260",
INIT_5C => X"320076BA767676BA76002A76001616161A16161616161616161616161A161616",
INIT_5D => X"607676767676767676BA7676767676007676767676BA767676767676767676BA",
INIT_5E => X"1A161616161A161A16161616161A16161A1616161600322032A62016161620A0",
INIT_5F => X"20767600161A1616161A161A161A161A161A1616161A16161A161616161A1616",
INIT_60 => X"7676BA76BA760032BA76767676BA767676BA76767676763200767676BA7632EE",
INIT_61 => X"1616161616161616161A16160020326032E0201666602A666676BA7676767676",
INIT_62 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_63 => X"76BA76767676BA767676BA76BA76320076767676767676007676001616161616",
INIT_64 => X"161616160032203260EEA000006660202A767676BA76BA7676767676BA2A0076",
INIT_65 => X"161A1616161A16161A1616161A1616161A161A16161616161A161A16161A1616",
INIT_66 => X"7676767676320076BA767676BA0076762A201616161A16161616161616161616",
INIT_67 => X"A03200004660A0667676BA76767676767676767676BA00767676767676767676",
INIT_68 => X"16161616161A16161616161A161A16161616161616161616161A161600EE20A6",
INIT_69 => X"76BA762A0076BA767600001616161A161A161A161A161A1616161A1616161616",
INIT_6A => X"7676767676BA76BA7676BA7676003276BA7676BA7676BA767676767676007676",
INIT_6B => X"1616161616161616161A16161A161A1616161600207632203260AA76AA0000AA",
INIT_6C => X"76000016161616161616161616161616161616161A161616161A161616161616",
INIT_6D => X"767676767600767676767676767676BA76BA7600767676767676760076767676",
INIT_6E => X"16161616161616161A160032206032200022BA76EE00003276BA767676767676",
INIT_6F => X"161616161616161A161616161616161616161616161A161A1616161616161A16",
INIT_70 => X"7676BA767676767676000076BA76BA7676202A76BA7676BA76EE001A16161616",
INIT_71 => X"161600203220762200767676767676767676BA76767676BA7676BA76000076BA",
INIT_72 => X"1A16161A1616161616161A1616161616161A161A16161616161A161616161616",
INIT_73 => X"00007676763276320076BA7676767676767600161A161A161A161A161A161616",
INIT_74 => X"7676BA767676BA76767676BA76767676767676EE7600E8BA767676BA76767676",
INIT_75 => X"161616161616161A1616161616161A1616161A161A1616161A16003220326020",
INIT_76 => X"76767676BA7676BA760016161616161616161616161616161616161616161A16",
INIT_77 => X"0000E8BA7676BA7676BA76762220767676767676BA7676760000EE7676767600",
INIT_78 => X"16161A161616161616161616161A1616161200322060004676767676767676EE",
INIT_79 => X"0246161616161616161616161A1616161A1616161616161A16161A161A161616",
INIT_7A => X"76BA7600007676BA7676767676BA76AA0000BA00767600BA7676767676767676",
INIT_7B => X"161616161616161A1600322032A000327676BA7676BA7676BA20003276767676",
INIT_7C => X"161A1616161A16161616161616161616161616161616161616161A1616161A16",
INIT_7D => X"76BA767676327632000000000076767676BA7676BA76760002020000161A161A",
INIT_7E => X"16003260A666607676767676767676767676000032BA76767676000076767676",
INIT_7F => X"161616161A16161A1616161A16161A161616161A161616161A161A1616161616",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFFFEF80000000000013FFC07FFFFFF88000000000000BFFE61FFFFFFC0000",
INITP_01 => X"000000E7FFFFFFFFFFFC00000000000047FFCFFFFFFFFF80000000000003FFE1",
INITP_02 => X"FFF000000000000001FFF87FFFFFF800000000000000FFFEFFFFFFFE00000000",
INITP_03 => X"0001FF56FE0FFF0000000000000001FFA37FFFFFC000000000000001FFE53FFF",
INITP_04 => X"0000000000000003FDFB0003F80000000000000003FEBDE007FE000000000000",
INITP_05 => X"03EC000000400000000000000003F6000001E00000000000000003FBC00001F0",
INITP_06 => X"00000000000001A0000000000000000000000003D80000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000003000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"76767676767676BA76767676767600000000000016161616161616161616161A",
INIT_01 => X"7676BA7676BA767676767600EE7676EE0000AA76BA76767676767676BA763276",
INIT_02 => X"16161616161616161616161616161A161616161A1616161A000000A020A03276",
INIT_03 => X"76BA7676BA00E82076000000161616161A1616161A1616161616161616161616",
INIT_04 => X"7676EE0000000000002A767676BA7676BA76767676BA767676BA76BA76767676",
INIT_05 => X"1A16161A16161616161616161A16161600000032E00276BA76767676767676BA",
INIT_06 => X"76AA0016161A1616161A161616161616161A16161A16161A16161A16161A1616",
INIT_07 => X"76BA767676767676BA7676767676BA76767676BA767676767676760076BA7676",
INIT_08 => X"1616161616161616160000A022A0767676BA7676BA76767676BA76000000EE32",
INIT_09 => X"161616161A16161616161616161616161616161616161616161616161616161A",
INIT_0A => X"7676BA767676767676767676BA76BA7676767676767676BA76001A1616161616",
INIT_0B => X"0076AA2000767676767676767676BA767676AAAA32BA76BA76767676BA767676",
INIT_0C => X"1A1616161A16161A16161A16161A16161A1616161A1616161A1616161A161A16",
INIT_0D => X"76767676767676767676762ABA76000016161616161A1616161A161616161616",
INIT_0E => X"BA7676767676767676BA76767676767676BA767676767676BA7676767676BA76",
INIT_0F => X"1616161616161616161A161616161616161A16161616160032762A22AA767676",
INIT_10 => X"6600200000001616161A161616161A161616161616161616161A161616161616",
INIT_11 => X"7676BA767676BA76767676BA76BA76767676BA76767676BA7676767676BA76EE",
INIT_12 => X"1616161A161616161616161616160000BA76BA7676BA767676BA7676BA76BAE8",
INIT_13 => X"161A1616161616161A161616161A16161616161A1616161A16161A16161A1616",
INIT_14 => X"76767676767676767676BA7676767676BA76BA7676EE000020200020161A1616",
INIT_15 => X"161A161A16160032767676767676767676767676760020000076767676767676",
INIT_16 => X"1616161616161616161616161A161616161616161616161616161616161A1616",
INIT_17 => X"76767676BA767676767676326000202000001616161616161616161A16161616",
INIT_18 => X"7676BA7676BA767676BA76000032007600EE76BA7676BA76BA7676767676BA76",
INIT_19 => X"1A16161616161A16161A1616161A161A16161A1616161A161616161616160076",
INIT_1A => X"767600002060600016161A16161A1616161A16161A1616161A16161616161A16",
INIT_1B => X"76007600EE007676007676767676767676BA76BA767676767676BA7676767676",
INIT_1C => X"16161A1616161616161616161616161616161A161600EEBA767676767676BA76",
INIT_1D => X"1616161616161A1616161616161A161616161A16161616161616161616161616",
INIT_1E => X"7676BA76767676EEAAEEEEEE76BA76BA76767676BA76BA76EE00200020200016",
INIT_1F => X"161A1616161A161A1616161A1600EE767676BA7676767676007600320032BA00",
INIT_20 => X"16161616161616161616161A1616161A161A1616161A16161616161616161A16",
INIT_21 => X"000000606632767676767676767676200020202000161A16161A161616161616",
INIT_22 => X"16161616160076BA7676767676BA7600BAE8BA7676760076767676EEA0000000",
INIT_23 => X"161616161616161616161A1616161A161616161A1616161616161A1616161616",
INIT_24 => X"76BA767676EE0060A02000661616161616161A16161A16161A161A1616161616",
INIT_25 => X"7676BA7676760076BA7676767600BA76A0000000206020202060000000A02A76",
INIT_26 => X"16161616161616161A16161616161A16161616161616161A16161A1616007676",
INIT_27 => X"0016161A16161A161616161616161616161616161A161616161A16161A161616",
INIT_28 => X"7632002000AA46002020202020002020202020200020AA767676BA7666002000",
INIT_29 => X"1616161A1616161616161A161616161616161616160076BA7676767676007676",
INIT_2A => X"161A16161A161616161A161616161A1616161616161A161616161A1616161A16",
INIT_2B => X"2020202020202020202060200000002A76767660202000201616161616161616",
INIT_2C => X"1616161A16161A16161A16161600767676BA76760076BAE82000000000002060",
INIT_2D => X"16161616161616161A16161616161A161616161A161616161A161616161A161A",
INIT_2E => X"0000000000002066EE2A00200000161A16161A1616161A161616161616161A16",
INIT_2F => X"16161A161600767676BA76007676200020000000002020000060206000602020",
INIT_30 => X"161A161616161A16161616161616161616161616161616161616161616161616",
INIT_31 => X"00600000161616161616161A161616161A16161A161616161616161616161616",
INIT_32 => X"767600BA32002020200000206000202020202020000000001616161616161600",
INIT_33 => X"16161A16161A16161A161A16161616161A16161A16161A161616161A16007676",
INIT_34 => X"16161616161616161616161616161A161616161A161A161616161A161616161A",
INIT_35 => X"2020202020600020000000161616161616161A1616161616161616161616161A",
INIT_36 => X"1616161A161A16161616161616161616161616161600EE76760076A000202020",
INIT_37 => X"1A16161A16161616161616161616161616161616161616161616161616161616",
INIT_38 => X"161616161A161A161616161A1616161A16161A161A16161616161A161A161616",
INIT_39 => X"1616161A16161A1616161A16160076BA00460020202000000020602020000016",
INIT_3A => X"161616161A161A16161A16161A16161A16161A16161A1616161616161616161A",
INIT_3B => X"161616161A161616161616161616161A16161616161A161616161616161A1616",
INIT_3C => X"1616161A1600002200000020602000200000001616161616161A161616161A16",
INIT_3D => X"1616161616161616161616161616161A16161616161616161A1616161616161A",
INIT_3E => X"161616161A16161616161616161616161A16161616161616161A161616161616",
INIT_3F => X"20002020200000166616161616161A1616161616161616161A1616161616161A",
INIT_40 => X"161A16161A1616161A161A161A1616161616161A161616161616161616000000",
INIT_41 => X"161A1616161A1616161A16161616161616161616161A16161A16161A16161A16",
INIT_42 => X"1A161A1616161616161A161616161A16161616161A1616161A1616161616161A",
INIT_43 => X"16161616161616161A1616161616161A1616161616AA00006060200000161616",
INIT_44 => X"16161A1616161A16161A16161616161616161616161616161616161616161616",
INIT_45 => X"16161A16161616161A16161616161616161A16161A16161616161A1616161616",
INIT_46 => X"16161A161A1616161A161A1616600000202000166A1A16161616161A16161A16",
INIT_47 => X"16161A16161A16161A16161A16161A16161A16161A1616161616161A161A1616",
INIT_48 => X"1A1616161A161616161616161616161616161616161A16161616161616161616",
INIT_49 => X"1616161A160020600020161A16161616161616161616161616161A1616161616",
INIT_4A => X"16161616161616161616161616161A161A161616161616161616161616161616",
INIT_4B => X"1A1616161A161A1616161A1616161A1616161616161A16161616161616161616",
INIT_4C => X"16161616161A161A16161A1616161A16161616161A161616161A1616161A1616",
INIT_4D => X"1A16161A1616161616161616161A161A16161616161A16161616161616000046",
INIT_4E => X"161616161616161A1616161616161A16161A16161A16161A16161A16161A1616",
INIT_4F => X"1616161A1616161616161A16161616161616161616161616161A16161616161A",
INIT_50 => X"1A161A16161616161A161A1616161A161616161616161616161A161616161616",
INIT_51 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_52 => X"161616161A1616161A1616161A1616161616161616161616161A161616161616",
INIT_53 => X"161616161616161A161A1616161616161616161616161A1616161616161A161A",
INIT_54 => X"161A16161A16161A16161A16161A16161A16161A161A16161616161616161616",
INIT_55 => X"161616161616161616161616161616161616161616161616161A1616161A1616",
INIT_56 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_57 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_58 => X"0000000000000000000000000000001616161616161616161616161616161616",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end menu_bg_blk_mem_gen_prim_width;
architecture STRUCTURE of menu_bg_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.menu_bg_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \menu_bg_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\menu_bg_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \menu_bg_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\menu_bg_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \menu_bg_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\menu_bg_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \menu_bg_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \menu_bg_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \menu_bg_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \menu_bg_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\menu_bg_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end menu_bg_blk_mem_gen_generic_cstr;
architecture STRUCTURE of menu_bg_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.menu_bg_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena_array(0) => ena_array(0)
);
\has_mux_a.A\: entity work.menu_bg_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[2].ram.r_n_8\,
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(11 downto 3)
);
\ramloop[0].ram.r\: entity work.menu_bg_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\menu_bg_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\menu_bg_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[2].ram.r_n_0\,
\douta[10]\(6) => \ramloop[2].ram.r_n_1\,
\douta[10]\(5) => \ramloop[2].ram.r_n_2\,
\douta[10]\(4) => \ramloop[2].ram.r_n_3\,
\douta[10]\(3) => \ramloop[2].ram.r_n_4\,
\douta[10]\(2) => \ramloop[2].ram.r_n_5\,
\douta[10]\(1) => \ramloop[2].ram.r_n_6\,
\douta[10]\(0) => \ramloop[2].ram.r_n_7\,
\douta[11]\(0) => \ramloop[2].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\menu_bg_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\menu_bg_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[4].ram.r_n_0\,
\douta[10]\(6) => \ramloop[4].ram.r_n_1\,
\douta[10]\(5) => \ramloop[4].ram.r_n_2\,
\douta[10]\(4) => \ramloop[4].ram.r_n_3\,
\douta[10]\(3) => \ramloop[4].ram.r_n_4\,
\douta[10]\(2) => \ramloop[4].ram.r_n_5\,
\douta[10]\(1) => \ramloop[4].ram.r_n_6\,
\douta[10]\(0) => \ramloop[4].ram.r_n_7\,
\douta[11]\(0) => \ramloop[4].ram.r_n_8\,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_top : entity is "blk_mem_gen_top";
end menu_bg_blk_mem_gen_top;
architecture STRUCTURE of menu_bg_blk_mem_gen_top is
begin
\valid.cstr\: entity work.menu_bg_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end menu_bg_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of menu_bg_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.menu_bg_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of menu_bg_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of menu_bg_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of menu_bg_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of menu_bg_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of menu_bg_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of menu_bg_blk_mem_gen_v8_3_5 : entity is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of menu_bg_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of menu_bg_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of menu_bg_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of menu_bg_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.22775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of menu_bg_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of menu_bg_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of menu_bg_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of menu_bg_blk_mem_gen_v8_3_5 : entity is "menu_bg.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of menu_bg_blk_mem_gen_v8_3_5 : entity is "menu_bg.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 11025;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 11025;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of menu_bg_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of menu_bg_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of menu_bg_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of menu_bg_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of menu_bg_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 11025;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 11025;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of menu_bg_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of menu_bg_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of menu_bg_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of menu_bg_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of menu_bg_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of menu_bg_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of menu_bg_blk_mem_gen_v8_3_5 : entity is "yes";
end menu_bg_blk_mem_gen_v8_3_5;
architecture STRUCTURE of menu_bg_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.menu_bg_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity menu_bg is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of menu_bg : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of menu_bg : entity is "menu_bg,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of menu_bg : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of menu_bg : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end menu_bg;
architecture STRUCTURE of menu_bg is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.22775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "menu_bg.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "menu_bg.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 11025;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 11025;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 11025;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 11025;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.menu_bg_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 896ce2dc0f65fc29a901f5735b047db7 | 0.720653 | 3.321267 | false | false | false | false |
huukit/logicsynth | excercises/vhd/piano.vhd | 1 | 10,301 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Bonus 5
-- Project :
-------------------------------------------------------------------------------
-- File : piano.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 10.2.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pieno synth player (sequencer actually).
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 10.02.2016 1.0 huukit Created from synthesizer.vhd.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity piano is -- synthesizer generics and ports
-- generics
generic(
clk_freq_g : integer := 18432000;
melody_clk_div : integer := 18432000 / 2; -- Speed of melody.
sample_rate_g : integer := 48000;
data_width_g : integer := 16;
n_keys_g : integer := 4
);
-- ports
port(
clk : in std_logic;
rst_n : in std_logic;
keys_in : in std_logic_vector(n_keys_g - 1 downto 0);
melody_in : in std_logic;
aud_bclk_out : out std_logic;
aud_data_out : out std_logic;
aud_lrclk_out : out std_logic
);
end piano;
architecture rtl of piano is -- Defining used signals and components
component wave_gen is
generic(
width_g : integer; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end component;
component multi_port_adder is
generic(
operand_width_g : integer := 16; -- Specify default value for both.
num_of_operands_g : integer := 4
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
operands_in : in std_logic_vector((operand_width_g * num_of_operands_g) - 1 downto 0); -- Operand inputs
sum_out : out std_logic_vector(operand_width_g - 1 downto 0) -- Calculation result.
);
end component;
component audio_ctrl is
generic(
ref_clk_freq_g : integer := 18432000; -- Reference clock.
sample_rate_g : integer := 48000; -- Sample clock fs.
data_width_g : integer := 16 -- Data width.
);
port(
clk : in std_logic; -- Main clock.
rst_n : in std_logic; -- Reset, active low.
left_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, left.
right_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, right.
aud_bclk_out : out std_logic; -- Audio bitclock.
aud_data_out : out std_logic; -- Audio data.
aud_lrclk_out : out std_logic -- Audio bitclock L/R select.
);
end component;
type wavegen_output_arr is array (0 to n_keys_g - 1) -- Define an array type to hold
of std_logic_vector(data_width_g - 1 downto 0); -- wavegen output values,
-- so they can be easily modified
constant melody_len_c : integer := 32; -- Define the array and length to hold the
type melody_arr is array (0 to melody_len_c - 1) -- melody that is supposed to play.
of std_logic_vector(n_keys_g -1 downto 0);
constant melody_data_c : melody_arr :=( "1110", -- Melody data, not very musical. :)
"1101",
"1011",
"0111",
"1011",
"1101",
"1110",
"1100",
"1001",
"0011",
"1001",
"1100",
"1010",
"0101",
"0111",
"1101",
"1011",
"1110",
"0111",
"1011",
"1101",
"1110",
"1110",
"1101",
"1011",
"0111",
"0000",
"1111",
"1001",
"1111",
"0110",
"1111");
-- registers
signal wavegen_output_r : wavegen_output_arr;
signal adder_input_r : std_logic_vector((data_width_g * n_keys_g) - 1 downto 0);
signal adder_output_r : std_logic_vector(data_width_g - 1 downto 0);
signal aud_bclk_r : std_logic;
signal aud_data_r : std_logic;
signal aud_lrclk_r : std_logic;
signal keys_input_r : std_logic_vector(n_keys_g - 1 downto 0);
signal melody_counter_r : integer;
signal melody_clkcnt_r : integer;
constant melody_clkdiv_c : integer := melody_clk_div;
begin -- rtl
-- registers to outputs
aud_bclk_out <= aud_bclk_r;
aud_data_out <= aud_data_r;
aud_lrclk_out <= aud_lrclk_r;
-- Melody player. Reads keys, or plays the melody.
melody_play : process(clk, rst_n)
begin
if(rst_n = '0') then -- Reset outputs.
melody_clkcnt_r <= melody_clkdiv_c;
melody_counter_r <= 0;
keys_input_r <= (others => '1');
elsif(clk'event and clk = '1') then
if(melody_in = '0') then -- If no melody requested, use keys.
keys_input_r <= keys_in;
melody_counter_r <= 0;
else -- Else step through sequencer pattern.
keys_input_r <= melody_data_c(melody_counter_r);
if(melody_clkcnt_r = 0) then
melody_clkcnt_r <= melody_clkdiv_c;
melody_counter_r <= melody_counter_r + 1;
if(melody_counter_r = (melody_len_c - 1)) then
melody_counter_r <= 0;
end if;
else
melody_clkcnt_r <= melody_clkcnt_r - 1;
end if;
end if;
end if;
end process melody_play;
-- a process that scales wavegen output according to how many wavegenerators
-- are online. If 1 is on, output is divided by 1, 2 = 2, and so on.
-- This prevents overflow that comes from adding two signals together.
waveform_scaling : process(clk, rst_n)
-- process variables
variable temp : integer := 0;
variable divider : integer := 0;
begin
-- Only process on clock rising edge, and when NOT in reset mode
if(clk'event and clk = '1' and rst_n = '1') then -- Calculate on rising edge of clock.
divider := 0;
for I in 0 to n_keys_g - 1 loop -- calculate how many buttons are pushed
if (keys_input_r(I) = '0') then
divider := divider + 1;
end if;
end loop;
if (divider = 0) then -- failsafe to prevent div-by-0
divider := 1;
end if;
for I in 0 to n_keys_g - 1 loop -- modify wavegen outputs
temp := to_integer(signed(wavegen_output_r(I)));
temp := temp / divider;
adder_input_r((I+1)*data_width_g - 1 downto I*data_width_g) <= std_logic_vector(to_signed(temp, wavegen_output_r(I)'length));
end loop;
end if;
end process waveform_scaling;
-- instantiate as many wave generators as needed
wave_generators:
for I in 0 to n_keys_g - 1 generate
wavegen_arr : wave_gen
generic map
(
width_g => data_width_g,
step_g => 2**I
)
port map
(
clk => clk,
rst_n => rst_n,
sync_clear_in => keys_input_r(I),
value_out => wavegen_output_r(I)
);
end generate wave_generators;
i_adder : multi_port_adder
generic map
(
operand_width_g => data_width_g,
num_of_operands_g => n_keys_g
)
port map
(
clk => clk,
rst_n => rst_n,
operands_in => adder_input_r,
sum_out => adder_output_r
);
i_audio_ctrl : audio_ctrl
generic map
(
ref_clk_freq_g => clk_freq_g,
sample_rate_g => sample_rate_g,
data_width_g => data_width_g
)
port map
(
clk => clk,
rst_n => rst_n,
left_data_in => adder_output_r,
right_data_in => adder_output_r,
aud_bclk_out => aud_bclk_r,
aud_data_out => aud_data_r,
aud_lrclk_out => aud_lrclk_r
);
end rtl;
| gpl-2.0 | be8899fba700c473e85df3cbaa9ff8f1 | 0.425784 | 4.3965 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/lsu.vhd | 1 | 2,964 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
use work.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
| mit | 5b711ac8f068dc73d62ecb9f3e91b833 | 0.507085 | 3.04 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_sa_sigmadeltaDAC.vhd | 13 | 3,029 | --
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
| mit | 034bc0f7738cc427c60363db86368f58 | 0.702872 | 3.373051 | false | false | false | false |
algebrato/eldig | Sette_segmenti/sette_seg.vhd | 2 | 1,519 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sette_seg is
Port ( enable : in STD_LOGIC ;
SEG : out STD_LOGIC_VECTOR(0 to 6);
AN : out STD_LOGIC_VECTOR(3 downto 0);
CLK100M : in STD_LOGIC;
CLK_1K_O : out STD_LOGIC
);
end sette_seg;
architecture Behavioral of sette_seg is
signal N: UNSIGNED(3 downto 0);
signal NN: UNSIGNED(15 downto 0);
signal clk_1k: STD_LOGIC;
begin
--N_OUT <= STD_LOGIC_VECTOR(N);
CLK_1K_O <= clk_1k; --collego le varie scatole con i segnali
SEG(0)<='0' when N=0 or N=2 or N=3 or N>4 else '1';
SEG(1)<='0' when N=0 or N=1 or N=2 or N=3 or N=4 or N=7 or N=8 or N=9 else '1';
SEG(2)<='0' when N=0 or N=1 or N=3 or N=4 or N=5 or N=6 or N=7 or N=8 or N=9 else '1';
SEG(3)<='0' when N=0 or N=2 or N=3 or N=5 or N=6 or N=8 or N>9 else '1';
SEG(4)<='0' when N=0 or N=2 or N=6 or N=8 or N>9 else '1';
SEG(5)<='0' when N=0 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
SEG(6)<='0' when N=2 or N=3 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
AN <= "0000";
contatore_4bit:process(enable)
begin
if rising_edge(enable) then
if N=9 then N<= "0000";
else N<=N+1;
end if;
end if;
end process contatore_4bit;
--il punto e` essere in grado di modificare il duty cycle del segnale.
--Ton/(Ton+Toff)
mod_freq:process(CLK100M)
begin
if rising_edge(CLK100M) then
if NN=49999 then
NN<=(others => '0');
clk_1k <= not clk_1k;
else
NN<=NN+1;
end if;
end if;
end process mod_freq;
end Behavioral;
| gpl-3.0 | 611e85371ad0a9a28f14e623606310a8 | 0.629361 | 2.284211 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/rle_enc.vhd | 13 | 3,072 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle_enc is
generic(
data_width : integer := 32
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end rle_enc;
architecture behavioral of rle_enc is
signal count, data, rle_out_i : std_logic_vector ((data_width-1) downto 0);
signal c0, c1, c2, c3, valid, rle : std_logic;
signal state : std_logic_vector(3 downto 0);
begin
-- count repeating data
process(clock)
begin
if rising_edge(clock) then
if raw_inp_valid = '1' then
if data = raw_inp then
count <= count + 1;
else
data <= raw_inp;
count <= (others => '0');
end if;
end if;
end if;
end process;
-- previous and current data is not the same; send old data
c0 <= '1' when data /= raw_inp and count = 0 else '0';
-- start of repeating data; send current data
c1 <= '1' when data = raw_inp and count = 0 else '0';
-- end of repeating data; send count
c2 <= '1' when data /= raw_inp and count /= 0 else '0';
-- count overflow; send count
c3 <= '1' when data = raw_inp and 0 = not count else '0';
state <= c3 & c2 & c1 & c0;
rle_out_i <=
data when state = "0001" else
data when state = "0010" else
count when state = "0100" else
count when state = "1000" else
(others => 'X');
valid <=
'1' when state = "0001" else
'1' when state = "0010" else
'1' when state = "0100" else
'1' when state = "1000" else
'0';
rle <=
'1' when state = "0100" else
'1' when state = "1000" else
'0';
process(clock)
begin
if rising_edge(clock) then
if raw_inp_valid = '1' then
rle_out <= rle_out_i;
rle_out_valid <= valid;
rle_bit <= rle;
else
rle_out_valid <= '0';
rle_bit <= '0';
end if;
end if;
end process;
end behavioral;
| mit | a605f7f52c2cead9ec9db6eab0a12a8a | 0.595703 | 3.233684 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to100_dcm.vhd | 13 | 6,307 | -- file: clk_32to100_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to100_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to100_dcm;
architecture xilinx of clk_32to100_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to100_dcm,clk_wiz_v3_6,{component_name=clk_32to100_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 8,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit | 4b3efb82cc226d697724e24d25ec0fd2 | 0.575075 | 4.24428 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_250k/prom-generic-dp-32.vhd | 13 | 102,419 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(13 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(13 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport;
architecture behave of prom_generic_dualport is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 4095) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit | 346885026bea440773036e63a459d4eb | 0.50435 | 1.510471 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/Clock/example_design/Clock_exdes.vhd | 1 | 7,032 | -- file: Clock_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Clock_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1);
-- Status and control signals
LOCKED : out std_logic
);
end Clock_exdes;
architecture xilinx of Clock_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 4;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component Clock is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_100M : out std_logic;
CLK_50M : out std_logic;
CLK_25M : out std_logic;
CLK_10M : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : Clock
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_100M => clk_int(1),
CLK_50M => clk_int(2),
CLK_25M => clk_int(3),
CLK_10M => clk_int(4),
-- Status and control signals
LOCKED => locked_int);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
clk(3) <= clk_int(3);
clk(4) <= clk_int(4);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| mit | 77452be76d618ff59c7630dd9c0d687d | 0.617036 | 3.811382 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/shadow_pixel_1/synth/shadow_pixel.vhd | 1 | 14,368 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY shadow_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END shadow_pixel;
ARCHITECTURE shadow_pixel_arch OF shadow_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF shadow_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF shadow_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF shadow_pixel_arch : ARCHITECTURE IS "shadow_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF shadow_pixel_arch: ARCHITECTURE IS "shadow_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=shadow" &
"_pixel.mif,C_INIT_FILE=shadow_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=1080,C_READ_DEPTH_A=1080,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12," &
"C_WRITE_DEPTH_B=1080,C_READ_DEPTH_B=1080,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0" &
",C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5913 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "shadow_pixel.mif",
C_INIT_FILE => "shadow_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 1080,
C_READ_DEPTH_A => 1080,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 1080,
C_READ_DEPTH_B => 1080,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5913 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END shadow_pixel_arch;
| gpl-3.0 | 3fed13ffc1f58cf10f3359d7e4d4afb4 | 0.626322 | 3.026754 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/zpuino_vga_ram.vhd | 13 | 4,286 | --
-- VGA RAM for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0);
mi_addr: in std_logic_vector(14 downto 0)
);
end entity zpuino_vga_ram;
--
-- Address 0 to 15: 1st char
-- Address 16 to 31: 2st char
--
--
architecture behave of zpuino_vga_ram is
signal v_ram_0_en, v_ram_1_en: std_logic;
signal v_ram_0_data, v_ram_1_data: std_logic_vector(7 downto 0);
signal v_addrh_q: std_logic;
signal mi_ram_0_en, mi_ram_1_en: std_logic;
signal mi_ram_0_dat_o, mi_ram_1_dat_o: std_logic_vector(7 downto 0);
signal mi_addrh_q: std_logic;
signal nodata: std_logic_vector(7 downto 0) := (others => '0');
begin
-- vport enable signals
v_ram_0_en <= v_en and not v_addr(14);
v_ram_1_en <= v_en and v_addr(14);
-- vport address decode
process(v_clk)
begin
if rising_edge(v_clk) then
v_addrh_q <= v_ram_1_en;
end if;
end process;
-- vport Output select
v_data <= v_ram_0_data when v_addrh_q='0' else v_ram_1_data;
-- miport enable signals
mi_ram_0_en <= mi_en and not mi_addr(14);
mi_ram_1_en <= mi_en and mi_addr(14);
-- vport address decode
process(mi_clk)
begin
if rising_edge(mi_clk) then
mi_addrh_q <= mi_ram_1_en;
end if;
end process;
-- vport Output select
mi_dat_o <= mi_ram_0_dat_o when mi_addrh_q='0' else mi_ram_1_dat_o;
ram0: generic_dp_ram
generic map (
address_bits => 14,
data_bits => 8
)
port map (
clka => v_clk,
ena => v_ram_0_en,
wea => '0',
addra => v_addr(13 downto 0),
dia => nodata,
doa => v_ram_0_data,
clkb => mi_clk,
enb => mi_ram_0_en,
web => mi_we,
addrb => mi_addr(13 downto 0),
dib => mi_dat_i,
dob => mi_ram_0_dat_o
);
ram1: generic_dp_ram
generic map (
address_bits => 12,
data_bits => 8
)
port map (
clka => v_clk,
ena => v_ram_1_en,
wea => '0',
addra => v_addr(11 downto 0),
dia => nodata,
doa => v_ram_1_data,
clkb => mi_clk,
enb => mi_ram_1_en,
web => mi_we,
addrb => mi_addr(11 downto 0),
dib => mi_dat_i,
dob => mi_ram_1_dat_o
);
end behave;
| mit | 19cc198a7ccdf3e761dac7c258487b16 | 0.621092 | 3.072401 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpu_core_extreme_icache.vhd | 13 | 47,502 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
cache_flush: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_icache;
architecture behave of zpu_core_extreme_icache is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
component zpuino_icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(wordSize-1 downto 0);
address: in std_logic_vector(maxAddrBit downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end component;
signal cache_valid: std_logic;
signal cache_data: std_logic_vector(wordSize-1 downto 0);
signal cache_address: std_logic_vector(maxAddrBit downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_LoadStack,
State_Loadb,
State_Loadh,
State_Resync2,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Loadh,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := stackSize_bits-1;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_LSU,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
-- LSU
signal lsu_req: std_logic;
signal lsu_we: std_logic;
signal lsu_busy: std_logic;
signal lsu_data_read: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_write: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_sel: std_logic_vector(3 downto 0);
signal lsu_address: std_logic_vector(maxAddrBitIncIO downto 0);
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
--dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
--dbg_out.stacka <= std_logic_vector(exr.tos);
--dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
-- synopsys translate_off
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
-- synopsys translate_on
cache: zpuino_icache
generic map (
ADDRESS_HIGH => maxAddrBitBRAM
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => cache_flush,
-- Master wishbone interface
m_wb_ack_i => rom_wb_ack_i,
m_wb_dat_i => rom_wb_dat_i,
m_wb_adr_o => rom_wb_adr_o,
m_wb_cyc_o => rom_wb_cyc_o,
m_wb_stb_o => rom_wb_stb_o,
m_wb_stall_i => rom_wb_stall_i
);
lsu: zpuino_lsu
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_ack_i => wb_ack_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_adr_o => wb_adr_o(maxAddrBitIncIO downto 2),
wb_cyc_o => wb_cyc_o,
wb_stb_o => wb_stb_o,
wb_sel_o => wb_sel_o,
wb_we_o => wb_we_o,
req => lsu_req,
we => lsu_we,
busy => lsu_busy,
data_read => lsu_data_read,
data_write => lsu_data_write,
data_sel => lsu_data_sel,
address => lsu_address
);
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(cache_data, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(cache_data(31 downto 24));
when 1 => tOpcode := std_logic_vector(cache_data(23 downto 16));
when 2 => tOpcode := std_logic_vector(cache_data(15 downto 8));
when 3 => tOpcode := std_logic_vector(cache_data(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Loadh) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadh;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_StoreH) then
sampledDecodedOpcode<=Decoded_StoreH;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
--sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_LSU;
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
cache_enable <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, cache_valid, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, cache_stall
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
cache_address(maxAddrBit downto 0) <= std_logic_vector(decr.fetchpc(maxAddrBit downto 0));
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
cache_strobe <= DontCareValue;
else
cache_strobe <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and cache_stall='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cyc_o<='0';
cache_strobe<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
--rom_wb_cyc_o <='0';
cache_strobe <= '0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
--if exu_busy='0' then
w.valid := cache_valid;
--end if;
end if;
if cache_valid='1' then
--if exu_busy='0' then
w.im := sampledOpcode(7);
--end if;
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and cache_stall='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
--if cache_stall='0' then
if exu_busy='0' then
w.opcode := sampledOpcode;
end if;
--end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
if cache_stall='0' then
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
end if;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
--rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
if exu_busy='0' then
w.valid := decr.valid;
end if;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
--| Decoded_Load
| Decoded_LoadH
| Decoded_Store
| Decoded_StoreH
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(spMaxBit downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(spMaxBit downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
lsu_address <= std_logic_vector(exr.tos(maxAddrBitIncIO downto 0));
--wb_cyc_o <= exr.wb_cyc;
--wb_stb_o <= exr.wb_stb;
--wb_we_o <= exr.wb_we;
--lsu_data_write <= std_logic_vector( nos );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output,
lsu_busy, lsu_data_read
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
variable datawrite: std_logic_vector(wordSize-1 downto 0);
variable sel: std_logic_vector(3 downto 0);
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= (others => '0');
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= (others => '0');
wroteback := wroteback_q;
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
lsu_req <= '0';
lsu_we <= DontCareValue;
lsu_data_sel <= (others => DontCareValue);
lsu_data_write <= (others => DontCareValue);
case exr.state is
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(spMaxBit downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when Tos_Source_LSU =>
if lsu_busy='0' then
w.tos := unsigned(lsu_data_read);
end if;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<=(others =>'1');
wroteback:='1';
stack_b_enable<= '0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= (others => '1');
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= (others =>'1');
when Decoded_StoreSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<=(others =>'1');
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store | Decoded_StoreB | Decoded_StoreH =>
if prefr.decodedOpcode=Decoded_Store then
datawrite := std_logic_vector(nos);
sel := "1111";
elsif prefr.decodedOpcode=Decoded_StoreH then
datawrite := (others => DontCareValue);
if exr.tos(1)='1' then
datawrite(15 downto 0) := std_logic_vector(nos(15 downto 0)) ;
sel := "0011";
else
datawrite(31 downto 16) := std_logic_vector(nos(15 downto 0)) ;
sel := "1100";
end if;
else
datawrite := (others => DontCareValue);
case exr.tos(1 downto 0) is
when "11" =>
datawrite(7 downto 0) := std_logic_vector(nos(7 downto 0)) ;
sel := "0001";
when "10" =>
datawrite(15 downto 8) := std_logic_vector(nos(7 downto 0)) ;
sel := "0010";
when "01" =>
datawrite(23 downto 16) := std_logic_vector(nos(7 downto 0)) ;
sel := "0100";
when "00" =>
datawrite(31 downto 24) := std_logic_vector(nos(7 downto 0)) ;
sel := "1000";
when others =>
end case;
end if;
stack_a_writeenable <=sel;
lsu_data_sel <= sel;
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_write <= datawrite;
stack_a_writeenable <= sel;
w.state := State_ResyncFromStoreStack;
else
--w.wb_we := '1';
--w.wb_cyc := '1';
--w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
-- stack_a_enable<='0';
stack_a_enable<=not lsu_busy;
stack_a_writeenable <= (others => '0');
-- stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_b_enable<= not lsu_busy;
lsu_data_write <= datawrite;
instruction_executed := '0';
exu_busy <= '1';
lsu_req <= '1';
lsu_we <= '1';
if lsu_busy='0' then
wroteback := '0';
w.state := State_Resync2;
end if;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_Loadh =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_enable<='1';
exu_busy <= '1';
w.state := State_LoadStack;
else
exu_busy <= lsu_busy;
lsu_req <= '1';
lsu_we <= '0';
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable <= not lsu_busy;
if lsu_busy='0' then
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
end if;
end if;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadh =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1) is
when '1' =>
w.tos(15 downto 0) := unsigned(exr.tos(15 downto 0));
when '0' =>
w.tos(15 downto 0) := unsigned(exr.tos(31 downto 16));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
wroteback_q <= '0';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
| mit | 5db95e517aa4005ad74d730db0b32b9c | 0.553156 | 3.59292 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen_hyperion.vhd | 13 | 10,525 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- This is a clockgen file for the Hyperion board type to be used with a Papilio One 500K. The sysclock runs at 92Mhz instead of 96Mhz.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen_hyperion;
architecture behave of clkgen_hyperion is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
signal clkin_i_2: std_logic;
signal vgaclk_0_b, vgaclk_fb, vgaclk_fx_b, vgaclk_in: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 8,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 23,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkin_i_2 <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
vgaclkout <= '0';
-- vgaclkfx_inst: BUFG
-- port map (
-- I => vgaclk_fx_b,
-- O => vgaclkout
-- );
-- VGADCM_inst : DCM -- Generate 50Mhz
-- generic map (
-- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 16,--8, -- Can be any integer from 1 to 32
-- CLKFX_MULTIPLY => 25,--23, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-- CLKIN_PERIOD => 31.25, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
-- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
-- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
-- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
-- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-- )
-- port map (
-- CLK0 => open,--vgaclk_0_b, -- 0 degree DCM CLK ouptput
-- CLK180 => open, -- 180 degree DCM CLK output
-- CLK270 => open, -- 270 degree DCM CLK output
-- CLK2X => open, -- 2X DCM CLK output
-- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-- CLK90 => open, -- 90 degree DCM CLK output
-- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => vgaclk_fx_b, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => open, -- 180 degree CLK synthesis out
-- LOCKED => open,--dcmlocked_b, -- DCM LOCK status output
-- PSDONE => open, -- Dynamic phase adjust done output
-- STATUS => open, -- 8-bit DCM status bits output
-- CLKFB => '0',--vgaclk_fb, -- DCM clock feedback
-- CLKIN => clkin_i_2, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => '0', -- Dynamic phase adjust clock input
-- PSEN => '0', -- Dynamic phase adjust enable input
-- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
-- RST => '0' -- DCM asynchronous reset input
-- );
end behave;
| mit | dda3ab41d5e989598b90d8d0a8d70e48 | 0.619952 | 3.45082 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.b-decode.core/a.b.b.e-Hazard_Detection_Unit.vhd | 1 | 4,376 | --------------------------------------------------------------------------------------------------------------
-- Hazard Detection Unit
-- This unit is the Hazard Detection Unit. It works in tight collaboration with the forwarding unit in the
-- EX stage. Since most of the data hazards are solved by the forwarding unit, the control hazards have their
-- own hazard detection unit, this unit is in charge for checking and solving(by forcing a nop and freezing
-- the decode and fetch stage) hazards due to MEM instruction followed by an ALU instruction
--------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity hdu is
port (
-- INPUTS
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
idex_mem_read : in std_logic_vector(3 downto 0); -- ID/EX MemRead control signals (lbu, lw, lhu, lb)
idex_rt : in std_logic_vector(4 downto 0); -- ID/EX Rt address
rs : in std_logic_vector(4 downto 0); -- Rs address instruction (25-21)
rt : in std_logic_vector(4 downto 0); -- Rt address instruction (20-16)
-- OUTPUTS
pcwrite : out std_logic; -- control signal write enable for the PC register
ifidwrite : out std_logic; -- control signal write enable for the pipeline register IF/ID
mux_op : out std_logic -- control signal directed to the mux stall
);
end hdu;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of hdu is
-- Sub-type declarations
type state_type is (RESET, CHECK, STALL);
-- Current state signal
signal current_state : state_type;
-- Next state signal
signal next_state : state_type;
-- Internal signals
signal lbu_i : std_logic;
signal lw_i : std_logic;
signal lhu_i : std_logic;
signal lb_i : std_logic;
begin
-- Cuncurrent statement
lbu_i <= idex_mem_read(3);
lw_i <= idex_mem_read(2);
lhu_i <= idex_mem_read(1);
lb_i <= idex_mem_read(0);
-------------------------
-- State Register
-- Type: Sequential
-- Reset: Synchronous
-- Purpose: Implement
-- state register
-------------------------
state_reg:process(clk)
begin
if(clk = '1' and clk'event) then
if (rst = '1') then
current_state <= RESET;
else
current_state <= next_state;
end if;
end if;
end process;
-----------------------------
-- Comb Logic
-- Type: Combinational
-- Purpose: Implement the
-- combinational logic of
-- the FSM.
-- Note that the FSM is a
-- Melay machine.
-----------------------------
comb_logic:process(lbu_i, lw_i, lhu_i, lb_i, idex_rt,rs,rt, current_state)
begin
case current_state is
when RESET =>
pcwrite <= '1';
ifidwrite <= '1';
mux_op <= '0';
next_state <= CHECK;
when CHECK =>
if ( ((lbu_i = '1') or (lw_i = '1') or (lhu_i = '1') or (lb_i = '1')) and
( (idex_rt = rs) or (idex_rt = rt) ) ) then
pcwrite <= '0';
ifidwrite <= '0';
mux_op <= '1';
next_state <= STALL;
else
pcwrite <= '1';
ifidwrite <= '1';
mux_op <= '0';
next_state <= CHECK;
end if;
when STALL =>
pcwrite <= '1';
ifidwrite <= '1';
mux_op <= '0';
next_state <= CHECK;
when others =>
pcwrite <= '0';
ifidwrite <= '0';
mux_op <= '0';
next_state <= RESET;
end case;
end process;
end behavioral;
| mit | ba5442a7c0f4046f584a83393a0ffa0c | 0.438071 | 4.389168 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/title2_1/synth/title2.vhd | 1 | 14,290 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY title2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END title2;
ARCHITECTURE title2_arch OF title2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF title2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF title2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF title2_arch : ARCHITECTURE IS "title2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF title2_arch: ARCHITECTURE IS "title2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=title2.mif,C" &
"_INIT_FILE=title2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=10404,C_READ_DEPTH_A=10404,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=" &
"10404,C_READ_DEPTH_B=10404,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WAR" &
"N_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.227751 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "title2.mif",
C_INIT_FILE => "title2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 10404,
C_READ_DEPTH_A => 10404,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 10404,
C_READ_DEPTH_B => 10404,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.227751 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END title2_arch;
| gpl-3.0 | f8246b8ac578096d38d6786439a90fe2 | 0.625332 | 3.008421 | false | false | false | false |
huukit/logicsynth | excercises/vhd/adder.vhd | 1 | 2,330 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 03
-- Project :
-------------------------------------------------------------------------------
-- File : adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 4.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Third excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 4.11.2015 1.0 tuhu Created
-- 18.11.2015 1.1 tuhu Modified process.
-- 20.11.2015 1.1 nikulaj Added bonus feature
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic(
operand_width_g : integer -- Width of input and output. Note, that if the definition of the input width
-- is i.e 8, the definition below must be (8 - 1) because the vector starts from 0.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
a_in : in std_logic_vector(operand_width_g - 1 downto 0); -- Input a.
b_in : in std_logic_vector(operand_width_g - 1 downto 0); -- Input b.
sum_out : out std_logic_vector(operand_width_g downto 0) -- Sum output.
);
end adder;
architecture rtl of adder is
SIGNAL result_r : signed((operand_width_g) downto 0); -- Result register.
begin -- rtl
sum_out <= std_logic_vector(result_r); -- Assign register to output.
calculate : process (clk, rst_n) -- Handle the actual calculation of values and reset.
begin
if(rst_n = '0') then -- Reset
result_r <= (others => '0');
elsif(clk'event and clk = '1') then -- Calculate on rising edge of clock.
result_r <= resize(signed(a_in), operand_width_g + 1) + resize(signed(b_in), operand_width_g + 1);
end if;
end process calculate;
end rtl;
| gpl-2.0 | 86a354130c31dfc962edb7b706f474c9 | 0.460944 | 4.205776 | false | false | false | false |
huukit/logicsynth | excercises/vhd/i2c_config.vhd | 1 | 10,027 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 12
-- Project :
-------------------------------------------------------------------------------
-- File : i2c_config.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 20.1.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: I2C bus controller, for Wolfson Audio Codec configuration
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 20.01.2016 1.0 nikulaj Created
-- 03.02.2016 1.1 huukitu Moved data to pkg.
-- 02.03.2016 1.2 nikulaj Assign finished_out sequentially
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- define the entity
entity i2c_config is
generic(
ref_clk_freq_g : integer := 50000000; -- reference clk
i2c_freq_g : integer := 20000; -- wanted i2c frequency
n_params_g : integer := 10 -- amount of 3 byte transmissions
);
port(
clk : in std_logic;
rst_n : in std_logic; -- active low rst
sdat_inout : inout std_logic; -- i2c dataline
sclk_out : out std_logic; -- i2c clk
param_status_out : out std_logic_vector(n_params_g - 1 downto 0); -- status "display"
finished_out : out std_logic -- 1 when done sending
);
end i2c_config;
architecture rtl of i2c_config is
-- type definitions
type state_type is (start_condition, stop_condition, acknowledge, data_transfer);
type temp_transmission_arr is array (2 downto 0) of std_logic_vector(7 downto 0);
-- constants
-- max value for clk prescaler
constant prescaler_max_c : integer := (ref_clk_freq_g / i2c_freq_g) / 2;
-- data to be sent
constant codec_address_c : std_logic_vector(7 downto 0) := "00110100";
type transmission_data_arr is array (n_params_g - 1 downto 0) of std_logic_vector(15 downto 0);
-- Actual transmission data array.
constant transmission_data_c : transmission_data_arr := (
"0001001000000001",
"0001000000000010",
"0000111000000001",
"0000110000000000",
"0000101000000110",
"0000100011111000",
"0000011001111011",
"0000010001111011",
"0000001000011010",
"0000000000011010"
);
-- registers
signal finished_r : std_logic;
signal sclk_r : std_logic;
signal sclk_prescaler_r : unsigned(integer(ceil(log2(real(prescaler_max_c)))) downto 0);
signal present_state_r : state_type;
signal bit_counter_r : unsigned(2 downto 0);
signal byte_counter_r : unsigned(1 downto 0);
signal status_counter_r : unsigned(3 downto 0);
signal param_status_r : std_logic_vector(n_params_g - 1 downto 0);
signal temp_transmission_r : temp_transmission_arr;
begin
finished_out <= finished_r;
param_status_out <= param_status_r;
-- Only output clk when NOT finished
with param_status_r(n_params_g - 1) select
sclk_out <=
sclk_r when '0',
'Z' when others;
-- i2c clk generation process
-- Increments counter, until it hits max value. At that point the clk
-- changes value
generate_sclk : process(clk, rst_n)
begin
if(rst_n = '0') then
sclk_r <= '0';
sclk_prescaler_r <= (others => '0');
elsif(clk'event and clk = '1') then
if(sclk_prescaler_r = prescaler_max_c) then
sclk_prescaler_r <= (others => '0');
sclk_r <= not sclk_r;
else
sclk_prescaler_r <= sclk_prescaler_r + 1;
end if;
end if;
end process generate_sclk;
-- i2c data output process
generate_sdat : process(clk, rst_n)
begin
if(rst_n = '0') then -- reset all values that need it
sdat_inout <= 'Z';
present_state_r <= start_condition;
bit_counter_r <= to_unsigned(7, bit_counter_r'length);
byte_counter_r <= to_unsigned(0, byte_counter_r'length);
status_counter_r <= to_unsigned(0, status_counter_r'length);
param_status_r <= (others => '0');
temp_transmission_r(0) <= (others => '0');
temp_transmission_r(1) <= (others => '0');
temp_transmission_r(2) <= (others => '0');
finished_r <= '0';
elsif(clk'event and clk = '1') then
if(param_status_r(n_params_g - 1) = '1') then
sdat_inout <= 'Z'; -- When finished, take config logic
finished_r <= '1'; -- out of the circuit
-- and set finished signal to 1
elsif(present_state_r = acknowledge and sclk_prescaler_r = 0) then
sdat_inout <= 'Z'; -- set to high-Z, so that ack can be received
elsif(sclk_prescaler_r = prescaler_max_c / 2) then
case present_state_r is
when start_condition =>
-- when sdat is high, a transition to low triggers a
-- start condition
-- also prepare for data transfer
if(sdat_inout = '1' and sclk_r = '1') then
sdat_inout <= '0';
present_state_r <= data_transfer;
bit_counter_r <= to_unsigned(7, bit_counter_r'length);
byte_counter_r <= to_unsigned(0, byte_counter_r'length);
temp_transmission_r(0) <= codec_address_c;
temp_transmission_r(1) <= transmission_data_c(to_integer(status_counter_r))(15 downto 8);
temp_transmission_r(2) <= transmission_data_c(to_integer(status_counter_r))(7 downto 0);
elsif(sclk_r = '0') then
-- set sdat high so it can be pulled low
sdat_inout <= '1';
end if;
when stop_condition =>
if(sdat_inout = '0' and sclk_r = '1') then
-- when sdat is low, a transition to high
-- triggers a stop condition
sdat_inout <= '1';
-- 3 byte transfer is done, increment status
status_counter_r <= status_counter_r + 1;
param_status_r(to_integer(status_counter_r)) <= '1';
-- after stop cond, go to start
present_state_r <= start_condition;
elsif(sclk_r = '0') then
sdat_inout <= '0';
end if;
when acknowledge =>
bit_counter_r <= to_unsigned(7, bit_counter_r'length);
-- listening for ack (or nack)
if(sclk_r = '1') then
if(sdat_inout = '1') then
-- on nack, go to start
present_state_r <= start_condition;
elsif(sdat_inout = '0') then
-- on ack, got to stop if all 3 bytes sent
if(byte_counter_r = 2) then
present_state_r <= stop_condition;
-- otherwise to next byte
else
present_state_r <= data_transfer;
byte_counter_r <= byte_counter_r + 1;
end if;
end if;
end if;
when data_transfer =>
-- when clk is low, change state, so that line is
-- stable for high
if(sclk_r = '0') then
sdat_inout <= temp_transmission_r(to_integer(byte_counter_r))(to_integer(bit_counter_r));
else
-- When bit is being sent, check if whole byte is
-- sent. If so, go to ack, otherwise
-- increment bit counter.
if(bit_counter_r = 0) then
present_state_r <= acknowledge;
else
bit_counter_r <= bit_counter_r - 1;
end if;
end if;
end case;
end if;
end if;
end process generate_sdat;
end rtl;
| gpl-2.0 | 51614e96e5dd6ff36db5c3e2b5eeb0a2 | 0.42206 | 4.834619 | false | false | false | false |
huukit/logicsynth | excercises/vhd/ripple_carry_adder.vhd | 1 | 2,250 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 02
-- Project :
-------------------------------------------------------------------------------
-- File : ripple_carry_adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 28.10.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Second excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 28.10.2015 1.0 tuhu, nikulaj Created
-------------------------------------------------------------------------------
-- TODO: Add library called ieee here
-- And use package called std_logic_1164 from the library
library ieee;
use ieee.std_logic_1164.all;
-- TODO: Declare entity here
-- Name: ripple_carry_adder
-- No generics yet
-- Ports: a_in 3-bit std_logic_vector
-- b_in 3-bit std_logic_vector
-- s_out 4-bit std_logic_vector
entity ripple_carry_adder is
PORT (
a_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end ripple_carry_adder;
-------------------------------------------------------------------------------
-- Architecture called 'gate' is already defined. Just fill it.
-- Architecture defines an implementation for an entity
architecture gate of ripple_carry_adder is
-- TODO: Add your internal signal declarations here
SIGNAL carry_ha : STD_LOGIC;
SIGNAL carry_fa : STD_LOGIC;
SIGNAL C, D, E, F, G, H : STD_LOGIC;
begin -- gate
-- Half adder.
s_out(0) <= a_in(0) XOR b_in(0);
carry_ha <= a_in(0) AND b_in(0);
-- Full adder 1.
C <= a_in(1) XOR b_in(1);
D <= carry_ha AND C;
E <= a_in(1) AND b_in(1);
s_out(1) <= carry_ha XOR C;
carry_fa <= D OR E;
-- Full adder 2.
F <= a_in(2) XOR b_in(2);
G <= carry_fa AND F;
H <= a_in(2) AND b_in(2);
s_out(2) <= carry_fa XOR F;
s_out(3) <= G OR H;
end gate;
| gpl-2.0 | 9f00d1ed47e4ddaaf0cac98b4b700e2f | 0.456889 | 3.731343 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_tex/bg_tex_sim_netlist.vhdl | 1 | 126,813 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat Dec 24 01:08:44 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_tex/bg_tex_sim_netlist.vhdl
-- Design : bg_tex
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_bindec : entity is "bindec";
end bg_tex_bindec;
architecture STRUCTURE of bg_tex_bindec is
begin
\/i_\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end bg_tex_blk_mem_gen_mux;
architecture STRUCTURE of bg_tex_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I4 => sel_pipe_d1(0),
O => douta(7)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I4 => sel_pipe_d1(0),
O => douta(8)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I4 => sel_pipe_d1(0),
O => douta(0)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I4 => sel_pipe_d1(0),
O => douta(1)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I4 => sel_pipe_d1(0),
O => douta(2)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I4 => sel_pipe_d1(0),
O => douta(3)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I4 => sel_pipe_d1(0),
O => douta(4)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I4 => sel_pipe_d1(0),
O => douta(5)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I4 => sel_pipe_d1(0),
O => douta(6)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_tex_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_tex_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0200000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"1000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"000000000E000000000000000000000000000000000000000000000000000000",
INIT_0D => X"00000000000000000000300000000000000000000000001C0000000000000000",
INIT_0E => X"0C00000000000000000000000000000400000000000000000000000000000000",
INIT_0F => X"0000000000007000000000000000000000000038000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000040000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"8000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000028000000000000000000000008000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000004000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000040000",
INIT_19 => X"0800000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0080200000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000040000000000020000000000000000000000000000000000000",
INIT_1C => X"00000000000080000000000000008004000000000000000000000A0000000000",
INIT_1D => X"0000000000000200000000000000000000000000000000001000000000000001",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000002000",
INIT_1F => X"0000000008000000010000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000004000040000000000000000000000000000000000000",
INIT_21 => X"000000A000000000001000000000000000000000000000000000000000080000",
INIT_22 => X"0000000000000000000000000000000000000000000000020000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000040000",
INIT_24 => X"0000000000000000000400020000000000000000000000000000000000000000",
INIT_25 => X"0000000001400000000000000000000000010000000000000000000004000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0080000000000000000000000000000000000000000000000000800000000000",
INIT_28 => X"0000000000000800000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"00000000000000000000000C0000000000000000000000000200000000000000",
INITP_05 => X"00000007E0000000000000000000000000F00000000000000000000000003800",
INITP_06 => X"0000F0000000000001FF8000000000700000000000003FC00000000020000000",
INITP_07 => X"FFFBF80000000003F8000001FFFFFFFE0000000001F00000000FFF07FF000000",
INITP_08 => X"1FFE0000FFFFFFF9C0000000000FFE00003FFFFFF3F00000000007F8000007FF",
INITP_09 => X"F800000000007FFF801FFFFFFFF800000000003FFF0007FFFFFFF90000000000",
INITP_0A => X"F0FFFFFFFFFFF00000000001FFFE03FFFFFFFFF80000000000FFFF807FFFFFFF",
INITP_0B => X"0000000007F87FFFFFFFFFFFE00000000007FF0FFFFFFFFFFFF00000000003FF",
INITP_0C => X"FFFFFFFFC40000000000021FFFFFFFFFFFF1800000000007C3FFFFFFFFFFFFC0",
INITP_0D => X"000000001FFFFFFFFFFE020000000000001FFFFFFFFFFF190000000000001FFF",
INITP_0E => X"81FFF8300000000000003FFFFFE1FFF8080000000000001FFFFFFFFFFC040000",
INITP_0F => X"000007FFBFFC23FFFFE00000000000074047FE11FFF8E00000000000040FC0FF",
INIT_00 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_01 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_02 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_03 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_04 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_05 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_06 => X"1A161A161A161A161A161A161616161616161616161616161616161616161616",
INIT_07 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_08 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_09 => X"1616161616161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_0A => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0B => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0D => X"161616161616161616161616161616161616161616161616161A161616161616",
INIT_0E => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0F => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_10 => X"1A161A161A161A161A161A161A161A1616161616161616161616161616161616",
INIT_11 => X"1A161A161A161A161A161A161A161A161A161A161A0020161A161A161A161A16",
INIT_12 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_13 => X"1616161616161616161616161A161A161A161A161A161A161A161A161A161A16",
INIT_14 => X"1616161616161616161616060000161616161616161616161616161616161616",
INIT_15 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_16 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_17 => X"16160000201616161616161616161616161616161616161616161616161A1616",
INIT_18 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_19 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_1A => X"1A161A161A161A161A161A161A161A161A161A1616161616161A161616161616",
INIT_1B => X"1A161A161A161A161A161A161A161A161A161A161A161A160000000016161A16",
INIT_1C => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_1D => X"1616161616161616161616161A161616161616161A161A161A161A161A161A16",
INIT_1E => X"161616161616161616161616161600000000001A161616161616161616161616",
INIT_1F => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_20 => X"1616161616161616161A16161616161616161616161616161616161616161616",
INIT_21 => X"1616161600007600000016161616161616161616161616161616161616161616",
INIT_22 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_23 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_24 => X"0016161A161A161A161A161A161A161A161A161A161A161A161616161616161A",
INIT_25 => X"161A161A161A161A161A161A161A161A161A161A161A161A161A000076760000",
INIT_26 => X"161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A",
INIT_27 => X"16161616161616161616161616161616161A161A16161616161A161A161A161A",
INIT_28 => X"1616161616161616161616161616160000007676760000001616161616161616",
INIT_29 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_2A => X"1616161616161A161616161A1616161616161616161616161616161616161616",
INIT_2B => X"16161616000000EE7676BA76000020161A161616161616161616161616161616",
INIT_2C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_2D => X"161616161A161A16161600001616161616161616161616161616161616161616",
INIT_2E => X"7676760000001616161A161A161A161A161A161A161A161A161A161616161616",
INIT_2F => X"161A161A161A161A161A161A161A161A161A161A161A161A161A0000EE767676",
INIT_30 => X"16007600001A161A161A161A161A161A161A161A161A161A161A161A161A161A",
INIT_31 => X"1616161616161616161616161616161616161A16161A1616161616161616161A",
INIT_32 => X"1616161616161616161616161616161600007676BA76BA767676000016161616",
INIT_33 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_34 => X"1616161616161616161616161616161616161616161616160076767600161616",
INIT_35 => X"001616161600007676767676767676BA76000016161A16161616161616161616",
INIT_36 => X"1616161616161616161616161616161616161616160000000000000000000000",
INIT_37 => X"161A16161A161616161A161A1616160076BA7676001616161616161616161616",
INIT_38 => X"76BA76767676767600001A1616161A161A161A161A161A161A161A161A161A16",
INIT_39 => X"161A161A161A161A000000007676767676767676767676760000000000767676",
INIT_3A => X"16161616161A0076763276760002161A161A161A161A161A161A161A161A161A",
INIT_3B => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_3C => X"767676BA7676BA7676BA7676BA76767676767676BA76BA767676BA7676767600",
INIT_3D => X"BA76767676000016461A16161616161616161616161616161616161616160076",
INIT_3E => X"161616161616161616161616161A16161A16161616161A161616161A16007676",
INIT_3F => X"7676767676BA76BA76BA767676EE7676327676BA76EE0016161A161616161616",
INIT_40 => X"1616161616161616161616161616161616161600007676767676767676767676",
INIT_41 => X"1A161A16161616161A1616161616161A161616160076767676BA767676EE0202",
INIT_42 => X"76767676AA003276767676760216161616161A161A161A161A161A161A161A16",
INIT_43 => X"1A161A161A161A161A0076767676BA76BA7676BA7676BA7676BA767676767676",
INIT_44 => X"161616161616161A1616160076BA7676767676BA7676760000161A161A161A16",
INIT_45 => X"BA76461616161A1616161616161616161616161616161616161616161A161616",
INIT_46 => X"767676BA7676767676767676767676767676BA76767676767676BA7676006676",
INIT_47 => X"1A16007676767676BA7676763276760000161616161616161616161616160000",
INIT_48 => X"1616161616161616161616161616161616161616161616161A16161A16161616",
INIT_49 => X"7676BA7676BA7676767676BA76BA76BA767676767620AA766620161616161616",
INIT_4A => X"7676BA76BA76767600001616161616161616161600767676BA767676767676BA",
INIT_4B => X"161A161A161A161A16161A161A161616161616161616161616007676BA767676",
INIT_4C => X"767676767676767676BA76BA7622002016161A16161A161A161A161A161A161A",
INIT_4D => X"BA0000AA1A161A161A16007676BA76767676BA76BA767676767676767676BA76",
INIT_4E => X"161616161616161616161A16161A161600BA767676BA76767676767676BA7676",
INIT_4F => X"7676767632006606161616161616161616161616161616161616161616161616",
INIT_50 => X"0076BA767676767676767676767676BA7676BA76767676BA7676767676767676",
INIT_51 => X"161616161616160076767676767676BA7676767676767676764600AA16161600",
INIT_52 => X"16161A16161616161616161616161616161616161616161A161616161A161616",
INIT_53 => X"76767676BA7676767676767676767676BA76BA76BA76BA767676BA767600161A",
INIT_54 => X"76BA7676BA76767676BA767676BA76EE64000000000076767676767676BA76BA",
INIT_55 => X"161A161A161A161A161A161A16161616161A161616161616161A16161A160032",
INIT_56 => X"76BA76BA76767676767676767676767676767676001616161616161A161A161A",
INIT_57 => X"7676762A640000AA327676767676BA767676BA7676767676BA7676767676BA76",
INIT_58 => X"161616161A1616161616161616161A16161616161600327676767676767676BA",
INIT_59 => X"7676767676BA767676BA767600161A1616161616161616161616161616161616",
INIT_5A => X"BA7676BA767676BA767676767676767676BA76767676767676767676BA767676",
INIT_5B => X"161A1616161616161A1616160032BA7676BA7676BA767676A06600AA32BA7676",
INIT_5C => X"767632001616161A1616161616161616161616161616161616161616161A1616",
INIT_5D => X"76BA7676BA767676767676BA7676BA76767676767676BA76BA76BA767676BA76",
INIT_5E => X"16161A16007676767676767676600200EE767676767676767676767676767676",
INIT_5F => X"161A161A161A161A161A161A161A161A161A161616161A161616161616161616",
INIT_60 => X"BA76767676767676BA7676BA76767676767676767676767676BA001616161616",
INIT_61 => X"7632460022EE76BA7676BA7676BA7676BA767676BA7676767676767676BA7676",
INIT_62 => X"16161616161616161616161616161616161616161A16161A16161600007676BA",
INIT_63 => X"76767676767676767676BA32000000767600161A1616161A1616161616161616",
INIT_64 => X"767676767676767676BA767676BA767676BA7676767676767676BA767676BA76",
INIT_65 => X"1A161A1616161A16161616161616161616168E1600AA76460000007676BA7676",
INIT_66 => X"76760000EE33EEEEEE0016161A16161616161616161616161616161616161616",
INIT_67 => X"767676767676BA7676767676BA7676BA767676BA76767676BA7676BA76BA76BA",
INIT_68 => X"161A16161A16161A161A16002000000000006676767676BA7676BA7676BA7676",
INIT_69 => X"0016161616161616161A161A161A161A161A161A161A16161616161A16161616",
INIT_6A => X"76BA767676767676767676767676767676767676767676760000007777AA0076",
INIT_6B => X"16160000000000000000667676767676767676767676767676BA767676767676",
INIT_6C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_6D => X"7676BA7676BA7676BA76767676767600000066EE460076001A16161A16161A16",
INIT_6E => X"00000076BA3276BA767676BA7676BA767676BA767676BA76767676BA767676BA",
INIT_6F => X"16161616161A161A1616161A16161616161A16161A1616161616000000000000",
INIT_70 => X"76BA76BA76760000000000000076001616161616161616161616161616161616",
INIT_71 => X"BA76767676767676767676BA7676767676767676BA7676767676767676767676",
INIT_72 => X"1A1616161616161A16161616161A161A16161600000000000000007676767676",
INIT_73 => X"00000000760016161A16161A16161A161A161A161A161A161A161A1616161616",
INIT_74 => X"7676767676BA76BA767676000000007676BA767676BA767676767676BA000000",
INIT_75 => X"161A1616161616161A1616000000000000007676BA7676767676BA7676BA7676",
INIT_76 => X"1616161616161616161616161616161616161616161616161616161A16161616",
INIT_77 => X"7600004666AA00767676BA767676767676767676760000000000767600161616",
INIT_78 => X"161616000076AA00000000EE7676767676760000000000007676767676767676",
INIT_79 => X"161616161616161616161A161A1616161A16161A161616161616161616161616",
INIT_7A => X"7676767676BA76BA76BA7676760000007676BAEE001A16161A16161A16161616",
INIT_7B => X"EE76000000000000007600EEEE767676BA76BA76767676000000EEBBEE000076",
INIT_7C => X"16161616161A161616161616161A161A16161A161A1616161A16161600767632",
INIT_7D => X"76767676767676767676760000161616161616161A161A161A161A161A161A16",
INIT_7E => X"76007676BA767676767676BA76BA000000AA77EE000076BA767676BA76767676",
INIT_7F => X"161616161616161616161616161A1616161A16160076BA767676767676767676",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"E1F9E0000000000007FEFFF00FFFFC40000000000007FF7FF807FFFF00000000",
INITP_01 => X"000FF7FFC1FF8FCFC0000000000007FBFFE07FC3E7E0000000000007FDFFE01F",
INITP_02 => X"3E0000000000003FDFFFFFFFF99F0000000000001FEFFFFFFFFF9F8000000000",
INITP_03 => X"F07C7C7F0F7F00000000000001FC7F1C7FE0BF38000000000000FF3FC07FFF07",
INITP_04 => X"00000000001F81F3FDFFCDFF0000000000000FE0F9FEFFCEFFC0000000000007",
INITP_05 => X"DFCFFFFFF00000000000002C01CFF7FFCFF80000000000001C01E7FBFF8BFE00",
INITP_06 => X"000000007801C07FFFFFF00000000000003003CF1FFFFFD00000000000003801",
INITP_07 => X"FFFFFFC0000000000000B81E7FFFFFFFE00000000000007C0CC3FFFFFFE00000",
INITP_08 => X"00000FA1FFFFFFFFFF80000000000003D87FFFFFFFFFC0000000000001F81F3F",
INITP_09 => X"FFFE0000000000007607FFFFFFFFFF0000000000003F83FFFFFFFFFF80000000",
INITP_0A => X"01603FFF7FFFEFFC000000000000F01FFFFFFFF7FE000000000000FC0FFFFFFF",
INITP_0B => X"60000000000003807FFEFFFFBFB0000000000003403FFEFFFFDFD80000000000",
INITP_0C => X"C0FFFDFFFDFB8000000000000782FFFDFFFEFEC0000000000007827FFDFFFF7E",
INITP_0D => X"00000000001F31FFFBFFEFEF8000000000000F90FFFBFFFBF780000000000002",
INITP_0E => X"1FF3FF1EFF8000000000001CFFFFE9FF3F7FC000000000001E7FFFF3FF9FBF80",
INITP_0F => X"0000000031FFCFCFFF07FE00000000000039FF9FE7FE2DFF00000000000018FE",
INIT_00 => X"4600000000161A16161A161616161616161616161616161A1616161616161616",
INIT_01 => X"76767676760000000000000000767676BA76767676767676BA76BA767676BA76",
INIT_02 => X"16161616161616161616161A007676BA76BA76BA76BA76760076767676BA7676",
INIT_03 => X"16161616161616161616161616161616161A1616161A1616161A161616161A16",
INIT_04 => X"00000000767676767676767676BA7676767676BA767600206060600000161616",
INIT_05 => X"1A161616003276767676767676BA760076BA7676767676BA7676767600000000",
INIT_06 => X"161A161A16161A1616161A161616161616161A161616161A161A1616161A1616",
INIT_07 => X"7676BAEE6600AA76767676763200A0606060600016161A16161A161A161A161A",
INIT_08 => X"767676767676007676767676BA76767676BA76000000000000000076BA7676BA",
INIT_09 => X"16161616161616161616161A1616161616161A16161616161616161600767676",
INIT_0A => X"767676EE00606060A06060001616161616161616161616161616161616161616",
INIT_0B => X"BA767676767676BA767676000000000000767676767676767676000000AABA76",
INIT_0C => X"161616161616161616161616161A16161A16161602BA76BA7676BA7676007676",
INIT_0D => X"60600016161A1616161616161616161616161A1616161A1616161A1616161A16",
INIT_0E => X"7676EE000000007676BA7676BA7676BA76AA4620767676BA7676AA0060A06060",
INIT_0F => X"16161A1616161616161A1600767676767676767600BA767676BA7676BA767676",
INIT_10 => X"161A161A161A161A1616161A1616161A161616161616161A16161A161A161A16",
INIT_11 => X"76767676767676767676BA76767632BA76EE0060606060A0600016161616161A",
INIT_12 => X"161600767676BA7676BA7600767676767676767676767676BA76767676767676",
INIT_13 => X"16161616161616161616161616161616161616161616161A161616161A161616",
INIT_14 => X"767676BA7600AA76BA00206060206060001A16161A1616161616161616161616",
INIT_15 => X"767600767676BA7676BA7676767632327676BA7676BA7676BA767676BA7676BA",
INIT_16 => X"1616161A1616161A16161616161616161616161616161A16160076BA76767676",
INIT_17 => X"AA2060A0606060001616161616161616161616161616161A1616161A1616161A",
INIT_18 => X"7676AA2000200020EE7676767676767676BA7676767676760000000000767676",
INIT_19 => X"1A161A161616161A161616161A161600767676767676BA76000076BA76767676",
INIT_1A => X"161A16161A161A161A161A161A1616161A1616161A161616161616161A161616",
INIT_1B => X"66BA3276BA7676767676760000000060600076767676767666006060A0001616",
INIT_1C => X"1A161616161600767676BA76767600160076767676BA3276000060606020A000",
INIT_1D => X"1616161616161616161616161616161616161616161616161616161A16161616",
INIT_1E => X"EE0000006060A02000767676BA76BA76AA000000000616161616161616161616",
INIT_1F => X"7676767600161616007676767676AA00E060A06060A0A6206676767676BA7676",
INIT_20 => X"1A1616161A1616161A1616161A1616161616161A161616161A161616003276BA",
INIT_21 => X"76BA3276767676BA7676001616161A16161A161616161616161616161A161616",
INIT_22 => X"76BA7676BA6400A0606020606060200076BA7676767676BA7676000020606000",
INIT_23 => X"161A1616161A161A161616161A161616161A1600BA76767676BA7600161A1600",
INIT_24 => X"EE00161A1616161616161A161A161A161A161616161A1616161A161616161616",
INIT_25 => X"60A06060606000327676767676BA767676760060606000767676767676767676",
INIT_26 => X"1616161616161616161600767676763276001616161600767676767600A06060",
INIT_27 => X"1616161616161616161A16161616161616161616161616161616161616161616",
INIT_28 => X"BA76BA76767676BA76EE00A060007676BA76BA767676760016161616161A1616",
INIT_29 => X"16160076BA32E82000161A1616160076BA767620606020606060A02020003276",
INIT_2A => X"16161616161A1616161A1616161A1616161A161616161A16161A16161A161616",
INIT_2B => X"7676000076BA767676763276BA00161A1616161616161A161616161616161616",
INIT_2C => X"1616161A1600EE7676764660A060A060606060200032767676767676767676BA",
INIT_2D => X"1616161616161A161616161A1616161616161616161A161A1600BAE820326000",
INIT_2E => X"76BA7676001616161A161A161616161A161A161A161A161A16161A1616161A16",
INIT_2F => X"BA7620602060606060A0E00076BA7676767676BA76767676BA76767676767676",
INIT_30 => X"1A16161616161A16161A1616161616161600207660E00000161616161600EE76",
INIT_31 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_32 => X"6420AA767676BA76BA767676767676767676BA7676BA76767676007600161616",
INIT_33 => X"161616161616161600EE2032E8AA200016161A160A00767676BA206060A06060",
INIT_34 => X"1616161616161A16161A1616161A161616161A16161616161616161A16161616",
INIT_35 => X"7676BA7676BA7676767676767676BA767676763200161616161A161A16161616",
INIT_36 => X"0032603260A622001616161A000000767676A0A0E020E0606076BA7676767676",
INIT_37 => X"16161616161616161616161A16161A161A161616161A16161A161A161A161616",
INIT_38 => X"76BA76767676767676BA760000161A1616161616161A161A161A161A16161616",
INIT_39 => X"161616007676000076766000A0A076767676767676767676767676767676BA76",
INIT_3A => X"1616161616161616161616161616161616161616161A16120020326032202000",
INIT_3B => X"767676001616161616161A16161616161616161616161A16161A16161A161616",
INIT_3C => X"007676BA76BA3276BA7676BA76BA76BA7676BA76767676767676BA767676BA76",
INIT_3D => X"1A161A16161A1616161616161616160032AA203260EE001A1600EE76BA767600",
INIT_3E => X"16161616161616161616161A16161616161616161616161A1616161A16161616",
INIT_3F => X"76327676767676767676767676BA7676767676BA76767676BA76001616161A16",
INIT_40 => X"1A1616161A1600206032203220A6001600EEEE7676BA76760000767676767676",
INIT_41 => X"1A161616161A16161A161616161616161A161616161A16161616161616161A16",
INIT_42 => X"76BA76767676BA767676767676BA76767676001A1616161A16161A161A161A16",
INIT_43 => X"3220EE7620001600EE3276767676767676BA7676BA7676BA767676767676BA76",
INIT_44 => X"1A1616161616161616161A1616161616161A161616161616161A161616003220",
INIT_45 => X"76767676767676BA760016161616161616161616161616161616161616161616",
INIT_46 => X"76767676BA76BA76767676767676767676BA76BA7676767676BA7676767676BA",
INIT_47 => X"16161616161A161616161A1616161616161616003220322076E0200016160076",
INIT_48 => X"7600161A1616161A1616161616161616161A16161A161616161616161A161616",
INIT_49 => X"BA7676BA7676BA767676767676BA76767676BA7676767676BA76BA7676767676",
INIT_4A => X"161616161A161A161600322032603220324600161600767676BA767676767676",
INIT_4B => X"1A161A161A161A1616161616161616161A161616161A161A16161A1616161A16",
INIT_4C => X"7676767676767676767676BA76763276767676BA767676BA001616161A161616",
INIT_4D => X"00207620EE2032A00016161A0076BA7676767676767676767676767676767676",
INIT_4E => X"1A16161A161A16161616161616161616161616161616161616161A161616161A",
INIT_4F => X"76767676BA76327676767676BA76760016161616161616161616161616161616",
INIT_50 => X"1616160076767676BA76BA76BA767676BA3276BA7676BA76BA767676BA7676BA",
INIT_51 => X"161A161616161A16161A1616161A161A16161616161616003220322076600016",
INIT_52 => X"76767676767676001A1616161A16161616161616161616161616161616161616",
INIT_53 => X"7676767676BA7676767676767676767676BA7676767676767676767600BA76BA",
INIT_54 => X"16161A16161616161616161A1616160032203220A016161A1616007676767676",
INIT_55 => X"161A1616161A161A161A161A161A16161A161616161616161616161A16161616",
INIT_56 => X"007676BA7676767676767676BA767676BA76320076767676BA76767676760016",
INIT_57 => X"1A1616161A160060A66032001A16161616002ABA76BA7676767676767676BA76",
INIT_58 => X"1616161616161616161A16161A1616161A16161616161A161616161616161616",
INIT_59 => X"76BA767676BA7676763200767676767676760076BA0016161616161616161616",
INIT_5A => X"EE20001616161A0060AA76767676BA76BA7676767676320076767676BA767676",
INIT_5B => X"16161616161616161616161A1616161616161A161A1616161616161616163260",
INIT_5C => X"320076BA767676BA76002A76001616161A16161616161616161616161A161616",
INIT_5D => X"607676767676767676BA7676767676007676767676BA767676767676767676BA",
INIT_5E => X"1A161616161A161A16161616161A16161A1616161600322032A62016161620A0",
INIT_5F => X"20767600161A1616161A161A161A161A161A1616161A16161A161616161A1616",
INIT_60 => X"7676BA76BA760032BA76767676BA767676BA76767676763200767676BA7632EE",
INIT_61 => X"1616161616161616161A16160020326032E0201666602A666676BA7676767676",
INIT_62 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_63 => X"76BA76767676BA767676BA76BA76320076767676767676007676001616161616",
INIT_64 => X"161616160032203260EEA000006660202A767676BA76BA7676767676BA2A0076",
INIT_65 => X"161A1616161A16161A1616161A1616161A161A16161616161A161A16161A1616",
INIT_66 => X"7676767676320076BA767676BA0076762A201616161A16161616161616161616",
INIT_67 => X"A03200004660A0667676BA76767676767676767676BA00767676767676767676",
INIT_68 => X"16161616161A16161616161A161A16161616161616161616161A161600EE20A6",
INIT_69 => X"76BA762A0076BA767600001616161A161A161A161A161A1616161A1616161616",
INIT_6A => X"7676767676BA76BA7676BA7676003276BA7676BA7676BA767676767676007676",
INIT_6B => X"1616161616161616161A16161A161A1616161600207632203260AA76AA0000AA",
INIT_6C => X"76000016161616161616161616161616161616161A161616161A161616161616",
INIT_6D => X"767676767600767676767676767676BA76BA7600767676767676760076767676",
INIT_6E => X"16161616161616161A160032206032200022BA76EE00003276BA767676767676",
INIT_6F => X"161616161616161A161616161616161616161616161A161A1616161616161A16",
INIT_70 => X"7676BA767676767676000076BA76BA7676202A76BA7676BA76EE001A16161616",
INIT_71 => X"161600203220762200767676767676767676BA76767676BA7676BA76000076BA",
INIT_72 => X"1A16161A1616161616161A1616161616161A161A16161616161A161616161616",
INIT_73 => X"00007676763276320076BA7676767676767600161A161A161A161A161A161616",
INIT_74 => X"7676BA767676BA76767676BA76767676767676EE7600E8BA767676BA76767676",
INIT_75 => X"161616161616161A1616161616161A1616161A161A1616161A16003220326020",
INIT_76 => X"76767676BA7676BA760016161616161616161616161616161616161616161A16",
INIT_77 => X"0000E8BA7676BA7676BA76762220767676767676BA7676760000EE7676767600",
INIT_78 => X"16161A161616161616161616161A1616161200322060004676767676767676EE",
INIT_79 => X"0246161616161616161616161A1616161A1616161616161A16161A161A161616",
INIT_7A => X"76BA7600007676BA7676767676BA76AA0000BA00767600BA7676767676767676",
INIT_7B => X"161616161616161A1600322032A000327676BA7676BA7676BA20003276767676",
INIT_7C => X"161A1616161A16161616161616161616161616161616161616161A1616161A16",
INIT_7D => X"76BA767676327632000000000076767676BA7676BA76760002020000161A161A",
INIT_7E => X"16003260A666607676767676767676767676000032BA76767676000076767676",
INIT_7F => X"161616161A16161A1616161A16161A161616161A161616161A161A1616161616",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFFFEF80000000000013FFC07FFFFFF88000000000000BFFE61FFFFFFC0000",
INITP_01 => X"000000E7FFFFFFFFFFFC00000000000047FFCFFFFFFFFF80000000000003FFE1",
INITP_02 => X"FFF000000000000001FFF87FFFFFF800000000000000FFFEFFFFFFFE00000000",
INITP_03 => X"0001FF56FE0FFF0000000000000001FFA37FFFFFC000000000000001FFE53FFF",
INITP_04 => X"0000000000000003FDFB0003F80000000000000003FEBDE007FE000000000000",
INITP_05 => X"03EC000000400000000000000003F6000001E00000000000000003FBC00001F0",
INITP_06 => X"00000000000001A0000000000000000000000003D80000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000003000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"76767676767676BA76767676767600000000000016161616161616161616161A",
INIT_01 => X"7676BA7676BA767676767600EE7676EE0000AA76BA76767676767676BA763276",
INIT_02 => X"16161616161616161616161616161A161616161A1616161A000000A020A03276",
INIT_03 => X"76BA7676BA00E82076000000161616161A1616161A1616161616161616161616",
INIT_04 => X"7676EE0000000000002A767676BA7676BA76767676BA767676BA76BA76767676",
INIT_05 => X"1A16161A16161616161616161A16161600000032E00276BA76767676767676BA",
INIT_06 => X"76AA0016161A1616161A161616161616161A16161A16161A16161A16161A1616",
INIT_07 => X"76BA767676767676BA7676767676BA76767676BA767676767676760076BA7676",
INIT_08 => X"1616161616161616160000A022A0767676BA7676BA76767676BA76000000EE32",
INIT_09 => X"161616161A16161616161616161616161616161616161616161616161616161A",
INIT_0A => X"7676BA767676767676767676BA76BA7676767676767676BA76001A1616161616",
INIT_0B => X"0076AA2000767676767676767676BA767676AAAA32BA76BA76767676BA767676",
INIT_0C => X"1A1616161A16161A16161A16161A16161A1616161A1616161A1616161A161A16",
INIT_0D => X"76767676767676767676762ABA76000016161616161A1616161A161616161616",
INIT_0E => X"BA7676767676767676BA76767676767676BA767676767676BA7676767676BA76",
INIT_0F => X"1616161616161616161A161616161616161A16161616160032762A22AA767676",
INIT_10 => X"6600200000001616161A161616161A161616161616161616161A161616161616",
INIT_11 => X"7676BA767676BA76767676BA76BA76767676BA76767676BA7676767676BA76EE",
INIT_12 => X"1616161A161616161616161616160000BA76BA7676BA767676BA7676BA76BAE8",
INIT_13 => X"161A1616161616161A161616161A16161616161A1616161A16161A16161A1616",
INIT_14 => X"76767676767676767676BA7676767676BA76BA7676EE000020200020161A1616",
INIT_15 => X"161A161A16160032767676767676767676767676760020000076767676767676",
INIT_16 => X"1616161616161616161616161A161616161616161616161616161616161A1616",
INIT_17 => X"76767676BA767676767676326000202000001616161616161616161A16161616",
INIT_18 => X"7676BA7676BA767676BA76000032007600EE76BA7676BA76BA7676767676BA76",
INIT_19 => X"1A16161616161A16161A1616161A161A16161A1616161A161616161616160076",
INIT_1A => X"767600002060600016161A16161A1616161A16161A1616161A16161616161A16",
INIT_1B => X"76007600EE007676007676767676767676BA76BA767676767676BA7676767676",
INIT_1C => X"16161A1616161616161616161616161616161A161600EEBA767676767676BA76",
INIT_1D => X"1616161616161A1616161616161A161616161A16161616161616161616161616",
INIT_1E => X"7676BA76767676EEAAEEEEEE76BA76BA76767676BA76BA76EE00200020200016",
INIT_1F => X"161A1616161A161A1616161A1600EE767676BA7676767676007600320032BA00",
INIT_20 => X"16161616161616161616161A1616161A161A1616161A16161616161616161A16",
INIT_21 => X"000000606632767676767676767676200020202000161A16161A161616161616",
INIT_22 => X"16161616160076BA7676767676BA7600BAE8BA7676760076767676EEA0000000",
INIT_23 => X"161616161616161616161A1616161A161616161A1616161616161A1616161616",
INIT_24 => X"76BA767676EE0060A02000661616161616161A16161A16161A161A1616161616",
INIT_25 => X"7676BA7676760076BA7676767600BA76A0000000206020202060000000A02A76",
INIT_26 => X"16161616161616161A16161616161A16161616161616161A16161A1616007676",
INIT_27 => X"0016161A16161A161616161616161616161616161A161616161A16161A161616",
INIT_28 => X"7632002000AA46002020202020002020202020200020AA767676BA7666002000",
INIT_29 => X"1616161A1616161616161A161616161616161616160076BA7676767676007676",
INIT_2A => X"161A16161A161616161A161616161A1616161616161A161616161A1616161A16",
INIT_2B => X"2020202020202020202060200000002A76767660202000201616161616161616",
INIT_2C => X"1616161A16161A16161A16161600767676BA76760076BAE82000000000002060",
INIT_2D => X"16161616161616161A16161616161A161616161A161616161A161616161A161A",
INIT_2E => X"0000000000002066EE2A00200000161A16161A1616161A161616161616161A16",
INIT_2F => X"16161A161600767676BA76007676200020000000002020000060206000602020",
INIT_30 => X"161A161616161A16161616161616161616161616161616161616161616161616",
INIT_31 => X"00600000161616161616161A161616161A16161A161616161616161616161616",
INIT_32 => X"767600BA32002020200000206000202020202020000000001616161616161600",
INIT_33 => X"16161A16161A16161A161A16161616161A16161A16161A161616161A16007676",
INIT_34 => X"16161616161616161616161616161A161616161A161A161616161A161616161A",
INIT_35 => X"2020202020600020000000161616161616161A1616161616161616161616161A",
INIT_36 => X"1616161A161A16161616161616161616161616161600EE76760076A000202020",
INIT_37 => X"1A16161A16161616161616161616161616161616161616161616161616161616",
INIT_38 => X"161616161A161A161616161A1616161A16161A161A16161616161A161A161616",
INIT_39 => X"1616161A16161A1616161A16160076BA00460020202000000020602020000016",
INIT_3A => X"161616161A161A16161A16161A16161A16161A16161A1616161616161616161A",
INIT_3B => X"161616161A161616161616161616161A16161616161A161616161616161A1616",
INIT_3C => X"1616161A1600002200000020602000200000001616161616161A161616161A16",
INIT_3D => X"1616161616161616161616161616161A16161616161616161A1616161616161A",
INIT_3E => X"161616161A16161616161616161616161A16161616161616161A161616161616",
INIT_3F => X"20002020200000166616161616161A1616161616161616161A1616161616161A",
INIT_40 => X"161A16161A1616161A161A161A1616161616161A161616161616161616000000",
INIT_41 => X"161A1616161A1616161A16161616161616161616161A16161A16161A16161A16",
INIT_42 => X"1A161A1616161616161A161616161A16161616161A1616161A1616161616161A",
INIT_43 => X"16161616161616161A1616161616161A1616161616AA00006060200000161616",
INIT_44 => X"16161A1616161A16161A16161616161616161616161616161616161616161616",
INIT_45 => X"16161A16161616161A16161616161616161A16161A16161616161A1616161616",
INIT_46 => X"16161A161A1616161A161A1616600000202000166A1A16161616161A16161A16",
INIT_47 => X"16161A16161A16161A16161A16161A16161A16161A1616161616161A161A1616",
INIT_48 => X"1A1616161A161616161616161616161616161616161A16161616161616161616",
INIT_49 => X"1616161A160020600020161A16161616161616161616161616161A1616161616",
INIT_4A => X"16161616161616161616161616161A161A161616161616161616161616161616",
INIT_4B => X"1A1616161A161A1616161A1616161A1616161616161A16161616161616161616",
INIT_4C => X"16161616161A161A16161A1616161A16161616161A161616161A1616161A1616",
INIT_4D => X"1A16161A1616161616161616161A161A16161616161A16161616161616000046",
INIT_4E => X"161616161616161A1616161616161A16161A16161A16161A16161A16161A1616",
INIT_4F => X"1616161A1616161616161A16161616161616161616161616161A16161616161A",
INIT_50 => X"1A161A16161616161A161A1616161A161616161616161616161A161616161616",
INIT_51 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_52 => X"161616161A1616161A1616161A1616161616161616161616161A161616161616",
INIT_53 => X"161616161616161A161A1616161616161616161616161A1616161616161A161A",
INIT_54 => X"161A16161A16161A16161A16161A16161A16161A161A16161616161616161616",
INIT_55 => X"161616161616161616161616161616161616161616161616161A1616161A1616",
INIT_56 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_57 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_58 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_59 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_5A => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_5B => X"0000000000001616161616161616161616161616161616161616161616161616",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_tex_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_tex_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_tex_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_tex_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_tex_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.bg_tex_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena_array(0) => ena_array(0)
);
\has_mux_a.A\: entity work.bg_tex_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[2].ram.r_n_8\,
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(11 downto 3)
);
\ramloop[0].ram.r\: entity work.bg_tex_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[2].ram.r_n_0\,
\douta[10]\(6) => \ramloop[2].ram.r_n_1\,
\douta[10]\(5) => \ramloop[2].ram.r_n_2\,
\douta[10]\(4) => \ramloop[2].ram.r_n_3\,
\douta[10]\(3) => \ramloop[2].ram.r_n_4\,
\douta[10]\(2) => \ramloop[2].ram.r_n_5\,
\douta[10]\(1) => \ramloop[2].ram.r_n_6\,
\douta[10]\(0) => \ramloop[2].ram.r_n_7\,
\douta[11]\(0) => \ramloop[2].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[4].ram.r_n_0\,
\douta[10]\(6) => \ramloop[4].ram.r_n_1\,
\douta[10]\(5) => \ramloop[4].ram.r_n_2\,
\douta[10]\(4) => \ramloop[4].ram.r_n_3\,
\douta[10]\(3) => \ramloop[4].ram.r_n_4\,
\douta[10]\(2) => \ramloop[4].ram.r_n_5\,
\douta[10]\(1) => \ramloop[4].ram.r_n_6\,
\douta[10]\(0) => \ramloop[4].ram.r_n_7\,
\douta[11]\(0) => \ramloop[4].ram.r_n_8\,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_tex_blk_mem_gen_top;
architecture STRUCTURE of bg_tex_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_tex_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_tex_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_tex_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_tex_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_tex_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_tex_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_tex_blk_mem_gen_v8_3_5 : entity is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_tex_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_tex_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_tex_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_tex_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.22775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_tex_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_tex_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_tex_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_tex_blk_mem_gen_v8_3_5 : entity is "bg_tex.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_tex_blk_mem_gen_v8_3_5 : entity is "bg_tex.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_tex_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_tex_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_tex_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_tex_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_tex_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_tex_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_tex_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_tex_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_tex_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_tex_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_tex : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_tex : entity is "bg_tex,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_tex : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_tex : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_tex;
architecture STRUCTURE of bg_tex is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.22775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_tex.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_tex.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 11130;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 11130;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 11130;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 11130;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_tex_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 68067f2b5dbfc93943f89e2ba0f111a3 | 0.720281 | 3.317367 | false | false | false | false |
kgugala/axi-coprocessor-interface-hw | project_1.srcs/sources_1/edk/module_1/pcores/coprocessor_v2_00_a/hdl/vhdl/user_logic.vhd | 1 | 24,413 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 2.00.a
-- Description: User logic.
-- Date: Sat Nov 23 17:12:23 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
-- Author: Karol Gugala <[email protected]>
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_MEM -- Number of memory spaces
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select for user logic memory selection
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_BurstLength -- Bus to IP burst length
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- Type_of_xfer -- Transfer Type
-- IP2Bus_AddrAck -- IP to Bus address acknowledgement
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- Bus protocol parameters, do not add to or delete
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_NUM_MEM : integer := 3
);
port
(
led_out : out std_logic_vector(7 downto 0);
sw_in : in std_logic_vector(7 downto 0);
btn_in : in std_logic_vector(4 downto 0);
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Addr : in std_logic_vector(C_SLV_AWIDTH-1 downto 0);
Bus2IP_CS : in std_logic_vector(C_NUM_MEM-1 downto 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_MEM-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_MEM-1 downto 0);
Bus2IP_Burst : in std_logic;
Bus2IP_BurstLength : in std_logic_vector(7 downto 0);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
Type_of_xfer : in std_logic;
IP2Bus_AddrAck : out std_logic;
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
component student_logic
port(
clk : in std_logic;
reset_n : in std_logic;
-- hardware interface
btn_in : in std_logic_vector(4 downto 0);
sw_in : in std_logic_vector(7 downto 0);
led_out : out std_logic_vector(7 downto 0);
-- fifo control
fifo_in_transfer : in std_logic;
fifo_out_transfer : in std_logic;
read_en : out std_logic;
write_en : out std_logic;
in_fifo_empty : in std_logic;
in_fifo_full : in std_logic;
out_fifo_empty : in std_logic;
out_fifo_full : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
-- registers
user_reg0 : inout std_logic_vector(31 downto 0);
user_reg1 : inout std_logic_vector(31 downto 0);
user_reg2 : inout std_logic_vector(31 downto 0);
user_reg3 : inout std_logic_vector(31 downto 0);
user_reg4 : inout std_logic_vector(31 downto 0);
user_reg5 : inout std_logic_vector(31 downto 0));
end component;
-- FIFO from core gen
COMPONENT fifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
signal FIFO_In_Data_In : std_logic_vector(31 downto 0);
signal FIFO_In_Data_Out : std_logic_vector(31 downto 0);
signal FIFO_In_Empty : std_logic;
signal FIFO_In_Full : std_logic;
signal FIFO_In_Write_Enable : std_logic;
signal FIFO_In_Read_Enable : std_logic;
signal FIFO_Out_Data_In : std_logic_vector(31 downto 0);
signal FIFO_Out_Data_Out : std_logic_vector(31 downto 0);
signal FIFO_Out_Empty : std_logic;
signal FIFO_Out_Full : std_logic;
signal FIFO_Out_Write_Enable : std_logic;
signal FIFO_Out_Read_Enable : std_logic;
------------------------------------------
-- Registers
------------------------------------------
signal reg0 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg1 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg2 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg3 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg4 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg5 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg6 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg7 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg8 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal reg9 : std_logic_vector (C_SLV_DWIDTH-1 downto 0) := (others => '0');
------------------------------------------
signal FIFO_reset : std_logic;
signal Copy_In_Data_2_FIFO : std_logic;
signal Copy_FIFO_Data_2_Out : std_logic;
signal FIFO_In_Copying : std_logic;
signal FIFO_Out_Copying : std_logic;
------------------------------------------
-- copying FSM's signals
------------------------------------------
signal In_data_amount: integer range 0 to 511 := 0;
signal In_FIFO_address: integer range 0 to 512 := 0;
signal In_FIFO_state: integer range 0 to 3:= 0;
signal Out_FIFO_address: integer range 0 to 511 := 0;
signal Out_FIFO_state: integer range 0 to 2:= 0;
signal mem_2_FIFO_address: std_logic_vector(8 downto 0);
signal FIFO_2_mem_address: std_logic_vector(8 downto 0);
------------------------------------------
-- RAM data routing
------------------------------------------
type ram_address is array (0 to 1) of std_logic_vector(8 downto 0);
signal mem_read_address : ram_address;
signal mem_write_address: ram_address;
type ram_input is array (0 to 1) of std_logic_vector(31 downto 0);
signal mem_input : ram_input;
type ram_write_enable is array (0 to 1) of std_logic_vector(0 to 3);
signal mem_write_enable : ram_write_enable;
------------------------------------------
-- Signals for user logic memory space example
------------------------------------------
type BYTE_RAM_TYPE is array (0 to 511) of std_logic_vector(7 downto 0);
type DO_TYPE is array (0 to C_NUM_MEM-1) of std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal mem_data_out : DO_TYPE;
signal mem_address : std_logic_vector(8 downto 0);
signal mem_select : std_logic_vector(0 to 2);
signal mem_read_enable : std_logic;
signal mem_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal mem_read_ack_dly1 : std_logic;
signal mem_read_ack_dly2 : std_logic;
signal mem_read_ack : std_logic;
signal mem_write_ack : std_logic;
begin
------------------------------------------
mem_select <= Bus2IP_CS;
mem_read_enable <= ( Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) );
mem_read_ack <= mem_read_ack_dly1 and (not mem_read_ack_dly2);
mem_write_ack <= ( Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) );
mem_address <= Bus2IP_Addr(10 downto 2);
-- RAM input data, read and write addresses
-- Mem 1 is writeble from Bus and readable by internal logic
-- Mem 2 is writeble by internal logic and readable from Bus
mem_read_address(0) <= mem_2_FIFO_address;
mem_read_address(1) <= mem_address;
mem_write_address(0) <= mem_address;
mem_write_address(1) <= FIFO_2_mem_address;
mem_input(0) <= Bus2IP_Data;
mem_input(1) <= FIFO_Out_Data_Out;
mem_write_enable(0)(0) <= (Bus2IP_WrCE(1) and Bus2IP_BE(0));
mem_write_enable(0)(1) <= (Bus2IP_WrCE(1) and Bus2IP_BE(1));
mem_write_enable(0)(2) <= (Bus2IP_WrCE(1) and Bus2IP_BE(2));
mem_write_enable(0)(3) <= (Bus2IP_WrCE(1) and Bus2IP_BE(3));
mem_write_enable(1)(0) <= FIFO_Out_Read_Enable;
mem_write_enable(1)(1) <= FIFO_Out_Read_Enable;
mem_write_enable(1)(2) <= FIFO_Out_Read_Enable;
mem_write_enable(1)(3) <= FIFO_Out_Read_Enable;
-- this process generates the read acknowledge 1 clock after read enable
-- is presented to the BRAM block. The BRAM block has a 1 clock delay
-- from read enable to data out.
BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Resetn = '0' ) then
mem_read_ack_dly1 <= '0';
mem_read_ack_dly2 <= '0';
else
mem_read_ack_dly1 <= mem_read_enable;
mem_read_ack_dly2 <= mem_read_ack_dly1;
end if;
end if;
end process BRAM_RD_ACK_PROC;
-- implement registers write
reg_write : process ( Bus2IP_Clk ) is
begin
if ( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Resetn = '0') then
reg0 <= (others => '0');
--reg1 <= (others => '0');
reg2 <= (others => '0');
--reg3 <= (others => '0');
reg4 <= (others => '0');
reg5 <= (others => '0');
reg6 <= (others => '0');
reg7 <= (others => '0');
reg8 <= (others => '0');
reg9 <= (others => '0');
else
if( Bus2IP_WrCE(0) = '1') then
case mem_address is
when "000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- reg1 is read only
--when "000000001" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- reg3 read only
--when "000000011" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000101" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000110" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000111" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000001001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- implement registers read
reg_read: process( Bus2IP_RdCE(0), mem_address, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9)
begin
if(Bus2IP_RdCE(0) = '1') then
case mem_address is
when "000000000" => mem_data_out(0) <= reg0;
when "000000001" => mem_data_out(0) <= reg1;
when "000000010" => mem_data_out(0) <= reg2;
when "000000011" => mem_data_out(0) <= reg3;
when "000000100" => mem_data_out(0) <= reg4;
when "000000101" => mem_data_out(0) <= reg5;
when "000000110" => mem_data_out(0) <= reg6;
when "000000111" => mem_data_out(0) <= reg7;
when "000001000" => mem_data_out(0) <= reg8;
when "000001001" => mem_data_out(0) <= reg9;
when others => mem_data_out(0) <= (others => '0');
end case;
end if;
end process;
-- implement Block RAM(s)
BRAM_GEN : for i in 1 to C_NUM_MEM-1 generate
constant NUM_BYTE_LANES : integer := (C_SLV_DWIDTH+7)/8;
begin
BYTE_BRAM_GEN : for byte_index in 0 to NUM_BYTE_LANES-1 generate
signal ram : BYTE_RAM_TYPE;
signal write_enable : std_logic;
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal read_address : std_logic_vector(8 downto 0);
begin
write_enable <= mem_write_enable(i-1)(byte_index);
data_in <= mem_input(i-1)(byte_index*8+7 downto byte_index*8);
BYTE_RAM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( write_enable = '1' ) then
ram(CONV_INTEGER(mem_write_address(i-1))) <= data_in;
end if;
read_address <= mem_read_address(i-1);
end if;
end process BYTE_RAM_PROC;
data_out <= ram(CONV_INTEGER(read_address));
mem_data_out(i)(byte_index*8+7 downto byte_index*8) <= data_out;
end generate BYTE_BRAM_GEN;
end generate BRAM_GEN;
-- implement Block RAM read mux
MEM_IP2BUS_DATA_PROC : process( mem_data_out, mem_select ) is
begin
case mem_select is
when "001" => mem_ip2bus_data <= mem_data_out(0);
--when "010" => mem_ip2bus_data <= mem_data_out(1);
when "100" => mem_ip2bus_data <= mem_data_out(2);
when others => mem_ip2bus_data <= (others => '0');
end case;
end process MEM_IP2BUS_DATA_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= mem_ip2bus_data when mem_read_ack = '1' else
(others => '0');
IP2Bus_AddrAck <= mem_write_ack or (mem_read_enable and mem_read_ack);
IP2Bus_WrAck <= mem_write_ack;
IP2Bus_RdAck <= mem_read_ack;
IP2Bus_Error <= '0';
------------------------------------------
-- FIFO logic
------------------------------------------
Copy_In_Data_2_FIFO <= reg0(0);
Copy_FIFO_Data_2_Out <= reg0(1);
mem_2_FIFO_address <= CONV_STD_LOGIC_VECTOR(In_FIFO_Address, 9);
reg3(8 downto 0) <= mem_2_FIFO_Address;
FIFO_2_mem_address <= CONV_STD_LOGIC_VECTOR(Out_FIFO_Address, 9);
reg3(17 downto 9) <= FIFO_2_mem_address;
reg1 <= CONV_STD_LOGIC_VECTOR(0, 26) & FIFO_Out_Copying & FIFO_Out_Full & FIFO_Out_Empty & FIFO_In_Copying & FIFO_In_Full & FIFO_In_Empty;
copy_to_fifo: process(Bus2IP_Clk)
begin
if( rising_edge(Bus2IP_Clk) ) then
case In_FIFO_State is
when 0 =>
if(Copy_In_Data_2_FIFO = '1') then
FIFO_In_Copying <= '1';
In_FIFO_Address <= 0;
In_FIFO_State <= 1;
In_Data_Amount <= CONV_INTEGER(reg2(8 downto 0));
end if;
when 1 =>
if(FIFO_In_Full = '0' and In_FIFO_Address < In_Data_Amount) then
FIFO_In_Write_Enable <='1';
In_FIFO_Address <= In_FIFO_Address + 1;
else
In_FIFO_State <= 2;
end if;
when 2 => --clock cycle for the last data
In_FIFO_State <= 3;
FIFO_In_Write_Enable <= '0';
when 3 =>
FIFO_In_Copying <= '0';
if( Copy_In_Data_2_FIFO = '0') then
In_FIFO_State <= 0;
end if;
end case;
end if;
end process;
copy_to_mem: process(Bus2IP_Clk)
begin
if( rising_edge(Bus2IP_Clk) ) then
case Out_FIFO_State is
when 0 =>
if(Copy_FIFO_Data_2_Out = '1') then
FIFO_Out_Copying <= '1';
Out_FIFO_Address <= 0;
FIFO_Out_Read_Enable <= '1';
Out_FIFO_State <= 1;
end if;
when 1 =>
--if out fifo is not empty and we did not reach last address
if(FIFO_Out_Empty = '0' and Out_FIFO_Address < 511) then
Out_FIFO_Address <= Out_FIFO_Address + 1;
else
FIFO_Out_Read_Enable <= '0';
Out_FIFO_State <= 2;
end if;
when 2 =>
--if Out fifo address is not at the last position we need to decrement
--it, because the software expects (n-1)*4 number of bytes
if(Out_FIFO_Address /= 511 and FIFO_Out_Copying = '1') then
Out_FIFO_Address <= Out_FIFO_Address - 1;
end if;
FIFO_Out_Copying <= '0';
if( Copy_FIFO_Data_2_Out = '0') then
Out_FIFO_State <= 0;
--Out_FIFO_Address <= Out_FIFO_Address - 1;
end if;
end case;
end if;
end process;
--fifo reset is driven high
FIFO_reset <= not Bus2IP_Resetn;
FIFO_In_Inst : fifo
PORT MAP (
clk => Bus2IP_Clk,
rst => FIFO_reset,
din => mem_data_out(1),--FIFO_In_Data_In,
wr_en => FIFO_In_Write_Enable,
rd_en => FIFO_In_Read_Enable,
dout => FIFO_In_Data_Out,
full => open,
empty => FIFO_In_Empty,
prog_full => FIFO_In_Full
);
FIFO_Out_Inst : fifo
PORT MAP (
clk => Bus2IP_Clk,
rst => FIFO_reset,
din => FIFO_Out_Data_In,
wr_en => FIFO_Out_Write_Enable,
rd_en => FIFO_Out_Read_Enable,
dout => FIFO_Out_Data_Out,
full => open,
empty => FIFO_Out_Empty,
prog_full => FIFO_Out_Full
);
student_logic_inst: student_logic port map(
clk => Bus2IP_Clk,
reset_n => Bus2IP_Resetn,
-- hardware interface
btn_in => btn_in,
led_out => led_out,
sw_in => sw_in,
--fifo
fifo_in_transfer => FIFO_In_Copying,
fifo_out_transfer => FIFO_Out_Copying,
read_en => FIFO_IN_Read_Enable,
write_en => FIFO_OUT_Write_Enable,
in_fifo_empty => FIFO_IN_Empty,
in_fifo_full => FIFO_IN_Full,
out_fifo_empty => FIFO_OUT_Empty,
out_fifo_full => FIFO_OUT_Full,
data_in => FIFO_IN_Data_Out,
data_out => FIFO_OUT_Data_In,
--user registers
user_reg0 => reg4,
user_reg1 => reg5,
user_reg2 => reg6,
user_reg3 => reg7,
user_reg4 => reg8,
user_reg5 => reg9);
end IMP;
| mit | 2edd4df029518adfe6a1958d2dd7c07b | 0.519191 | 3.307995 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev113.vhd | 1 | 31,011 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev113 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev113 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
--constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
--constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
--constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
--constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
--constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
--constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDIXD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : integer;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2 = LDIXD) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when ((Opcode3=RETI or Opcode3 = LDIXD) and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2=LDIXD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= 0;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
wout <= std_logic_vector(mvect(rcount));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
-- elsif (Opcode2= MLOAD0) then
-- mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
-- mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
-- mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
-- mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
-- elsif (Opcode2= MLOAD1) then
-- mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
-- mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
-- mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
-- mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
-- elsif (Opcode2= MLOAD2) then
-- mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
-- mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
-- mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
-- mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
-- elsif (Opcode2= MLOAD3) then
-- mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
-- mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
-- mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
-- mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
elsif (Opcode2 = LDIXD) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2 = LDIXD) then
mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))(63 downto 32) <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=LDIXD) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY3))))
+ (unsigned(M3) + 1));
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3=LDIXD) then
mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX3))))))(31 downto 0) <= MEM_in;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 3420482a18a9bddc6f6d3c187f42943c | 0.6261 | 2.827923 | false | false | false | false |
kgugala/axi-coprocessor-interface-hw | project_1.srcs/sources_1/edk/module_1/module_1_stub.vhd | 1 | 5,296 | -------------------------------------------------------------------------------
-- module_1_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity module_1_stub is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
coprocessor_0_LED_OUT_pin : out std_logic_vector(7 downto 0);
coprocessor_0_SW_IN_pin : in std_logic_vector(7 downto 0);
coprocessor_0_BTN_IN_pin : in std_logic_vector(4 downto 0)
);
end module_1_stub;
architecture STRUCTURE of module_1_stub is
component module_1 is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
coprocessor_0_LED_OUT_pin : out std_logic_vector(7 downto 0);
coprocessor_0_SW_IN_pin : in std_logic_vector(7 downto 0);
coprocessor_0_BTN_IN_pin : in std_logic_vector(4 downto 0)
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of module_1 : component is "user_black_box";
begin
module_1_i : module_1
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
coprocessor_0_LED_OUT_pin => coprocessor_0_LED_OUT_pin,
coprocessor_0_SW_IN_pin => coprocessor_0_SW_IN_pin,
coprocessor_0_BTN_IN_pin => coprocessor_0_BTN_IN_pin
);
end architecture STRUCTURE;
| mit | 1f177bbb6c0d9b173d926accd58440c9 | 0.663708 | 3.139301 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/decoder.vhd | 13 | 3,366 | ----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
| mit | e5c0fe3257f5b65861125b0c217f7015 | 0.582294 | 3.379518 | false | false | false | false |
kgugala/axi-coprocessor-interface-hw | project_1.srcs/sources_1/edk/module_1/hdl/module_1.vhd | 1 | 90,004 | -------------------------------------------------------------------------------
-- module_1.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity module_1 is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
coprocessor_0_LED_OUT_pin : out std_logic_vector(7 downto 0);
coprocessor_0_SW_IN_pin : in std_logic_vector(7 downto 0);
coprocessor_0_BTN_IN_pin : in std_logic_vector(4 downto 0)
);
end module_1;
architecture STRUCTURE of module_1 is
component module_1_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(5 downto 0);
S_AXI_HP0_RID : out std_logic_vector(5 downto 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP0_WID : in std_logic_vector(5 downto 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(0 to 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component module_1_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(11 downto 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(0 to 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(11 downto 0);
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(11 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(11 downto 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(0 to 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(11 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component module_1_coprocessor_0_wrapper is
port (
LED_OUT : out std_logic_vector(7 downto 0);
SW_IN : in std_logic_vector(7 downto 0);
BTN_IN : in std_logic_vector(4 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RLAST : out std_logic
);
end component;
-- Internal signals
signal axi_interconnect_1_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARESETN : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(0 to 0);
signal coprocessor_0_BTN_IN : std_logic_vector(4 downto 0);
signal coprocessor_0_LED_OUT : std_logic_vector(7 downto 0);
signal coprocessor_0_SW_IN : std_logic_vector(7 downto 0);
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_PS_SRSTB : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of module_1_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of module_1_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of module_1_coprocessor_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_PS_SRSTB <= processing_system7_0_PS_SRSTB_pin;
processing_system7_0_PS_CLK <= processing_system7_0_PS_CLK_pin;
processing_system7_0_PS_PORB <= processing_system7_0_PS_PORB_pin;
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
coprocessor_0_LED_OUT_pin <= coprocessor_0_LED_OUT;
coprocessor_0_SW_IN <= coprocessor_0_SW_IN_pin;
coprocessor_0_BTN_IN <= coprocessor_0_BTN_IN_pin;
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
processing_system7_0 : module_1_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => net_gnd0,
I2C0_SDA_O => open,
I2C0_SDA_T => open,
I2C0_SCL_I => net_gnd0,
I2C0_SCL_O => open,
I2C0_SCL_T => open,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi_interconnect_1_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi_interconnect_1_S_AWVALID(0),
M_AXI_GP0_BREADY => axi_interconnect_1_S_BREADY(0),
M_AXI_GP0_RREADY => axi_interconnect_1_S_RREADY(0),
M_AXI_GP0_WLAST => axi_interconnect_1_S_WLAST(0),
M_AXI_GP0_WVALID => axi_interconnect_1_S_WVALID(0),
M_AXI_GP0_ARID => axi_interconnect_1_S_ARID,
M_AXI_GP0_AWID => axi_interconnect_1_S_AWID,
M_AXI_GP0_WID => axi_interconnect_1_S_WID,
M_AXI_GP0_ARBURST => axi_interconnect_1_S_ARBURST,
M_AXI_GP0_ARLOCK => axi_interconnect_1_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi_interconnect_1_S_ARSIZE,
M_AXI_GP0_AWBURST => axi_interconnect_1_S_AWBURST,
M_AXI_GP0_AWLOCK => axi_interconnect_1_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi_interconnect_1_S_AWSIZE,
M_AXI_GP0_ARPROT => axi_interconnect_1_S_ARPROT,
M_AXI_GP0_AWPROT => axi_interconnect_1_S_AWPROT,
M_AXI_GP0_ARADDR => axi_interconnect_1_S_ARADDR,
M_AXI_GP0_AWADDR => axi_interconnect_1_S_AWADDR,
M_AXI_GP0_WDATA => axi_interconnect_1_S_WDATA,
M_AXI_GP0_ARCACHE => axi_interconnect_1_S_ARCACHE,
M_AXI_GP0_ARLEN => axi_interconnect_1_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi_interconnect_1_S_ARQOS,
M_AXI_GP0_AWCACHE => axi_interconnect_1_S_AWCACHE,
M_AXI_GP0_AWLEN => axi_interconnect_1_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi_interconnect_1_S_AWQOS,
M_AXI_GP0_WSTRB => axi_interconnect_1_S_WSTRB,
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0(0),
M_AXI_GP0_ARREADY => axi_interconnect_1_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi_interconnect_1_S_AWREADY(0),
M_AXI_GP0_BVALID => axi_interconnect_1_S_BVALID(0),
M_AXI_GP0_RLAST => axi_interconnect_1_S_RLAST(0),
M_AXI_GP0_RVALID => axi_interconnect_1_S_RVALID(0),
M_AXI_GP0_WREADY => axi_interconnect_1_S_WREADY(0),
M_AXI_GP0_BID => axi_interconnect_1_S_BID,
M_AXI_GP0_RID => axi_interconnect_1_S_RID,
M_AXI_GP0_BRESP => axi_interconnect_1_S_BRESP,
M_AXI_GP0_RRESP => axi_interconnect_1_S_RRESP,
M_AXI_GP0_RDATA => axi_interconnect_1_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => open,
S_AXI_HP0_AWREADY => open,
S_AXI_HP0_BVALID => open,
S_AXI_HP0_RLAST => open,
S_AXI_HP0_RVALID => open,
S_AXI_HP0_WREADY => open,
S_AXI_HP0_BRESP => open,
S_AXI_HP0_RRESP => open,
S_AXI_HP0_BID => open,
S_AXI_HP0_RID => open,
S_AXI_HP0_RDATA => open,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => net_gnd0,
S_AXI_HP0_ARVALID => net_gnd0,
S_AXI_HP0_AWVALID => net_gnd0,
S_AXI_HP0_BREADY => net_gnd0,
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => net_gnd0,
S_AXI_HP0_WLAST => net_gnd0,
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => net_gnd0,
S_AXI_HP0_ARBURST => net_gnd2,
S_AXI_HP0_ARLOCK => net_gnd2,
S_AXI_HP0_ARSIZE => net_gnd3,
S_AXI_HP0_AWBURST => net_gnd2,
S_AXI_HP0_AWLOCK => net_gnd2,
S_AXI_HP0_AWSIZE => net_gnd3,
S_AXI_HP0_ARPROT => net_gnd3,
S_AXI_HP0_AWPROT => net_gnd3,
S_AXI_HP0_ARADDR => net_gnd32,
S_AXI_HP0_AWADDR => net_gnd32,
S_AXI_HP0_ARCACHE => net_gnd4,
S_AXI_HP0_ARLEN => net_gnd4,
S_AXI_HP0_ARQOS => net_gnd4,
S_AXI_HP0_AWCACHE => net_gnd4,
S_AXI_HP0_AWLEN => net_gnd4,
S_AXI_HP0_AWQOS => net_gnd4,
S_AXI_HP0_ARID => net_gnd6,
S_AXI_HP0_AWID => net_gnd6,
S_AXI_HP0_WID => net_gnd6,
S_AXI_HP0_WDATA => net_gnd64,
S_AXI_HP0_WSTRB => net_gnd8,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => net_gnd1(0 to 0),
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
axi_interconnect_1 : module_1_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi_interconnect_1_M_ARESETN(0 to 0),
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => axi_interconnect_1_S_AWID,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => axi_interconnect_1_S_AWLOCK,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => axi_interconnect_1_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY(0 to 0),
S_AXI_WID => axi_interconnect_1_S_WID,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi_interconnect_1_S_WVALID(0 to 0),
S_AXI_WREADY => axi_interconnect_1_S_WREADY(0 to 0),
S_AXI_BID => axi_interconnect_1_S_BID,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID(0 to 0),
S_AXI_BREADY => axi_interconnect_1_S_BREADY(0 to 0),
S_AXI_ARID => axi_interconnect_1_S_ARID,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => axi_interconnect_1_S_ARLOCK,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => axi_interconnect_1_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY(0 to 0),
S_AXI_RID => axi_interconnect_1_S_RID,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_1_S_RREADY(0 to 0),
M_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
M_AXI_AWID => axi_interconnect_1_M_AWID,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_1_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_1_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_1_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_1_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_1_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_1_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0 to 0),
M_AXI_WID => open,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => axi_interconnect_1_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_1_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_1_M_BID,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_1_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_1_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_1_M_ARID,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_1_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_1_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_1_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_1_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_1_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_1_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_1_M_RID,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => axi_interconnect_1_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_1_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_1_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
coprocessor_0 : module_1_coprocessor_0_wrapper
port map (
LED_OUT => coprocessor_0_LED_OUT,
SW_IN => coprocessor_0_SW_IN,
BTN_IN => coprocessor_0_BTN_IN,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi_interconnect_1_M_ARESETN(0),
S_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
S_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_WDATA => axi_interconnect_1_M_WDATA,
S_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
S_AXI_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
S_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_RDATA => axi_interconnect_1_M_RDATA,
S_AXI_RRESP => axi_interconnect_1_M_RRESP,
S_AXI_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_BRESP => axi_interconnect_1_M_BRESP,
S_AXI_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXI_AWID => axi_interconnect_1_M_AWID,
S_AXI_AWLEN => axi_interconnect_1_M_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_M_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_M_AWBURST,
S_AXI_AWLOCK => axi_interconnect_1_M_AWLOCK(0),
S_AXI_AWCACHE => axi_interconnect_1_M_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_M_AWPROT,
S_AXI_WLAST => axi_interconnect_1_M_WLAST(0),
S_AXI_BID => axi_interconnect_1_M_BID,
S_AXI_ARID => axi_interconnect_1_M_ARID,
S_AXI_ARLEN => axi_interconnect_1_M_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_M_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_M_ARBURST,
S_AXI_ARLOCK => axi_interconnect_1_M_ARLOCK(0),
S_AXI_ARCACHE => axi_interconnect_1_M_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_M_ARPROT,
S_AXI_RID => axi_interconnect_1_M_RID,
S_AXI_RLAST => axi_interconnect_1_M_RLAST(0)
);
end architecture STRUCTURE;
| mit | 9b3ef6d759baa27831e4e2f6bd18635f | 0.598929 | 2.881696 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/sid_6581.vhd | 13 | 16,739 | -------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | a9cb96ae242f56cbea7387c35c26c906 | 0.558516 | 2.833757 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_pokey.vhd | 13 | 19,476 | --
-- A simulation model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 002 return 00 on allpot when fast scan completed to fix self test
-- version 001 initial release (this version should be considered Beta
-- it seems to make all the right sort of sounds however ... )
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_pokey is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
data_out: out std_logic_vector(7 downto 0) --Digital data out - this should be fed into an audio mixer or Delta-Sigma DAC.
);
end;
architecture RTL of AUDIO_zpuino_wb_pokey is
type array_8x8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array_4x8 is array (1 to 4) of std_logic_vector(7 downto 0);
type array_4x4 is array (1 to 4) of std_logic_vector(3 downto 0);
type array_4x9 is array (1 to 4) of std_logic_vector(8 downto 0);
type array_2x17 is array (1 to 2) of std_logic_vector(16 downto 0);
type bool_4 is array (1 to 4) of boolean;
--signal oe : std_logic;
--
signal ena : std_logic;
signal ena_64k_15k : std_logic;
signal cnt_64k : std_logic_vector(4 downto 0) := (others => '0');
signal ena_64k : std_logic;
signal cnt_15k : std_logic_vector(6 downto 0) := (others => '0');
signal ena_15k : std_logic;
--
signal poly4 : std_logic_vector(3 downto 0) := (others => '0');
signal poly5 : std_logic_vector(4 downto 0) := (others => '0');
signal poly9 : std_logic_vector(8 downto 0) := (others => '0');
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
signal poly_17_9 : std_logic;
-- registers wb_dat_i
signal audf : array_4x8 := (x"00",x"00",x"00",x"00");
signal audc : array_4x8 := (x"00",x"00",x"00",x"00");
signal audctl : std_logic_vector(7 downto 0) := "00000000";
signal stimer : std_logic_vector(7 downto 0);
signal skres : std_logic_vector(7 downto 0);
signal potgo : std_logic;
signal serout : std_logic_vector(7 downto 0);
signal irqen : std_logic_vector(7 downto 0);
signal skctls : std_logic_vector(7 downto 0);
--signal reset : std_logic;
--
-- registers wb_dat_o
--signal kbcode : std_logic_vector(7 downto 0);
signal random : std_logic_vector(7 downto 0);
--signal serin : std_logic_vector(7 downto 0);
--signal irqst : std_logic_vector(7 downto 0);
--signal skstat : std_logic_vector(7 downto 0);
--
--
--signal pot_fin : std_logic;
--signal pot_cnt : std_logic_vector(7 downto 0);
--signal pot_val : array_8x8;
--signal pin_reg : std_logic_vector(7 downto 0);
--signal pin_reg_gated : std_logic_vector(7 downto 0);
--
signal chan_ena : std_logic_vector(4 downto 1);
signal tone_gen_div : std_logic_vector(4 downto 1);
signal tone_gen_cnt : array_4x8 := (others => (others => '0'));
signal tone_gen_div_mux : std_logic_vector(4 downto 1);
signal tone_gen_zero : std_logic_vector(4 downto 1);
signal tone_gen_zero_t : array_4x8 := (others => (others => '0'));
signal chan_done_load : std_logic_vector(4 downto 1) := (others => '0');
--
signal poly_sel : std_logic_vector(4 downto 1);
signal poly_sel_hp : std_logic_vector(4 downto 1);
signal poly_sel_hp_t1 : std_logic_vector(4 downto 1);
signal poly_sel_hp_reg : std_logic_vector(4 downto 1);
signal tone_gen_final : std_logic_vector(4 downto 1) := (others => '0');
signal o_audio : std_logic_vector(7 downto 0) := (others => '0');
-- clock divider
constant PRE_CLOCK_DIVIDER: integer := 54;
signal clk177: std_logic := '0';
signal predivcnt: integer;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- wishbone signals
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
ena <= '1';
data_out <= o_audio;
predivider: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
clk177 <= '0';
predivcnt <= PRE_CLOCK_DIVIDER;
else
clk177 <='0';
if predivcnt=0 then
clk177 <='1';
predivcnt <= PRE_CLOCK_DIVIDER;
else
predivcnt <= predivcnt -1 ;
end if;
end if;
end if;
end process;
p_dividers : process
begin
wait until rising_edge(wb_clk_i);
if clk177='1' then
if (ena = '1') then
ena_64k <= '0';
if cnt_64k = "00000" then
cnt_64k <= "11011"; -- 28 - 1
ena_64k <= '1';
else
cnt_64k <= cnt_64k - "1";
end if;
ena_15k <= '0';
if cnt_15k = "0000000" then
cnt_15k <= "1110001"; -- 114 - 1
ena_15k <= '1';
else
cnt_15k <= cnt_15k - "1";
end if;
end if;
end if;
end process;
p_ena_64k_15k : process(ena_64k, ena_15k, audctl)
begin
if (audctl(0) = '1') then
ena_64k_15k <= ena_15k;
else
ena_64k_15k <= ena_64k;
end if;
end process;
p_poly : process
variable poly9_zero : std_logic;
variable poly17_zero : std_logic;
begin
wait until rising_edge(wb_clk_i);
if (ena = '1') then
poly4 <= poly4(2 downto 0) & not (poly4(3) xor poly4(2));
poly5 <= poly5(3 downto 0) & not (poly5(4) xor poly4(2)); -- used inverted
-- not correct
poly9_zero := '0';
if (poly9 = "000000000") then poly9_zero := '1'; end if;
poly9 <= poly9(7 downto 0) & (poly9(8) xor poly9(3) xor poly9_zero);
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
poly17 <= poly17(15 downto 0) & (poly17(16) xor poly17(2) xor poly17_zero);
end if;
end process;
p_random_mux : process(audctl, poly9, poly17)
begin
-- bit unnecessary this ....
for i in 0 to 7 loop
if (audctl(7) = '1') then -- 9 bit poly
random(i) <= poly9(8-i);
else
random(i) <= poly17(16-i);
end if;
end loop;
if (audctl(7) = '1') then
poly_17_9 <= poly9(8);
else
poly_17_9 <= poly17(16);
end if;
end process;
p_wdata : process
begin
wait until rising_edge(wb_clk_i);
potgo <= '0';
--if (reset = '1') then
-- no idea what the reset state is
--audf <= (others => (others => '0'));
--audc <= (others => (others => '0'));
--audctl <= x"00";
--else
if (wb_we_i = '1' and wb_cyc_i='1' and wb_stb_i='1') then
case wb_adr_i(5 downto 2) is
when x"0" => audf(1) <= wb_dat_i(7 downto 0);
when x"1" => audc(1) <= wb_dat_i(7 downto 0);
when x"2" => audf(2) <= wb_dat_i(7 downto 0);
when x"3" => audc(2) <= wb_dat_i(7 downto 0);
when x"4" => audf(3) <= wb_dat_i(7 downto 0);
when x"5" => audc(3) <= wb_dat_i(7 downto 0);
when x"6" => audf(4) <= wb_dat_i(7 downto 0);
when x"7" => audc(4) <= wb_dat_i(7 downto 0);
when x"8" => audctl <= wb_dat_i(7 downto 0);
when x"9" => stimer <= wb_dat_i(7 downto 0);
when x"A" => skres <= wb_dat_i(7 downto 0);
when x"B" => potgo <= '1';
--when x"C" =>
when x"D" => serout <= wb_dat_i(7 downto 0);
when x"E" => irqen <= wb_dat_i(7 downto 0);
when x"F" => skctls <= wb_dat_i(7 downto 0);
when others => null;
end case;
end if;
--end if;
end process;
--p_reset : process(skctls)
--begin
-- chip in reset if bits 1..0 of skctls are both zero
--reset <= '0';
--if (skctls(1 downto 0) = "00") then
-- reset <= '1';
--end if;
--end process;
p_rdata : process(wb_adr_i, random) --,pin_reg_gated, pot_val, kbcode, serin, irqst, skstat)
begin
case wb_adr_i(5 downto 2) IS
when x"A" =>
wb_dat_o(7 downto 0) <= random;
when others =>
wb_dat_o(7 downto 0) <= (others => DontCareValue);
end case;
end process;
-- POT ANALOGUE IN UNTESTED !!
-- p_pot_cnt : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- if (potgo = '1') then
-- pot_cnt <= x"00";
-- elsif ((ena_15k = '1') or (skctls(2) = '1')) and (ena = '1') then -- fast scan mode
-- pot_cnt <= pot_cnt + "1";
-- end if;
-- end process;
--
-- p_pot_comp : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- if (reset = '1') then
-- pot_fin <= '1';
-- else
-- if (potgo = '1') then
-- pot_fin <= '0';
-- elsif (pot_cnt = x"E4") then -- 228
-- pot_fin <= '1';
-- end if;
-- end if;
-- end process;
--
-- p_pot_val : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- for i in 0 to 7 loop
-- if (pot_fin = '0') and (pin_reg(i) = '0') then
-- -- continue latching counter value until input reaches ViH threshold
-- pot_val(i) <= pot_cnt;
-- end if;
-- end loop;
-- end process;
-- dump transistors
--PIN <= x"00" when (pot_fin = '1') else (others => 'Z');
-- p_in_gate : process(pin_reg, reset) -- dump transistor fakeup
-- begin
-- pin_reg_gated <= pin_reg;
-- -- I think the datasheet lies about dump transistors being disabled
-- -- in fast scan mode, as the self test fails ....
-- if (reset = '1') or (pot_fin = '1') then --and (skctls(2) = '0'))
-- pin_reg_gated <= x"00";
-- end if;
-- end process;
p_tone_cnt_ena : process(audctl, ena_64k_15k, tone_gen_div)
variable chan_ena1, chan_ena3 : std_ulogic;
begin
if (audctl(6) = '1') then
chan_ena1 := '1'; -- 1.5 MHz,
else
chan_ena1 := ena_64k_15k;
end if;
chan_ena(1) <= chan_ena1;
if (audctl(4) = '1') then -- chan 1/2 joined
chan_ena(2) <= chan_ena1;
else
chan_ena(2) <= ena_64k_15k;
end if;
if (audctl(5) = '1') then
chan_ena3 := '1'; -- 1.5 MHz,
else
chan_ena3 := ena_64k_15k; -- 64 KHz
end if;
chan_ena(3) <= chan_ena3;
if (audctl(3) = '1') then -- chan 3/4 joined
chan_ena(4) <= chan_ena3;
else
chan_ena(4) <= ena_64k_15k; -- 64 KHz
end if;
end process;
p_tone_generator_zero : process(tone_gen_cnt, chan_ena)
begin
for i in 1 to 4 loop
if (tone_gen_cnt(i) = "00000000") and (chan_ena(i) = '1') then
tone_gen_zero(i) <= '1';
else
tone_gen_zero(i) <= '0';
end if;
end loop;
end process;
p_tone_generators : process
variable chan_load : std_logic_vector(4 downto 1);
variable chan_dec : std_logic_vector(4 downto 1);
begin
-- quite tricky this .. but I think it does the correct stuff
-- bet this is not how is was done originally !
--
-- nasty frig to easily get exact chip behaviour in high speed mode
-- fout = fin / 2(audf + n) when n=4 or 7 in 16 bit mode
wait until rising_edge(wb_clk_i);
if (ena = '1' and clk177='1') then
tone_gen_div <= "0000";
if (audctl(4) = '1') then -- chan 1/2 joined
chan_load(1) := '0';
chan_load(2) := '0';
if (tone_gen_zero_t(1)(5) = '1') and (tone_gen_zero_t(2)(5) = '1') and (chan_done_load(1) = '0') then
chan_load(1) := '1';
chan_load(2) := '1';
end if;
chan_dec(1) := '1';
chan_dec(2) := tone_gen_zero(1);
else
chan_load(1) := tone_gen_zero_t(1)(2) and not chan_done_load(1);
chan_load(2) := tone_gen_zero_t(2)(2) and not chan_done_load(2);
chan_dec(1) := '1';
chan_dec(2) := '1';
end if;
if (audctl(3) = '1') then -- chan 1/2 joined
chan_load(3) := '0';
chan_load(4) := '0';
if (tone_gen_zero_t(3)(5) = '1') and (tone_gen_zero_t(4)(5) = '1') and (chan_done_load(3) = '0') then
chan_load(3) := '1';
chan_load(4) := '1';
end if;
chan_dec(3) := '1';
chan_dec(4) := tone_gen_zero(3);
else
chan_load(3) := tone_gen_zero_t(3)(2) and not chan_done_load(3);
chan_load(4) := tone_gen_zero_t(4)(2) and not chan_done_load(4);
chan_dec(3) := '1';
chan_dec(4) := '1';
end if;
for i in 1 to 4 loop
if (chan_load(i) = '1') then
chan_done_load(i) <= '1';
tone_gen_div(i) <= '1';
tone_gen_cnt(i) <= audf(i);
elsif (chan_dec(i) = '1') and (chan_ena(i) = '1') then
chan_done_load(i) <= '0';
tone_gen_cnt(i) <= tone_gen_cnt(i) - "1";
end if;
tone_gen_div(i) <= chan_load(i);
tone_gen_zero_t(i)(7 downto 0) <= tone_gen_zero_t(i)(6 downto 0) & tone_gen_zero(i);
end loop;
end if;
end process;
p_tone_generator_mux : process(audctl, tone_gen_div)
begin
if (audctl(4) = '1') then -- chan 1/2 joined
tone_gen_div_mux(1) <= tone_gen_div(1); -- do they both waggle
tone_gen_div_mux(2) <= tone_gen_div(2); -- or do I mute chan 1?
else
tone_gen_div_mux(1) <= tone_gen_div(1);
tone_gen_div_mux(2) <= tone_gen_div(2);
end if;
if (audctl(3) = '1') then -- chan 3/4 joined
tone_gen_div_mux(3) <= tone_gen_div(3); -- ditto
tone_gen_div_mux(4) <= tone_gen_div(4);
else
tone_gen_div_mux(3) <= tone_gen_div(3);
tone_gen_div_mux(4) <= tone_gen_div(4);
end if;
end process;
p_poly_gating : process(audc, poly4, poly5, poly_17_9, tone_gen_div_mux)
variable filter_a : std_logic_vector(4 downto 1);
variable filter_b : std_logic_vector(4 downto 1);
begin
for i in 1 to 4 loop
if (audc(i)(7) = '0') then
filter_a(i) := poly5(4) and tone_gen_div_mux(i);-- 5 bit poly
else
filter_a(i) := tone_gen_div_mux(i);
end if;
if (audc(i)(6) = '0') then
filter_b(i) := poly_17_9 and filter_a(i);-- 17 bit poly
else
filter_b(i) := poly4(3) and filter_a(i);-- 4 bit poly
end if;
if (audc(i)(5) = '0') then
poly_sel(i) <= filter_b(i);
else
poly_sel(i) <= filter_a(i);
end if;
end loop;
end process;
p_high_pass_filters : process(audctl, poly_sel, poly_sel_hp_reg)
begin
poly_sel_hp <= poly_sel;
if (audctl(2) = '1') then
poly_sel_hp(1) <= poly_sel(1) xor poly_sel_hp_reg(1);
end if;
if (audctl(1) = '1') then
poly_sel_hp(2) <= poly_sel(2) xor poly_sel_hp_reg(2);
end if;
end process;
p_audio_out : process
begin
wait until rising_edge(wb_clk_i);
if (ena = '1' and clk177='1') then
for i in 1 to 4 loop
-- filter reg
if (tone_gen_div(3) = '1') then -- tone gen 1 clocked by gen 3
poly_sel_hp_reg(1) <= poly_sel(1);
end if;
if (tone_gen_div(4) = '1') then -- tone gen 2 clocked by gen 4
poly_sel_hp_reg(2) <= poly_sel(2);
end if;
poly_sel_hp_t1 <= poly_sel_hp;
if (poly_sel_hp(i) = '1') and (poly_sel_hp_t1(i) = '0') then -- rising edge
tone_gen_final(i) <= not tone_gen_final(i);
end if;
end loop;
end if;
end process;
p_op_mixer : process
variable vol : array_4x4;
variable sum12 : std_logic_vector(4 downto 0);
variable sum34 : std_logic_vector(4 downto 0);
variable sum : std_logic_vector(5 downto 0);
begin
wait until rising_edge(wb_clk_i);
if (ena = '1') then
for i in 1 to 4 loop
if (audc(i)(4) = '1') then -- vol only
vol(i) := audc(i)(3 downto 0);
else
if (tone_gen_final(i) = '1') then
vol(i) := audc(i)(3 downto 0);
else
vol(i) := "0000";
end if;
end if;
end loop;
sum12 := ('0' & vol(1)) + ('0' & vol(2));
sum34 := ('0' & vol(3)) + ('0' & vol(4));
sum := ('0' & sum12) + ('0' & sum34);
if (wb_rst_i = '1') then
o_audio <= "00000000";
else
if (sum(5) = '0') then
o_audio <= sum(4 downto 0) & "000";
else -- clip
o_audio <= "11111111";
end if;
end if;
end if;
end process;
-- keyboard / serial etc to do
end architecture RTL;
| mit | 5423ce4778d83ddbc54d2d3ab0433d9c | 0.551294 | 3.020471 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.h-PSWreg.vhd | 2 | 806 | library ieee;
use ieee.std_logic_1164.all;
-- Processor Status Word (PSW)
-- configured as:
-- bits: 31 - 2 | 1 | 0
-- content: 0 ... 0 | ovf | unaligned
entity PSWreg is
port(
-- inputs
rst : in std_logic;
clk : in std_logic;
unaligned : in std_logic;
-- cout : in std_logic;
ovf : in std_logic;
-- outputs
status : out std_logic_vector(31 downto 0)
);
end PSWreg;
architecture rtl of PSWreg is
begin
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
status <= (others => '0');
else
status(0) <= unaligned;
status(1) <= ovf;
status(31 downto 2) <= (others => '0');
end if;
end if;
end process;
end rtl;
| mit | 55fe4774e2b4ac1037167ecad74ce2f6 | 0.506203 | 3.330579 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.e-forward.vhd | 1 | 1,540 | library ieee;
use ieee.std_logic_1164.all;
-- forwarding unit for data hazards
-- following the idea in Patterson/Hennessy book
entity forward is
port(
-- inputs
rt_addr_IDEX : in std_logic_vector(4 downto 0);
rs_addr_IDEX : in std_logic_vector(4 downto 0);
rd_addr_EXMEM : in std_logic_vector(4 downto 0);
rd_addr_MEMWB : in std_logic_vector(4 downto 0);
regwrite_EXMEM : in std_logic;
regwrite_MEMWB : in std_logic;
-- outputs
forwardA : out std_logic_vector(1 downto 0); -- 00 from regfile, 01 from memwb, 10 from previous alu result
forwardB : out std_logic_vector(1 downto 0) -- as above
);
end forward;
architecture rtl of forward is
begin
process(rt_addr_IDEX, rs_addr_IDEX, rd_addr_EXMEM, rd_addr_MEMWB, regwrite_EXMEM, regwrite_MEMWB)
begin
-- FORWARD A
if((regwrite_EXMEM = '1') and (rd_addr_EXMEM /= "00000") and (rd_addr_EXMEM = rs_addr_IDEX)) then
forwardA <= "10";
-- MEM hazards
elsif ((regwrite_MEMWB = '1') and (rd_addr_MEMWB /= "00000") and (rd_addr_MEMWB = rs_addr_IDEX) ) then
forwardA <= "01";
else
forwardA <= "00";
end if;
-- FORWARD B
if((regwrite_EXMEM = '1') and (rd_addr_EXMEM /= "00000") and (rd_addr_EXMEM = rt_addr_IDEX)) then
forwardB <= "10";
-- MEM hazards
elsif ((regwrite_MEMWB = '1') and (rd_addr_MEMWB /= "00000") and (rd_addr_MEMWB = rt_addr_IDEX) ) then
forwardB <= "01";
else
forwardB <= "00";
end if;
end process;
end rtl;
| mit | 9b3ac807ab8be97651306ac892b70056 | 0.613636 | 3.195021 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.g-ID_EX_Reg.vhd | 1 | 4,465 | ---------------------------------------------------------------------------
-- ID/EX Pipeline Register
-- It propagates inputs coming from the decode stage to the ex stage
-- Note the use of the flush control signal: it used to flush the pipeline
-- register in case of control hazards(fluhs when the signal is asseted).
-- The reset is synchronous with respet to the clock, whereas the flush is
-- asynchronous.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
entity idex_reg is
port (
-- INPUTS
cw_to_ex_dec : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec : in std_logic_vector(31 downto 0); -- jump address extended
pc_4_dec : in std_logic_vector(31 downto 0); -- PC incremented by 4 from decode
read_data_1_dec : in std_logic_vector(31 downto 0); -- reg 1 read from decode
read_data_2_dec : in std_logic_vector(31 downto 0); -- reg 2 read from decode
immediate_ext_dec : in std_logic_vector(31 downto 0); -- immediate sign extended from decode
immediate_dec : in std_logic_vector(15 downto 0); -- immediate for lui instrucion from decode
rt_dec : in std_logic_vector(4 downto 0); -- rt address from decode
rd_dec : in std_logic_vector(4 downto 0); -- rs address from decode
rs_dec : in std_logic_vector(4 downto 0); -- rd address from decode
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word for ex stage
jump_address : out std_logic_vector(31 downto 0); -- jump address to ex stage
pc_4 : out std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0);
immediate_ext : out std_logic_vector(31 downto 0);
immediate : out std_logic_vector(15 downto 0);
rt : out std_logic_vector(4 downto 0);
rd : out std_logic_vector(4 downto 0);
rs : out std_logic_vector(4 downto 0)
);
end idex_reg;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of idex_reg is
begin
------------------------
-- Reg Proc
-- Type: Sequiential
-- Purpose: Implement
-- the behavior of the
-- pipeline register
-- Reset is synchronous
------------------------
Reg_proc: process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
cw_to_ex <= (others => '0');
jump_address <= (others => '0');
pc_4 <= (others => '0');
read_data_1 <= (others => '0');
read_data_2 <= (others => '0');
immediate_ext <= (others => '0');
immediate <= (others => '0');
rt <= (others => '0');
rd <= (others => '0');
rs <= (others => '0');
else
cw_to_ex <= cw_to_ex_dec;
jump_address <= jump_address_dec;
pc_4 <= pc_4_dec;
read_data_1 <= read_data_1_dec;
read_data_2 <= read_data_2_dec;
immediate_ext <= immediate_ext_dec;
immediate <= immediate_dec;
rt <= rt_dec;
rd <= rd_dec;
rs <= rs_dec;
end if;
end if;
end process;
end behavioral;
| mit | c5d6e826865232f775de9e9ab34302ee | 0.439194 | 4.487437 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/ALU.vhd | 1 | 2,143 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lpm;
use lpm.all;
entity alu is
port (alu_op: in std_logic_vector(2 downto 0);
operand0, operand1 : in std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0);
alu_out : out std_logic_vector(31 downto 0);
carry, overflow : out std_logic
);
end;
architecture alu_arch of alu is
signal add_sub : std_logic;
signal add_sub_out : std_logic_vector(31 downto 0);
signal product : std_logic_vector(63 downto 0);
signal asov, mov: std_logic;
component lpm_add_sub
generic (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
port (
dataa : in std_logic_vector (31 downto 0);
add_sub : in std_logic ;
datab : in std_logic_vector (31 downto 0);
overflow : out std_logic ;
cout : out std_logic ;
result : out std_logic_vector (31 downto 0)
);
end component;
begin
lpm_add_sub_component : lpm_add_sub
generic map (
lpm_direction => "unused",
lpm_hint => "one_input_is_CONSTANT=NO,Cin_used=NO",
lpm_representation => "SIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 32
)
port map (
dataa => operand0,
add_sub => add_sub,
datab => operand1,
overflow => asov,
cout => carry, --not(borrow) when SUB
result => add_sub_out
);
add_sub <= '0' when alu_op="010" else '1'; --'0' for sub; '1' for add
overflow <= mov when alu_op="011" else asov; --multiplication overflow is different
mov <= '0' when product(63)=product(31) else '1';
product <= std_logic_vector(signed(operand0) * signed(operand1));
alu_out <= add_sub_out when alu_op="000" else
add_sub_out when alu_op="001" else
add_sub_out when alu_op="010" else
product(31 downto 0) when alu_op="011" else
operand0 and operand1 when alu_op="100" else
operand0 or operand1 when alu_op="101" else
operand0 xor operand1 when alu_op="110" else
std_logic_vector(rotate_right(unsigned(operand0), to_integer(unsigned(n))));
end alu_arch; | gpl-3.0 | 8847db3acad776c85a80a405665dd1ad | 0.633224 | 2.880376 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.e-writeback.core/a.b.e.a-mux21.vhd | 1 | 413 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- a goes through when s='1', b with s='0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
A: In std_logic_vector(NBIT-1 downto 0);
B: In std_logic_vector(NBIT-1 downto 0);
S: In std_logic;
Y: Out std_logic_vector(NBIT-1 downto 0)
);
end mux21;
architecture beh of MUX21 is
begin
Y <= A when S='1' else B;
end beh;
| mit | 680be91312eb35a8b567233b1ea4110b | 0.653753 | 2.443787 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_zxspectrum.vhd | 13 | 16,636 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_vga_zxspectrum is
port(
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
-- Wishbone MASTER interface
mi_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
mi_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
mi_wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
mi_wb_sel_o: out std_logic_vector(3 downto 0);
mi_wb_cti_o: out std_logic_vector(2 downto 0);
mi_wb_we_o: out std_logic;
mi_wb_cyc_o: out std_logic;
mi_wb_stb_o: out std_logic;
mi_wb_ack_i: in std_logic;
-- VGA signals
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_b: out std_logic;
vga_r: out std_logic;
vga_g: out std_logic;
vga_bright: out std_logic
);
end entity;
architecture behave of VIDEO_zpuino_wb_vga_zxspectrum is
component gh_fifo_async_rrd_sr_wf is
GENERIC (add_width: INTEGER :=8; -- min value is 2 (4 memory locations)
data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
qfull : out STD_LOGIC;
hfull : out STD_LOGIC;
qqqfull : out STD_LOGIC;
afull : out STD_LOGIC;
full : out STD_LOGIC);
end component;
signal fifo_full: std_logic;
signal fifo_almost_full: std_logic;
signal fifo_write_enable: std_logic;
signal fifo_quad_full: std_logic;
signal fifo_half_full: std_logic;
-- signal readclk: std_logic:='0';
signal fifo_clear: std_logic:='0';
signal read_enable: std_logic:='0';
signal fifo_write, read: std_logic_vector(3 downto 0);
signal fifo_empty: std_logic;
signal char_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal char_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal char_wb_adr_i: std_logic_vector(maxIObit downto minIObit);
signal char_wb_cyc_i: std_logic;
signal char_wb_stb_i: std_logic;
signal char_wb_ack_o: std_logic;
signal membase: std_logic_vector(wordSize-1 downto 0) := (others => '0');
signal palletebase: std_logic_vector(wordSize-1 downto 0) := (others => '0');
type state_type is (
fetch_char,
fetch_pallete,
load_char,
fill,
next_line,
sleep
);
type vgaregs_type is record
state: state_type;
chars: std_logic_vector(wordSize-1 downto 0);
pallete: std_logic_vector(wordSize-1 downto 0);
--charline: std_logic_vector(7 downto 0); -- The 8 pixels of a char row
--charpal: std_logic_vector(7 downto 0); -- Pallete for this char
hptr: integer range 0 to 79; -- horizontal counter
hoff: unsigned(4 downto 0);
voff: unsigned(4 downto 0);
memptr: unsigned(wordSize-1 downto 0);
palleteptr: unsigned(wordSize-1 downto 0);
ls_memptr: unsigned(wordSize-1 downto 0);
ls_palleteptr: unsigned(wordSize-1 downto 0);
end record;
signal r: vgaregs_type;
--# 640x480 @ 72Hz (VESA) hsync: 37.9kHz
--ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
--# 640x480 @ 75Hz (VESA) hsync: 37.5kHz
--ModeLine "640x480" 31.5 640 656 720 840 480 481 484 500 -hsync -vsync
--# 640x480 @ 85Hz (VESA) hsync: 43.3kHz
--ModeLine "640x480" 36.0 640 696 752 832 480 481 484 509 -hsync -vsync
constant VGA_H_BORDER: integer := 64;
constant VGA_H_SYNC: integer := 40;
constant VGA_H_FRONTPORCH: integer := 24+VGA_H_BORDER;
constant VGA_H_DISPLAY: integer := 640 - (2*VGA_H_BORDER);
constant VGA_H_BACKPORCH: integer := 128+VGA_H_BORDER;
constant VGA_V_BORDER: integer := 48;
constant VGA_V_FRONTPORCH: integer := 29+VGA_V_BORDER;
constant VGA_V_SYNC: integer := 2;
constant VGA_V_DISPLAY: integer := 480 - (2*VGA_V_BORDER);
constant VGA_V_BACKPORCH: integer := 9+VGA_V_BORDER;
-- constant VGA_H_BORDER: integer := 0;
-- constant VGA_H_SYNC: integer := 2;
-- constant VGA_H_FRONTPORCH: integer := 2;
-- constant VGA_H_DISPLAY: integer := 128;
-- constant VGA_H_BACKPORCH: integer := 2;
-- constant VGA_V_BORDER: integer := 0;
-- constant VGA_V_FRONTPORCH: integer := 2;
-- constant VGA_V_SYNC: integer := 2;
-- constant VGA_V_DISPLAY: integer := 192;
-- constant VGA_V_BACKPORCH: integer := 2;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '1';
constant h_polarity: std_logic := '1';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
signal rstq1: std_logic:='1';
signal rstq2: std_logic;
signal v_display: std_logic;
signal v_display_in_wbclk: std_logic;
signal v_display_q: std_logic;
--signal v_border: std_logic;
signal cache_clear: std_logic;
signal vga_reset_q1, vga_reset_q2: std_logic;
signal rdly: std_logic;
signal hdup: std_logic := '1';
signal hflip: std_logic;
begin
-- Wishbone register access
wb_dat_o(31 downto 1) <= (others => DontCareValue);
wb_dat_o(0) <= v_display_in_wbclk;
mi_wb_dat_o <= (others => DontCareValue);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
rdly<='0';
wb_ack_o<='0';
else
if rdly='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
if wb_we_i='1' then
case wb_adr_i(3 downto 2) is
when "00" =>
membase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when "01" =>
palletebase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when others =>
end case;
end if;
wb_ack_o<='1';
rdly <= '1';
end if;
else
rdly <= '0';
wb_ack_o<='0';
end if;
end if;
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (vcount_q < VGA_V_DISPLAY) then
v_display_in_wbclk <= '1';
else
v_display_in_wbclk <= '0';
end if;
end if;
end process;
process(wb_clk_i, wb_rst_i, r, mi_wb_ack_i, mi_wb_dat_i,membase,palletebase)
variable w: vgaregs_type;
variable current_char: std_logic_vector(7 downto 0);
variable current_pallete: std_logic_vector(7 downto 0);
variable vdisp_char: std_logic_vector(2 downto 0); -- Vertical offset in char (0 to 7)
variable pixel: std_logic_vector(3 downto 0);
variable hmax: integer range 0 to 7;
begin
mi_wb_stb_o <= '0';
mi_wb_cyc_o <= '0';
mi_wb_we_o <= '0';
mi_wb_adr_o <= (others => '0');
fifo_write_enable<='0';
char_wb_cyc_i<='0';
char_wb_stb_i<='0';
char_wb_adr_i <= (others => DontCareValue);
pixel := (others => DontCareValue);
-- vdisp_char := std_logic_vector(r.voff(3 downto 1)); -- Ignore last bit - will duplicate vertical line
--if hdup='1' then
hmax := 7; -- 8 32-bit values = 256 bits
--else
-- hmax := 79;
--end if;
w := r;
if wb_rst_i='1' or vga_reset_q1='1' then
w.state := sleep;
--w.palloff := (others => '0');
fifo_clear <='1';
w.hptr := 0;
w.hoff := (others =>'0');
w.voff := (others =>'0');
w.memptr := unsigned(membase);
w.palleteptr := unsigned(palletebase);
mi_wb_adr_o <= (others => DontCareValue);
w.ls_memptr := unsigned(membase);
w.ls_palleteptr := unsigned(palletebase);
else
fifo_clear<='0';
case r.state is
when fetch_char =>
mi_wb_stb_o <= '1';
mi_wb_cyc_o <= '1';
mi_wb_adr_o <= std_logic_vector( r.memptr(maxAddrBitIncIO downto 0) );
--w.charoff := (others => '0');
w.chars := mi_wb_dat_i;
w.hoff := (others => '0');
if mi_wb_ack_i='1' then
w.state := fill;
end if;
when fetch_pallete =>
mi_wb_stb_o <= '1';
mi_wb_cyc_o <= '1';
mi_wb_adr_o <= std_logic_vector( r.palleteptr(maxAddrBitIncIO downto 0) );
w.pallete := mi_wb_dat_i;
if mi_wb_ack_i='1' then
w.state := fetch_char;
end if;
when fill =>
-- Choose color
case r.palleteptr(1 downto 0) is
when "11" => current_pallete := r.pallete(7 downto 0);
when "10" => current_pallete := r.pallete(15 downto 8);
when "01" => current_pallete := r.pallete(23 downto 16);
when "00" => current_pallete := r.pallete(31 downto 24);
when others =>
end case;
--w.charpal := current_pallete;
case r.chars(31) is
when '1' =>
pixel := current_pallete(6) & current_pallete(2 downto 0);
when '0' =>
pixel := current_pallete(6) & current_pallete(5 downto 3);
when others =>
end case;
-- Other bits have extended attributes
if fifo_almost_full='0' then
fifo_write_enable<='1';
-- Shift r.chars
w.chars(31 downto 1) := r.chars(30 downto 0);
w.chars(0) := DontCareValue;
w.hoff := r.hoff + 1;
if r.hoff="11111" then -- Meaning we just output the 32 bits
if r.hptr=hmax then -- Finished a whole line
w.hptr := 0;
w.voff := r.voff + 1;
if r.voff(0)='1' then
-- Finished a whole character line
w.memptr := r.memptr + 4;
if r.voff(3 downto 0) /="1111" then
w.palleteptr := r.ls_palleteptr;
else
w.palleteptr := r.palleteptr + 1;
end if;
w.state := next_line;
else
w.memptr := r.ls_memptr;
w.palleteptr := r.ls_palleteptr;
w.state := sleep;
end if;
else
-- Still doing a line
w.hptr := w.hptr + 1;
w.memptr := r.memptr + 4;
w.palleteptr := r.palleteptr + 1;
--if r.palleteptr(1 downto 0)="11" then
-- Increase pointer
w.state := fetch_pallete;
--elsif r.memptr(1 downto 0)="11" then
-- Increase pointer
--else
-- w.state := fetch_char;
--end if;
--else
-- w.state := load_char;
--end if;
end if;
else
if r.hoff(2 downto 0)="111" then -- Just output 8 bits
w.palleteptr := r.palleteptr + 1;
if r.palleteptr(1 downto 0)="11" then
-- Increase pointer
w.state := fetch_pallete;
end if;
end if;
end if;
end if;
when sleep =>
w.state := fetch_pallete;
when next_line =>
if r.voff(3 downto 0)="0000" then
w.ls_palleteptr := r.palleteptr;
end if;
w.ls_memptr := r.memptr;
w.state := fetch_pallete;
when others =>
end case;
end if;
fifo_write <= pixel;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
--
--
-- VGA part
--
--
process(vgaclk, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(vgaclk) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
hcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
else
hcount_q <= hcount_q + 1;
end if;
end if;
end if;
end process;
process(hcount_q, vcount_q)
begin
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end process;
process(vgaclk)
begin
if rising_edge(vgaclk) then
v_display_q <= v_display;
end if;
end process;
hsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_FRONTPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_BACKPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
end if;
end if;
end if;
end if;
end process;
-- Cache clear.
vclear: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
cache_clear <= '1';
else
cache_clear<='0';
--if vcount_q = VGA_V_DISPLAY and h_sync_tick='1' then
-- cache_clear<='1';
--end if;
if not (vcount_q < VGA_V_DISPLAY) then
cache_clear <='1';
end if;
end if;
end if;
end process;
vsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_vsync<=v_polarity;
--cache_clear <= '1';
else
--cache_clear <= '0';
if vcount_q = (VGA_V_DISPLAY + VGA_V_FRONTPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_BACKPORCH) then
vga_vsync <= v_polarity;
--cache_clear <= '1';
end if;
end if;
end if;
end process;
-- Synchronous output
process(vgaclk)
begin
if rising_edge(vgaclk) then
if v_display='0' then
vga_b <= '0';
vga_r <= '0';
vga_g <= '0';
vga_bright <= '0';
else
vga_b <= read(0);
vga_r <= read(1);
vga_g <= read(2);
vga_bright <= read(3);
end if;
end if;
end process;
process(wb_clk_i,cache_clear)
begin
if cache_clear='1' then
vga_reset_q1<='1';
vga_reset_q2<='1';
elsif rising_edge(wb_clk_i) then
vga_reset_q2<='0';
vga_reset_q1<=vga_reset_q2;
end if;
end process;
-- In order to perform H duplication, we use a trick here
process(vgaclk,v_display,v_display_q)
begin
if rising_edge(vgaclk) then
if v_display='1' and v_display_q='0' then
-- Starting an horizontal line display, reset hflip if needed
hflip <= '1';
else
if v_display='0' then
hflip <='0';
else
hflip <= hflip xor hdup;
end if;
end if;
end if;
end process;
read_enable <= v_display and not hflip;
myfifo: gh_fifo_async_rrd_sr_wf
generic map (
data_width => 4,
add_width => 4
)
port map (
clk_WR => wb_clk_i,
clk_RD => vgaclk,
rst => '0',
srst => fifo_clear,
WR => fifo_write_enable,
RD => read_enable,
D => fifo_write,
Q => read,
empty => fifo_empty,
qfull => fifo_quad_full,
hfull => fifo_half_full,
qqqfull => fifo_almost_full,
full => fifo_full
);
end behave;
| mit | 269b6a92e9271e0c4275d74081902684 | 0.547067 | 3.171178 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/000-globals.vhd | 1 | 7,039 | ------------------------------------------------------------------------------------------
-- This file contains the declaration of the constants used in all other submodules.
-- In this file are defined:
--
-- - Size of LUTs used
-- - Size of ALU Operation, Control Word, OPCODE and Function
-- - Control Words that the CU should produce for each instruction
-- - OPCODE, FUNC, ALUOP for each instruction
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package globals is
-- Size of the LUT within the CU Hardwired (taking into account unused operations)
constant SIZE_LUT : integer := 62;
-- CW size
constant CW_SIZE : integer := 18;
-- ALU Operation
constant ALUOP_SIZE : integer := 5;
-- OPCODE
constant OPCODE_SIZE : integer := 6;
-- FUNCTION FIELD SIZE
constant FUNC_SIZE : integer := 11;
-- FUNC FIELDS FOR EACH INSTRUCTION
constant FUNC_SLL : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000000100";
constant FUNC_SRL : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000000110";
constant FUNC_SRA : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000000111";
constant FUNC_ADD : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100000";
constant FUNC_ADDU : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100001";
constant FUNC_SUB : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100010";
constant FUNC_SUBU : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100011";
constant FUNC_AND : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100100";
constant FUNC_OR : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100101";
constant FUNC_XOR : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000100110";
constant FUNC_SEQ : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000101000";
constant FUNC_SNE : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000101001";
constant FUNC_SLT : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000101010";
constant FUNC_SGT : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000101011";
constant FUNC_SLE : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000101100";
constant FUNC_SGE : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000101101";
constant FUNC_MOVS2I : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000110001";
constant FUNC_SLTU : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000111010";
constant FUNC_SGTU : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000111011";
constant FUNC_SGEU : std_logic_vector(FUNC_SIZE-1 downto 0) := "00000111101";
-- OPCODE FIELD
constant RTYPE : std_logic_vector (OPCODE_SIZE-1 downto 0) := "000000";
constant J_TYPE_J : std_logic_vector (OPCODE_SIZE-1 downto 0) := "000010";
constant J_TYPE_JAL : std_logic_vector (OPCODE_SIZE-1 downto 0) := "000011";
constant I_TYPE_BEQZ : std_logic_vector (OPCODE_SIZE-1 downto 0) := "000100";
constant I_TYPE_BNEZ : std_logic_vector (OPCODE_SIZE-1 downto 0) := "000101";
constant I_TYPE_ADDI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001000";
constant I_TYPE_ADDUI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001001";
constant I_TYPE_SUBI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001010";
constant I_TYPE_SUBUI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001011";
constant I_TYPE_ANDI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001100";
constant I_TYPE_ORI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001101";
constant I_TYPE_XORI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001110";
constant I_TYPE_LHI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "001111";
constant J_TYPE_JR : std_logic_vector (OPCODE_SIZE-1 downto 0) := "010010";
constant J_TYPE_JALR : std_logic_vector (OPCODE_SIZE-1 downto 0) := "010011";
constant I_TYPE_SLLI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "010100";
constant N_TYPE_NOP : std_logic_vector (OPCODE_SIZE-1 downto 0) := "010101";
constant I_TYPE_SRLI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "010110";
constant I_TYPE_SRAI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "010111";
constant I_TYPE_SEQI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "011000";
constant I_TYPE_SNEI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "011001";
constant I_TYPE_SLTI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "011010";
constant I_TYPE_SGTI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "011011";
constant I_TYPE_SLEI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "011100";
constant I_TYPE_SGEI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "011101";
constant I_TYPE_LB : std_logic_vector (OPCODE_SIZE-1 downto 0) := "100000";
constant I_TYPE_LW : std_logic_vector (OPCODE_SIZE-1 downto 0) := "100011";
constant I_TYPE_LBU : std_logic_vector (OPCODE_SIZE-1 downto 0) := "100100";
constant I_TYPE_LHU : std_logic_vector (OPCODE_SIZE-1 downto 0) := "100101";
constant I_TYPE_SB : std_logic_vector (OPCODE_SIZE-1 downto 0) := "101000";
constant I_TYPE_SW : std_logic_vector (OPCODE_SIZE-1 downto 0) := "101011";
constant I_TYPE_SLTUI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "111010";
constant I_TYPE_SGTUI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "111011";
constant I_TYPE_SGEUI : std_logic_vector (OPCODE_SIZE-1 downto 0) := "111101";
-- ALU OPERATION
constant ALUOP_SLL : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00001";
constant ALUOP_SRL : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00010";
constant ALUOP_SRA : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00011";
constant ALUOP_ADD : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00100";
constant ALUOP_ADDU : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00101";
constant ALUOP_SUB : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00110";
constant ALUOP_SUBU : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00111";
constant ALUOP_AND : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01000";
constant ALUOP_OR : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01001";
constant ALUOP_XOR : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01010";
constant ALUOP_SEQ : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01011";
constant ALUOP_SNE : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01100";
constant ALUOP_SLT : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01101";
constant ALUOP_SGT : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01110";
constant ALUOP_SLE : std_logic_vector(ALUOP_SIZE-1 downto 0) := "01111";
constant ALUOP_SGE : std_logic_vector(ALUOP_SIZE-1 downto 0) := "10000";
constant ALUOP_MOVS2I : std_logic_vector(ALUOP_SIZE-1 downto 0) := "00000";
constant ALUOP_SLTU : std_logic_vector(ALUOP_SIZE-1 downto 0) := "10001";
constant ALUOP_SGTU : std_logic_vector(ALUOP_SIZE-1 downto 0) := "10010";
constant ALUOP_SGEU : std_logic_vector(ALUOP_SIZE-1 downto 0) := "10011";
end globals;
| mit | fbe2683cb5e4888fd57f10c2e5b6400a | 0.653218 | 3.127055 | false | false | false | false |
huukit/logicsynth | excercises/tb/tb_ripple_carry_adder.vhd | 1 | 4,248 | -------------------------------------------------------------------------------
-- Title : TKT-1212, Exercise 02
-- Project :
-------------------------------------------------------------------------------
-- File : tb_ripple_carry_adder.vhd
-- Author : Antti Rasmus
-- Company : TUT/DCS
-- Created : 2008-11-28
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Tests all combinations of summing two 3-bit values
-------------------------------------------------------------------------------
-- Copyright (c) 2008
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2008-11-28 1.0 ege Created
-------------------------------------------------------------------------------
-- Include default libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Include own logic (=compiled ripple_carry_adder)
use work.all;
-- Testbech needs no input or output signals
entity tb_ripple_carry_adder is
end tb_ripple_carry_adder;
-- The behavior is written inside architecture
architecture testbench of tb_ripple_carry_adder is
-- First, there are definitions
-- Define constants: bit widths and duration of clk period
constant input_w_c : integer := 3;
constant output_w_c : integer := 4;
constant clk_period_c : time := 100 ns;
-- Component declaration of Design Under Verification (DUV)
component ripple_carry_adder
port (
a_in : in std_logic_vector(2 downto 0);
b_in : in std_logic_vector(2 downto 0);
s_out : out std_logic_vector(3 downto 0));
end component;
-- Define the needed signals
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal term1_r : unsigned(input_w_c-1 downto 0);
signal term2_r : unsigned(input_w_c-1 downto 0);
signal sum : unsigned(output_w_c-1 downto 0);
signal sum_slv : std_logic_vector(output_w_c-1 downto 0);
begin -- testbench
-- The actual behavior starts here
-- Instantiate DUV and connect it to testbench's signals
i_ripple_carry_adder : ripple_carry_adder
port map (
a_in => std_logic_vector(term1_r),
b_in => std_logic_vector(term2_r),
s_out => sum_slv);
sum <= unsigned(sum_slv);
-- Generate rst signals to initialize registers
rst_n <= '1' after clk_period_c*2;
-- purpose: Generate clock signal for DUV
-- type : combinational
-- inputs : clk (this is a special case for test purposes!)
-- outputs: clk
clk_gen : process (clk)
begin -- process clk_gen
clk <= not clk after clk_period_c/2;
end process clk_gen;
-- purpose: Generate all possible inputs values and check the result
-- type : sequential
-- inputs : clk, rst_n
-- outputs: term1_r, term2_r
input_gen_output_check : process (clk, rst_n)
begin -- process input_gen_output_check
if rst_n = '0' then -- asynchronous reset (active low)
-- Reset all registers here
term1_r <= (others => '0');
term2_r <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Increment term1 on every clock cycle (else-branch)
-- Increment also term2 when term1 has max value (if-branch)
-- Simulation terminates when term2 has max value
if (to_integer(term1_r) = 2**input_w_c-1) then
term1_r <= (others => '0');
if (term2_r = 2**input_w_c-1) then
assert false report "Simulation ended!" severity failure;
-- "Failure" forces simulator to stop, so it is not dangerous in this
-- case
else
term2_r <= to_unsigned(to_integer(term2_r) + 1, input_w_c);
end if;
else
term1_r <= to_unsigned(to_integer(term1_r) + 1, input_w_c);
end if;
-- Check the result. This condition should always be true. If not, the report message will be printed.
assert to_integer(sum) = to_integer(term1_r) + to_integer(term2_r)
report "Output signal is not equal to the sum of the inputs"
severity error;
end if;
end process input_gen_output_check;
end testbench;
| gpl-2.0 | dab3bbca9f3f6f453f665c348b77cc49 | 0.564736 | 3.830478 | false | true | false | false |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/soc_system_inst.vhd | 1 | 19,817 | component soc_system is
port (
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
clk_clk : in std_logic := 'X'; -- clk
custom_leds_0_leds_leds : out std_logic_vector(7 downto 0); -- leds
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_system;
u0 : component soc_system
port map (
button_pio_external_connection_export => CONNECTED_TO_button_pio_external_connection_export, -- button_pio_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
custom_leds_0_leds_leds => CONNECTED_TO_custom_leds_0_leds_leds, -- custom_leds_0_leds.leds
dipsw_pio_external_connection_export => CONNECTED_TO_dipsw_pio_external_connection_export, -- dipsw_pio_external_connection.export
hps_0_f2h_cold_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_cold_reset_req_reset_n, -- hps_0_f2h_cold_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_debug_reset_req_reset_n, -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_stm_hw_events_stm_hwevents => CONNECTED_TO_hps_0_f2h_stm_hw_events_stm_hwevents, -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_f2h_warm_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_warm_reset_req_reset_n, -- hps_0_f2h_warm_reset_req.reset_n
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| gpl-2.0 | 5aaf682632b40f7b6d84b86dc27ecf73 | 0.457183 | 2.954674 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/bscan_spi_spartan6.vhd | 13 | 4,308 | ----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4
-- Description: a simple implementation of the BSCAN_SPARTAN3E module to access
-- external SPI Flash via JTAG.
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added header recognation of header and TDO alignment (requires
-- 4 bytes of preamble and 1 byte post). Based on design
-- of xc3sprog (changes made to CS handling and header length).
-- Additional Comments: tested on Butterfly One with xc3s250e
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bscan_spi is
Port ( SPI_MISO : in STD_LOGIC;
SPI_MOSI : inout STD_LOGIC;
SPI_CS : inout STD_LOGIC;
SPI_SCK : inout STD_LOGIC);
end bscan_spi;
architecture Behavioral of bscan_spi is
--component BSCAN_SPARTAN6
-- port (CAPTURE : out STD_ULOGIC;
-- DRCK1 : out STD_ULOGIC;
-- DRCK2 : out STD_ULOGIC;
-- RESET : out STD_ULOGIC;
-- SEL1 : out STD_ULOGIC;
-- SEL2 : out STD_ULOGIC;
-- SHIFT : out STD_ULOGIC;
-- TDI : out STD_ULOGIC;
-- UPDATE : out STD_ULOGIC;
-- TDO1 : in STD_ULOGIC;
-- TDO2 : in STD_ULOGIC);
-- end component;
signal user_CAPTURE : std_ulogic;
signal user_DRCK1 : std_ulogic;
signal user_DRCK2 : std_ulogic;
signal user_RESET : std_ulogic;
signal user_SEL1 : std_ulogic;
signal user_SEL2 : std_ulogic;
signal user_SHIFT : std_ulogic;
signal user_TDI : std_ulogic;
signal user_UPDATE : std_ulogic;
signal user_TDO1 : std_ulogic;
signal user_TDO2 : std_ulogic;
signal tdi_mem : std_logic_vector(31 downto 0);
signal tdo_mem : std_logic_vector(7 downto 0);
signal len : std_logic_vector(15 downto 0);
signal CS_GO_PREP : std_logic;
signal CS_GO : std_logic;
signal CS_STOP_PREP : std_logic;
signal CS_STOP : std_logic;
signal reset : std_logic;
signal have_header : std_logic;
begin
reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1);
BS : BSCAN_SPARTAN6
port map (
CAPTURE => user_CAPTURE,
DRCK => user_DRCK1,
--DRCK2 => user_DRCK2,
RESET => user_RESET,
SEL => user_SEL1,
--SEL2 => user_SEL2,
SHIFT => user_SHIFT,
TDI => user_TDI,
UPDATE => user_UPDATE,
TDO => user_TDO1
--TDO2 => user_TDO2
);
process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1)
begin
-- default assignments (put outputs in High-Z state if not in USER1)
--user_TDO1<=SPI_MISO;
user_TDO1<=tdo_mem(tdo_mem'high);
SPI_MOSI<='Z';
SPI_SCK<='Z';
SPI_CS<='Z';
if (user_SEL1='1') then
SPI_MOSI<='0';
SPI_SCK<='1';
--SPI_CS<='1';
SPI_CS<=not(CS_GO and not(CS_STOP));
if(user_SHIFT='1') then
SPI_SCK<=user_DRCK1;
--SPI_CS<='0';
SPI_MOSI<=user_TDI;
end if;
end if;
end process;
process(user_DRCK1)
variable i : integer;
begin
if(reset = '1')then
have_header<='0';
CS_GO<='0';
elsif(falling_edge(user_DRCK1))then
if ( have_header='0') then
if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then
len <= tdi_mem(15 downto 0);
have_header <= '1';
if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then
CS_GO <= '1';
end if;
end if;
elsif (len /= 0) then
len <= len - 1;
end if;
end if;
end process;
process(user_DRCK1)
variable i : integer;
variable j : integer;
begin
if(reset ='1') then
tdo_mem<=(others => '0');
tdi_mem<=(others => '0');
CS_STOP<='0';
elsif(rising_edge(user_DRCK1))then
tdi_mem(0)<=user_TDI;
for j in 1 to tdi_mem'high loop
tdi_mem(j)<=tdi_mem(j-1);
end loop;
tdo_mem(0)<=SPI_MISO;
for i in 1 to tdo_mem'high loop
tdo_mem(i)<=tdo_mem(i-1);
end loop;
if(CS_GO='1' and len=0)then
CS_STOP<='1';
end if;
end if;
end process;
end Behavioral;
| mit | 5201bf09887274337030c18ebca31d0b | 0.620009 | 2.899058 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/controller.vhd | 13 | 6,873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end controller;
architecture behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, DATAWAIT, READWAIT, RLE_POSTSCRIPT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter, ctr_delay : std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg, memoryWrite_i, memoryRead_i, rle_read_i, send_i : std_logic;
signal output_i : std_logic_vector (31 downto 0);
begin
rdstate <= '1' when state /= SAMPLE and state /= DELAY else '0';
ctr_delay <=
"00" & x"0000" when trig_delay = "01" else
"11" & x"fffe" when trig_delay = "10" else
"11" & x"fffd";
-- synchronization and reset logic
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= SAMPLE;
else
state <= nstate;
counter <= ncounter;
end if;
-- register outputs
output <= output_i;
memoryOut <= la_input;
memoryWrite <= memoryWrite_i;
memoryRead <= memoryRead_i;
send_i <= sendReg;
send <= sendReg;
rle_read <= rle_read_i;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, la_inputReady, bwd, busy, rle_busy,
data_ready, send_i, ctr_delay, abort, rle_mode, memoryIn)
begin
case state is
-- default mode: sample data from la_input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= ctr_delay;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- keep sampling for 4 * fwd + 4 samples after run condition
when DELAY =>
if (counter = fwd & "00") or (abort = '1') then
ncounter <= (others => '1');
nstate <= READ;
else
if la_inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmitter time
when READ =>
if counter = bwd & "11" then
if rle_busy = '1' then
ncounter <= counter;
nstate <= DATAWAIT;
rle_read_i <= '1';
else
ncounter <= (others => '0');
if rle_mode = '1' then
nstate <= RLE_POSTSCRIPT;
else
nstate <= SAMPLE;
end if;
rle_read_i <= '0';
end if;
memoryRead_i <= '0';
else
if rle_busy = '1' then
ncounter <= counter;
memoryRead_i <= '0';
else
ncounter <= counter + 1;
memoryRead_i <= '1';
end if;
nstate <= DATAWAIT;
rle_read_i <= '1';
end if;
memoryWrite_i <= '0';
sendReg <= '0';
output_i <= memoryIn;
when DATAWAIT =>
if data_ready = '1' then
nstate <= READWAIT;
sendReg <= '1';
else
nstate <= state;
sendReg <= '0';
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and send_i = '0' then
nstate <= READ;
else
nstate <= state;
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- send 0x00 0x00 0x00 0x00 0x55 as stop marker after the RLE data
when RLE_POSTSCRIPT =>
if busy = '0' then
if counter = 5 then
sendReg <= '0';
ncounter <= (others => '0');
nstate <= SAMPLE;
output_i <= (others => '0');
elsif counter = 4 and send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= x"00000055";
elsif send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= (others => '0');
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
| mit | bcce06e37f1bce2b13266ca929cbfbb6 | 0.586352 | 3.312289 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd | 13 | 8,035 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_UART is
generic (
bits: integer := 4
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
enabled: out std_logic; --An output that is active high when the UART is not in a reset state
tx: out std_logic; --UART Transmit pin
rx: in std_logic --UART Receive pin
);
end entity COMM_zpuino_wb_UART;
architecture behave of COMM_zpuino_wb_UART is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 8b7ddceed4f3bbfd9a2e46536a02b7d6 | 0.586185 | 3.187227 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/wb_bootloader.vhd | 14 | 2,328 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wb_bootloader is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(11 downto 2);
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
wb2_dat_o: out std_logic_vector(31 downto 0);
wb2_adr_i: in std_logic_vector(11 downto 2);
wb2_cyc_i: in std_logic;
wb2_stb_i: in std_logic;
wb2_ack_o: out std_logic;
wb2_stall_o: out std_logic
);
end wb_bootloader;
architecture behave of wb_bootloader is
component bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(11 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end component bootloader_dp_32;
signal ack: std_logic;
signal en: std_logic;
signal ack2: std_logic;
signal en2: std_logic;
begin
wb_stall_o <= '0';
wb2_stall_o <= '0';
wb_ack_o <= ack;
wb2_ack_o <= ack2;
en <= wb_cyc_i and wb_stb_i;
en2 <= wb2_cyc_i and wb2_stb_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack <= '0';
ack2 <= '0';
else
ack <= en;
ack2 <= en2 and not ack2;
end if;
end if;
end process;
rom: bootloader_dp_32
port map (
CLK => wb_clk_i,
WEA => '0',
ENA => en,
MASKA => (others => '1'),
ADDRA => wb_adr_i,
DIA => (others => DontCareValue),
DOA => wb_dat_o,
WEB => '0',
ENB => en2,
ADDRB => wb2_adr_i,
DIB => (others => DontCareValue),
MASKB => (others => '1'),
DOB => wb2_dat_o
);
end behave;
| mit | 1ec1d2419da427a3dc2df06dfcb1b951 | 0.542096 | 2.866995 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/rle_fmt.vhd | 13 | 3,532 | ---------------------------------------------------------------------------------
-- rle_fmt.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- inserts a zero count when the rle bit is not set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle_fmt is
generic(
data_width : integer := 32
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end rle_fmt;
architecture behavioral of rle_fmt is
type state_type is (S0, S1, S2, S3, S4);
signal state, nstate : state_type;
signal tmp, tmp_r, fmt_out_i, fmt_out_r : std_logic_vector ((data_width-1) downto 0);
signal busy_i, rle_ready_i : std_logic;
begin
fmt_out <= fmt_out_i;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= S0;
else
state <= nstate;
tmp_r <= tmp;
busy <= busy_i;
fmt_out_r <= fmt_out_i;
rle_ready <= rle_ready_i;
end if;
end if;
end process;
busy_i <= '1' when state = S4 else '0';
process(state, rle_inp_valid, raw_ready, rle_inp, tmp, tmp_r, fmt_out_r)
begin
case state is
when S0 =>
if rle_inp_valid = '1' then
nstate <= S1;
else
nstate <= state;
end if;
fmt_out_i <= fmt_out_r;
tmp <= tmp_r;
rle_ready_i <= '0';
when S1 =>
if raw_ready = '1' then
if rle_inp(data_width) = '1' then
nstate <= S2;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
else
nstate <= S4;
fmt_out_i <= (others => '0');
end if;
else
nstate <= state;
fmt_out_i <= fmt_out_r;
end if;
tmp <= rle_inp((data_width - 1) downto 0);
rle_ready_i <= raw_ready;
when S2 => -- send RLE data
if rle_inp_valid = '1' then
nstate <= S3;
else
nstate <= state;
end if;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
tmp <= tmp_r;
rle_ready_i <= '0';
when S3 =>
if raw_ready = '1' then
nstate <= S0;
else
nstate <= state;
end if;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
tmp <= tmp_r;
rle_ready_i <= raw_ready;
when S4 => -- send RLE data, counts = 0
if rle_inp_valid = '1' then
nstate <= S0;
fmt_out_i <= tmp;
else
nstate <= state;
fmt_out_i <= fmt_out_r;
end if;
tmp <= tmp_r;
rle_ready_i <= rle_inp_valid;
end case;
end process;
end behavioral;
| mit | d603e1ddfaa9744d1369c041f2cdc091 | 0.567384 | 3.03176 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev6.vhd | 1 | 38,078 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev6 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev6 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant ROUND2 : std_logic_vector(5 downto 0) := "111101";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal preev : WORD_VECTOR(0 to 15);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD2) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3=WPAD2) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
wout <= std_logic_vector(mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))));
elsif (Opcode2 = WPAD2) then
tmp1 <= std_Logic_vector(
unsigned((unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)))));
tmp2 <= std_logic_vector(
unsigned((unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8) xor unsigned(shift_right(unsigned(mvect(1)),7)))) +
unsigned(mvect(0))));
elsif (Opcode2 = ROUND1 ) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout)
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
register_file(to_integer(unsigned(RY2))) <= wout(63 downto 32);
register_file(to_integer(unsigned(RZ2))) <= wout(31 downto 0);
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD2) then
wout <= std_logic_vector(unsigned(tmp1)+unsigned(tmp2));
elsif (Opcode2 = ROUND1) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
register_file(to_integer(unsigned(RA2))) <= wva(63 downto 32);
register_file(to_integer(unsigned(RB2))) <= wva(31 downto 0);
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD2) then
mvect(15) <= wout;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3 = WPAD2) then
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
elsif (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 0d1f7cd091a6061a5087ea338e7f9fab | 0.647408 | 2.911162 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_hqvga.vhd | 13 | 10,522 | --
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
| mit | 7ac2c38a60975fa97ada5962ea0aeb84 | 0.592378 | 3.198176 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_spi.vhd | 13 | 7,384 | --
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
| mit | 640c1c199258e295b8e5df5ac92c28a1 | 0.559453 | 3.170459 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_io.vhd | 13 | 8,220 | --
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
| mit | fc0d009d12a1e3ae7f7a927a210345b0 | 0.615815 | 3.136208 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/muldex_16.vhd | 13 | 3,865 | ----------------------------------------------------------------------------------
-- muldex_8.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public Licenstate_wre as published by
-- the Free Software Foundation; either version 2 of the Licenstate_wre, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public Licenstate_wre for more details.
--
-- You should have received a copy of the GNU General Public Licenstate_wre along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Multiplexes and demultiplexes the 16 bit data into a 32 bit memory bus.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex_16 is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end muldex_16;
architecture behavioral of muldex_16 is
type wr_state_type is (W0, W1);
type rd_state_type is (RI, R0, R1);
signal state_wr, nstate_wr : wr_state_type;
signal state_rd, nstate_rd : rd_state_type;
signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (33 downto 0);
signal mw, mr : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state_wr <= W0;
state_rd <= RI;
else
state_wr <= nstate_wr;
state_rd <= nstate_rd;
end if;
wrtmp_r <= wrtmp;
rdtmp_r <= rdtmp;
-- registered outputs
mem_out <= wrtmp;
mem_wr <= mw;
mem_rd <= mr;
end if;
end process;
process(state_wr, data_wr, rle_in, wrtmp_r, data_inp)
begin
case state_wr is
when W0 =>
if data_wr = '1' then
nstate_wr <= W1;
wrtmp <= wrtmp_r(33) & rle_in
& wrtmp_r(31 downto 16) & data_inp;
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W1 =>
if data_wr = '1' then
nstate_wr <= W0;
wrtmp <= rle_in & wrtmp_r(32) & data_inp
& wrtmp_r(15 downto 0);
mw <= '1';
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
mw <= '0';
end if;
end case;
end process;
process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp)
begin
case state_rd is
when RI =>
if data_rd = '1' then
if state_wr = W0 then
nstate_rd <= R0;
mr <= '1';
else
nstate_rd <= R1;
mr <= '0';
end if;
else
nstate_rd <= state_rd;
mr <= '0';
end if;
rdtmp <= wrtmp;
data_out <= (others => 'X');
rle_out <= 'X';
when R0 =>
if data_rd = '1' then
nstate_rd <= R1;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(31 downto 16);
rle_out <= rdtmp_r(33);
when R1 =>
if data_rd = '1' then
nstate_rd <= R0;
rdtmp <= mem_inp;
mr <= '1';
else
nstate_rd <= state_rd;
rdtmp <= rdtmp_r;
mr <= '0';
end if;
data_out <= rdtmp_r(15 downto 0);
rle_out <= rdtmp_r(32);
end case;
end process;
end behavioral;
| mit | 68e8b89f442473a9185ec611d4c081ce | 0.564812 | 2.925814 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_spi.vhd | 1 | 7,379 | --
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
| mit | a4400e385c2607da0f19f77ad5ff0a05 | 0.559154 | 3.168313 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipeline4.vhd | 1 | 29,479 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipeline4 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipeline4 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-----------------------------------
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WPAD : std_logic_vector(5 downto 0) := "011101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
----------------------------------------------------------------
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
signal w_80 : WORD_VECTOR(0 to 79);
-------------------------------------------------------------------
--constant K_TABLE : WORD_VECTOR(0 to 79) := (
-- 0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
-- 1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
-- 2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
-- 3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
-- 4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
-- 5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
-- 6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
-- 7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
-- 8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
-- 9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
-- 10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
-- 11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
-- 12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
-- 13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
-- 14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
-- 15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
-- 16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
-- 17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
-- 18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
-- 19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
-- 20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
-- 21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
-- 22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
-- 23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
-- 24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
-- 25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
-- 26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
-- 27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
-- 28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
-- 29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
-- 30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
-- 31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
-- 32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
-- 33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
-- 34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
-- 35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
-- 36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
-- 37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
-- 38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
-- 39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
-- 40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
-- 41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
-- 42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
-- 43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
-- 44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
-- 45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
-- 46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
-- 47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
-- 48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
-- 49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
-- 50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
-- 51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
-- 52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
-- 53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
-- 54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
-- 55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
-- 56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
-- 57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
-- 58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
-- 59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
-- 60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
-- 61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
-- 62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
-- 63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
-- 64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
-- 65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
-- 66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
-- 67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
-- 68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
-- 69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
-- 70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
-- 71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
-- 72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
-- 73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
-- 74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
-- 75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
-- 76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
-- 77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
-- 78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
-- 79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
-- );
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal message0 : std_logic_vector(63 downto 0);
signal message1 : std_logic_vector(63 downto 0);
signal message2 : std_logic_vector(63 downto 0);
signal message3 : std_logic_vector(63 downto 0);
signal message4 : std_logic_vector(63 downto 0);
signal message5 : std_logic_vector(63 downto 0);
signal message6 : std_logic_vector(63 downto 0);
signal message7 : std_logic_vector(63 downto 0);
signal message8 : std_logic_vector(63 downto 0);
signal message9 : std_logic_vector(63 downto 0);
signal message10 : std_logic_vector(63 downto 0);
signal message11 : std_logic_vector(63 downto 0);
signal message12 : std_logic_vector(63 downto 0);
signal message13 : std_logic_vector(63 downto 0);
signal message14 : std_logic_vector(63 downto 0);
signal message15 : std_logic_vector(63 downto 0);
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2=STM or Opcode2=STR or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
variable h0 : WORD_TYPE;
variable h1 : WORD_TYPE;
variable h2 : WORD_TYPE;
variable h3 : WORD_TYPE;
variable h4 : WORD_TYPE;
variable h5 : WORD_TYPE;
variable h6 : WORD_TYPE;
variable h7 : WORD_TYPE;
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2= MLOAD0) then
message0 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message1 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message2 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message3 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
message4 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message5 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message6 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message7 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
message8 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message9 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message10 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message11 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
message12 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message13 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message14 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message15 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = WPAD) then
w_80(0) <= message0;
w_80(1) <= message1;
w_80(2) <= message2;
w_80(3) <= message3;
w_80(4) <= message4;
w_80(5) <= message5;
w_80(6) <= message6;
w_80(7) <= message7;
w_80(8) <= message8;
w_80(9) <= message9;
w_80(10) <= message10;
w_80(11) <= message11;
w_80(12) <= message12;
w_80(13) <= message13;
w_80(14) <= message14;
w_80(15) <= message15;
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif(Opcode2 = ROUND1) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))))
);
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
elsif(opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = ROUND1) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
elsif (Opcode2 = WPAD) then
w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))) <=
std_logic_vector(
unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 19)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 61)) xor unsigned(shift_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 6)) +
unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-7)) +
unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 1)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 8)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 7))+
unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-16)));
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR ) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
stage3 <= S2;
end if;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 03e403c97cf1f4ccd99459fab99fcfe3 | 0.630517 | 2.833974 | false | false | false | false |
algebrato/eldig | Contatore_1_cifra/Component_Contatore.vhd | 1 | 1,368 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Component_Contatore is
Port (
enable_in : in STD_LOGIC ;
N_out : out STD_LOGIC_VECTOR(3 downto 0);
enable_out : out STD_LOGIC;
clock_timer : in STD_LOGIC;
reset : in STD_LOGIC;
preset: in STD_LOGIC;
N_preset : in STD_LOGIC;
);
end Component_Contatore;
architecture Behavioral of Component_Contatore is
signal N: UNSIGNED(3 downto 0);
signal NN: UNSIGNED(15 downto 0);
signal clk_1k: STD_LOGIC;
begin
CLK_1K_O <= clk_1k; --collego le varie scatole con i segnali
N <= "0000";
mod_freq:process(CLK100M)
begin
if rising_edge(CLK100M) then
if NN=49999 then
NN<=(others => '0');
clk_1k <= not clk_1k;
else
NN<=NN+1;
end if;
end if;
end process mod_freq;
contatore_1_cifra:process(clk_1k)
begin
if rising_edge(contatore_1_cifra) then
if(reset = '1') then
C <=(others => '0');
else
if(preset ='1') then
C<= C_preset;
else
if(enable_in='1')then
if(up_down='1')then
if C = 9 then
C <=(others=>'0');
else
C<=C+1;
end if;
else
if C=0 then
C <= "1001";
else
C<=C-1;
end if;
end if;
end if;
end process contatore_1_cifra;
enable_out <= '1' when(((C=9) and up_down='1') or (C=0 and up_down='0')) and else '0';
end Behavioral;
| gpl-3.0 | 7632b7c4d1d42e42946123d5d5436c01 | 0.615497 | 2.561798 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/I2C/testbench/i2c_memory.vhdl | 1 | 16,292 | ------------------------------------------------------------------------------
---- ----
---- I2C Memory Simulator (slave) ----
---- ----
---- Internal file, can't be downloaded. ----
---- Based on code from: http://www.opencores.org/projects/i2c/ ----
---- ----
---- Description: ----
---- I2C memory simulator. The sda_x and scl_x signals should be ----
---- connected to "pull-ups" using 'H'. ----
---- This code is a translation of Verilog code from OpenCores. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Authors: ----
---- - Richard Herveille, [email protected] (Verilog) www.asics.ws ----
---- - John Sheahan, [email protected] ----
---- - Salvador E. Tropea, salvador en inti gov ar (VHDL translation) ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2001,2002 Richard Herveille <[email protected]> ----
---- ----
---- Covered by the GPL license. ----
---- ----
---- Original distribution policy: ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_Memory(Simulator) (Entity and architecture) ----
---- File name: i2c_memory.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- c.stdio_h ----
---- Target FPGA: None ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: None ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: i2c_memory.vhdl,v $
-- Revision 1.6 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.5 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.4 2005/05/18 14:50:20 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library c;
use c.stdio_h.all;
entity I2C_Memory is
generic(
-- I2C device address
I2C_ADR : std_logic_vector(6 downto 0):="0010000";
-- To make it more verbose
DEBUG : boolean:=false);
port(
-- I2C Clock signal, needs a pull-up ('H')
scl_x_i : in std_logic;
-- I2C Data signal, needs a pull-up ('H')
sda_x_io : inout std_logic;
-- Asynchronous reset
rst_i : in std_logic);
end entity I2C_Memory;
architecture Simulator of I2C_Memory is
type memory is array (3 downto 0) of std_logic_vector(7 downto 0);
signal mem : memory;
signal mem_adr : unsigned(1 downto 0); -- memory address
signal mem_do : std_logic_vector(7 downto 0); -- memory data output
signal sta, d_sta : std_logic;
signal sto, d_sto : std_logic;
signal sr : std_logic_vector(7 downto 0):=(others => '0'); -- 8bit shift register
signal rw : std_logic; -- read/write direction
signal i2c_reset : std_logic; -- i2c-statemachine reset
signal bit_cnt : unsigned(2 downto 0):=(others => '0'); -- 3bit downcounter
signal acc_done : boolean; -- 8bits transfered
signal ld : std_logic; -- load downcounter
signal sda_o : std_logic:='1'; -- sda-drive level
signal scl : std_logic;
signal sda : std_logic;
-- statemachine declaration
type states is (idle, slave_ack, get_mem_adr, gma_ack, data, data_ack);
signal state : states:=idle;
begin
Shift_Register:
process
begin
wait until scl'event;
if scl='1' and rst_i='0' then
--Wait for 1 us;
sr <= sr(6 downto 0) & sda;
end if;
end process Shift_Register;
Bit_Counter:
process
begin
wait until scl'event or rst_i'event;
if rst_i='1' then
bit_cnt <= "000";
elsif scl'event and scl='1' then
if ld='1' then
--Wait for 1 us;
bit_cnt <= "111";
else
--Wait for 1 us;
bit_cnt <= bit_cnt-1;
end if;
end if;
end process Bit_Counter;
-- Access done signal
acc_done <= bit_cnt="000";
Detect_Start_Condition:
process
begin
wait until sda'event;
if sda='0' then
if scl='1' then
if DEBUG then
assert false report "Start condition" severity note;
end if;
sta <= '1';
d_sta <= '0';
else
--Wait for 1 us;
sta <= '0';
end if;
else -- sda=1 rising edge
-- Stop condition
if scl='1' then
sta <= '0';
end if;
end if;
end process Detect_Start_Condition;
Delayed_Start:
process
begin
wait until scl'event;
if scl='1' then
--Wait for 1 us;
d_sta <= sta;
end if;
end process Delayed_Start;
Detect_Stop_Condition:
process
begin
wait until sda'event;
if sda='1' then
if scl='1' then
if DEBUG then
assert false report "Stop condition" severity note;
end if;
--Wait for 1 us;
sto <= '1';
else
--Wait for 1 us;
sto <= '0';
end if;
else -- sda=0 falling edge
-- Start condition
if scl='1' then
--Wait for 1 us;
sto <= '0';
end if;
end if;
end process Detect_Stop_Condition;
i2c_reset <= sta or sto;
Statemachine:
process
variable my_adr : boolean:=false;
begin
wait until scl'event or sto'event;
if scl='0' or sto='1' then
if sto='1' or (sta='1' and d_sta='0') then
if DEBUG then
assert false report "Reset statemachine" severity note;
end if;
--Wait for 1 us;
state <= idle; -- reset statemachine
sda_o <= '1';
ld <= '1';
my_adr:=false;
else
--Wait for 1 us;
-- Initial settings
sda_o <= '1';
ld <= '0';
case state is
when idle => -- idle state
if acc_done and not(my_adr) then
my_adr:=sr(7 downto 1)=I2C_ADR;
end if;
if DEBUG then
printf("state=idle acc_done=%d",acc_done);
printf(" my_adr=%d\n",my_adr);
end if;
if acc_done and my_adr then
state <= slave_ack;
rw <= sr(0);
sda_o <= '0'; -- generate i2c_ack
if DEBUG then
assert false report "Command byte received" severity note;
if sr(0)='1' then
printf("\n\nRead command 0x%X\n\n",sr);
else
printf("\n\nWrite command 0x%X\n\n",sr);
end if;
end if;
if sr(0)='1' then
--Wait for 1 us;
mem_do <= mem(to_integer(mem_adr));
if DEBUG then
assert false report "Data block read" severity note;
end if;
end if;
end if;
when slave_ack =>
if DEBUG then
printf("state=slave_ack\n");
end if;
if rw='1' then
--Wait for 1 us;
state <= data;
ld <= '1';
sda_o <= mem_do(7);
mem_do<= mem_do(6 downto 0) & '1'; -- insert '1' for host ack generation
else
--Wait for 1 us;
state <= get_mem_adr;
ld <= '1';
end if;
when get_mem_adr => -- wait for memory address
if DEBUG then
printf("state=get_mem_adr\n");
end if;
if acc_done then
if unsigned(sr)<=15 then -- generate i2c_ack, for valid address
--Wait for 1 us;
sda_o <= '0';
else
--Wait for 1 us;
sda_o <= '1';
end if;
state <= gma_ack;
mem_adr <= unsigned(sr(1 downto 0)); -- store memory address
if DEBUG then
assert false report "Address received" severity note;
printf("\nMemory Address 0x%X (next state is gma_ack)\n\n",sr);
end if;
end if;
when gma_ack =>
if DEBUG then
printf("state=gma_ack\n");
end if;
--Wait for 1 us;
state <= data;
ld <= '1';
when data => -- receive or drive data
if DEBUG then
printf("state=data bit_cnt=%d",to_integer(bit_cnt));
printf(" acc_done=%d\n",acc_done);
end if;
if rw='1' then
--Wait for 1 us;
sda_o <= mem_do(7);
mem_do <= mem_do(6 downto 0) & '1'; -- insert '1' for host ack generation
end if;
if acc_done then
state <= data_ack;
if rw='0' and (mem_adr<=15) then
sda_o <= '0'; -- send ack on write
end if;
--Wait for 1 us;
mem_adr <= mem_adr+1;
if rw='1' then
--Wait for 3 us;
mem_do <= mem(to_integer(mem_adr+1));
if DEBUG then
assert false report "Data block read" severity note;
printf("\nEnd of read address 0x%X=",to_integer(mem_adr));
printf("0x%X\n\n",mem(to_integer(mem_adr)));
end if;
else
--Wait for 1 us;
mem(to_integer(mem_adr)) <= sr; -- store data in memory
if DEBUG then
assert false report "Data block write" severity note;
printf("\nEnd of write 0x%X ",sr);
printf("to 0x%X\n\n",to_integer(mem_adr));
end if;
end if;
end if;
when data_ack =>
if DEBUG then
printf("state=data_ack\n");
end if;
--Wait for 1 us;
ld <= '1';
if rw='1' then
if sda='1' then -- read operation && master send NACK
state <= idle;
sda_o <= '1';
else
state <= data;
sda_o <= mem_do(7);
mem_do<= mem_do(6 downto 0) & '1'; -- insert '1' for host ack generation
end if;
else
state <= data;
sda_o <= '1';
end if;
end case;
end if;
end if;
end process Statemachine;
-- Generate tri-states
sda_x_io<= 'Z' when sda_o='1' else '0';
-- Solve the "H" state
sda <= to_x01z(sda_x_io);
scl <= to_x01z(scl_x_i);
end architecture Simulator; -- of entity I2C_Memory
| mit | 4829d2a162cc6c2b3ebf372184037d6c | 0.372146 | 5.002149 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/prom-generic-dp-32.vhd | 13 | 200,723 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(14 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(14 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport;
architecture behave of prom_generic_dualport is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 8191) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit | 00e71dd55eb36b2a4b96455dc3d7a94d | 0.502219 | 1.505381 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.b-decode.core/a.b.b.c-Sign_Extender.vhd | 2 | 1,342 | -------------------------------------------------------------------------------------------------------------
-- Sign Extender
-- This block performs the sign extension in for the jump address(instruction 25-0)
-------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
entity sign_extender is
port (
-- INPUTS
immediate_jump : in std_logic_vector(25 downto 0); -- instructon (25-0)
-- OUTPUTS
extended_jump : out std_logic_vector(31 downto 0) -- sign-extended jump immediate
);
end sign_extender;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
architecture behavioral of sign_extender is
begin
extended_jump(25 downto 0) <= immediate_jump;
extended_jump(31 downto 26) <= (others => '1') when (immediate_jump(25) = '1') else (others => '0');
end behavioral;
| mit | 3704e7337e066dc6ec9b7089c56ae60d | 0.330849 | 6.36019 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_sigmadelta.vhd | 1 | 6,744 | --
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 �lvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
use work.zpu_config.all;
use work.zpuinopkg.all;
entity zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end entity zpuino_sigmadelta;
architecture behave of zpuino_sigmadelta is
signal delta_adder1: unsigned(17 downto 0);
signal sigma_adder1: unsigned(17 downto 0);
signal sigma_latch1: unsigned(17 downto 0);
signal delta_b1: unsigned(17 downto 0);
signal delta_adder2: unsigned(17 downto 0);
signal sigma_adder2: unsigned(17 downto 0);
signal sigma_latch2: unsigned(17 downto 0);
signal delta_b2: unsigned(17 downto 0);
signal dat_q1: unsigned(17 downto 0);
signal dat_q2: unsigned(17 downto 0);
signal sync_dat_q1: unsigned(17 downto 0);
signal sync_dat_q2: unsigned(17 downto 0);
signal sd_en_q: std_logic_vector(1 downto 0);
signal sdout: std_logic_vector(1 downto 0);
signal sdtick: std_logic;
signal sdcnt: integer;
signal le_q: std_logic;
signal do_sync: std_logic;
signal extsync_q: std_logic;
begin
wb_dat_o <= (others => DontCareValue);
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
raw_out(17 downto 2) <= std_logic_vector(dat_q1(15 downto 0));
raw_out(1 downto 0)<=(others => '0');
process(wb_clk_i)
variable in_le1,in_le2: std_logic_vector(15 downto 0);
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dat_q1 <= (others =>'0');
dat_q1(15) <= '1';
dat_q2 <= (others =>'0');
dat_q2(15) <= '1';
sd_en_q <= (others =>'0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(2) is
when '0' =>
sd_en_q(0) <= wb_dat_i(0);
sd_en_q(1) <= wb_dat_i(1);
le_q <= wb_dat_i(2);
extsync_q <= wb_dat_i(3);
when '1' =>
--report "SigmaDelta set: " & hstr(wb_dat_i(15 downto 0)) severity note;
case le_q is
when '0' =>
dat_q1(15 downto 0) <= unsigned(wb_dat_i(15 downto 0));
dat_q2(15 downto 0) <= unsigned(wb_dat_i(31 downto 16));
when '1' =>
in_le1(15 downto 8) := wb_dat_i(7 downto 0);
in_le1(7 downto 0) := wb_dat_i(15 downto 8);
in_le2(15 downto 8) := wb_dat_i(23 downto 16);
in_le2(7 downto 0) := wb_dat_i(31 downto 24);
dat_q1(15 downto 0) <= unsigned(in_le1);
dat_q2(15 downto 0) <= unsigned(in_le2);
when others =>
end case;
when others =>
end case;
end if;
end if;
end if;
end process;
process(extsync_q,sync_in)
begin
if extsync_q='1' then
do_sync <= sync_in;
else
do_sync <='1';
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if do_sync='1' then
sync_dat_q1 <= dat_q1;
sync_dat_q2 <= dat_q2;
end if;
end if;
end process;
process(sigma_latch1)
begin
delta_b1(17) <= sigma_latch1(17);
delta_b1(16) <= sigma_latch1(17);
delta_b1(15 downto 0) <= (others => '0');
end process;
process(sigma_latch2)
begin
delta_b2(17) <= sigma_latch2(17);
delta_b2(16) <= sigma_latch2(17);
delta_b2(15 downto 0) <= (others => '0');
end process;
process(sync_dat_q1, delta_b1)
begin
delta_adder1 <= sync_dat_q1 + delta_b1;
end process;
process(sync_dat_q2, delta_b2)
begin
delta_adder2 <= sync_dat_q2 + delta_b2;
end process;
process(delta_adder1,sigma_latch1)
begin
sigma_adder1 <= delta_adder1 + sigma_latch1;
end process;
process(delta_adder2,sigma_latch2)
begin
sigma_adder2 <= delta_adder2 + sigma_latch2;
end process;
-- Divider
-- process(wb_clk_i)
-- begin
-- if rising_edge(wb_clk_i) then
-- if wb_rst_i='1' then
-- sdtick<='0';
-- sdcnt<=3;
-- else
-- if sdcnt/=0 then
-- sdcnt<=sdcnt-1;
-- sdtick<='0';
-- else
-- sdtick<='1';
-- sdcnt<=3;
-- end if;
-- end if;
-- end if;
-- end process;
sdtick <= '1'; -- for now
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
sigma_latch1 <= (others => '0');
sigma_latch1(17) <= '1';
sdout <= (others=>'0');
sigma_latch2 <= (others => '0');
sigma_latch2(17) <= '1';
else
if sdtick='1' then
if sd_en_q(0)='1' then
sigma_latch1 <= sigma_adder1;
sdout(0) <= sigma_latch1(17);
end if;
if sd_en_q(1)='1' then
sdout(1) <= sigma_latch2(17);
sigma_latch2 <= sigma_adder2;
end if;
end if;
end if;
end if;
end process;
spp_data <= sdout;
spp_en <= sd_en_q;
end behave;
| mit | e0374df469620f996de657d977ffd10e | 0.617324 | 2.968736 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/zpu_config.vhd | 14 | 2,691 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
| mit | 2b3d9f01de38c31ba5b63a7cd3c8ecfd | 0.736529 | 3.7375 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/example_design/frame_buffer_exdes.vhd | 1 | 5,000 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: frame_buffer_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY frame_buffer_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END frame_buffer_exdes;
ARCHITECTURE xilinx OF frame_buffer_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT frame_buffer IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : frame_buffer
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| mit | 3598da33c062bf4c8cb3306d13e7dcf5 | 0.5598 | 4.655493 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/muldex_8.vhd | 13 | 4,970 | ----------------------------------------------------------------------------------
-- muldex_8.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Multiplexes and demultiplexes the 8 bit data into a 32 bit memory bus.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex_8 is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end muldex_8;
architecture behavioral of muldex_8 is
type wr_state_type is (W0, W1, W2, W3);
type rd_state_type is (RI, R0, R1, R2, R3);
signal state_wr, nstate_wr : wr_state_type;
signal state_rd, nstate_rd : rd_state_type;
signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (35 downto 0);
signal mw, mr : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state_wr <= W0;
state_rd <= RI;
else
state_wr <= nstate_wr;
state_rd <= nstate_rd;
end if;
wrtmp_r <= wrtmp;
rdtmp_r <= rdtmp;
-- registered outputs
mem_out <= wrtmp;
mem_wr <= mw;
mem_rd <= mr;
end if;
end process;
process(state_wr, data_wr, rle_in, wrtmp_r, data_inp)
begin
case state_wr is
when W0 =>
if data_wr = '1' then
nstate_wr <= W1;
wrtmp <= wrtmp_r(35 downto 33) & rle_in
& wrtmp_r(31 downto 8) & data_inp;
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W1 =>
if data_wr = '1' then
nstate_wr <= W2;
wrtmp <= wrtmp_r(35 downto 34) & rle_in
& wrtmp_r(32 downto 16)
& data_inp & wrtmp_r(7 downto 0);
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W2 =>
if data_wr = '1' then
nstate_wr <= W3;
wrtmp <= wrtmp_r(35 downto 35) & rle_in
& wrtmp_r(33 downto 24) & data_inp
& wrtmp_r(15 downto 0);
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W3 =>
if data_wr = '1' then
nstate_wr <= W0;
wrtmp <= rle_in & wrtmp_r(34 downto 32)
& data_inp & wrtmp_r(23 downto 0);
mw <= '1';
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
mw <= '0';
end if;
end case;
end process;
process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp)
begin
case state_rd is
when RI =>
if data_rd = '1' then
if state_wr = W0 then
nstate_rd <= R0;
mr <= '1';
elsif state_wr = W1 then
nstate_rd <= R1;
mr <= '0';
elsif state_wr = W2 then
nstate_rd <= R2;
mr <= '0';
else
nstate_rd <= R3;
mr <= '0';
end if;
else
nstate_rd <= state_rd;
mr <= '0';
end if;
rdtmp <= wrtmp;
data_out <= (others => 'X');
rle_out <= 'X';
when R0 =>
if data_rd = '1' then
nstate_rd <= R3;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(31 downto 24);
rle_out <= rdtmp_r(35);
when R1 =>
if data_rd = '1' then
nstate_rd <= R0;
rdtmp <= mem_inp;
mr <= '1';
else
nstate_rd <= state_rd;
rdtmp <= rdtmp_r;
mr <= '0';
end if;
data_out <= rdtmp_r(7 downto 0);
rle_out <= rdtmp_r(32);
when R2 =>
if data_rd = '1' then
nstate_rd <= R1;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(15 downto 8);
rle_out <= rdtmp_r(33);
when R3 =>
if data_rd = '1' then
nstate_rd <= R2;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(23 downto 16);
rle_out <= rdtmp_r(34);
end case;
end process;
end behavioral;
| mit | 0b92c709e1e1e388c31f34f5f61f1755 | 0.544266 | 2.81746 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/title1_1/title1_sim_netlist.vhdl | 1 | 143,561 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:30 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title1_1/title1_sim_netlist.vhdl
-- Design : title1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_bindec : entity is "bindec";
end title1_bindec;
architecture STRUCTURE of title1_bindec is
begin
\ENOUT_inferred__5/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(1),
I1 => addra(2),
I2 => addra(0),
O => ena_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_7_out : in STD_LOGIC_VECTOR ( 8 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end title1_blk_mem_gen_mux;
architecture STRUCTURE of title1_blk_mem_gen_mux is
signal \douta[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\douta[1]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[1]_INST_0_i_1_n_0\,
I1 => \douta[1]_INST_0_i_2_n_0\,
O => douta(0),
S => sel_pipe_d1(2)
);
\douta[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(0),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
O => \douta[1]_INST_0_i_1_n_0\
);
\douta[1]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(0),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
O => \douta[1]_INST_0_i_2_n_0\
);
\douta[2]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[2]_INST_0_i_1_n_0\,
I1 => \douta[2]_INST_0_i_2_n_0\,
O => douta(1),
S => sel_pipe_d1(2)
);
\douta[2]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(1),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
O => \douta[2]_INST_0_i_1_n_0\
);
\douta[2]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(1),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
O => \douta[2]_INST_0_i_2_n_0\
);
\douta[3]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_1_n_0\,
I1 => \douta[3]_INST_0_i_2_n_0\,
O => douta(2),
S => sel_pipe_d1(2)
);
\douta[3]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(2),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
O => \douta[3]_INST_0_i_1_n_0\
);
\douta[3]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(2),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
O => \douta[3]_INST_0_i_2_n_0\
);
\douta[4]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => \douta[4]_INST_0_i_2_n_0\,
O => douta(3),
S => sel_pipe_d1(2)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(3),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
O => \douta[4]_INST_0_i_1_n_0\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(3),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
O => \douta[4]_INST_0_i_2_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => \douta[5]_INST_0_i_2_n_0\,
O => douta(4),
S => sel_pipe_d1(2)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(4),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
O => \douta[5]_INST_0_i_1_n_0\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(4),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
O => \douta[5]_INST_0_i_2_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => \douta[6]_INST_0_i_2_n_0\,
O => douta(5),
S => sel_pipe_d1(2)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(5),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
O => \douta[6]_INST_0_i_1_n_0\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(5),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
O => \douta[6]_INST_0_i_2_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => \douta[7]_INST_0_i_2_n_0\,
O => douta(6),
S => sel_pipe_d1(2)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(6),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
O => \douta[7]_INST_0_i_1_n_0\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(6),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
O => \douta[7]_INST_0_i_2_n_0\
);
\douta[8]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[8]_INST_0_i_1_n_0\,
I1 => \douta[8]_INST_0_i_2_n_0\,
O => douta(7),
S => sel_pipe_d1(2)
);
\douta[8]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOADO(7),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
O => \douta[8]_INST_0_i_1_n_0\
);
\douta[8]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(7),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
O => \douta[8]_INST_0_i_2_n_0\
);
\douta[9]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[9]_INST_0_i_1_n_0\,
I1 => \douta[9]_INST_0_i_2_n_0\,
O => douta(8),
S => sel_pipe_d1(2)
);
\douta[9]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => DOPADOP(0),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
O => \douta[9]_INST_0_i_1_n_0\
);
\douta[9]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => p_7_out(8),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
O => \douta[9]_INST_0_i_2_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end title1_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of title1_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0800000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000002000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000001000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000600000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[8]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title1_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"000000000000000000000FC00000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000003C00000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000407F80000000000000000",
INITP_06 => X"001FFFF800000000000000000000000000000000000000000000001FFBF80000",
INITP_07 => X"000000000000003FFFFE8000000000000FA00000000000000000000000000000",
INITP_08 => X"800000000000000000000000000F87FFC000000000005FD0001C000000000000",
INITP_09 => X"00001C7F001FF00000000000000000000000000403FFE000000000003FE0001F",
INITP_0A => X"000FFC00000000001CFF0017FE00000000000000000000000000003FE0000000",
INITP_0B => X"000000000000000F9C00000000001FBFC003FF00000000000000000000000000",
INITP_0C => X"080000020000000000000000000FC400000000000EBFC001FFE0000000000000",
INITP_0D => X"003FC0007FF00000007FF0000000000000000007E00000000000003FC000FFF0",
INITP_0E => X"E80000000000003FE0003FB80400007FFC000000000000000007E00000000000",
INITP_0F => X"000000000003F00000000000003FE0000FC80E0000FFFC000000000000000001",
INIT_00 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_01 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_02 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_03 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_04 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_05 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_06 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_07 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_08 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_09 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0E => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_10 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_11 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_12 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_13 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_14 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_15 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_16 => X"7878000000000000000078787878787878787878787878787878787878787878",
INIT_17 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_18 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_19 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_1A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_1B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_1C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_1D => X"7878787878787878787878787878787878780000A05050505050087878787878",
INIT_1E => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_1F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_20 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_21 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_22 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_23 => X"7800000000C8F8F8F8F860000078787878787878787878787878787878787878",
INIT_24 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_25 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_26 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_27 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_28 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_29 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_2A => X"7878787878787878787878000010000000002020201050F8F8F8F8F810007878",
INIT_2B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_2C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_2D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_2E => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_2F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_30 => X"50D8F8F8F8E850F8F8F8F8F8D800007878787878787878787878787878787878",
INIT_31 => X"7878787878787878787878787878787878787878787878787878005050505050",
INIT_32 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_33 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_34 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_35 => X"7878787878787878787878787878787878787800000000000000787878787878",
INIT_36 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_37 => X"7878787878787878780000F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8600000",
INIT_38 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_39 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_3A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_3B => X"787800A8F8F8F8F8F82010000000000078787878787878787878000000007800",
INIT_3C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_3D => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8A898007878787878787878787878787878",
INIT_3E => X"787878787878787878787878787878787878787878787878780070F8F8F8F8F8",
INIT_3F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_40 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_41 => X"0000787878787878780000505050E80008007878787878787878787878787878",
INIT_42 => X"78787878787878787878787878787878001000F8F8F8F8F8F8F8E81000000000",
INIT_43 => X"F850887878787878787878787878787878787878787878787878787878787878",
INIT_44 => X"7878787878787878000020A83078F8F8F8E8A8A8A850F8F8F8F8F8F8F8F8F8F8",
INIT_45 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_46 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_47 => X"7000000078787878787878787878787878787878787878787878787878787878",
INIT_48 => X"8080D8F8F8F870B8F8F8F820000000000000787878787878780000F8F8F8F870",
INIT_49 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_4A => X"88880000000070F8F8F8F8F8F8F8F8F8F8F87000787878787878787878787878",
INIT_4B => X"7878787878787878787878787878787878787878787878000000000000108888",
INIT_4C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_4D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_4E => X"C808787878787878780868F8F8F8F8F8F8F8F8F8200000787878787878787878",
INIT_4F => X"78787878787878787878787878787878780060F8F8F8000060F8F8F8F8F8F8F8",
INIT_50 => X"F8F8F8E820000078787878787878787878787878787878787878787878787878",
INIT_51 => X"78787878787878000000000000000000000000000000000000001870F8F8F8F8",
INIT_52 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_53 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_54 => X"F8F8F8F8F8505000107878787878787878787878787878787878787878787878",
INIT_55 => X"000020F8F8F800A870F8F8F8F8F8F8F8C8080000787878780000A830C8F8F8F8",
INIT_56 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_57 => X"000000000000000000000040F8F8F8F8F8F8F8F8F8D800787878787878787878",
INIT_58 => X"7878787878787878787878787878787878787878787878000000000000000000",
INIT_59 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_5A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_5B => X"F898080078787878000000008860F8F8F8F8F8F8F8F8F870D000787878787878",
INIT_5C => X"78787878787878787878787878787878000000F8F8F870F8F888B8F8F8F8F8F8",
INIT_5D => X"F8408898F8F80078787878787878787878787878787878787878787878787878",
INIT_5E => X"7878787878787800000000000008080000000000000000000000008870F8F8F8",
INIT_5F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_60 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_61 => X"F8F8F8F8F8F8F8F8F8F898087878787878787878787878787878787878787878",
INIT_62 => X"00000060F8F8F860100030F8F8F8F8F8F8F808007878780008000000000068F8",
INIT_63 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_64 => X"78000008080808080000000050F8F8F8F8F8A800005000787878787878787878",
INIT_65 => X"7878787878787878787878787878787878787878787878787800000000000000",
INIT_66 => X"0000000000787878787878787878787878787878787878787878787878787878",
INIT_67 => X"7878787888200000787878787878787878787878787878000000001028209800",
INIT_68 => X"F8F800007878780000000000000088C8F8F8F8F8F8F8F8F8F8F8F85878787878",
INIT_69 => X"7878787878787878787878787878787800000000A8A82000000030F8F8F8F8F8",
INIT_6A => X"F8F8F80000000078787878787878787878787878787878787878787878787878",
INIT_6B => X"7878787878787878787878787878787878780000000000000000000000B8F8F8",
INIT_6C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_6D => X"7878787878780000009898D8F8F8F85050505050000000787878787878787878",
INIT_6E => X"90F8F8F8F8F8F8F8F8F8F8500078787878787878808888000078787878787878",
INIT_6F => X"0000000000000800000030F8F8F8F8F8F8F80008007878780000000000000088",
INIT_70 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_71 => X"7878787878787800000000000010F8F8F8F8F860000078787878787878787878",
INIT_72 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_73 => X"F8F8F8F870D80000787878787878787878787878787878787878787878787878",
INIT_74 => X"78787800207000080078787878787878787878787800000000F8F8F8F8F8F8F8",
INIT_75 => X"F8F898000078787878000000000000008860F8F8F8F8F8F87060F8F898787878",
INIT_76 => X"7878787878787878787878787878787878080000000000000000C0F8F8F8F8F8",
INIT_77 => X"F8F8F8E810007878787878787878787878787878787878787878787878787878",
INIT_78 => X"78787878787878787878787800000000000000000000000000000000008840F8",
INIT_79 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_7A => X"7878780000008860F8F8F8F8F8F8F8F8F8F8F8F8F8F840A80078787878787878",
INIT_7B => X"0000B0E8F8F8F8F87010B0409878787878780020F8F870000000787878787878",
INIT_7C => X"7800000000000000000030F8F8F8F8F8F8F87000007878787878000000000000",
INIT_7D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_7E => X"88889088888888908800000000001070F8F8F8F8400078787878787878787878",
INIT_7F => X"7878787878787878787878787878787878787878787878787878780000000888",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[8]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[9]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title1_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0FFFFF80000000000003FFC0F00000000000003FE0000FC03F0001FFFF800000",
INITP_01 => X"E0000FC01F803FFFFFC000000000004FFF82780000000000001FF0000FC03F80",
INITP_02 => X"001C0000003FE00007F01FF0FFFE0FF00000000000BFFFFDFC0000000000003F",
INITP_03 => X"00FFFFFFFE0000BE0000003FF00001F81FFFFFFC03F00000000000FFFFFFFC00",
INITP_04 => X"03F00000000000FFFFFFFC00007F8000003FF80001F80FFFFFF007F800000000",
INITP_05 => X"007C03FFFFE001F0003C000001FFBF7FFC00001F8000003FF80000F807FFFFE0",
INITP_06 => X"F200007FF800003C01FFFF800060003C001001FE0007FD000017C400007FF800",
INITP_07 => X"0000BE0187FFF000007FFC00003C00FFFE000000007FC3F001FD0000FE00000F",
INITP_08 => X"07FFFA7801FC00000C038FFFFF8800FFFC00003E001FFE00000001FFF0F001FC",
INITP_09 => X"0000000000000BFFFE7000FC00001C0E1FFFFFF8007FFE00003E000000000000",
INITP_0A => X"017EFF00001E00000000000007BFFFBC00FC0000000F3FFFFFFC007FFF00001E",
INITP_0B => X"003E3F807FFF01FEFE00001E0000000000000E1E5FBC00FC0000003E3FFFFFFF",
INITP_0C => X"87FE003F800000783F807FFF03FEFF00001E0000000000001E3F0FFE007E0000",
INITP_0D => X"000000001C1F03FE023FC00000703F805FC301FE3F00000E0000000000001E3F",
INITP_0E => X"3FC0001C0000000000001E3F01FF001FF00020303F803FC001FC3FC0000C0000",
INITP_0F => X"1FE00FF0003E1FE000180000000000001C3F807F800FFC03E0701F800FC0007C",
INIT_00 => X"F8F8F8F8F8F8F8F8C00000787878787878787878787878787878787878787878",
INIT_01 => X"7800B8F8F8F8F8B8000000787878787878000000000860F8F8F8F8F8F8F8F8F8",
INIT_02 => X"F8F8700000787878787878000000000000000088F8F8F8F8F870000888787878",
INIT_03 => X"787878787878787878787878787878787800007878787808000030F8F8F8F8F8",
INIT_04 => X"F8F8F8F848007878787878787878787878787878787878787878787878787878",
INIT_05 => X"78787878787878780000000000E8707070707070707070707018000000000088",
INIT_06 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_07 => X"780000085070F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8A8000078787878",
INIT_08 => X"00000000F8F8F8F8F8F88800007878787808E0F8F8F8F8F89808007878787878",
INIT_09 => X"7878787878780000000040F8F8F8F8F8F8F87098007878787878787800000000",
INIT_0A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0B => X"F8F8F8F8F8F8F8F8F8A820202020100060F8F8F8F8B000787878787878787878",
INIT_0C => X"7878787878787878787878787878787878787878787878000010202050F8F8F8",
INIT_0D => X"F8F8F8F8F8F8F8F8F8F820087878787878787878787878787878787878787878",
INIT_0E => X"780060F8F8F8F8F8F800080000000000000810F8F8F8F8F8F8F8F8F8F8F8F8F8",
INIT_0F => X"F8F8F8C80078787878787878780000000000000030F8F8F8F8F8C80008787878",
INIT_10 => X"7878787878787878787878787878787878787878787800000088F8F8F8F8F8F8",
INIT_11 => X"D8F8F8F8F8F80078787878787878787878787878787878787878000000000078",
INIT_12 => X"787878787878000018E8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8E850",
INIT_13 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_14 => X"5050D8F8F8F8F8F8F8F8F8F8F8F8F8E8A8A8A8A8F8F8F8F8F8F8F8B800787878",
INIT_15 => X"000000000030F8F8F8F8F85008787878000020F8F8F8F8F8F850501000000000",
INIT_16 => X"78787878787800000088F8F8F8F8F8F8F8F8F8C8000078787878787878780000",
INIT_17 => X"7878787878787878000060707070000000787878787878787878787878787878",
INIT_18 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F808787878787878787878",
INIT_19 => X"78787878787878787878787878787878787878787878000898F8F8F8F8F8F8F8",
INIT_1A => X"0000000088A8F8F8F8F8F8D80078787878787878787878787878787878787878",
INIT_1B => X"000090F8F8F8F8F8F8F8F8F870707070F8F8F8F8F8F8F8F8F8F8F8F8F8308888",
INIT_1C => X"F8F8F8D8900800787878787878787800080000000000C8F8F8F8F8F898787878",
INIT_1D => X"0000787878787878787878787878787878787878787800000088F8F8F8F8F8F8",
INIT_1E => X"F8F8F8F8F8F8980078787878787878787878787878780008D8E8F8F8F8F87020",
INIT_1F => X"7878787878780000F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8",
INIT_20 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_21 => X"F8F8F8F8F8F8F8F8F8F8F8F84088000000000000009870F8F8F8F8F830787878",
INIT_22 => X"0000000000000030F8F8F8F89808787800000088F8F8F8F8F8F8F8F8F8F8F8F8",
INIT_23 => X"78787878787800000088F8F8F8F8F8F8F8F8F8F8980800007878787878787878",
INIT_24 => X"7878787878000000001870F8F8F8F8F8D8080080787878787878787878787878",
INIT_25 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8E8087878787878787878",
INIT_26 => X"7878787878787878787878787878787878787878780000C8F8F8F8F8F8F8F8F8",
INIT_27 => X"00000000000098F8F8F8F8F8A878787878787878787878787878000000000078",
INIT_28 => X"00000000D0F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8A800000000",
INIT_29 => X"F8F8F8F8700000807878787878787878780000000000000830F8F8F870880078",
INIT_2A => X"F860000080787878787878787878787878787878787800000098F8F8F8F8F8F8",
INIT_2B => X"F8F8F8F8F8F8E80078787878787878787878787800080000000088F8F8F8F8F8",
INIT_2C => X"7878787878000070F8F8F8F8F8F8F8F8F8881818181818189070F8F8F8F8F8F8",
INIT_2D => X"78787878787878787878987070D8007878787878787878787878787878787878",
INIT_2E => X"F8F8F8F8F8F8F8F8F8F8F890080000000800000000000010F8F8F8F8A8787878",
INIT_2F => X"7800000000000000A8F8F8F8F8980078000000000060F8F8F8F8F8F8F8F8F8F8",
INIT_30 => X"787878787878000000F8F8F8F8F8F8F8F8F8F8F8300000007878787878787878",
INIT_31 => X"000078787800000000009010E8F8F8F8F8702000000000787878787878787878",
INIT_32 => X"8808000000000000000000000010F8F8F8F8F8F8F8F8E8987878787878787800",
INIT_33 => X"000000007800000000008090787878787878787878000070F8F8F8F8F8F8F8E8",
INIT_34 => X"000000000000000020F8F8C80078787878787878787878780000F8F8F8F84800",
INIT_35 => X"78000000000000D870F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8D888000000007800",
INIT_36 => X"F8F8F8F8F8C800007878787878787878787800000000000088E8F8F8F8700078",
INIT_37 => X"F8F8F8D8008000787878787878787878787878787878000000F8F8F8F8F8F8F8",
INIT_38 => X"F8F8F8F8F8F8F84000787878787800C8000078000000008800000000B8F8F8F8",
INIT_39 => X"7878787878008870F8F8F8F8F8F8E8180000000000000000000000000000A8A8",
INIT_3A => X"78787878787878000050F8F8F8F8F8D8505000000000105050505010A8787878",
INIT_3B => X"F8F8F8F8F8F8F8400000000000787878000000080000000088A8A80800787878",
INIT_3C => X"78787800000000000088F8F8F8700000787808000000000098F8F8F8F8F8F8F8",
INIT_3D => X"787878787878000000F8F8F8F8F8F8F8F8F8F8F8F87000007878787878787878",
INIT_3E => X"B80000000010707070707070F8F8F8F8F8F8F8F8008808000000007878787878",
INIT_3F => X"000000000000000000000000000000882040F8F8F8F8F84000787878780060F8",
INIT_40 => X"F8F870D8880888C8F8F8F870007878787878787878000070F8F8F8F8F8F86000",
INIT_41 => X"78787800080000000000000078787878787878787878007070F8F8F8F8F8F8F8",
INIT_42 => X"78780008000000000088A8F8F8F8F8F8F8F8F8F830A098900000007878787878",
INIT_43 => X"F8F8F8F8F8700000007878787878787878787878000000000000F8F8F8F85808",
INIT_44 => X"F8F8F8F8F8F8F8F85020A82098000078787878787800000098F8F8F8F8F8F8F8",
INIT_45 => X"00000060F8F8E8007878787888C8F8F83000009070F8F8F8F8F8F8F8F8F8F8F8",
INIT_46 => X"7878787878000050F8F8F8F8F8F8600000000808080800000000000000000000",
INIT_47 => X"787878787898F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8A8A00000F8F8F898007878",
INIT_48 => X"0000000000000000008078787878787878787800000000000008007878787878",
INIT_49 => X"7878787878000000000030F8F8F8500078787800000000000000000000000000",
INIT_4A => X"787878787878000060F8F8F8F8F8F8F8F8F8F8F8F8F830000078787878787878",
INIT_4B => X"000000B8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8C80000",
INIT_4C => X"000000000000000000000000000000000000001050F8E80078787800D8F8F8E8",
INIT_4D => X"F8F8F8F8F8F870A800B8F8F8600078787878787878000000F8F8F8F8F8F86000",
INIT_4E => X"787878780000000000007878787878787878787898E8F8F8F8F8F8F8F8F8F8F8",
INIT_4F => X"7878787878000000000000000000000000000000000000007878787878787878",
INIT_50 => X"F8F8F8F8F8F8F89800787878787878787878787878000800000088F8F8F85000",
INIT_51 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F84080007878787878000060F8F8F8F8F8F8F8",
INIT_52 => X"000000000088887878787800F8F8F820000010F8F8F8F8F8F8F8F8F8F8F8F8F8",
INIT_53 => X"7878787878000000F8F8F8F8F8F8600000007878787878787878000008000000",
INIT_54 => X"7878787820F8F8F83088F8F8F8F8F8F8F8F8F8F8F8F8F8F870A8F8F8F8300078",
INIT_55 => X"0000000000007878787878787878787878787878780000007878787878787878",
INIT_56 => X"7878787878780008000088F8F8F8D88878787878787800000000000000000000",
INIT_57 => X"7878787878780010E8F8F8F8F8F8F80030F8F8F8F8F8F8980000787878787878",
INIT_58 => X"0000F8F8F8F8F8F8F870D8D8D8D8D8D8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F898",
INIT_59 => X"00000078787878787878780000000000000000000000787878789870F8F81000",
INIT_5A => X"00B860F8F8F8F8F8F8E850F8F8F88800787878787800000098F8F8F8F8F8E888",
INIT_5B => X"7878787878787878787878787878787878787800F8F8F8C8009860F8F8F8F888",
INIT_5C => X"7878787878787878000000000000000000000000007878787878787878787878",
INIT_5D => X"30F8F8F8F8F8F82008007878787878787878787878780000000088F8F8F85000",
INIT_5E => X"20F8F8F8F8F8F8F8F8F8F8F8F8F8F8A07878787878000830F8F8F8F8F8F8F800",
INIT_5F => X"00000000000078787800B8F8F8F810000000F8F8F8F8F8F8F840000000000000",
INIT_60 => X"787878787800000088D8F8F8F8F8F8E888880000787878787878787878780000",
INIT_61 => X"78780050F8F8F800000098F8F8F8F850000000A8D8F8F8F8F8F8F8F8F8F85000",
INIT_62 => X"0078787878787878787878787878787878787878787878787878787878787878",
INIT_63 => X"7878787878787800080088F8F8F8500078787878787878787878000000000000",
INIT_64 => X"787878787800A8F8F8F8F8F8F8F8F80030F8F8F8F8F8F8F80000787878787878",
INIT_65 => X"0000F8F8F8F8F8F8F84000000000000000F8F8F8F8F8F8F8F8F8F8F8F8F8F898",
INIT_66 => X"7000000000787878787878787878787800000008007878787810F8F8F8400000",
INIT_67 => X"D80000000070F8F8F8F8F8F8F8F8F80000787878780000000040F8F8F8F8F8F8",
INIT_68 => X"7878787878787878787878787878787878780070F8F81000000070F8F8F8F8F8",
INIT_69 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_6A => X"0060F8F8F8F8F8F800080078787878787878787878787878000000A8F8F8B800",
INIT_6B => X"0010E8F8F8F8F8F8F8F800000090E01000787878780088F8F8F8F8F8F8F8F800",
INIT_6C => X"78000000007878787898F8F8E8000000000010F8F8F8F8F8F840000000000000",
INIT_6D => X"0078787878A81000000050F8F8F8F8F8F8F8C808000000787878787878787878",
INIT_6E => X"780000F8F8F88800000060F8F8F8F8F8600000000088D870F8F8F8F8F8F8F860",
INIT_6F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_70 => X"7878787878787878000000A8F870007878787878787878787878787878787878",
INIT_71 => X"00787878780888F8F8F8F8F8F8F840000060F8F8F8F8F8F850B8007878787878",
INIT_72 => X"000098F8F8F8F8F8F84000080000000000009870F8F8F8F8F8F8000000000800",
INIT_73 => X"F8F8F8D800000800000000007800000000A85000787878780060F8F8E8000000",
INIT_74 => X"6000000000000098F8F8F8F8F8F8F8702078787878787800000088F8F8F8F8F8",
INIT_75 => X"78787878787878787878787878787878780000F8F8F81800000098F8F8F8F8F8",
INIT_76 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_77 => X"0060F8F8F8F8F8F8F8500000787878787878787878787878000088F8F8700078",
INIT_78 => X"00000088F8F8F8F8F8F86000000878787878787878000088E8F8F8F8F8F82000",
INIT_79 => X"70F898787878787800F8F8F8E8007808000020F8F8F8F8F8F8C8000000080000",
INIT_7A => X"307878787878787808000020F8F8F8F8F8F8F8F870B80000000000000090B870",
INIT_7B => X"78000070F8F88808000098F8F8F8F8F8F8A800000000000088F8F8F8F8F8F8F8",
INIT_7C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_7D => X"7878787878787878000088F8F800787878787878787878787878787878787878",
INIT_7E => X"78787878780800000060F8F8F8F89800000060F8F8F8F8F8F8D8100000787878",
INIT_7F => X"000020F8F8F8F8F8F8F810000000000000000000F8F8F8F8F8F8F85000080078",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[8]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title1_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"8001FFFF40701FE00FF8001E1FE000380000000000001E3FC17F8007FFFFA078",
INITP_01 => X"00001F0FC79F80003FFC00701FE007F8000C1FE000380000000000001E1FCE3F",
INITP_02 => X"01E00000000000000E87C7E780000FD800701FC001FC000007F8007800000000",
INITP_03 => X"01F8000E03FE01E00000000000000F87D7E78000000000701FE001FC000007FC",
INITP_04 => X"0000007007E001FE002000FFEFC00000000000000F87FFE780000000007007E0",
INITP_05 => X"07E3FF83C0000000007007F8007E0040003FFF800000000000000FC3FF87C000",
INITP_06 => X"00000000000003FFFF8380000000007003F0003F0000001FFC00000000000000",
INITP_07 => X"80000000000000000000000000FFFF0380000000003007F0003F80000007E000",
INITP_08 => X"000000FC001F800000000000000000000000007FFF0100000000000007F4003F",
INITP_09 => X"7C0300000000000000FE001FC00000000000000000000000001FFC0180000000",
INITP_0A => X"0000000000003E8000000000000000FC001F8000000000000000000000000008",
INITP_0B => X"0000000000000000000000003F0000000000000000FE01078000000000000000",
INITP_0C => X"003F8FC7E0000000000000000000000000001F80000000000000007F83C7C000",
INITP_0D => X"000000000000001FFFC7E0000000000000000000000000001FE0000000000000",
INITP_0E => X"000000000000000000000000000FFF8380000000000000000000000000000F80",
INITP_0F => X"000000000000000000000000000000000000000FFF8000000000000000000000",
INIT_00 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8E810787878787800F8F8F850087800",
INIT_01 => X"F830000000A8A810001070F8F8F8F8F83078787878787878000000000050F8F8",
INIT_02 => X"78787878787878787878787878787878780800F8F8F8F80800009870F8F8F8F8",
INIT_03 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_04 => X"000088F8F8F8F8F8F8F8D8000000787878787878787878780000D8F8F8007878",
INIT_05 => X"00000000B8F8F8F8F8F8F8F89800007878787878780000000000C8F8F8F89800",
INIT_06 => X"A89878787878787800F8F8F80800780800008850F8F8F8F8F8F8100000000800",
INIT_07 => X"3078787878787878780000000000A8D8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8",
INIT_08 => X"780008F8F8F8F80000000050F8F8F8F8F8308800C0F8F860000098F8F8F8F8F8",
INIT_09 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0A => X"78787878787878780000F8F8F800787878787878787878787878787878787878",
INIT_0B => X"787878787878000000000060F850000000000830F8F8F8F8F8F8F8E800007878",
INIT_0C => X"080000B8F8F8F8F8F8F81008000000000000000000B8F8F8F8F8F8F898000000",
INIT_0D => X"8820F8F8F8F8F8F8F8F8F8F8F8F84088787878787878787800F8F8F808787808",
INIT_0E => X"F8F88800C8F8F8F870008870F8F8F8F830787878787878787878780800000088",
INIT_0F => X"78787878787878787878787878787878780008F8F8F8F8500000000070F8F8F8",
INIT_10 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_11 => X"00000000C8F8F8F8F8F8F8701800000000787878787878000098F8F898007878",
INIT_12 => X"000000000000E8F8F8F8F8F8F898000078787878788000000000000008080000",
INIT_13 => X"787878787878787800F8F8F808787808080000B8F8F8F8F8F8F8A80000007800",
INIT_14 => X"F888787878787878787878787808000000000000D8D8D8D8D8D860D8D8000078",
INIT_15 => X"78000000F8F8F8E81000000000F8F8F8F8F88800C8F8F8F8F8F8B88860F8F8F8",
INIT_16 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_17 => X"00007878787800185070F8608878787878787878787878787878787878787878",
INIT_18 => X"787878787880008880000008008080800000000090F8F8F8F8F8F8F870100000",
INIT_19 => X"080000B8F8F8F8F8F8F8F8000000780008000000000020F8F8F8F8F8F8708800",
INIT_1A => X"00000000000000000000000000807878787878787878787800F8F8F808787808",
INIT_1B => X"F8F88810E8F8F8F8F8F8B80020F8F8F8F8887878787878787878787878787800",
INIT_1C => X"7878787878787878787878787878787878000088F8F8F8F83000000000F8F8F8",
INIT_1D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_1E => X"000000000020F8F8F8F8F8F8F87070C80800000000000078F8F8700000787878",
INIT_1F => X"00080000000088F8F8F8F8F8F8E8000078787878787800008080000000008080",
INIT_20 => X"787878787878787800F8F8F80878780000000000E8F8F8F8F8F8F80000007800",
INIT_21 => X"F888787878787878787878787878787878800000000000080078787878787878",
INIT_22 => X"78000000F8F8F8F8F888000000F8F8F8F8F87070F8F8F8F8F8F8B80028F8F8F8",
INIT_23 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_24 => X"F8F8D820F8F8F8F870D800007878787878787878787878787878787878787878",
INIT_25 => X"0000787878787878780000808080000000080000000000D0F8F8F8F8F8F8F8F8",
INIT_26 => X"0000000000F8F8F8F8F8F8E8000078780000000000000010F8F8F8F8F8F85088",
INIT_27 => X"78787878787878787878787878787878787878787878787800F8F8F808787878",
INIT_28 => X"F8F8F8F8F8F8F8F8F860000000B8F8F8F8A87878787878787878787878787878",
INIT_29 => X"78787878787878787878787878787878780000009870F8F8F8F820880020F8F8",
INIT_2A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_2B => X"7878000000000008B0C8F8F8F8F8F8F8F8F8F8F8F8F8F8F89800007878787878",
INIT_2C => X"7800000000000000C8F8F8F8F8F8F82000089878787878787800800000007878",
INIT_2D => X"787878787878787800F8F8F8007878780000000000F8F8F8F8F8F8F830007878",
INIT_2E => X"F810787878787878787878787878787878787878787878787878787878787878",
INIT_2F => X"787800000050F8F8F8F8F8600020F8F8F8F8F8F8F8F8F8F8F8200000000070F8",
INIT_30 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_31 => X"F8F8F8F8F8508888007878787878787878787878787878787878787878787878",
INIT_32 => X"080000787878787878787878787878787878000000000000000060F8F8F8F8F8",
INIT_33 => X"0000000000A8F8F8F8F8F8F840007878780000000000000000E8F8F8F8F8F898",
INIT_34 => X"78787878787878787878787878787878787878787878787800F8F8F888787878",
INIT_35 => X"F8F8F8F8F8F8F8F8F8080000008870F8F8887878787878787878787878787878",
INIT_36 => X"78787878787878787878787878787878787800080000F8F8F8F8F8F87070F8F8",
INIT_37 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_38 => X"78787878000800000000000020D8D8D8D8D8B800000000007878787878787878",
INIT_39 => X"78780000000000000000F8F8F8F8F8F898008078787878787878787878787878",
INIT_3A => X"7878787878787878780030F800007878000000000010F8F8F8F8F8F840000000",
INIT_3B => X"F888787878787878787878787878787878787878787878787878787878787878",
INIT_3C => X"7878000000000060F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F890000000000050F8",
INIT_3D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_3E => X"0000000000007878787878787878787878787878787878787878787878787878",
INIT_3F => X"7000000078787878787878787878787878787878787800000800000000000000",
INIT_40 => X"000000000010F8F8F8F8F8F8E810000078787800000000000000F8F8F8F8F8F8",
INIT_41 => X"7878787878787878787878787878787878787878787878787800002800007878",
INIT_42 => X"F8F8F8F8F8F8F85088007800000000F8C8887878787878787878787878787878",
INIT_43 => X"787878787878787878787878787878787878780000000088A8F8F8F8F8F8F8F8",
INIT_44 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_45 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_46 => X"0078787800000000000030F8F8F8F8F870880080787878787878787878787878",
INIT_47 => X"7878787878787878780000000000787878000800000088E8F8F8F8F8F8700000",
INIT_48 => X"3078787878787878787878787878787878787878787878787878787878787878",
INIT_49 => X"787878780000000000888850F8F8F8F8F8F8F8F8F8F8E88800787800000000F8",
INIT_4A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_4B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_4C => X"7010000078787878787878787878787878787878787878787878787878787878",
INIT_4D => X"78780000000000E8F8F8F8F8F8F898000078787800000000000008B8F8F8F8F8",
INIT_4E => X"7878787878787878787878787878787878787878787878787878000078787878",
INIT_4F => X"6070F8F8F8F8E88800007800000050D8A8787878787878787878787878787878",
INIT_50 => X"78787878787878787878787878787878787878780000000000000008D8606060",
INIT_51 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_52 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_53 => X"0000787800000000000000B8F8F8F8F8F8C80078787878787878787878787878",
INIT_54 => X"7878787878787878787800007878787878780000000000B0F8F8F8F8F8F8E800",
INIT_55 => X"0078787878787878787878787878787878787878787878787878787878787878",
INIT_56 => X"7878787878780000000000000000000008C8F8F8F8F8F8601800787800000800",
INIT_57 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_58 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_59 => X"F8C8007878787878787878787878787878787878787878787878787878787878",
INIT_5A => X"787800000000000098F8F8F8F8F8F8400000000000086070C8000090E8F8F8F8",
INIT_5B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_5C => X"008870F8F8F8F8F8880800780000087878787878787878787878787878787878",
INIT_5D => X"7878787878787878787878787878787878787878787878000000000000000000",
INIT_5E => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_5F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_60 => X"C000000898C8F8F8F8B8000000F8F8F8F8D80000787878787878787878787878",
INIT_61 => X"7878787878787878787878787878787878787800080000008870F8F8F8F8F8F8",
INIT_62 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_63 => X"78787878787878787878000008000000000000F8F8F8F8F8F820900000080078",
INIT_64 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_65 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_66 => X"F8F8D80078787878787878787878787878787878787878787878787878787878",
INIT_67 => X"78787878000800000040F8F8F8F8F8F8F8C800C8D8F8F8F8F8F8D0000030F8F8",
INIT_68 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_69 => X"000000B8F8F8F8F8F8F830000000787878787878787878787878787878787878",
INIT_6A => X"7878787878787878787878787878787878787878787878787878780000000000",
INIT_6B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_6C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_6D => X"F8F870F8F8F8F8F8F8F8E8000010F8F8F8F8F800787878787878787878787878",
INIT_6E => X"7878787878787878787878787878787878787878780000000000E8F8F8F8F8F8",
INIT_6F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_70 => X"787878787878787878787878787878000800000858F8F8F8F888007878787878",
INIT_71 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_72 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_73 => X"5000000078787878787878787878787878787878787878787878787878787878",
INIT_74 => X"787878787810000000000060F8F8F8F8F8F8F8F8F8F8F8F8F8E800000088D8D8",
INIT_75 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_76 => X"0000000000006060880000787878787878787878787878787878787878787878",
INIT_77 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_78 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_79 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_7A => X"F8F8F8F8F8F8F8F8D88800000000000000007878787878787878787878787878",
INIT_7B => X"7878787878787878787878787878787878787878787800000000008850F8F8F8",
INIT_7C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_7D => X"7878787878787878787878787878787878000000000000007878787878787878",
INIT_7E => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_7F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[8]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[9]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
p_7_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title1_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"F800000000000000000000000000000000000000000000000003FE0000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0878787878787878787878787878787878787878787878787878787878787878",
INIT_01 => X"7878787878787878080000000088F8F8F8F8F8F8F8F8F8880000000000000000",
INIT_02 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_03 => X"7878000000007878787878787878787878787878787878787878787878787878",
INIT_04 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_05 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_06 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_07 => X"D8D8D8D850000878787878000000007878787878787878787878787878787878",
INIT_08 => X"78787878787878787878787878787878787878787878787800000000000000A8",
INIT_09 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0A => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0B => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0C => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0D => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_0E => X"7878787878787878780000000000000000000000000078787878787878787878",
INIT_0F => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_10 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_11 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_12 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_13 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_14 => X"0078787878787878787878787878787878787878787878787878787878787878",
INIT_15 => X"7878787878787878787878787878787878787878787878787878787878000000",
INIT_16 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_17 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_18 => X"7878787878787878787878787878787878787878787878787878787878787878",
INIT_19 => X"0000000000000000000000000000000078787878787878787878787878787878",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1) => '0',
DIPADIP(0) => dina(8),
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => p_7_out(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => p_7_out(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title1_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_01 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_02 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_03 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_04 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_05 => X"5555555555555555500005555555555555555555555555555555555555555555",
INIT_06 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_07 => X"5555555555555555555555555555555555555555502AA1555555555555555555",
INIT_08 => X"402FFC1555555555555555555555555555555555555555555555555555555555",
INIT_09 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0A => X"555555555555555555555400054BFF0555555555555555555555555555555555",
INIT_0B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0C => X"5555555555555555555555555555555555555555555552AAAFFBFF8155555555",
INIT_0D => X"555543FFFFFFFFF0555555555555555555555555540005555555555555555555",
INIT_0E => X"51FFD00055555004555555555555555555555555555555555555555555555555",
INIT_0F => X"55555555555555555555555555554FFFFFFFFFFD055555555555555555555555",
INIT_10 => X"E1555555555555555555555503FFFC00055542AC055555555555555555555555",
INIT_11 => X"C055555555555555555555555555555555555555555555555555057FF56FFFFF",
INIT_12 => X"5555555555540000000FFFFFFC55555555555555555555550BFDFD00055543FF",
INIT_13 => X"555555554FF0FFFF85554FFFFF41555555555555555555555555555555555555",
INIT_14 => X"5555555555555555555555555555555555540000000003FFFF41555555555555",
INIT_15 => X"000002FFFFE15555555555555555555507F1FFFF805505BFFFE8155555555555",
INIT_16 => X"C055003FFFFF8555555555555555555555555555555555555555555555540000",
INIT_17 => X"555555555555555555540000000000FFE0F15555555555555555555503FFC7FF",
INIT_18 => X"555555555555555503FF07FFF054000FFFFFF055555555555555555555555555",
INIT_19 => X"551055555554005000155555555555555555555555554000400000BFF4215555",
INIT_1A => X"555555555000001FFC0155555555555555555555005407FFF0540002FFFFFE55",
INIT_1B => X"000007FFF01500003FFFFE1555001555555002FEAA0155555555555555555555",
INIT_1C => X"FFE055555555555555555555555555555554000FFF0555555555555555555555",
INIT_1D => X"FF0555555555555555555555400007FFF01540003FFFFF155470155555403FFF",
INIT_1E => X"07FFC61551FC05555403FFFFFFF915555555555555555555555555000000000B",
INIT_1F => X"555555555555540000000003FF8555555555555555555555400007FFFC155000",
INIT_20 => X"55555555415407FFFC15540000FFF01547FD0155400FFFFFFFFF415555555555",
INIT_21 => X"40BFFFFFFFFFD05555555555555555555555003FFFFFC000FF85555555555555",
INIT_22 => X"FFFFD550FFD15555555555555555555555500BFFFC15550000FFF0154BFF0155",
INIT_23 => X"FE155540007FF8154FFFC00003FFFFFFFFFFF4555555555555555555555405BF",
INIT_24 => X"555555555555555555503FFFFFFFFFFEBFF15555555550015555555555500FFF",
INIT_25 => X"55550FF01555555555500FFFFE055550001FFE1507FFE800ABFFFFFF55FFFD15",
INIT_26 => X"03FFFFFFFFFFFFD0001FFE15555555555555555555503FFFFFFFFFFFFFF15555",
INIT_27 => X"5550FFFFFFFFFFFFFFF055555550BFFD0555555555500FFFFE015554000BFF15",
INIT_28 => X"55500FFFFF0055550001FF0500FFFFFFFFFFFF80000FFF555555555555555555",
INIT_29 => X"0003FF5555555001555555555542FFFFFFFFFFFFFFFC555555400FFF80555555",
INIT_2A => X"FFFC5555550003FFF015555555500FFFFFC0555540007FC100BFFFFFFFFFFD00",
INIT_2B => X"40007FC1003FFFFFFFFFFC000000FF55555553E1555555555543FFFFC0003FFF",
INIT_2C => X"004000555543FFFF0000000FFFFC5554054000FFF401555555503FFFFF405555",
INIT_2D => X"FE01555555503FFFFFE0555550003FF14002FFFFFFFF800400007E1555550FF8",
INIT_2E => X"FFFE00150000141555542FFEA002A8555543FFFC00000005FFFE15520400007F",
INIT_2F => X"000000002FFE154F400FFFFFFF00015555503FFFFFF0555554000FF050003FFF",
INIT_30 => X"FFF0155555000FF8500007FFFF400155540000555553FFFFFE02FF155543FFFC",
INIT_31 => X"554FFFFFFFD03F055542FFFC0000000003FC552F40FFFFFFFFFF950155403FFF",
INIT_32 => X"01FFFFFFFFFFFFE05550FFFFFFF41555554007F8540000000000055554000155",
INIT_33 => X"554000000000555555000555553FFFFFFFFD1FC55540FFFC0000000000BC54BF",
INIT_34 => X"5540FFFC05555000000154FC03FFFFFFFFFFFFF81550FFFFFFFC1555554003F8",
INIT_35 => X"5550FFFC7FFC0555555003F8555000000005555555405555557F4FFFFFFFDFD1",
INIT_36 => X"5555555554FE0FFC1FFFFBF055403FFC01555400000553F00FFFFAAAFFFFFFFC",
INIT_37 => X"000547F00FFFE0007FFFFFFC5541FFFC7FFD0555555003F85555000000155555",
INIT_38 => X"555403F855555000155555555555555552FC03FE01BFFFF855402FFF00555550",
INIT_39 => X"803FFFFC15402FFFC015555500154FE00FFFE0003FFFFFFC5543FFFC7FFF0555",
INIT_3A => X"0FFFF0081543FFFC3FFF0155555501F455555555555555555555555553F00FFF",
INIT_3B => X"555555555555555543F00FFFC00BFFFF15500BFFF801555540154FC003FFE000",
INIT_3C => X"FE00004018553FC003FFE00003FFF0001543FFF83FFF9155555501F155555555",
INIT_3D => X"3FFFE055555503F155555555555555555555555543F003FFC000FFFF555403FF",
INIT_3E => X"43F003FFD0003FFF555501FFFFD00007F1553FC407FFE00000FFFC055540FFF4",
INIT_3F => X"07FFF00000FFFE0155403FF00FFFE015555503C5555555555555555555555555",
INIT_40 => X"55555555555555555555555543FC03FFD0140FFF5555002FFFFFFFFFF1553F84",
INIT_41 => X"55554006FFFFFFFF45553F0402FFF000007FFF0155400BF003FFF80555550BC5",
INIT_42 => X"555003E001FFFF0555550FC555555555555555555555555543FC02FFD07F03FF",
INIT_43 => X"5555555543FE00FFF0BFC3FF555554001FFFFFF855553F1401FFF000001FFF00",
INIT_44 => X"55553F1401FFF404000FFFC05540000000BFFF0015540F055555555555555555",
INIT_45 => X"0550BF1555555555555555555555555540FF003FF0BFF4FFC555554000AAAE81",
INIT_46 => X"F0FFF47FC55555540000000555553F1401FFFC040007FFF055400000003FFFC0",
INIT_47 => X"0003FFF055500000001FFFFE0003FC1555555555555555555555555540FF403F",
INIT_48 => X"555555555555555540FFC03FFFFFF47FC55555554000155555553F1400FFFC04",
INIT_49 => X"5555555555553F15003FFF050000FFF8055540000002FFFFF9FFE05555555555",
INIT_4A => X"50006FFFFFFF0155555555555555555555555555403FF41FFFFFF01FC5555555",
INIT_4B => X"502FFF1FFFFFD00FC55555555555555555553F15003FFF454000BFFD01554005",
INIT_4C => X"001FFF8540003FFC0155555550000FFFFFE01555555555555555555555555555",
INIT_4D => X"555555555555555555555555500FFFFFFFFFC00FC55555555555555555553F15",
INIT_4E => X"C55555555555555555554705000FFF8050000FFF015555555500006AA4005555",
INIT_4F => X"C055555555500000000555555555555555555555555555555003FFFFFFFF000B",
INIT_50 => X"5555555554007FFFFFFE0403855555555555555555554105000FFFC054000FFF",
INIT_51 => X"555540054003FFF0150007FFC055555555555555555555555555555555555555",
INIT_52 => X"55555555555555555555555555555555550002FFFFFC14035555555555555555",
INIT_53 => X"FFFC040A5555555555555555555550555003FFF0150001FFC055555555555555",
INIT_54 => X"050001FFE15555555555555555555555555555555555555555555555550000BF",
INIT_55 => X"5555555555555555555000002FFF05001555555555555555555550555001FFFC",
INIT_56 => X"555555555555555550003FFE000F80FFE1555555555555555555555555555555",
INIT_57 => X"5555555555555555555555555555555555555555555400000FFF010155555555",
INIT_58 => X"5555500003FFD00155555555555555555555555554003FFF402FD03FE0555555",
INIT_59 => X"55002FFFE2BFF81FF85555555555555555555555555555555555555555555555",
INIT_5A => X"5555555555555555555555555555540001FFF405555555555555555555555555",
INIT_5B => X"55555555555555555555555555400FFFFFFFFC0FFC5555555555555555555555",
INIT_5C => X"8055555555555555555555555555555555555555555555555555555400BFC155",
INIT_5D => X"5555555555555555000F0155555555555555555555555555554003FFFFFFF00A",
INIT_5E => X"55555555555000BFFFFF80000555555555555555555555555555555555555555",
INIT_5F => X"5555555555555555555555555555555555555555400055555555555555555555",
INIT_60 => X"500555555555555555555555555555555555000FFFFC00001555555555555555",
INIT_61 => X"AA81540155555555555555555555555555555555555555555555555555555555",
INIT_62 => X"5555555555555555555555555555555555555555555555555555555555550001",
INIT_63 => X"5555555555555555555540000005555555555555555555555555555555555555",
INIT_64 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_65 => X"5555555555555555555555555555555555555555555555401555555555555555",
INIT_66 => X"0000000000000000000000000000000000000000555555555555555555555555",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end title1_blk_mem_gen_prim_width;
architecture STRUCTURE of title1_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.title1_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[8]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \title1_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\title1_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[8]\(7 downto 0) => \douta[8]\(7 downto 0),
\douta[9]\(0) => \douta[9]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_width__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \title1_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\title1_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[8]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \title1_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\title1_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[8]\(7 downto 0) => \douta[8]\(7 downto 0),
\douta[9]\(0) => \douta[9]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_width__parameterized3\ is
port (
p_7_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \title1_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\title1_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
ena_array(0) => ena_array(0),
p_7_out(8 downto 0) => p_7_out(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title1_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title1_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \title1_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \title1_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\title1_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end title1_blk_mem_gen_generic_cstr;
architecture STRUCTURE of title1_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 6 to 6 );
signal p_7_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.title1_bindec
port map (
addra(2 downto 0) => addra(13 downto 11),
ena_array(0) => ena_array(6)
);
\has_mux_a.A\: entity work.title1_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[3].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[3].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[3].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[3].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[3].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[3].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[3].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[1].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[3].ram.r_n_8\,
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
DOPADOP(0) => \ramloop[2].ram.r_n_8\,
addra(2 downto 0) => addra(13 downto 11),
clka => clka,
douta(8 downto 0) => douta(9 downto 1),
p_7_out(8 downto 0) => p_7_out(8 downto 0)
);
\ramloop[0].ram.r\: entity work.title1_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\title1_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(9 downto 1),
\douta[8]\(7) => \ramloop[1].ram.r_n_0\,
\douta[8]\(6) => \ramloop[1].ram.r_n_1\,
\douta[8]\(5) => \ramloop[1].ram.r_n_2\,
\douta[8]\(4) => \ramloop[1].ram.r_n_3\,
\douta[8]\(3) => \ramloop[1].ram.r_n_4\,
\douta[8]\(2) => \ramloop[1].ram.r_n_5\,
\douta[8]\(1) => \ramloop[1].ram.r_n_6\,
\douta[8]\(0) => \ramloop[1].ram.r_n_7\,
\douta[9]\(0) => \ramloop[1].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\title1_blk_mem_gen_prim_width__parameterized1\
port map (
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
DOPADOP(0) => \ramloop[2].ram.r_n_8\,
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(9 downto 1),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\title1_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(9 downto 1),
\douta[8]\(7) => \ramloop[3].ram.r_n_0\,
\douta[8]\(6) => \ramloop[3].ram.r_n_1\,
\douta[8]\(5) => \ramloop[3].ram.r_n_2\,
\douta[8]\(4) => \ramloop[3].ram.r_n_3\,
\douta[8]\(3) => \ramloop[3].ram.r_n_4\,
\douta[8]\(2) => \ramloop[3].ram.r_n_5\,
\douta[8]\(1) => \ramloop[3].ram.r_n_6\,
\douta[8]\(0) => \ramloop[3].ram.r_n_7\,
\douta[9]\(0) => \ramloop[3].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\title1_blk_mem_gen_prim_width__parameterized3\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(9 downto 1),
ena_array(0) => ena_array(6),
p_7_out(8 downto 0) => p_7_out(8 downto 0),
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\title1_blk_mem_gen_prim_width__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(11 downto 10),
douta(1 downto 0) => douta(11 downto 10),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_top : entity is "blk_mem_gen_top";
end title1_blk_mem_gen_top;
architecture STRUCTURE of title1_blk_mem_gen_top is
begin
\valid.cstr\: entity work.title1_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end title1_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of title1_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.title1_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of title1_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of title1_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of title1_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of title1_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of title1_blk_mem_gen_v8_3_5 : entity is "2";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of title1_blk_mem_gen_v8_3_5 : entity is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of title1_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of title1_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of title1_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of title1_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.153268 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of title1_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of title1_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of title1_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of title1_blk_mem_gen_v8_3_5 : entity is "title1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of title1_blk_mem_gen_v8_3_5 : entity is "title1.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of title1_blk_mem_gen_v8_3_5 : entity is 13104;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of title1_blk_mem_gen_v8_3_5 : entity is 13104;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of title1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of title1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of title1_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of title1_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of title1_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of title1_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of title1_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of title1_blk_mem_gen_v8_3_5 : entity is 13104;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of title1_blk_mem_gen_v8_3_5 : entity is 13104;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of title1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of title1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of title1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of title1_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of title1_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title1_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of title1_blk_mem_gen_v8_3_5 : entity is "yes";
end title1_blk_mem_gen_v8_3_5;
architecture STRUCTURE of title1_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.title1_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title1 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of title1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of title1 : entity is "title1,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of title1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of title1 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end title1;
architecture STRUCTURE of title1 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "2";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.153268 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "title1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "title1.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 13104;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 13104;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 13104;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 13104;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.title1_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | b6489883b28c5f1f9b8c845e76382e5a | 0.714135 | 3.124763 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/menu_bg/synth/menu_bg.vhd | 1 | 14,303 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY menu_bg IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END menu_bg;
ARCHITECTURE menu_bg_arch OF menu_bg IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF menu_bg_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF menu_bg_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF menu_bg_arch : ARCHITECTURE IS "menu_bg,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF menu_bg_arch: ARCHITECTURE IS "menu_bg,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=menu_bg.mif" &
",C_INIT_FILE=menu_bg.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=11025,C_READ_DEPTH_A=11025,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH" &
"_B=11025,C_READ_DEPTH_B=11025,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_" &
"WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.22775 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "menu_bg.mif",
C_INIT_FILE => "menu_bg.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 11025,
C_READ_DEPTH_A => 11025,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 11025,
C_READ_DEPTH_B => 11025,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.22775 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END menu_bg_arch;
| gpl-3.0 | 25d22730ddd503ed237a3a82c9175c93 | 0.624624 | 3.002939 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev9.vhd | 1 | 38,997 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev9 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev9 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : integer;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= 0;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif(rcount < 16) then
wout <= std_logic_vector(mvect(rcount));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 5cb57641b1fa1a2fc1413e88c93169aa | 0.641998 | 2.909138 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/stack.vhd | 14 | 1,802 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
| mit | 95290b963ecb3de78643cee92bfb8e4e | 0.623196 | 2.824451 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/ZPUino_Papilio_One_V1.vhd | 13 | 42,659 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit | 2a10540f676cc7e52f4795560d3eb444 | 0.604609 | 2.630998 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/BRAM6k36bit.vhd | 13 | 3,666 | ----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
| mit | ac14695e295fdb32b133ffbe8d3b46f8 | 0.591926 | 3.587084 | false | false | false | false |
huukit/logicsynth | ex1_tutorial/vhd/tb_lock.vhd | 1 | 5,152 | -------------------------------------------------------------------------------
-- Title : tb_lock
-- Project :
-------------------------------------------------------------------------------
-- File : tb_lock.vhd
-- Author : <alhonena@BUMMALO>
-- Company :
-- Last update: 2008/06/18
-- Platform :
-------------------------------------------------------------------------------
-- Description: Testbench for lock.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2008/06/18 1.0 alhonena Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lock_pkg.all;
entity tb_lock is
-- Entity with no ports; clock and reset is generated in the testbench.
-- Remember that this kind of clock generation works only in the simulation.
end tb_lock;
architecture testbench of tb_lock is
signal clk, rst_n : std_logic := '0';
constant clock_period_c : time := 20 ns;
type intarray is array (0 to 3) of integer range 0 to 9;
constant correct_sequence_c : intarray := (4,1,6,9);
type state_type is (send1, send2, send3, send4, increment);
signal state_r : state_type;
signal current_value_r : intarray;
component lock
port (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
keys_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
lock_out : OUT STD_LOGIC);
end component;
signal simulated_keys_r : std_logic_vector(3 downto 0);
signal lock_status : std_logic;
begin -- testbench
clk <= not clk after clock_period_c;
rst_n <= '1' after clock_period_c*2;
-- instantiation of the DUV, device under verification.
lock_inst: lock
port map (
clk => clk,
rst_n => rst_n,
keys_in => simulated_keys_r,
lock_out => lock_status);
-- All possible sequences are tried in this FSM.
FSM: process (clk, rst_n)
begin -- process FSM
if rst_n = '0' then -- asynchronous reset (active low)
state_r <= send1;
current_value_r <= (others => 0);
elsif clk'event and clk = '1' then -- rising clock edge
case state_r is
when send1 => simulated_keys_r <=
std_logic_vector(to_unsigned(current_value_r(0),4));
state_r <= send2;
when send2 => simulated_keys_r <=
std_logic_vector(to_unsigned(current_value_r(1),4));
state_r <= send3;
when send3 => simulated_keys_r <=
std_logic_vector(to_unsigned(current_value_r(2),4));
state_r <= send4;
when send4 => simulated_keys_r <=
std_logic_vector(to_unsigned(current_value_r(3),4));
state_r <= increment;
when increment => if current_value_r(0) = 9 then
current_value_r(0) <= 0;
if current_value_r(1) = 9 then
current_value_r(1) <= 0;
if current_value_r(2) = 9 then
current_value_r(2) <= 0;
if current_value_r(3) = 9 then -- the last one
assert false report
"Simulation completed succesfully!"
severity failure;
else
current_value_r(3) <= current_value_r(3) + 1;
end if;
else
current_value_r(2) <= current_value_r(2) + 1;
end if;
else
current_value_r(1) <= current_value_r(1) + 1;
end if;
else
current_value_r(0) <= current_value_r(0) + 1;
end if;
state_r <= send1;
when others => null;
end case;
end if;
end process FSM;
-- Process that checks if the door opens with a wrong sequence or if
-- the door doesn't open with the correct sequence.
check: process (clk, rst_n)
begin -- process check
if rst_n = '0' then -- asynchronous reset (active low)
elsif clk'event and clk = '1' then -- rising clock edge
if lock_status = '1' then
assert current_value_r = correct_sequence_c
report "Lock opens with a wrong sequence!" severity failure;
end if;
-- The DUV should open the door after the fourth digit was
-- sent, that is, when the state_r is 'increment'.
if current_value_r = correct_sequence_c and state_r = increment then
assert lock_status = '1'
report "Lock does not open with the correct sequence!"
severity failure;
end if;
end if;
end process check;
end testbench;
| gpl-2.0 | 869d9a4e2553b0e1a5d44861bbe59d00 | 0.472244 | 4.296914 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to288_dcm.vhd | 13 | 6,306 | -- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit | 667f93750e3d5d76594ebae813eb8774 | 0.575008 | 4.243607 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/wbmux2.vhd | 1 | 2,536 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end entity wbmux2;
architecture behave of wbmux2 is
signal select_zero: std_logic;
begin
select_zero<='1' when m_wb_adr_i(select_line)='0' else '0';
s0_wb_dat_o <= m_wb_dat_i;
s0_wb_adr_o <= m_wb_adr_i;
s0_wb_stb_o <= m_wb_stb_i;
s0_wb_we_o <= m_wb_we_i;
s0_wb_cti_o <= m_wb_cti_i;
s0_wb_sel_o <= m_wb_sel_i;
s1_wb_dat_o <= m_wb_dat_i;
s1_wb_adr_o <= m_wb_adr_i;
s1_wb_stb_o <= m_wb_stb_i;
s1_wb_we_o <= m_wb_we_i;
s1_wb_cti_o <= m_wb_cti_i;
s1_wb_sel_o <= m_wb_sel_i;
process(m_wb_cyc_i,select_zero)
begin
if m_wb_cyc_i='0' then
s0_wb_cyc_o<='0';
s1_wb_cyc_o<='0';
else
s0_wb_cyc_o<=select_zero;
s1_wb_cyc_o<=not select_zero;
end if;
end process;
process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i)
begin
if select_zero='0' then
m_wb_dat_o<=s1_wb_dat_i;
m_wb_ack_o<=s1_wb_ack_i;
else
m_wb_dat_o<=s0_wb_dat_i;
m_wb_ack_o<=s0_wb_ack_i;
end if;
end process;
end behave;
| mit | b3e7dd01d7f56ed8ae809c386d6ed534 | 0.623028 | 2.216783 | false | false | false | false |
ordepmalo/matrizled | rtl/vhdl/interface/sim/interface_tb.vhd | 1 | 2,782 | -------------------------------------------------------------------------------
-- Title : Testbench for design "interface"
-- Project :
-------------------------------------------------------------------------------
-- File : interface_tb.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created : 2015-04-23
-- Last update : 2015-04-24
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-23 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity interface_tb is
end entity interface_tb;
-------------------------------------------------------------------------------
architecture interface_tb_rtl of interface_tb is
-- component generics
constant MAX_VALUE : natural := 32;
constant MAX_VALUE_BITS : natural := 5;
-- component ports
signal sysclk : std_logic := '0';
signal reset_n : std_logic := '0';
signal en_i : std_logic := '0';
signal ctrl_o : std_logic_vector(MAX_VALUE_BITS - 1 downto 0);
signal stb_o : std_logic;
signal clk : std_logic;
begin -- architecture interface_tb_rtl
-- component instantiation
DUT : entity work.interface
generic map (
MAX_VALUE => MAX_VALUE,
MAX_VALUE_BITS => MAX_VALUE_BITS)
port map (
sysclk => sysclk,
reset_n => reset_n,
en_i => en_i,
ctrl_o => ctrl_o,
stb_o => stb_o,
clk => clk);
-- clock generation
sysclk <= not sysclk after 5 NS;
-- reset generation
reset_proc : process
begin
reset_n <= '0';
wait for 50 US;
reset_n <= '1';
wait;
end process reset_proc;
-- Stimulus generation
stimulus_proc : process
begin
wait for 100 US;
loop
wait until sysclk = '1';
en_i <= '1';
wait for 10 NS;
en_i <= '0';
wait for 100 US;
end loop;
-- Add stimulus here
wait;
end process stimulus_proc;
end architecture interface_tb_rtl;
-------------------------------------------------------------------------------
configuration interface_tb_interface_tb_rtl_cfg of interface_tb is
for interface_tb_rtl
end for;
end interface_tb_interface_tb_rtl_cfg;
-------------------------------------------------------------------------------
| mit | 9e39f60da0022f9b754c03bf11614333 | 0.424515 | 4.613599 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.d-memory.core/a.b.d.a-DRAM_block.core/a.b.d.a.c-MMU_out_DRAM.vhd | 1 | 5,414 | ----------------------------------------------------------------------------------------------------
-- MMU out
-- It arranges the output of the DRAM according to the control signals for the current mem operation
-- and on the control signal generated from MMU in
-- Note it arrenges byte according to the Big Endian format
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity mmu_out_dram is
port (
-- INPUTS
data_ram : in std_logic_vector(31 downto 0); -- data coming from the dram
mem_op : in std_logic_vector(5 downto 0); -- control signals grouped in the following order (sb, sw, lbu, lw, lhu, lb)
nibble : in std_logic_vector(1 downto 0); -- which byte should be selected
unaligned : in std_logic; -- in case of unaligned access set the output to zero
-- OUTPUTS
data_read : out std_logic_vector(31 downto 0) -- data in the correct format
);
end mmu_out_dram;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of mmu_out_dram is
begin
-------------------------
-- Name: Comb Logic
-- Type: Combinational
-- Purpose: Implemnt the
-- comb logic of the
-- MMU out
------------------------
comb_logic:process(data_ram, mem_op, nibble, unaligned)
begin
if (unaligned = '1') then
data_read <= (others => '0');
else
case mem_op is
when "000100" => -- lw
data_read <= data_ram;
when "000010" => -- lhu
if (nibble = "00") then
data_read(31 downto 16) <= (others => '0');
data_read(15 downto 0) <= data_ram(31 downto 16);
else
-- nibble = "10"
data_read(31 downto 16) <= (others => '0');
data_read(15 downto 0) <= data_ram(15 downto 0);
end if;
when "000001" => -- lb
case nibble is
when "00" =>
if (data_ram(31) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(31 downto 24);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(31 downto 24);
data_read(31 downto 8) <= (others => '0');
end if;
when "01" =>
if (data_ram(23) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(23 downto 16);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(23 downto 16);
data_read(31 downto 8) <= (others => '0');
end if;
when "10" =>
if (data_ram(15) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(15 downto 8);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(15 downto 8);
data_read(31 downto 8) <= (others => '0');
end if;
when "11" =>
if (data_ram(7) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(7 downto 0);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(7 downto 0);
data_read(31 downto 8) <= (others => '0');
end if;
when others =>
data_read <= (others => '0');
end case;
when "001000" => -- lbu
case nibble is
when "00" =>
data_read(7 downto 0) <= data_ram(31 downto 24);
data_read(31 downto 8) <= (others => '0');
when "01" =>
data_read(7 downto 0) <= data_ram(23 downto 16);
data_read(31 downto 8) <= (others => '0');
when "10" =>
data_read(7 downto 0) <= data_ram(15 downto 8);
data_read(31 downto 8) <= (others => '0');
when "11" =>
data_read(7 downto 0) <= data_ram(7 downto 0);
data_read(31 downto 8) <= (others => '0');
when others =>
data_read <= (others => '0');
end case;
when others =>
data_read <= (others => '0');
end case;
end if;
end process;
end behavioral;
| mit | 65a441977755be560bcdbd84ca4f70b4 | 0.401182 | 4.489221 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_config.vhd | 1 | 2,569 | --
-- Configuration file for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpuino_config is
-- General ZPUino configuration
type zpu_core_type is (
small,
large
);
-- ZPUino large is buggy, don't use it.
constant zpuinocore: zpu_core_type := small;
-- Set iobusyinput to 'true' to allow registered input to IO core. This also allows for IO
-- to become busy without needing to register its inputs. However, an extra clock-cycle is
-- required to access IO if this is used.
constant zpuino_iobusyinput: boolean := true;
-- For SPI blocking operation, you need to define also iobusyinput
constant zpuino_spiblocking: boolean := true;
-- Number of GPIO to map (number of FPGA pins)
constant zpuino_gpio_count: integer := 50;
-- Peripheral Pin Select
constant zpuino_pps_enabled: boolean := true;
-- Internal SPI ADC
constant zpuino_adc_enabled: boolean := true;
-- Number of IO select bits. Maps to maximum number of IO devices
constant zpuino_number_io_select_bits: integer := 4;
end package zpuino_config;
| mit | 82f55c937d0df24d7cab179f71b7db08 | 0.726353 | 3.892424 | false | true | false | false |
huukit/logicsynth | excercises/tb/tb_audio_ctrl.vhd | 1 | 7,347 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 09
-- Project :
-------------------------------------------------------------------------------
-- File : tb_audio_ctrl.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 11.1.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Ninth excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 11.1.2016 1.0 huukit Created.
-- 15.1.2016 1.1 huukit Added bonus feature.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Test bench entity.
entity tb_audio_ctrl is
generic(
data_width_g : integer := 16;
step_w_r_g : integer := 2;
step_w_l_g : integer := 10;
ref_clk_freq_g : integer := 20000000;
sample_rate_g : integer := 48000
);
end tb_audio_ctrl;
architecture testbench of tb_audio_ctrl is
-- Component definitions.
component audio_ctrl is
generic(
ref_clk_freq_g : integer := 20000000;
sample_rate_g : integer := 48000;
data_width_g : integer
);
port(
clk : in std_logic;
rst_n : in std_logic;
left_data_in : in std_logic_vector(data_width_g - 1 downto 0);
right_data_in : in std_logic_vector(data_width_g - 1 downto 0);
aud_bclk_out : out std_logic;
aud_data_out : out std_logic;
aud_lrclk_out : out std_logic
);
end component;
component audio_codec_model is
generic(
data_width_g : integer
);
port(
rst_n : in std_logic;
aud_data_in : in std_logic;
aud_bclk_in : in std_logic;
aud_lrclk_in : in std_logic;
value_left_out : out std_logic_vector(data_width_g - 1 downto 0);
value_right_out : out std_logic_vector(data_width_g - 1 downto 0)
);
end component;
component wave_gen is
generic (
width_g : integer;
step_g : integer := 1
);
port(
clk : in std_logic;
rst_n : in std_logic;
sync_clear_in : in std_logic;
value_out : out std_logic_vector(width_g - 1 downto 0)
);
end component;
-- Clock rate of simulation ~50 is ok.
constant clockrate_ns_c : time := 50 ns;
signal clk : std_logic := '0'; -- Main clock.
signal rst_n : std_logic := '0'; -- Main reset.
signal sync_r : std_logic := '0'; -- Sync signal for generators.
signal l_data_wg_actrl : std_logic_vector(data_width_g - 1 downto 0); -- Generator output.
signal r_data_wg_actrl : std_logic_vector(data_width_g - 1 downto 0); -- Generator output.
signal aud_bclk_out_r : std_logic; -- Codec serial bitclock.
signal aud_data_out_r : std_logic; -- Codec serial data output.
signal aud_lrclk_out_r : std_logic; -- Codec serial L/R data output.
signal l_data_codec_tb : std_logic_vector(data_width_g - 1 downto 0); -- Model output.
signal r_data_codec_tb : std_logic_vector(data_width_g - 1 downto 0); -- Model output.
constant fs_c : integer := (((ref_clk_freq_g / sample_rate_g) / data_width_g) / 4);
constant bc_time : integer := fs_c * 2 * (data_width_g * 2) - 1;
signal l_data_expected_r : std_logic_vector(data_width_g - 1 downto 0); -- Expected output from model.
signal r_data_expected_r : std_logic_vector(data_width_g - 1 downto 0); -- Expected output from model.
signal bitcounter_r : integer; -- Bitcounter for codec output analysis.
signal checkdelay_r : integer; -- Delay counter to check the sync input effect.
constant cdelay : integer := 1; -- Delay time for previous in main clock cycles.
begin -- testbench
-- Instances
i_acontrol : audio_ctrl
generic map(
data_width_g => data_width_g
)
port map(
rst_n => rst_n,
clk => clk,
aud_data_out => aud_data_out_r,
aud_bclk_out => aud_bclk_out_r,
aud_lrclk_out => aud_lrclk_out_r,
left_data_in => l_data_wg_actrl,
right_data_in => r_data_wg_actrl
);
i_amodel : audio_codec_model
generic map(
data_width_g => data_width_g
)
port map(
rst_n => rst_n,
aud_data_in => aud_data_out_r,
aud_bclk_in => aud_bclk_out_r,
aud_lrclk_in => aud_lrclk_out_r,
value_left_out => l_data_codec_tb ,
value_right_out => r_data_codec_tb
);
i_wavegen_left : wave_gen
generic map(
width_g => data_width_g,
step_g => step_w_l_g
)
port map(
clk => clk,
rst_n => rst_n,
sync_clear_in => sync_r,
value_out => l_data_wg_actrl
);
i_wavegen_right : wave_gen
generic map(
width_g => data_width_g,
step_g => step_w_r_g
)
port map(
clk => clk,
rst_n => rst_n,
sync_clear_in => sync_r,
value_out => r_data_wg_actrl
);
-- Clock, reset and sync generation.
clk <= not clk after clockrate_ns_c/2; -- Create clock pulse.
rst_n <= '1' after clockrate_ns_c * 4; -- Reset high after 4 pulses.
sync_r <= not sync_r after 5 ms; -- Note: I wish testbenches had a pseudo random number generator..
-- Check generator sync behavior.
check_generators : process(clk, rst_n)
begin
if(rst_n = '0') then
-- Reset registers ..
elsif(clk'event and clk = '1') then
if(sync_r = '1') then -- If sync is 1 we should have no output after 1 cycle.
if(checkdelay_r = cdelay) then
assert (signed(l_data_wg_actrl) = 0) report "Wave gen active on sync = 1" severity failure;
assert (signed(r_data_wg_actrl) = 0) report "Wave gen active on sync = 1" severity failure;
else
checkdelay_r <= checkdelay_r + 1;
end if;
else
checkdelay_r <= 0;
end if;
end if;
end process check_generators;
-- Check codec output from model.
data_checker : process(clk, rst_n)
begin
if(rst_n = '0') then
--Reset registers ..
l_data_expected_r <= (others => '0');
r_data_expected_r <= (others => '0');
bitcounter_r <= bc_time;
elsif(clk'event and clk = '1') then
if(bitcounter_r = 0) then -- When we reach zero check the output ..
l_data_expected_r <= l_data_wg_actrl;
r_data_expected_r <= r_data_wg_actrl;
if(sync_r = '0') then -- .. assuming we have output ..
assert (l_data_expected_r = l_data_codec_tb) report "Mismatch in left input/output data" severity failure;
assert (r_data_expected_r = r_data_codec_tb) report "Mismatch in right input/output data" severity failure;
end if;
bitcounter_r <= bc_time; -- .. and reset the counter to keep it in sync with the codec ..
else
bitcounter_r <= bitcounter_r - 1; -- Inrement counter (see previous explanation).
end if;
end if;
end process data_checker;
end testbench; | gpl-2.0 | 40c3c039fe25972d854ccd79993be5f9 | 0.53954 | 3.480341 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/receiver.vhd | 13 | 6,114 | ----------------------------------------------------------------------------------
-- receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the serial port. The first byte is the commands
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received it will be kept available for 10 cycles
-- on the op and data outputs. A valid command can be detected by checking if the
-- execute output is set. After 10 cycles the registers will be cleared
-- automatically and the receiver waits for new data from the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity receiver is
generic (
FREQ : integer;
RATE : integer
);
Port ( rx : in STD_LOGIC;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out STD_LOGIC_VECTOR (7 downto 0);
data : out STD_LOGIC_VECTOR (31 downto 0);
execute : out STD_LOGIC
);
end receiver;
architecture Behavioral of receiver is
type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY);
-- constant BITLENGTH : integer := FREQ / RATE;
constant BITLENGTH : integer := 16;
signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter
signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte
signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command
signal state, nstate : UART_STATES; -- receiver state
signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte
signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword
begin
op <= opcode;
data <= dataBuf;
process(clock, reset)
begin
if reset = '1' then
state <= INIT;
elsif rising_edge(clock) then
counter <= ncounter;
bitcount <= nbitcount;
bytecount <= nbytecount;
dataBuf <= ndataBuf;
opcode <= nopcode;
state <= nstate;
end if;
end process;
process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx)
begin
case state is
-- reset uart
when INIT =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= (others => '0');
ndataBuf <= (others => '0');
nstate <= WAITSTOP;
-- wait for stop bit
when WAITSTOP =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '1' then
nstate <= WAITSTART;
else
nstate <= state;
end if;
-- wait for start bit
when WAITSTART =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '0' then
nstate <= WAITBEGIN;
else
nstate <= state;
end if;
-- wait for first half of start bit
when WAITBEGIN =>
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = BITLENGTH / 2 then
ncounter <= 0;
nstate <= READBYTE;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
-- receive byte
when READBYTE =>
if counter = BITLENGTH then
ncounter <= 0;
nbitcount <= bitcount + 1;
if bitcount = 8 then
nbytecount <= bytecount + 1;
nstate <= ANALYZE;
nopcode <= opcode;
ndataBuf <= dataBuf;
else
nbytecount <= bytecount;
if bytecount = 0 then
nopcode <= rx & opcode(7 downto 1);
ndataBuf <= dataBuf;
else
nopcode <= opcode;
ndataBuf <= rx & dataBuf(31 downto 1);
end if;
nstate <= state;
end if;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nbitcount <= bitcount;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
nstate <= state;
end if;
-- check if long or short command has been fully received
when ANALYZE =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
-- long command when 5 bytes have been received
if bytecount = 5 then
nstate <= READY;
-- short command when set flag not set
elsif opcode(7) = '0' then
nstate <= READY;
-- otherwise continue receiving
else
nstate <= WAITSTOP;
end if;
-- done, give 10 cycles for processing
when READY =>
ncounter <= counter + 1;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = 10 then
nstate <= INIT;
else
nstate <= state;
end if;
end case;
end process;
-- set execute flag properly
process(state)
begin
if state = READY then
execute <= '1';
else
execute <= '0';
end if;
end process;
end Behavioral;
| mit | 2e1d707e811c4ae800c8f68efe579410 | 0.609748 | 3.838041 | false | false | false | false |
huukit/logicsynth | excercises/vhd/multi_port_adder_bonus.vhd | 1 | 3,779 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 04
-- Project :
-------------------------------------------------------------------------------
-- File : multi_port_adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 09.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fourth excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 09.11.2015 1.0 tuhu Created
-- 23.11.2015 1.1 nikulaj Added bonus feature
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity multi_port_adder is -- Multi port adder definition.
generic
(
operand_width_g : integer := 16; -- Specify default value for both.
num_of_operands_g : integer := 4
);
port
(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
operands_in : in std_logic_vector((operand_width_g * num_of_operands_g) - 1 downto 0); -- Operand inputs
sum_out : out std_logic_vector(operand_width_g - 1 downto 0) -- Calculation result.
);
end multi_port_adder;
architecture structural of multi_port_adder is -- Structural declaration utilizing the adder component.
component adder -- Declare component.
generic
(
operand_width_g : integer
);
port
( -- See component for definitions of signals.
clk : in std_logic;
rst_n : in std_logic;
a_in : in std_logic_vector(operand_width_g - 1 downto 0);
b_in : in std_logic_vector(operand_width_g - 1 downto 0);
sum_out : out std_logic_vector(operand_width_g downto 0)
);
end component;
type calculation_values_arr is array (0 to 2*num_of_operands_g - 2) -- Declare new type for all values.
of std_logic_vector(operand_width_g downto 0);
signal values_r : calculation_values_arr; -- All calculation values (inputs and outputs).
begin -- structural
assert ((num_of_operands_g mod 2) = 0) report -- Make sure the number of operands is a factor of 2.
"failure: num_of_operands_g is not a factor of 2!" severity failure;
inputs_to_arr: -- This signal assignment can't be done sequentially in a process, so it's done in a for...generate structure.
for I in 0 to (num_of_operands_g - 1) generate
values_r(I)(operand_width_g - 1 downto 0) <= operands_in((I+1)*operand_width_g - 1 downto I*operand_width_g);
values_r(I)(operand_width_g) <= '0'; -- fill up the missing bit (the above assignment is 4 <= 3).
end generate inputs_to_arr;
adders:
for I in 0 to num_of_operands_g - 2 generate -- Generating the adders
adder_arr : adder
generic map
(
operand_width_g => operand_width_g
)
port map
(
clk => clk,
rst_n => rst_n,
a_in => values_r(I*2)(operand_width_g - 1 downto 0),
b_in => values_r(I*2 + 1)(operand_width_g - 1 downto 0),
sum_out => values_r(num_of_operands_g + I)
);
end generate adders;
sum_out <= values_r(values_r'length - 1)(operand_width_g - 1 downto 0); -- The final result is the last element in the value array.
end structural;
| gpl-2.0 | 4200a759969d763a916d5f3c7a76a56f | 0.507012 | 4.054721 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/win_1/win_sim_netlist.vhdl | 1 | 148,310 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:35:24 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/win_1/win_sim_netlist.vhdl
-- Design : win
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 1 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_bindec : entity is "bindec";
end win_bindec;
architecture STRUCTURE of win_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end win_blk_mem_gen_mux;
architecture STRUCTURE of win_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe_d1(0),
O => douta(7)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0),
I5 => sel_pipe_d1(0),
O => douta(8)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe_d1(0),
O => douta(0)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe_d1(0),
O => douta(1)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe_d1(0),
O => douta(2)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe_d1(0),
O => douta(3)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe_d1(0),
O => douta(4)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe_d1(0),
O => douta(5)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe_d1(0),
O => douta(6)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end win_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of win_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"1800000000000000000000800000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000003000000000000000000003000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0040000000000000000000040000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000800000000000000000001600000000000000",
INIT_1B => X"2000008000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"8800008000000000000000600000200000000000004200002400000000000002",
INIT_1D => X"4080000800000000000000080000800000000000002000000800000000000000",
INIT_1E => X"0000000400000000000004000000000000000000005010000200000000000000",
INIT_1F => X"8006000200000000000002002000180000000000003001000080000000000001",
INIT_20 => X"000040004000000000000000000004000000000001C000000020000000000000",
INIT_21 => X"00003000100000000003000000800000000000000800000C001400300000001E",
INIT_22 => X"000001000C000000000C00000020006000000000200000000000000000000040",
INIT_23 => X"0000000200000000000800000000400800000000800000000000800000000380",
INIT_24 => X"0000000004100000000400000000008100000000800000000008000000000180",
INIT_25 => X"0000000780000000040000000000A80000000040000000000700010000300700",
INIT_26 => X"00000000000000000800000000000000000000040000000000D8000000024000",
INIT_27 => X"FD000000000000000000000000000000000000000E0000000000000000000000",
INIT_28 => X"0010070000000000000000010038000000000000000010030000000000008000",
INIT_29 => X"0001000000000000000000001000000000000000000000807800000000000000",
INIT_2A => X"0000100000000000000200000100000000000000000000100000000000000600",
INIT_2B => X"0000010000000000000000000010000000000000000000010000000000000020",
INIT_2C => X"0100001800000000000000000001000000000000000000001000000000000000",
INIT_2D => X"00200000C0000000000000000000080000000000000000000000000000000000",
INIT_2E => X"0010000000000000000000802000000400000000000802000002800000000000",
INIT_2F => X"0600000000200000000000006000000000000000000002000000040000000000",
INIT_30 => X"0000000000040000000000010000000020000000000010000000000000000000",
INIT_31 => X"0000080000018000000000000040000008000000000000000000008000000000",
INIT_32 => X"0000004000001000000000000004000001000000000000000000000000000000",
INIT_33 => X"0000000000000100000000000000000000100000000000000000000100000000",
INIT_34 => X"0000000040000008000000000000040000010000000000000000000010000000",
INIT_35 => X"0000000010000000200000000000000000000280000000000018000000820000",
INIT_36 => X"0000000000000000002000000000001000000002000000000001000000002000",
INIT_37 => X"0000000008000000000200000000008000000000200000000004000000000200",
INIT_38 => X"4000000000000000000000000000000000000000000000000000400000000010",
INIT_39 => X"0002202040000000000000000102000004000000000800000000008000000000",
INIT_3A => X"0400000000000000000000000C00002200100000000400000000000300000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"80000000000002000000000000000000000000000030000000000000C0000000",
INIT_3C => X"00000000000000000000030001000000002C0000000000000000000000000000",
INIT_3D => X"4000000000000080000000000000000000000000008000000000000030000000",
INIT_3E => X"0000000000000000000001000003000000000000000000000000000000000000",
INIT_3F => X"5000000400000001000000000000000000000000002000000000000002000000",
INIT_40 => X"0000000000000000000800000000100000001400000000000000000000000002",
INIT_41 => X"00000000000000000000000000000000000000000C0000000010000000000000",
INIT_42 => X"0000000000000000010000000000007000000200000008000000000000000950",
INIT_43 => X"0000000001000000080000000000000000000008000000000000000000030000",
INIT_44 => X"0000000000000000100000000000000400000000000000000000000000009400",
INIT_45 => X"0000000000014000001000000000000000000080000000000000000000002000",
INIT_46 => X"0000000000000000800000000000000000900000C00000000000000000094000",
INIT_47 => X"00000000000000050000000000000000000000C00000000000000000000000C0",
INIT_48 => X"0000000000000000500000000000000000000240018000000000000000020000",
INIT_49 => X"0000000000000000001400000000000000000080000000000000000000000000",
INIT_4A => X"00000000000025550000000000000000002A0000095000000000060000250000",
INIT_4B => X"000000000000007F00000000000000000030000000000000000000003F000000",
INIT_4C => X"0000000000004080000000000000000000000400000000000000002440000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"000000000000000003A9000000000000000000000000000000000001C0040000",
INIT_4F => X"5554000000000000000000000000000000040000000000000000000000000000",
INIT_50 => X"0000000000000400000000000000001A400000000000000000000002B0000000",
INIT_51 => X"000002C0000F00000000000000000000003800000000000000000FC000000000",
INIT_52 => X"0000000000000000000000000002800025800000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000040000000000000000000000000000000000000000240000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000100",
INIT_57 => X"E000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000100000000000000000000000000000000000000000",
INIT_59 => X"0003000000000180000000000000000000000000000009000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000800000000000000000000000000000000000000000C00000",
INIT_5C => X"000000000000000000000140000500000000000A400000000000000000000000",
INIT_5D => X"0180014000000000000010000000000000000000000140009700000000000000",
INIT_5E => X"000000000000000000000002C000000000000000004000000000000000000000",
INIT_5F => X"000E00000000000000000D00000000000000000000000A402400000000000000",
INIT_60 => X"0000000000000000000000000D00000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000600000000000000000000000040000000000000000",
INIT_62 => X"00C00000000000000000000000000000000000000000C0000000000000000000",
INIT_63 => X"0000000000500000000000034000000000000000000000000000300000000000",
INIT_64 => X"0000000000000000000000000000000100000000000000000000000000000000",
INIT_65 => X"000000000000300000000000000000000000000000000000000000D000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000400000000000014000000000000000000000000000300000",
INIT_6A => X"0000000000200000000000000000000000000080000000000000101000000000",
INIT_6B => X"0000000000000000000000000000000000400000000000000000000000010000",
INIT_6C => X"000000000000000C00000000000000000000000000000000000000000C000000",
INIT_6D => X"0000000000000000055400000000000000000C00000000000000000000000800",
INIT_6E => X"00000000000000000C00000000000000000000080000000000000000000C0000",
INIT_6F => X"000000000000000000C00000000000000000000C000000000000000000009000",
INIT_70 => X"0000000000000000000200000000000000000000100000000000000000000000",
INIT_71 => X"300000000000000000000300000000000000000000600000000000000000000E",
INIT_72 => X"0038000000000000000000400000000000000000000040000000000000000000",
INIT_73 => X"0C00000154000155400000000C00000000000000000B00000003000400000000",
INIT_74 => X"00000000000000000000001000000C0000000020000000010000000000000000",
INIT_75 => X"0000000040000000000000000001000000000000000000000038000000000004",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000000C000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000007C00000000000000000003C00000000000000000001C00000",
INITP_02 => X"0000000000000003FC0000000000000000001FC0000000000000000000FC0000",
INITP_03 => X"0000000000000001FFE000000000000000000FFC0000000000000000007FC000",
INITP_04 => X"00000000000000007FFE000000000000000007FFE000000000000000003FFE00",
INITP_05 => X"00000000000000000FFFE00000000000000000FFFE00000000000000000FFFE0",
INITP_06 => X"000000000000000003FFF000000000000000000FFFE00000000000000000FFFE",
INITP_07 => X"80000000000000003E3FF8000000000000000083FFC000000000000000003FFF",
INITP_08 => X"0000000000000001FFFFE000000000000000007FFFE00000000000000003E3FF",
INITP_09 => X"0000000000000001FF0000000000000000000FF8FC00000000000000003FFFFC",
INITP_0A => X"1FFFFF0000000000FC80003FFF000000000007FC0001FFE000000000003FE000",
INITP_0B => X"9FFFFFFF380000007E003EFFFFFFE400000003F803E7FFFFFE400000001FC000",
INITP_0C => X"CFFFFFFFFE600000061FFE7FFFFFFFCE00000079DFF3FFFFFFFDE0000007E03F",
INITP_0D => X"E7FFFFFFFFF80000001FFF3FFFFFFFFF80000001FFF9FFFFFFFFF800000043FF",
INITP_0E => X"FDFFFFFFFFFF8000000FFFE7FFFFFFFFF80000007FFE7FFFFFFFFF80000003FF",
INITP_0F => X"FF3F9FFFFFFF3E00000FFFF9FFFFFFFFFF8000007FFF9FFFFFFFFFF8000003FF",
INIT_00 => X"9E9E9E9E00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_01 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_02 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_03 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00EEAA009E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_06 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0066FE32009E",
INIT_07 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"9E9E9E9E9E00EEBAFE32009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E22AA98FEFE10009E9E9E9E9E9E9E9E9E",
INIT_0C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0D => X"FE10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0066FEFEFE",
INIT_0F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"9E9E9E9E9E9E00EE98FEFEFEFE10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_11 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_12 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_13 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E228898FEFEFEFEFE10009E9E9E9E9E",
INIT_14 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_15 => X"FEFEFEFEFE10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_16 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0088FEFE",
INIT_17 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_18 => X"9E9E9E9E9E9E9E00EE98FEFEFEFEFEFEFE10009E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_19 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E4488BAFEFEFEFEFEFEFEFE546622",
INIT_1C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1D => X"FEFEFEFEFEFEFEFEFEFEBA44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00AAFE",
INIT_1F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_20 => X"9E9E9E9E9E9E9E9E00EE98FEFEFEFEFEFEFEFEFEFEFEFE66009E9E9E9E9E9E9E",
INIT_21 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_22 => X"FEFEDC44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_23 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000BAFEFEFEFEFEFEFEFEFEFE",
INIT_24 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_25 => X"0098FEFEFEFEFEFEFEFEFEFEFEFEDC44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_26 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_27 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_28 => X"9E9E9E9E9E9E9E9E9E9E00AA10DCFEFEFEFEFEFEFEFEFEFEFEFEDC44009E9E9E",
INIT_29 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2A => X"FEFEFEFEFEFEDC44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00EEFEFEFEFEFEFEFEFE",
INIT_2C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2D => X"9E9E00EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC44009E9E9E9E9E9E9E9E9E9E9E",
INIT_2E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2F => X"009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_30 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E00CCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE44",
INIT_31 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_32 => X"FEFEFEFEFEFEFEFEFEDCBA66009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_33 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00EEFEFEFEFE",
INIT_34 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_35 => X"009E9E9E004476DCFEFEFEFEFEFEFEFEFEFEFEFEAA6666AAAA9E9E9E9E9E9E9E",
INIT_36 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_37 => X"000000AAEE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_38 => X"9E9E9E9E9E9E9E9E9E9E9E44AA449E9E0044DCFEFEFEFEFEFEFEFEFEFEFEBA10",
INIT_39 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3A => X"FEFEFEFEFEFEFEFEFEFECC009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00AAFECC009E0044BAFE",
INIT_3C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3D => X"9E0010BAFEBA32000022BAFEFEFEFEFEFEFEFEFEDCAA449E9E9E9E9E9E9E9E9E",
INIT_3E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3F => X"10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_40 => X"9E9E9E9E9E9E9E00000000004488BAFEFEFEDCAA88CCDCFEFEFEFEFEFEFEFEBA",
INIT_41 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_42 => X"FEFEFEFEFEFEFEFEFEFEFECC009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_43 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000AAFEFEFEFEFEFEFE",
INIT_44 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_45 => X"54545454BAFEFEFEFEFEFEFEFEFEFEFEFEFE98AAAAAAAA449E9E9E9E9E9E9E9E",
INIT_46 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000CC54",
INIT_47 => X"0000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_48 => X"9E9E9E9E9E9E9E20404052FEFEFEFEFEFE9898BAFEFEFEFEFEFE98989898EE00",
INIT_49 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4A => X"FEFEFEFEFEDC4400000044669E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00A02020B2FEFEFEFEFE540000AA",
INIT_4C => X"0000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4D => X"4040668EFCFEFE1088000044CCCCCCCCCCAA0000000000000000000000000000",
INIT_4E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0020A020",
INIT_4F => X"000022444444444444444444444444009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_50 => X"9E9E9E9E9E9E9E9E2080404020202042FCDE9822009E9E9E0000000000000000",
INIT_51 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_52 => X"9E9E9E9E9E9E9E9E9E9E9E000000AADCDCDCDCDCDCDCDCDCDCDCBA4400000000",
INIT_53 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000C020404020202064FE54229E",
INIT_54 => X"FEFEFEFEFEFEFE32EEEEEEAA0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_55 => X"204020204040E0A20EAA009E9E9E00000000000000000088EEEE76FEFEFEFEFE",
INIT_56 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0040A0",
INIT_57 => X"00222210FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE982222220000229E9E",
INIT_58 => X"9E9E9E9E9E9E9E9E9E008040402020404020600000009E9E9E9E222222222200",
INIT_59 => X"FEFEFEFEBABA3200EEBA2200009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5A => X"00000000000032BABADC5400CCBABADCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_5B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000C020404020204000402000",
INIT_5C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDCCCEE32EEEECC009E9E9E9E9E9E",
INIT_5D => X"00006020204040E0600000000066CCCCCCCCDCFEFE9810CC76FEFEFEFEFEFEFE",
INIT_5E => X"CC22BAFEFE66009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_5F => X"FE8844FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_60 => X"9E9E9E9E9E9E9E9E9E9E9E0000004020404020600000000000EEFEFEFEFEFEFE",
INIT_61 => X"FEFEFEFEFEFEFEFEFEFEFEFEBA546610FEBA10009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_62 => X"9400E00296DCFEFEFEFEFE9844EE98FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_63 => X"009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000404060E02010",
INIT_64 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEAAAA54FE7600",
INIT_65 => X"9E9E9E00000020A0C0A28A9AFA402062D4FAFEFEFEFE76EE8876FEFEFEFEFEFE",
INIT_66 => X"FEFEFEFEFEFEFEEE00BA54009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_67 => X"FEFE6666FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_68 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000C0000088FEFED8422020208EFEFE",
INIT_69 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA54AA66009E9E9E9E9E9E9E9E",
INIT_6A => X"7698FEFEFCD66820008CFEFE7666EE98FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6B => X"FE4400009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E40A878",
INIT_6C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6D => X"9E9E9E9E9E9E9E9E9E20E8F8FEFEFEFEFEFEB26868B2FE98EE6698FEFEFEFEFE",
INIT_6E => X"FEFEFEFEFEFEFEFEFEFEFEFEDC4400009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6F => X"FEFEDC44AAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_70 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E04040D6FEFEFEFEFEFEFE",
INIT_71 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC4400009E9E9E9E",
INIT_72 => X"C0204020D8FEFEFEFEFEFEFEFEFEFE0066FEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_73 => X"FEFEFEFEDC440000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0040",
INIT_74 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_75 => X"9E9E9E9E9E9E9E9E9E0044C240402040B2FAFEFEFEFEFEFEFEDC7688EEFEFEFE",
INIT_76 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC44000000009E9E9E9E9E9E9E9E9E9E",
INIT_77 => X"FEFEFEFEFE102276FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_78 => X"00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0022BAB220202020206AFEFE",
INIT_79 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC440000",
INIT_7A => X"AA54FEB2202020202066FEFEFEFEFEFEFEEE00BAFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7B => X"FEFEFEFEDCBAFEFEDC88220000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_7C => X"FEFEFEFEFEDCBAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7D => X"9E9E9E9E9E9E9E9E9E9E004454FEFEB2442020202068FEFEFEFEFEFEBAEE44BA",
INIT_7E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC44BAFEFEDC1000009E9E9E9E9E9E9E",
INIT_7F => X"2066FEFEFEFEFEBA44CCDCFEFEFEFEFEFEAA66DCFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFEFCFFFE68791F00007FFFF3F7FFFF1FEFE00003FFFF3F1FFFFBFE7E00001FF",
INITP_01 => X"FFF007FFFDC679F900007FFF8FBFFFDCE798700007FFFCFCFFFE4C790F00007F",
INITP_02 => X"FFFC1FFFFFE79FF0FC000FFFC03FFFFDC67E670000FFFE00FFFFDC27DFB0000F",
INITP_03 => X"3FFFFFFFFFFFFFFCFFE003FFF1FFFFFFF83FFFFC003FFF83FFFFFE79FF9FC003",
INITP_04 => X"03FFFFFFFFBFFFFFFFFE003FFFFFFFFFFFFFFFFFE003FFFFFFFFFFFFFF8FFE00",
INITP_05 => X"003FFFFFFFF9FFFFFCFFE003FFFFFFFF3FFFFFFFFE003FFFFFFFF3FFFFFFFFE0",
INITP_06 => X"000FFFFFFFFFF07FFE73F8007FFFFFFFFE0FFFC73FC007FFFFFFFFCFFFFC83FE",
INITP_07 => X"EE01FFFFFFFFFFFC7FFCFEC01FFFFFFFFFFFC7FF87EC01FFFFFFFFFFF3FFF73F",
INITP_08 => X"C1FC3FFFFFFFFFFFFF3FFF8F83FFFFFFFFFFFFF7FFF8F83FFFFFFFFFFFF8FFFF",
INITP_09 => X"000003C7FFFFFFE0FFFE0000043E7FFFFFFC1FFFE00000E3FFFFFFFF8FFFFC7F",
INITP_0A => X"000000000000000000000000000000000000000000000000601FF000000003C0",
INITP_0B => X"2000010000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"040000BA00000000000000200005800000000000008000002600000000000000",
INITP_0D => X"30000007A00000000000000000003A00000000000040000003A0000000000000",
INITP_0E => X"7F100003FA000000000008F100001FA0000000000067880004FA000000000000",
INITP_0F => X"3FF20002FFA00000000005FF100017FA00000000002FF000007FA00000000001",
INIT_00 => X"FEFE54009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0044BAFEFEFEFEDA442020",
INIT_01 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10EE10FEFEFEFEFEFEFEDCEECC10FEFE",
INIT_02 => X"00AA32FEFEFEFEFEFE6620206AB4FEFEFEFEFEDC00AAFEFEFEFEFEBAEEAAEEFE",
INIT_03 => X"FEFEFEFEFEDC760010FEDCFEFEFE5422009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"44EEFEFEFEFEDC320054FEFEFEFEFEFEFEFEFEFEFEFEFEDCDCFEFE9844000076",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E000054FEFEFEFEFEFEFC442040D8FEFEFEFEFEFE98",
INIT_06 => X"FEFEFECC88FE106698EE0044EEFEFEFEFECC8898EE444432FEFEDC9888009E9E",
INIT_07 => X"FC440040D6FEFEFEFEFE106676DCFEFEFEFE886698DCFEFEFEFEFEFEFEFEFEFE",
INIT_08 => X"EE00004432FEFEFE88009E9E9E9E9E9E9E9E9E9E9E9E9E000054FEFEFEFEFEFE",
INIT_09 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEBA32AAEEFEAA00FEBAAA0088FEFEFEFE6644FE",
INIT_0A => X"9E9E9E9E0032FEFEFEFEFEFEFE904620D6FEFEFEFE324400FEFEFEFEBA10AAEE",
INIT_0B => X"BAFEFE2288FEFEFEFE8844FE100000002298FEFE88009E9E9E9E9E9E9E9E9E9E",
INIT_0C => X"76000044BAFEFEFE100076FEFEFEFEFEFEFEFEFEFEFEFEFEFE540032FEFEAA22",
INIT_0D => X"88009E9E9E9E9E9E9E9E9E9E9E9E9E000054FEFEFEFEFEFEFEFEB240D6FEFEFE",
INIT_0E => X"FEFEFEFEFE540032FEFECC006654FE4488FEFEFEFE6622FEDC9898989866EEFE",
INIT_0F => X"FEFEFEFEFEFEFCD8FCFEFE104400000066664444AA76FEFEFEFEFEFEFEFEFEFE",
INIT_10 => X"FE10AA32BAFEFEDC548810FE88009E9E9E9E9E9E9E9E9E9E9E9E008876DCFEFE",
INIT_11 => X"32FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE540032FEFECC0000EEFE2288FEFEFE",
INIT_12 => X"9E9E9E9E9E9E0088FEFEFEFEFEFEFEFEFEFEFEFEFEDC54660000000000008888",
INIT_13 => X"FEFEEE000010FE44AAFEFEFEFEFE9800EEFEFEEE0098FEFE88009E9E9E9E9E9E",
INIT_14 => X"FE7600000000000000EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE540032",
INIT_15 => X"54FEFEFE9810009E9E9E9E9E9E9E9E9E9E9E0088FEFEFEFEFEFEFEFEFEFEFEFE",
INIT_16 => X"FEFEFEFEFEFEFEFEFEDC76AAAAFEDC9898EE663298FEFEFEFEFEFE54CC6666CC",
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFE7600000000AA7676BAFEFEFEFEFEFEFEFEFEFE",
INIT_18 => X"FEFEFEFEFEFEFEFE32444432FEFEFEFEFE7600009E9E9E9E9E9E9E9E9E001098",
INIT_19 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE6654989898EE66DC",
INIT_1A => X"809E9E9E9E9E9E9E000098FEFEFEFEFEFEFEFEFEFEFEFEFE98EE0044888876FE",
INIT_1B => X"FEFEFEFE9800000000EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE760020",
INIT_1C => X"FEFEFEFE88000032FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1D => X"76FEFEFEFEFEFEFEFEDC3286209E9E9E9E9E9E9E000076FEFEFEFEFEFEFEFEFE",
INIT_1E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE3232323298FEFEFEFEFEFEFE108888",
INIT_1F => X"000076FEFEFEFEFEFEFEFEFEFEFEFEFE543232DCFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_20 => X"FEFEFEFEFEFEFEFEFECC222232FEFEFEFEFEFEFEFEFEFECC009E9E9E9E9E9E9E",
INIT_21 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_22 => X"FEFEFEAC009E9E9E9E9E9E9E000076FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_23 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDCDCFEFEFEFEFEFEFEFE",
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_25 => X"FEFEFEFEFEFEFEFEFEFEFEFEF2EEEEA4009E9E9E9E9E9E9E000076FEFEFEFEFE",
INIT_26 => X"FEFEFEFEFEFEFEFE54EEDCFEFEFEFEFEFEFEFEF4EEEEEEF0FEFEFEFEFEFEFEFE",
INIT_27 => X"9E9E9E9E000076FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_28 => X"E0E0E0E2F6FCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFAE4E0E0A0009E9E9E",
INIT_29 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEAA00BAFEFEFEFEFEFEFEFAE8",
INIT_2A => X"FEFEF4E2E0E0E0A0009E9E9E9E9E9E9E000076FEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2B => X"AA00DCFEFEFEFEFEFEF6E4E0E0E0E0E0E2F0FEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2D => X"FEFE3254FE76F0F01032FEFEFEFEF2E0E0E0E0C0009E9E9E9E9E9E00000076FE",
INIT_2E => X"FEFEFEFEFEFEFEFEFEFEFEFE54CCCC76FEFEFEFEFEF4E0E0E0E0E0E0E0ECFEFE",
INIT_2F => X"009E9E9E9E9E9E0044EEBAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_30 => X"FEF6E0E0E0E0E0E0E0EEFEFEFEFE4466DCCA00000022BAFEFEFEF4E2E0E0C0A0",
INIT_31 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC22AADCDCDCDC",
INIT_32 => X"8022BAFEFEFEFCF8E68060409E9E9E9E9E9E9E00CCFEFEFEFEFEFEFEFEFEFEFE",
INIT_33 => X"FEFEFEFEFEFE98EE222222449CF8E0E0E0E0E0E0E0ECFEFEFEFE660044228080",
INIT_34 => X"AAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_35 => X"EAF4FEFEFEFE10660040E0E0C002BAFEFEFEFEFE68C0009E9E9E9E9E9E9E9E00",
INIT_36 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE76888888AAF050EEE4E0E0E0E0",
INIT_37 => X"88009E9E9E9E9E9E9E9E00AA32FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_38 => X"FEFEFEFE6668FEECE0E0E0E4FCFEFEFEFEFEFE760020E0E0C024BCFEFEFEFEDC",
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3A => X"76A64040EC98FEFEFEFE54663432009E9E9E9E9E9E0022BAFEFEFEFEFEFEFEFE",
INIT_3B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE98106640C2F8FAFAFEFEFEFEFEFEFEDE",
INIT_3C => X"9E0000BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3D => X"AC365678FEFEFEFEFEFEFEFEFE12686876FEFEFEFEFE100098DCAA449E9E9E9E",
INIT_3E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA6668",
INIT_3F => X"FEFE320076FEFEAA009E9E9E0066AABAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_40 => X"FEFEFEFEFEFEFEFEFEFEFEFE98000044BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_41 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_42 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEEE440076FEFE9810009E9E00EEFEFEFEFEFEFE",
INIT_43 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE5454328832FEFE",
INIT_44 => X"DC88449E00EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_45 => X"FEFEFEFEFEFEFEDC66AA7676BAFEFEFEFEFEFEFEFEFE987654222288BAFEFEFE",
INIT_46 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA7676DCFEFEFEFEFEFEFE",
INIT_47 => X"FEDC44000000AAFEFEFEFEFEFEFECC0000EEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_48 => X"FEAA000032FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE100000CCFEFEFEFEFEFEFE",
INIT_49 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_4A => X"FEBA322222CCCCCCCCCCCCCCCCAA0000000088EECCCCCCCC32FE100000EEFEFE",
INIT_4B => X"FEFEFEFEFEFEFEFEFEFEFEFEFE98EE0066CCCC76FEFEFEFEFEFEFEFEFEFEFEFE",
INIT_4C => X"000000004498CC0000EEFEFEFEFE32CCCCBAFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_4D => X"98989898989898989898DCFEFEFEBA440000000000000000000000009E9E9E00",
INIT_4E => X"FEFEFEFEFEFEFEFEBA98989898989898989898989898989898BA7600000000AA",
INIT_4F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E0000009E22229E00EEFEBA989866000010BAFE",
INIT_50 => X"222222222222229E9E9E9E002222222222222222222232FEFE322200009E9E9E",
INIT_51 => X"0010FE882222009E9E2288FEFEFEFEFEFEFEFEFEAA2222222222222222222222",
INIT_52 => X"000088EEEE6600009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E009E9E009E9E",
INIT_53 => X"440000000000000000000000000000000000009E9E9E9E9E0000000000000000",
INIT_54 => X"9E9E9E9E9E9E9E9E9E9E9E9E0088EE0000009E9E9E9E22EEEEEEEEEEEEEEEEEE",
INIT_55 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_56 => X"9E9E9E0000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_57 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E",
INIT_58 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_59 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5F => X"4444339E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E11669E9E9E9E9E9E9E",
INIT_60 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E6644",
INIT_61 => X"9E9E33CCEE10999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_62 => X"9E9E9E9E9E9E9E9E99EE00000000EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_63 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_64 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E994454FE22EE9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_65 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9ECC0000000022339E9E9E9E9E",
INIT_66 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_67 => X"2200000022999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E336676FEDC22119E",
INIT_68 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88",
INIT_69 => X"9E9E9E9EEE22DCFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6A => X"9E9E9E9E9E9E9E9E9E99EE0000000000449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE66DCFEBA22119E9E9E9E9E9E9E9E9E",
INIT_6D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE222200000000229E9E9E",
INIT_6E => X"BA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6F => X"88EEBABACC000000229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88EEBAFEFE",
INIT_70 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_71 => X"9E9E9E9E9E99EECC98FEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_72 => X"9E9E9E9E9E9E9E9E9E3311EECC98FEFE10000066119E9E9E9E9E9E9E9E9E9E9E",
INIT_73 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_74 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE66DCFEFEFEFEBA22119E9E9E9E9E",
INIT_75 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E99442266DCFEFEFEEE000011",
INIT_76 => X"FEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_77 => X"4476BABAFEFEFEFEEE0000119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88EEBAFE",
INIT_78 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E33",
INIT_79 => X"9E9E9E9E9E9E9E9E2210FEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_7A => X"9E9E9E9E9E9E9E9E9E9E33CC10FEFEFEFEFEFEFEEE0000EE9E9E9E9E9E9E9E9E",
INIT_7B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_7C => X"EE0022119E9E9E9E9E9E9E9E9E9E9E9E9E9E9EBB4410FEFEFEFEFEFEBA22119E",
INIT_7D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EBB4432FEFEFEFEFEFEFEFE",
INIT_7E => X"76DCFEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_7F => X"668876DCFEFEFEFEFEFEFEFEEE22779E9E9E9E9E9E9E9E9E9E9E9E9E9E9E3366",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FDFF80001FFA00000000003FF00003FFA000000003E3FF00004FFA0000000000",
INITP_01 => X"FFFFD0000FFFC00000023FFFFE80007FFC0000001C3FDFF0001BFFB000000001",
INITP_02 => X"FFFFFE800BFFFC000008FFFFFFC0005FFFC0000071FFFFF80001FFFC0000001F",
INITP_03 => X"FFFFFFFD0083FFC00003FFFFFFFF8003FFFC0000C7FFFFFFE4003FFFC000007F",
INITP_04 => X"FFFFFF0FFA07CFFE0001FFFFFFFFFF0039FFC000EFFFFFFFFFC8101FFC00007F",
INITP_05 => X"DFFFFFC73FC1F9FFA007FFFFFFFC73FC0FCFFA7F87FFFFFFE0FF9EFCFFC0003F",
INITP_06 => X"E7FFFFFE0FFF3F9FE0401F3FFFFFC07FF3F9FE0007FDFFFFFC73FE1F9FFA007F",
INITP_07 => X"FEFF0FFFFFFF8FF7E200100FFFFFFFFFFC7F9FD0000E7FFFFFF0FFF3F9FE0200",
INITP_08 => X"0013C73FDFFFF7FE720000003C73FFFFFF9FE780000007F07FFFFFF8FE7E0000",
INITP_09 => X"0000FF07FEF7FCFFCF4000000FC03F1FFFE7FE74000001BC33F9FFFE7FE74000",
INITP_0A => X"00000FFFFF1CFFFFFCF8000000FFFFFE07F3FFCF8000000FF0FFE67FDFFCF600",
INITP_0B => X"400000FFFFFE3FFFFFCFE800000FFFFC1CFFFFFCFE800000FFFFF1CFFFFFCFD0",
INITP_0C => X"FC000013FFFFFFFFFFFCFFD00000FFFFFFFFFFFFCFF000000FFFFFE3FFFFFCFE",
INITP_0D => X"7FD00000C7FFFF8FFFFFC7FD000003FFFFFE7FFFFCFFD00000BFFFFFFFFFFFCF",
INITP_0E => X"C9E800000007FFFFFFFFFC1E70000003FFFFFFFFFFC1F10000007FFFF9FFFFFC",
INITP_0F => X"F2740000000CFFFFFFFFFF87200000014FFFFFFFFFFC9C000000087FFFFFFFFF",
INIT_00 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88",
INIT_01 => X"9E9E9E9E9E9E9E9E9E55EEEEFEFEFEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E",
INIT_02 => X"9E9E9E9E9E9E9933333311000022FEFEFEFEFEFEFEFEFEFEEE449E9E9E9E9E9E",
INIT_03 => X"BA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"FEFEFEFEEE449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFEFEFEFEFE",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE00000000000044BAFEFEFEFEFE",
INIT_06 => X"9E22EEFEFEFEFEFEFEFEFEFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_07 => X"9898989898764410FEFEFEFEFEFEFEFE10229E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88666666EE98",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9EBB11CC76FEFEFEFEFEFEFEFEFEDCEE10339E9E9E9E",
INIT_0A => X"9E9E9E553311AACCCCCC76FEFEFEFEFEFEFECC54FEFEFEFEFEFEFE54EEEE9E9E",
INIT_0B => X"FEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0C => X"FEFEFEFEFEFEBA22339E9E9E9E9E9E9E9E9E9E9E9E9E9EEE44DCFEFEFEFEFEFE",
INIT_0D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9EBB220044DCFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_0E => X"9E9E88EEBAFEFEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE3288779E9E9E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E8866667698BAFEFE",
INIT_11 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E0010FEFEFEFEFEFEFEFEFEFEFEFEFEFEEE00",
INIT_12 => X"9E553311AACCEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC449E",
INIT_13 => X"FEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_14 => X"FEFEFEFEFEFEFEFEFE10449E9E9E9E9E9E9E9E9E9E9E9E9E9EBB4410FEFEFEFE",
INIT_15 => X"9E9E9E9E9E9E9E9E9E9E9E9EBB220044DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_16 => X"9E9E9E9E338876DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E",
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC7666559E9E9E9E9E9E9E",
INIT_18 => X"FEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAA6666549898FEFEFEFE",
INIT_19 => X"FEFEFEEEEE559E9E9E9E9E9E9E9E9E9EEE44FEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1A => X"BB11AACCEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10449E9E9E9E9E9E9E9E9E9EEE22BAFE",
INIT_1D => X"9E9E9E9E9E9E9E9E9E9E9E9EEE44DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1E => X"9E9E9E9E9E9E9E9E11004444446654FEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E",
INIT_1F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC546655",
INIT_20 => X"FEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAAEE98FEFEFEFEFEFE",
INIT_21 => X"FEFEFEFEFEFEFEFEFEFEEEEE779E9E9E9E9E9E55880088886600EEFEFEFEFEFE",
INIT_22 => X"B75511AA76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_23 => X"0044DCFEDC22EEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10449E9E9E9E9E9E22",
INIT_25 => X"9E9E9E9E9E9E9E9E9E9E9E9EC84044DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_26 => X"FEFEFEDC5466559E9E9E9E22CC98FEFEFE98CC88DCFEFEFEFEFEFEFEFEFE1000",
INIT_27 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE5466444488FEFEFEFE",
INIT_28 => X"BAFEFEFEFEFEFEFEFE54EEAA9E9E9E9E9E9E9E9E9EAA666600CA98FEFEFEFEFE",
INIT_29 => X"FEFE5488006688AA3298FEFEFEFEFEFEFEEEEE555555112210FEFEFEFEFECC00",
INIT_2A => X"33AAAAAAAA76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2B => X"0000000010FEFEFEFEFECC22DCFEFEFEFEFEFEFEBA22119E9EBB555555555555",
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEBA220022DDFFBB00EEFEFEFEFEFEFEFEFEEE00",
INIT_2D => X"DC22119E9EEE00000000000022DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2E => X"00CCFEFEFEFEFEFEFEFEEE0000000054DCFEFEFEDC88EE98FEFEFEFEFEFEFEFE",
INIT_2F => X"FEFE6610FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA220044FFFFFF",
INIT_30 => X"BA00EEFEFEFEFEFEFEFEFEBA32CC779E442200000000000044FEFEFEFEFEFEFE",
INIT_31 => X"FEFEFEFEFEBA22002233551100EEFEFEFEFEFEFEFEFE54880044CCFEFEFEFEFE",
INIT_32 => X"000000002232BAFEFEFEFEFE98108832FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_33 => X"FEFEFEBA00EEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEFEFEEE449E9E9E88220000",
INIT_34 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2200000000000010FEFEFEFEFEFE",
INIT_35 => X"FEFEFEEE229E9E9E9E110000000000000000EEFEFEFEFEFECC22DCFEFEFEFEFE",
INIT_36 => X"0000000054DCFEFEF4E8E8E8EAFEFEFE00EEFEFEFEFEFEFEBA00EEFEFEFEFEFE",
INIT_37 => X"FEFEFE88CC76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE98AA",
INIT_38 => X"FEFEFEFEDC00CCFEFEFEFEFEFEFE76EECC9E9E9E9E9E550000000000000022AA",
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFE54AAAAAACCFEFEFEF6E8E0E0E0E0F2B43200EEFEFE",
INIT_3A => X"9E9E9ECCAAAAAA440000000032543200EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3B => X"E0E0E0E0E0E0E0000010FEFEFEFEFEFEBA22EEFEFEFEFEFEFEBA22119E9E9E9E",
INIT_3C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFAE2",
INIT_3D => X"FEFEFEAA8888559E9E9E9E9E9E9E9E9E9E9E9E11000000000000000010FEFEFE",
INIT_3E => X"FEFEFEFEFEFEFEFEFEFEFAE2E0E0E0E0C0A0200054BAFEFEFEFEFE328854BAFE",
INIT_3F => X"777777777777552210FEFEFEFEFEFEFEAA66666654FEFEFEFEFEFEFEFEFEFEFE",
INIT_40 => X"FEFEFEFEFEFEFEAA00DCFEFEFEBA3288AACC9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_41 => X"EE76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFAE2E0E0E0E0C00024CC",
INIT_42 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E28AC76FEFEFEFEBA3200228888",
INIT_43 => X"FEFEFAE2E0E0E0E0A000F0FEFEFEFEFEFEFEFECC22DCFEFEFEEE449E9E9E9E9E",
INIT_44 => X"0622DCFEFEFEEE000011FFFFCC00BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_45 => X"22DCFEDCAAEE999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E32",
INIT_46 => X"FE3288DCFEFEFEFEFEFEFEFEFEFEFAE0E0E0E0208254BCFEFEFEFEFEFEFEFECC",
INIT_47 => X"9E9E9E9E9E9E9E9E9E9E9EBFCC00BAFEFEFEEE000033FFFFEF00BAFEFEFEFEFE",
INIT_48 => X"02DEFEFEFEFEFEFEFEFEFECC00BAFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_49 => X"00AA77778800BAFEFEFEFEFE766600DCFEFEFEFEFEFEFEFEFEFEFCECE4E0E0A0",
INIT_4A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9910CCDCFEFEFEEE00",
INIT_4B => X"FEFEFEFEFEFEFEFEEEE0E0C022DCFEFEFEFEFEFEFEFEFECC22DCFEBA22119E9E",
INIT_4C => X"9E9E9E2210FEFEFEFEFEEE00000000000022DCFEFEFEFEBA220022DCFEFEFEFE",
INIT_4D => X"FEDCAAEE76FEFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4E => X"FEFEFEFE7676548854FEFE32AADCFEFEFEFEFEFEFCF480C876FEFEFEFEFEFEFE",
INIT_4F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFEBA3200000000AA76FEFE",
INIT_50 => X"9A346834FEFEFEFEFEFEFEFEFEBA00EEFEFEFEDCAA10779E9E9E9E9E9E9E9E9E",
INIT_51 => X"FEFEFEFEAA88888876FEFEFEFEFEFEFEFEFEFE006856766600BAFEFEFEFEFEFE",
INIT_52 => X"FEEE449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFE",
INIT_53 => X"0000000022DCFEFEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFE",
INIT_54 => X"9E9E9E9E9E9E9E2210FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA22",
INIT_55 => X"FEFEFEFEFEBA00EEFEFEFEFEFEEE229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_56 => X"FEFEFEFEFEFEFEFECC88A8404000008A76FEFEFEFEFEFEFE9854FEFEFEFEFEFE",
INIT_57 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFEFEFEFEFEFEFE",
INIT_58 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFE54AA559E9E9E9E",
INIT_59 => X"10FEFEFEFEF6F6F6F6FCFEFEFEFEFEFEFEFEBA32000000E0E0E000F0FEFEFEFE",
INIT_5A => X"FEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E22",
INIT_5B => X"000020C0E0A000F0FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EE",
INIT_5C => X"9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFCE2E0E0E0F0FEFEFEFEFEFEFEFEEE00",
INIT_5D => X"FEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEDC00119E9E9E9E9E9E9E9E9E9E9E",
INIT_5E => X"E0E4ECFCFEFEFEFEFEFEBA5454765280608032BAFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_5F => X"EE999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEF4E8E0E0E0",
INIT_60 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEDCAA",
INIT_61 => X"9E9E9E2210FEFEECE0E0E0E0E0E0E0FAFEFEFEFEFEFEFEFEFEFEFE8A688AFEFE",
INIT_62 => X"FEBA00EEFEFEFEFEFEFEFEFEEE449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_63 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_64 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEEEE0E0E0E0E0E0E2FCFEFEFEFE",
INIT_65 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEFEFEBA32AA559E9E9E9E",
INIT_66 => X"E0E0E0E0E0E0E0FAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_67 => X"FEFEFEFEFEDC22EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E77EECCDEEE",
INIT_68 => X"FEFEFEBA76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFE",
INIT_69 => X"9E9E9E9E9E9E9E9E1102DEF6E6E0E0E0E0E2EAFCFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6A => X"FEFEFEFEFEBA00EEFEFEFEFEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22DCFEFAE2E0E0E0EEFEFE",
INIT_6D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2244CCFEFEFEFEFEFEFEFEDC2211",
INIT_6E => X"BB33A8AACCF4F4F4F4FAFEFEFEFEFEFEFEFEFEFEFEFEFEFE328888CC54FEFEFE",
INIT_6F => X"4254BAFEFEFEFEFEBA5464319E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_70 => X"FEFEFEFE32444454FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2200",
INIT_71 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9EAA886856DEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_72 => X"FEFEFEFEFEFEFEFEFEBA2262E600F0FEFEFEFEFEEE00E6959E9E9E9E9E9E9E9E",
INIT_73 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_74 => X"CE55B7DD9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E4410FE",
INIT_75 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2262E600EEFEFEFEFECC",
INIT_76 => X"9E9E9E9E9E9E9E9E9E4422AA8854FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_77 => X"FEDC22820800EEFEFEDC5466559E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_78 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_79 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E558822004432FEFEFEFEFEFE",
INIT_7A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEDC02E68C00EEFEFE10229E9E9E9E9E9E9E9E9E",
INIT_7B => X"44DCEE00BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7C => X"CCEE779E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E11",
INIT_7D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE54AA8A86A63098DC",
INIT_7E => X"9E9E9E9E9E9E9E9E9E9EEEEE76FEEE22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7F => X"FEFEFEFECC002E6600DEFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FF1F4000000BCFFFFFFFFFF0F40000001CFFFFFFFFFF2740000001CFFFFFFFFF",
INITP_01 => X"FFFBF4000000FCFFFFFFFFFF3F00000003CFFFFFFFFFF3F40000003CFFFFFFFF",
INITP_02 => X"FFFFCF0000000FCFFFFFFFFFFCE4000000FCFFFFFFFFFFCC0000000FCFFFFFFF",
INITP_03 => X"FFFFFF74000000FCFFFFFFFFFFFF4000000FCFFFFFFFFFFCF4000000FCFFFFFF",
INITP_04 => X"FFFFFFE6400000138FFFFFFFFFFE70000000FCFFFFFFFFFFE74000000FCFFFFF",
INITP_05 => X"FFFFFFFE400000003AFFFFFFFFFFE4000000042FFFFFFFFFFE48000000B8FFFF",
INITP_06 => X"FFFFFFFFC2000000000FFFFFFFFFFE1000000000FFFFFFFFFFE4000000000FFF",
INITP_07 => X"FFFFFFFFC80000000000FFFFFFFFFC40000000000FFFFFFFFFFA0000000000FF",
INITP_08 => X"1FFFFFFFFFC00000000009FFFFFFFFF900000000017FFFFFFFFF00000000002F",
INITP_09 => X"0FF800200FFF80000000027FC0FC01FFF20000000003FFE00FFFFE0000000000",
INITP_0A => X"0000000000200000000000180200003C00C000000003FF0000043FFE00000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_01 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0010FEFECC22DCFEFEFE",
INIT_02 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECE00ACC402BCFEBA22119E9E9E9E9E9E",
INIT_03 => X"9E9E2210FEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_04 => X"54FEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_05 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE0082EA",
INIT_06 => X"9E9E9E9E9E9E9E9E9E9E9E9E55CC3298FEFECC22DCFEFEFEFEFEFEFEFEFEFEFE",
INIT_07 => X"FEFEFEFEFEFEFEFEEE004454FEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22FEFEFEFECC22",
INIT_0A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC00BAFEFEFEFEBA22119E9E",
INIT_0B => X"9E9E9E9EEE22DCFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_0C => X"AA00FEFEFEFEFEDC22EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_0E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE1054FEFEFEFECC22DCFEFEFEFEFEFEFE",
INIT_0F => X"FEFEFEFEFEFEFEFEFEFEFEFE106676DCFEFEDC7688559E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"FEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_11 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0010FEFEFE",
INIT_12 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA22EEFEFEF044",
INIT_13 => X"9E9E9E9E9E9E9E2210FEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_14 => X"FEFEFEFEFEDC00A48C8C04A0CC779E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_15 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_16 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC22DCFEFEFE",
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA02604020402020EE9E9E9E9E9E9E",
INIT_18 => X"10FEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_19 => X"4020400020119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E22",
INIT_1A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA0260",
INIT_1B => X"9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFE",
INIT_1C => X"FEFEFEFEFEFEFEFEFEFE32284040400020119E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1D => X"DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC22",
INIT_1F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE90E020400020119E9E",
INIT_20 => X"9E9E9E2210FEFEFEFEFECC00BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_21 => X"FEFEFEEE0000600020119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_22 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_23 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC00BAFEFEFEFEFEFEFE",
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFECE0000602020EE9E9E9E9E9E9E9E9E9E9E",
INIT_25 => X"FEEE4422DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_26 => X"64339E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E55EEEEFEFE",
INIT_27 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE000040E0",
INIT_28 => X"9E9E9E9E9E9E9E9E334476BA76662244DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_29 => X"FEFEFEFEFEFEFEEE0020A042BB9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E994422449E1122DCFEFEFE",
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE0020A0449E9E9E9E9E9E9E9E",
INIT_2D => X"9E9E3311559E1122DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2E => X"0020A0229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE",
INIT_30 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22DCFEFEFEFEFEFEFEFEFEFEFE",
INIT_31 => X"FEFEFEFEFEFEFEFEFEFEFEEE0020A0229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_32 => X"DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_33 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22",
INIT_34 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10660080C8339E9E9E9E",
INIT_35 => X"9E9E9E9E9E9E9E9E9E9EEE22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_36 => X"DC7644444444559E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_37 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_38 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22DCFEFEFEFEFEFEFE",
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFEFE1044999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3A => X"9E9EEE22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE54CCCCEE559E9E9E9E9E9E",
INIT_3D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE44FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3E => X"FE102222109E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_40 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E116698DCFEFE",
INIT_41 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEDCDCEE669E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_42 => X"9E9E9E9E9E9E9E994432FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_43 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_44 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE98EECC99",
INIT_45 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E55EEEEDCFEFEFEFEFEFEFEFE",
INIT_46 => X"FEFEFEFEFEFEFEFEFEFE66EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_47 => X"9EEE66DCFEFEFEFEFEFEFEFEFEFEFEBABABABABABABABADCFEFEFEFEFEFEFEFE",
INIT_48 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_49 => X"22222266FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDCEE669E9E9E9E9E9E9E",
INIT_4A => X"9E9E9E9E9E9E9E9E9E9E9E9E66EEDCFEFEFEFEFEFEFEFEFEFEFEDC6622222222",
INIT_4B => X"FEFEFE98CCEE999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4C => X"FE10EEEEEEEECCEE1111111111116600CCEEEEEEEEEEEE98FEFEFEFEFEFEFEFE",
INIT_4D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E99CCCC98FEFEFEFEFEFE",
INIT_4E => X"442200CCBABAFEFEFEFEFEFEFEFEFEFEFE66EE9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4F => X"9E9EEE66FEFEFEFEFEFEFEDC980022444444669E9E9E9E9E9E9E334444444444",
INIT_50 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_51 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E990000222232FEFEFEFEFEFEFEFEFEFEFE1066",
INIT_52 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E6610FEFEFEFEFEFEFEFE322200CC9E9E9E9E9E",
INIT_53 => X"EEEEEEEEEEEEEEEE101088229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_54 => X"EEEEEE6622EE999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E33111111EEEE",
INIT_55 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00881010EEEEEE",
INIT_56 => X"9E9E9E9E9E9E9E9E9E9E11000000000000000000000000449E9E9E9E9E9E9E9E",
INIT_57 => X"9E9E9E9E9E2200000000000000000000449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_58 => X"000000000000000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end win_blk_mem_gen_prim_width;
architecture STRUCTURE of win_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.win_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized4\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end win_blk_mem_gen_generic_cstr;
architecture STRUCTURE of win_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.win_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena_array(1) => ena_array(3),
ena_array(0) => ena_array(0)
);
\has_mux_a.A\: entity work.win_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[3].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[3].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[3].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[3].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[3].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[3].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[3].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[3].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[2].ram.r_n_8\,
DOADO(7) => \ramloop[5].ram.r_n_0\,
DOADO(6) => \ramloop[5].ram.r_n_1\,
DOADO(5) => \ramloop[5].ram.r_n_2\,
DOADO(4) => \ramloop[5].ram.r_n_3\,
DOADO(3) => \ramloop[5].ram.r_n_4\,
DOADO(2) => \ramloop[5].ram.r_n_5\,
DOADO(1) => \ramloop[5].ram.r_n_6\,
DOADO(0) => \ramloop[5].ram.r_n_7\,
DOPADOP(0) => \ramloop[5].ram.r_n_8\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(11 downto 3)
);
\ramloop[0].ram.r\: entity work.win_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[2].ram.r_n_0\,
\douta[10]\(6) => \ramloop[2].ram.r_n_1\,
\douta[10]\(5) => \ramloop[2].ram.r_n_2\,
\douta[10]\(4) => \ramloop[2].ram.r_n_3\,
\douta[10]\(3) => \ramloop[2].ram.r_n_4\,
\douta[10]\(2) => \ramloop[2].ram.r_n_5\,
\douta[10]\(1) => \ramloop[2].ram.r_n_6\,
\douta[10]\(0) => \ramloop[2].ram.r_n_7\,
\douta[11]\(0) => \ramloop[2].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[3].ram.r_n_0\,
\douta[10]\(6) => \ramloop[3].ram.r_n_1\,
\douta[10]\(5) => \ramloop[3].ram.r_n_2\,
\douta[10]\(4) => \ramloop[3].ram.r_n_3\,
\douta[10]\(3) => \ramloop[3].ram.r_n_4\,
\douta[10]\(2) => \ramloop[3].ram.r_n_5\,
\douta[10]\(1) => \ramloop[3].ram.r_n_6\,
\douta[10]\(0) => \ramloop[3].ram.r_n_7\,
\douta[11]\(0) => \ramloop[3].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[4].ram.r_n_0\,
\douta[10]\(6) => \ramloop[4].ram.r_n_1\,
\douta[10]\(5) => \ramloop[4].ram.r_n_2\,
\douta[10]\(4) => \ramloop[4].ram.r_n_3\,
\douta[10]\(3) => \ramloop[4].ram.r_n_4\,
\douta[10]\(2) => \ramloop[4].ram.r_n_5\,
\douta[10]\(1) => \ramloop[4].ram.r_n_6\,
\douta[10]\(0) => \ramloop[4].ram.r_n_7\,
\douta[11]\(0) => \ramloop[4].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized4\
port map (
DOADO(7) => \ramloop[5].ram.r_n_0\,
DOADO(6) => \ramloop[5].ram.r_n_1\,
DOADO(5) => \ramloop[5].ram.r_n_2\,
DOADO(4) => \ramloop[5].ram.r_n_3\,
DOADO(3) => \ramloop[5].ram.r_n_4\,
DOADO(2) => \ramloop[5].ram.r_n_5\,
DOADO(1) => \ramloop[5].ram.r_n_6\,
DOADO(0) => \ramloop[5].ram.r_n_7\,
DOPADOP(0) => \ramloop[5].ram.r_n_8\,
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
ena_array(0) => ena_array(3),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_top : entity is "blk_mem_gen_top";
end win_blk_mem_gen_top;
architecture STRUCTURE of win_blk_mem_gen_top is
begin
\valid.cstr\: entity work.win_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end win_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of win_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.win_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of win_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of win_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of win_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of win_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of win_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of win_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of win_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.227751 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of win_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of win_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of win_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of win_blk_mem_gen_v8_3_5 : entity is "win.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of win_blk_mem_gen_v8_3_5 : entity is "win.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of win_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of win_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of win_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of win_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of win_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of win_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of win_blk_mem_gen_v8_3_5 : entity is "yes";
end win_blk_mem_gen_v8_3_5;
architecture STRUCTURE of win_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.win_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of win : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of win : entity is "win,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of win : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of win : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end win;
architecture STRUCTURE of win is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.227751 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "win.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "win.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 15120;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 15120;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 15120;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 15120;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.win_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 6ec0b49443dd80d096a535814f6ae2e9 | 0.723667 | 2.85563 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_uart.vhd | 1 | 6,941 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 20263ab94d269058bc585a23664984dd | 0.58493 | 3.111161 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_YM2149.vhd | 13 | 18,360 | --
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
-- accurate for designs where the outputs are buffered and not simply wired together.
-- The ouput level is more complex in that case and requires a larger table.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
data_out: out std_logic_vector(17 downto 0) --Digital data out - this should be fed into an audio mixer or Delta-Sigma DAC.
);
end;
architecture RTL of AUDIO_zpuino_wb_YM2149 is
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
-- signal addr : std_logic_vector(7 downto 0);
-- signal busctrl_addr : std_logic;
-- signal busctrl_we : std_logic;
-- signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
signal chan_vol : std_logic_vector(4 downto 0);
signal dac_amp : std_logic_vector(7 downto 0);
signal audio_mix : std_logic_vector(9 downto 0) := (others => '0');
signal audio_final : std_logic_vector(9 downto 0) := (others => '0');
signal O_AUDIO : std_logic_vector(7 downto 0) := (others => '0');
signal I_SEL_L : std_logic;
signal ENA : std_logic;
signal TEST_tone0: std_logic;
signal TEST_tone1: std_logic;
signal TEST_tone2: std_logic;
signal TEST_chan: unsigned(1 downto 0);
signal divclken: std_logic := '0';
signal predivcnt: integer;
constant PRE_CLOCK_DIVIDER: integer := (FREQMHZ/2)-1;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
TEST_chan <= unsigned( cnt_div(1 downto 0) );
TEST_tone0<=tone_gen_op(1);
TEST_tone1<=tone_gen_op(2);
TEST_tone2<=tone_gen_op(3);
-- wishbone signals
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
I_SEL_L <= '1';
ENA <= '1';
data_out <= O_AUDIO & "0000000000";
p_wdata : process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
reg <= (others => (others => '0'));
else
if wb_cyc_i='1' and wb_we_i='1' and wb_stb_i='1' then
reg(conv_integer(wb_adr_i(5 downto 2))) <= wb_dat_i(7 downto 0);
end if;
end if;
-- Envelope reset
env_reset <= '0';
if (wb_we_i = '1' and wb_cyc_i='1' and wb_stb_i='1') and (wb_adr_i(5 downto 2) = x"D") then
env_reset <= '1';
end if;
end if;
end process;
p_rdata : process(wb_adr_i, reg)
begin
wb_dat_o <= (others => '0'); -- 'X'
-- if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case wb_adr_i(5 downto 2) is
when x"0" => wb_dat_o(7 downto 0) <= reg(0) ;
when x"1" => wb_dat_o(7 downto 0) <= "0000" & reg(1)(3 downto 0) ;
when x"2" => wb_dat_o(7 downto 0) <= reg(2) ;
when x"3" => wb_dat_o(7 downto 0) <= "0000" & reg(3)(3 downto 0) ;
when x"4" => wb_dat_o(7 downto 0) <= reg(4) ;
when x"5" => wb_dat_o(7 downto 0) <= "0000" & reg(5)(3 downto 0) ;
when x"6" => wb_dat_o(7 downto 0) <= "000" & reg(6)(4 downto 0) ;
when x"7" => wb_dat_o(7 downto 0) <= reg(7) ;
when x"8" => wb_dat_o(7 downto 0) <= "000" & reg(8)(4 downto 0) ;
when x"9" => wb_dat_o(7 downto 0) <= "000" & reg(9)(4 downto 0) ;
when x"A" => wb_dat_o(7 downto 0) <= "000" & reg(10)(4 downto 0) ;
when x"B" => wb_dat_o(7 downto 0) <= reg(11);
when x"C" => wb_dat_o(7 downto 0) <= reg(12);
when x"D" => wb_dat_o(7 downto 0) <= "0000" & reg(13)(3 downto 0);
when others => null;
end case;
end process;
--
--
-- First divider.
--
predivider: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
divclken <= '0';
predivcnt <= PRE_CLOCK_DIVIDER;
else
divclken<='0';
if predivcnt=0 then
divclken<='1';
predivcnt <= PRE_CLOCK_DIVIDER;
else
predivcnt <= predivcnt -1 ;
end if;
end if;
end if;
end process;
p_divider : process
begin
wait until rising_edge(wb_clk_i);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if divclken='1' then
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(wb_clk_i);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(wb_clk_i);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(wb_clk_i);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, wb_clk_i)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if rising_edge(wb_clk_i) then
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
else
--if divclken='1' then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
begin
tone_ena_l <= '1'; tone_src <= '1';
noise_ena_l <= '1'; chan_vol <= "00000";
case cnt_div(1 downto 0) is
when "00" =>
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
noise_ena_l <= reg(7)(3);
when "01" =>
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
noise_ena_l <= reg(7)(4);
when "10" =>
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
noise_ena_l <= reg(7)(5);
when "11" => null; -- tone gen outputs become valid on this clock
when others => null;
end case;
end process;
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(wb_clk_i);
if (ENA = '1' and divclken='1') then
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
chan_amp := (others => '0');
if (chan_mixed = '1') then
if (chan_vol(4) = '0') then
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
chan_amp := "00000";
else
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
end if;
else
chan_amp := env_vol(4 downto 0);
end if;
end if;
dac_amp <= x"00";
case chan_amp is
when "11111" => dac_amp <= x"FF";
when "11110" => dac_amp <= x"D9";
when "11101" => dac_amp <= x"BA";
when "11100" => dac_amp <= x"9F";
when "11011" => dac_amp <= x"88";
when "11010" => dac_amp <= x"74";
when "11001" => dac_amp <= x"63";
when "11000" => dac_amp <= x"54";
when "10111" => dac_amp <= x"48";
when "10110" => dac_amp <= x"3D";
when "10101" => dac_amp <= x"34";
when "10100" => dac_amp <= x"2C";
when "10011" => dac_amp <= x"25";
when "10010" => dac_amp <= x"1F";
when "10001" => dac_amp <= x"1A";
when "10000" => dac_amp <= x"16";
when "01111" => dac_amp <= x"13";
when "01110" => dac_amp <= x"10";
when "01101" => dac_amp <= x"0D";
when "01100" => dac_amp <= x"0B";
when "01011" => dac_amp <= x"09";
when "01010" => dac_amp <= x"08";
when "01001" => dac_amp <= x"07";
when "01000" => dac_amp <= x"06";
when "00111" => dac_amp <= x"05";
when "00110" => dac_amp <= x"04";
when "00101" => dac_amp <= x"03";
when "00100" => dac_amp <= x"03";
when "00011" => dac_amp <= x"02";
when "00010" => dac_amp <= x"02";
when "00001" => dac_amp <= x"01";
when "00000" => dac_amp <= x"00";
when others => null;
end case;
if (cnt_div(1 downto 0) = "10") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & dac_amp);
end if;
end if;
if (wb_rst_i='1') then
O_AUDIO(7 downto 0) <= "00000000";
else
if divclken='1' then
if (audio_final(9) = '0') then
O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
else -- clip
O_AUDIO(7 downto 0) <= x"FF";
end if;
end if;
end if;
end process;
end architecture RTL;
| mit | 2572b0dfa2e706078f94f85bda279151 | 0.535403 | 3.207547 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/clkgen.vhd | 1 | 6,857 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk_1Mhz_out: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_ulogic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clkin_i_2: std_logic;
-- signal clk_div: std_logic;
-- signal count: integer;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
--process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
process(dcmlocked, clkout_i, rstin)
begin
--if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clk_1Mhz_out
);
clkin_i_1mhz <= clkout_i;
end behave;
| mit | 5d41182551afaf9298a577d112d62b9b | 0.613825 | 3.461383 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to300_pll.vhd | 13 | 5,098 | -- file: clk_32to300_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to300_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to300_pll;
architecture xilinx of clk_32to300_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to300_pll,clk_wiz_v3_6,{component_name=clk_32to300_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 28,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 3,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
| mit | fe472477efbee44c24aaf96a2b8abced | 0.668301 | 3.979703 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/I2C/testbench/tst_bench_top.vhdl | 1 | 15,615 | ------------------------------------------------------------------------------
---- ----
---- I2C Master Testbench ----
---- ----
---- Internal file, can't be downloaded. ----
---- ----
---- Description: ----
---- I2C module test bench. Connects a Wishbone handler and an I2C ----
---- memory to the module. Then it makes some write/read operations. ----
---- The test cases are the same performed by the Verilog test bench by ----
---- Richard Herveille. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti gov ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Covered by the GPL license. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TB(TestBench) (Entity and architecture) ----
---- File name: tst_bench_top.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- c.stdio_h ----
---- wb_handler.WishboneTB ----
---- irq_ctrl.I2C_TB ----
---- irq_ctrl.I2C_Master ----
---- Target FPGA: None ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: None ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: tst_bench_top.vhdl,v $
-- Revision 1.11 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.10 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.9 2005/05/18 14:50:20 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library c;
use c.stdio_h.all;
library wb_handler;
use wb_handler.WishboneTB.all;
library Work;
use Work.I2C_TB.all;
use Work.I2C_Master.all;
entity TB is
end entity TB;
architecture TestBench of TB is
-- Clock=100000 KHz
constant CLKPERIOD : time:=10 us;
signal delay : integer:=5;
signal veces : integer:=0;
signal addr : std_logic_vector(8-1 downto 0);
signal datai : std_logic_vector(8-1 downto 0);
signal datao : std_logic_vector(8-1 downto 0);
signal rd : std_logic:='0';
signal wr : std_logic:='0';
signal rde : std_logic;
signal wre : std_logic;
signal wb_rst : std_logic:='1';
signal wb_clk : std_logic;--:='0';
signal wb_adr : std_logic_vector(8-1 downto 0);
signal adr_o3 : unsigned(2 downto 0);
signal wb_dati : std_logic_vector(8-1 downto 0):=(others => 'Z');
signal wb_dato : std_logic_vector(8-1 downto 0);
signal wb_we : std_logic;
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal wb_ack : std_logic:='0';
signal inta : std_logic;
signal scl_padi : std_logic; -- i2c clock line input
signal scl_pado : std_logic; -- i2c clock line output
signal scl_padoen : std_logic; -- i2c clock line output enable, active low
signal sda_padi : std_logic; -- i2c data line input
signal sda_pado : std_logic; -- i2c data line output
signal sda_padoen : std_logic; -- i2c data line output enable, active low
signal scl : std_logic; -- i2c clock line
signal sda : std_logic; -- i2c data line
signal sdar : std_logic; -- i2c data line
signal sclr : std_logic; -- i2c data line
constant PREV_LO : std_logic_vector(8-1 downto 0):="00000001";
constant PREV_HI : std_logic_vector(8-1 downto 0):="00000000";
constant RD_B : std_logic:='1';
constant WR_B : std_logic:='0';
constant SADR : std_logic_vector(6 downto 0):="0010000";
--Constant FIXED_PRER : integer:=-1;
constant FIXED_PRER : integer:=1;
procedure DelayCk(signal wb_clk_i: in std_logic;
constant TIMES : in integer) is
variable count : integer;
begin
count:=TIMES;
while count>0 loop
wait until rising_edge(wb_clk_i);
count:=count-1;
end loop;
end procedure DelayCk;
procedure CheckTIP(signal addr_o : out std_logic_vector(8-1 downto 0);
signal data_i : in std_logic_vector(8-1 downto 0);
signal rd_o : out std_logic;
signal rde_i : in std_logic;
constant ACKV : in boolean:=true) is
begin
WBRead(addr_o,I2C_SR,rd_o,rde_i);
while data_i(1)='1' loop
WBRead(addr_o,I2C_SR,rd_o,rde_i);
end loop;
if ACKV then
assert data_i(7)='0' report "Expected ACK, received NACK"
severity failure;
else
assert data_i(7)='1' report "Expected NACK, received ACK"
severity failure;
end if;
end procedure CheckTIP;
begin
-- Clock
clock_generator:
process
begin
wb_clk <= '0';
wait for CLKPERIOD/2;
wb_clk <= '1';
wait for CLKPERIOD/2;
veces <= veces+1;
if veces=1500 then
assert false report "Fin de la simulación" severity failure;
end if;
end process clock_generator;
-- Reset pulse
p_reset:
process
begin
wb_rst <= '1';
wait until rising_edge(wb_clk);
wb_rst <= '0' after 500 ns;
wait;
end process p_reset;
-- Wishbone master simulator
wb_master: WBHandler
port map(
addr_i => addr, data_i => datai, data_o => datao,
rd_i => rd, wr_i => wr, rde_o => rde, wre_o => wre,
wb_rst_i => wb_rst, wb_clk_i => wb_clk, wb_ack_i => wb_ack,
wb_adr_o => wb_adr, wb_dat_i => wb_dati, wb_dat_o => wb_dato,
wb_we_o => wb_we, wb_stb_o => wb_stb, wb_cyc_o => wb_cyc);
-- I2C module (Wishbone slave, I2C master)
adr_o3 <= unsigned(wb_adr(2 downto 0));
wb_i2c: I2C_MasterTop
generic map(DEBUG => false,
FULL_SYNC => false,
FIXED_PRER => FIXED_PRER)
port map(-- Wishbone signals
wb_clk_i => wb_clk, wb_rst_i => wb_rst, wb_adr_i => adr_o3,
wb_dat_i => wb_dato, wb_dat_o => wb_dati, wb_we_i => wb_we,
wb_stb_i => wb_stb, wb_cyc_i => wb_cyc, wb_ack_o => wb_ack,
wb_inta_o => inta,
-- i2c lines
scl_pad_i => scl_padi, scl_pad_o => scl_pado, scl_padoen_o => scl_padoen,
sda_pad_i => sda_padi, sda_pad_o => sda_pado, sda_padoen_o => sda_padoen);
-- SCL/SDA pads
scl <= 'Z' when scl_padoen='1' else scl_pado;-- after 600 ns;
scl_padi <= sclr;
scl <= 'H'; -- Pull-up
sda <= 'Z' when sda_padoen='1' else sda_pado;-- after 600 ns;
sda_padi <= sdar;
sda <= 'H'; -- Pull-up
-- SCL/SDA values converted to X/0/1/Z
-- The I2C module can't handle 'H'
sdar <= to_x01z(sda);
sclr <= to_x01z(scl);
-- I2C memory (I2C slave)
i2c_mem: I2C_Memory
generic map(
I2C_ADR => SADR, DEBUG => false)
port map(
scl_x_i => scl, sda_x_io => sda, rst_i => wb_rst);
sequence:
process
begin
wait until wb_rst='0';
if FIXED_PRER=-1 then
-- load prescaler lo-byte
DelayCk(wb_clk,1);
WBWrite(addr,I2C_PRER_LO,datai,PREV_LO,wr,wre);
-- load prescaler hi-byte
WBWrite(addr,I2C_PRER_HI,datai,PREV_HI,wr,wre);
assert false report "Programmed registers" severity note;
-- verify
WBRead(addr,I2C_PRER_LO,rd,rde);
if not(datao=PREV_LO) then
printf("Prescaler lo: %s\n",datao);
assert false report "Wrong prescaler lo readback" severity failure;
end if;
WBRead(addr,I2C_PRER_HI,rd,rde);
assert datao=PREV_HI report "Wrong prescaler hi readback" severity failure;
else
assert false report "Using fixed pre-scaler" severity note;
end if;
-- enable core
WBWrite(addr,I2C_CTR,datai,"10000000",wr,wre); -- 0x80
assert false report "Core Enabled" severity note;
-- present slave address, set write-bit
WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20
-- set command (start, write)
WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90
assert false report "Generate Start" severity note;
CheckTIP(addr,datao,rd,rde);
-- send memory address
-- present slave's memory address
WBWrite(addr,I2C_TXR,datai,"00000001",wr,wre); -- 0x01
-- set command (write)
WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10
assert false report "Write slave memory address 01" severity note;
CheckTIP(addr,datao,rd,rde);
-- send memory contents
-- present data
WBWrite(addr,I2C_TXR,datai,"10100101",wr,wre); -- 0xA5
-- set command (write)
WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10
assert false report "Write data 0xA5" severity note;
CheckTIP(addr,datao,rd,rde);
-- send memory contents for next memory address (auto_inc)
-- present data
WBWrite(addr,I2C_TXR,datai,"01011010",wr,wre); -- 0x5A
-- set command (stop, write)
WBWrite(addr,I2C_CR,datai,"01010000",wr,wre); -- 0x50
assert false report "Write next data 0x5A, generate 'stop'" severity note;
CheckTIP(addr,datao,rd,rde);
DelayCk(wb_clk,30);
-- present slave address, set write-bit
WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20
-- set command (start, write)
WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90
assert false report "Generate Start" severity note;
CheckTIP(addr,datao,rd,rde);
-- send memory address
-- present slave's memory address
WBWrite(addr,I2C_TXR,datai,"00000001",wr,wre); -- 0x01
-- set command (write)
WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10
assert false report "Write slave memory address 01" severity note;
CheckTIP(addr,datao,rd,rde);
-- present slave address, set read-bit
WBWrite(addr,I2C_TXR,datai,SADR & RD_B,wr,wre); -- 0x21
-- set command (start, write)
WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90
assert false report "Generate 'Repeated Start' (RD)" severity note;
CheckTIP(addr,datao,rd,rde);
-- read data from slave
-- set command (read, ack_read)
WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20
assert false report "Sending read + ack" severity note;
CheckTIP(addr,datao,rd,rde);
-- check data just received
WBRead(addr,I2C_RXR,rd,rde);
if unsigned(datao)=16#A5# then
assert false report "Received ok" severity note;
else
printf("Wrong value: %s\n",datao);
assert false report "Wrong value received" severity failure;
end if;
-- read data from slave
-- set command (read, ack_read)
WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20
assert false report "Sending read + ack" severity note;
CheckTIP(addr,datao,rd,rde);
-- check data just received
WBRead(addr,I2C_RXR,rd,rde);
if unsigned(datao)=16#5A# then
assert false report "Received ok" severity note;
else
printf("Wrong value: %s\n",datao);
assert false report "Wrong value received" severity failure;
end if;
-- read data from slave
-- set command (read, ack_read)
WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20
assert false report "Sending read + ack" severity note;
CheckTIP(addr,datao,rd,rde);
-- check data just received
WBRead(addr,I2C_RXR,rd,rde);
printf("Received 0x%X from 3rd read address\n",to_integer(unsigned(datao)));
-- read data from slave
-- set command (read, ack_read)
WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20
assert false report "Sending read + ack" severity note;
CheckTIP(addr,datao,rd,rde);
-- check data just received
WBRead(addr,I2C_RXR,rd,rde);
printf("Received 0x%X from 4th read address\n",to_integer(unsigned(datao)));
-- present slave address, set read-bit
WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20
-- set command (start, write)
WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90
assert false report "Generate 'Repeated Start' (RD)" severity note;
CheckTIP(addr,datao,rd,rde);
-- send memory address
-- present slave's memory address
WBWrite(addr,I2C_TXR,datai,"00010000",wr,wre); -- 0x10
-- set command (write)
WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10
assert false report "Write slave memory address 0x10" severity note;
CheckTIP(addr,datao,rd,rde,false);
assert false report "OK, NACK received" severity note;
-- set command (stop)
WBWrite(addr,I2C_CR,datai,"01000000",wr,wre); -- 0x40
assert false report "Sending stop" severity note;
wait;
end process sequence;
end architecture TestBench; -- of entity TB
| mit | 2b6237fd3f7894c9356aac3bd1a6ac04 | 0.498751 | 3.830962 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev8.vhd | 1 | 38,635 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev7 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev7 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2=WPAD2) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
wout <= std_logic_vector(mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))));
elsif (Opcode2 = WPAD2) then
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
elsif (Opcode2 = WPAD2) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
elsif(Opcode3 = WPAD2) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3 = WPAD2) then
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 35a1e67870f263b8077f0233f34ac6db | 0.646823 | 2.912552 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/sid_voice.vhd | 13 | 28,809 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
| mit | d9a14405382239d11356e141be2542ca | 0.643618 | 3.207415 | false | false | false | false |
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