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natsutan/NPU
fpga_implement/npu8/npu8.srcs/sources_1/ip/mul17_16/mul17_16_sim_netlist.vhdl
1
634,578
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 -- Date : Sat Jan 21 14:43:33 2017 -- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS -- Command : write_vhdl -force -mode funcsim -rename_top mul17_16 -prefix -- mul17_16_ mult_17x16_sim_netlist.vhdl -- Design : mult_17x16 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xcku035-fbva676-3-e -- -------------------------------------------------------------------------------- `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA I7rHN/CieA== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5 Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo OP1PSFj5jpodG+LwXm4= `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF /kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3 251QPjQoZCw3A7W9PDc= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4 udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw== `protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7 rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61 /ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2 hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg== `protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50 ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" `protect encoding = (enctype="base64", line_length=76, bytes=256) `protect key_block OY2dawYF9tInyCemgCe6QEMkC/7TSGzSBNJnYt/Gc7EF5dCGsTH9VXcGbZ2mUocKtRfoAWdRBBEm bYfl6x6FbPUhb0/G1cVlVEQ4o/H18n5hF99JS0/fz0SNPWznJYrrCaGAm92JkSpjjAnro65+V/o9 mk6n/sqoLm3jlJlbEtRcocwBHWWmGWSA1JVq5EGq6rgZ6BzVS2QJTj0eNwmYiRwHm5C7pGUUPAmV Cpq+NReEyh8QLXu+MkLA6W5HNoZrOImyXs04lBJpjc65dBJP2XhsznwBdKX+HirxB4dO2zUVJzS/ mu4FWq0hsHmaMPi31gZ3qX43Fiv7fOwrRHPkkw== `protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa" `protect encoding = (enctype="base64", line_length=76, bytes=256) `protect key_block UpoKdwYrRaKo+uHA0pT6HjqBoVhgDYFTAVhYUatjhT0TKw0u0W/htQsFb4x/F/1WX+Ff5ztSA22r fuYQOx7SaKdiNQa9T+Uwe5fBhUbZYFfh9CTRMRLTJvjL94RMxL4C3N6tVm8vbbd6nTmK52jCWosD IiQVEYPWzIuJp8HD8re8/XAXVfmgXt582ne9Xr4rk496z2gymo9OsHuubbQsjX/+yJZ8C5lTeifG X2DJC37xBIY7LSqL/rtS2GvoBrJki3WFq8QHBp+BPdk+CbhPHpZAvvv78vOc1ewwE+YHYbjUx4+N YK2WZvPCcFynjhDUTfoohvkEMFVjoWObkMWOjA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 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K0+VfdiI0ILC/JttxlFYNF6R83jI/L9u1oqSAE40lTnAO1mL4WVS7oQ64DN+i7Nohbn9LaY41brn DW3IFtcKuilgV+7737oIKdoWrVvipuCRhlPVXsSdUbDRuE3ZELh8j9xikoy3Gii4QSn2dcp4Caze uCJ5mr8A3s1WgiP8ki6dYduDQKEkgp7h+IWaGi8LIw+NtWQNSipY0FlFrowpx+xgdOPc4GHxE68H ckn7t04gPj1YKf5DRx6uxILtW9icJFwVUDhw3+mLudBD5hbKCFC14Kn0seQ3rNcQEldTfCm5dS+d wtkzQEuWNMIEu+9jVV2tAOhvyji47OSvW+ri2oRvngnFVci2XTCxEpAlODM3XH8iiETsoIA+e2cT BdMeLccfhCFdEEcdeFm9wCOWJlDuVwxCohjkpp70deiwGrLLyNQ2N5kdUHCRGc1s `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity mul17_16_mult_gen_v12_0_12 is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 16 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); CE : in STD_LOGIC; SCLR : in STD_LOGIC; ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 ); P : out STD_LOGIC_VECTOR ( 24 downto 0 ); PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 ) ); attribute C_A_TYPE : integer; attribute C_A_TYPE of mul17_16_mult_gen_v12_0_12 : entity is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of mul17_16_mult_gen_v12_0_12 : entity is 17; attribute C_B_TYPE : integer; attribute C_B_TYPE of mul17_16_mult_gen_v12_0_12 : entity is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of mul17_16_mult_gen_v12_0_12 : entity is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of mul17_16_mult_gen_v12_0_12 : entity is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of mul17_16_mult_gen_v12_0_12 : entity is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_OPTIMIZE_GOAL : integer; attribute C_OPTIMIZE_GOAL of mul17_16_mult_gen_v12_0_12 : entity is 1; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of mul17_16_mult_gen_v12_0_12 : entity is 32; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of mul17_16_mult_gen_v12_0_12 : entity is 8; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of mul17_16_mult_gen_v12_0_12 : entity is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of mul17_16_mult_gen_v12_0_12 : entity is "kintexu"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of mul17_16_mult_gen_v12_0_12 : entity is "yes"; end mul17_16_mult_gen_v12_0_12; architecture STRUCTURE of mul17_16_mult_gen_v12_0_12 is signal \<const0>\ : STD_LOGIC; signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE of i_mult : label is 1; attribute C_A_WIDTH of i_mult : label is 17; attribute C_B_TYPE of i_mult : label is 1; attribute C_B_VALUE of i_mult : label is "10000001"; attribute C_B_WIDTH of i_mult : label is 16; attribute C_CCM_IMP of i_mult : label is 0; attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0; attribute C_HAS_CE of i_mult : label is 0; attribute C_HAS_SCLR of i_mult : label is 0; attribute C_HAS_ZERO_DETECT of i_mult : label is 0; attribute C_LATENCY of i_mult : label is 4; attribute C_MODEL_TYPE of i_mult : label is 0; attribute C_MULT_TYPE of i_mult : label is 0; attribute C_OUT_HIGH of i_mult : label is 32; attribute C_OUT_LOW of i_mult : label is 8; attribute C_ROUND_OUTPUT of i_mult : label is 0; attribute C_ROUND_PT of i_mult : label is 0; attribute C_VERBOSITY of i_mult : label is 0; attribute C_XDEVICEFAMILY of i_mult : label is "kintexu"; attribute c_optimize_goal of i_mult : label is 1; attribute downgradeipidentifiedwarnings of i_mult : label is "yes"; begin PCASC(47) <= \<const0>\; PCASC(46) <= \<const0>\; PCASC(45) <= \<const0>\; PCASC(44) <= \<const0>\; PCASC(43) <= \<const0>\; PCASC(42) <= \<const0>\; PCASC(41) <= \<const0>\; PCASC(40) <= \<const0>\; PCASC(39) <= \<const0>\; PCASC(38) <= \<const0>\; PCASC(37) <= \<const0>\; PCASC(36) <= \<const0>\; PCASC(35) <= \<const0>\; PCASC(34) <= \<const0>\; PCASC(33) <= \<const0>\; PCASC(32) <= \<const0>\; PCASC(31) <= \<const0>\; PCASC(30) <= \<const0>\; PCASC(29) <= \<const0>\; PCASC(28) <= \<const0>\; PCASC(27) <= \<const0>\; PCASC(26) <= \<const0>\; PCASC(25) <= \<const0>\; PCASC(24) <= \<const0>\; PCASC(23) <= \<const0>\; PCASC(22) <= \<const0>\; PCASC(21) <= \<const0>\; PCASC(20) <= \<const0>\; PCASC(19) <= \<const0>\; PCASC(18) <= \<const0>\; PCASC(17) <= \<const0>\; PCASC(16) <= \<const0>\; PCASC(15) <= \<const0>\; PCASC(14) <= \<const0>\; PCASC(13) <= \<const0>\; PCASC(12) <= \<const0>\; PCASC(11) <= \<const0>\; PCASC(10) <= \<const0>\; PCASC(9) <= \<const0>\; PCASC(8) <= \<const0>\; PCASC(7) <= \<const0>\; PCASC(6) <= \<const0>\; PCASC(5) <= \<const0>\; PCASC(4) <= \<const0>\; PCASC(3) <= \<const0>\; PCASC(2) <= \<const0>\; PCASC(1) <= \<const0>\; PCASC(0) <= \<const0>\; ZERO_DETECT(1) <= \<const0>\; ZERO_DETECT(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_mult: entity work.mul17_16_mult_gen_v12_0_12_viv port map ( A(16 downto 0) => A(16 downto 0), B(15 downto 0) => B(15 downto 0), CE => '0', CLK => CLK, P(24 downto 0) => P(24 downto 0), PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity mul17_16 is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 16 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); P : out STD_LOGIC_VECTOR ( 24 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of mul17_16 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of mul17_16 : entity is "mult_17x16,mult_gen_v12_0_12,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of mul17_16 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of mul17_16 : entity is "mult_gen_v12_0_12,Vivado 2016.4"; end mul17_16; architecture STRUCTURE of mul17_16 is signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE : integer; attribute C_A_TYPE of U0 : label is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of U0 : label is 17; attribute C_B_TYPE : integer; attribute C_B_TYPE of U0 : label is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of U0 : label is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of U0 : label is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of U0 : label is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of U0 : label is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of U0 : label is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of U0 : label is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of U0 : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of U0 : label is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of U0 : label is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of U0 : label is 32; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of U0 : label is 8; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of U0 : label is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of U0 : label is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of U0 : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "kintexu"; attribute c_optimize_goal : integer; attribute c_optimize_goal of U0 : label is 1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.mul17_16_mult_gen_v12_0_12 port map ( A(16 downto 0) => A(16 downto 0), B(15 downto 0) => B(15 downto 0), CE => '1', CLK => CLK, P(24 downto 0) => P(24 downto 0), PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE;
bsd-3-clause
b2751146dd55a7a6a9fcdf93eeeca064
0.950748
1.820581
false
false
false
false
MartinCura/SistDig-TP4
sin_usar/rot_ena_gen.vhd
1
507
library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; entity rot_ena_gen is generic( -- Cada cuántos ciclos rotar; no superar 50 MHz M: NATURAL := 50 * (10**6) -- 50 MHz ); port ( clk: in std_logic; ena: out std_logic := '0' ); end; architecture rot_ena_gen_arq of rot_ena_gen is begin process(clk) variable i : NATURAL; begin if rising_edge(clk) then ena <= '0'; i := i + 1; if i = M then i := 0; ena <= '1'; end if; end if; end process; end;
gpl-3.0
155a6c3a88a422fda911e469688561f0
0.596838
2.432692
false
false
false
false
elionne/easy_bitcoin_wallet
pw_string.vhdl
1
1,017
library IEEE; use ieee.std_logic_1164.all; entity pw_string is port ( push_pop : in std_logic; char : in character; clk : in std_logic; enable: in std_logic; pwd : out string ); end pw_string; architecture arch_pw_string of pw_string is signal zero_addr : std_logic := '0'; begin process(clk) variable addr : positive := 1; begin if falling_edge(clk) and enable = '1' then if push_pop = '1' then if addr < pwd'length then if zero_addr = '0' then zero_addr <= '1'; else addr := addr + 1; end if; pwd(addr) <= char; end if; else pwd(addr) <= nul; if addr > 1 then addr := addr - 1; else -- if addr = 0 then zero_addr <= '0'; end if; end if; end if; end process; end arch_pw_string;
mit
f7d1641fef2f1a284deabdbdb8721ad4
0.448378
3.988235
false
false
false
false
MartinCura/SistDig-TP4
old/Video_RAM/video_ram.vhd
1
2,279
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- La video ram es implementada con la dual port ram, por ende A es la escritura y B lectura. entity video_ram is generic( -- Bits por fila/columna N_bits_row : integer := 10; N_bits_col : integer := 10; -- Numero de filas/columnas N_rows : integer := 480; ---NO SE USAN N_cols : integer := 640 ); port( clock: in std_logic; write_enable : in std_logic; barrido: in std_logic; A_row : in std_logic_vector(N_bits_row-1 downto 0); B_row : in std_logic_vector(N_bits_row-1 downto 0); A_col : in std_logic_vector(N_bits_col-1 downto 0); B_col : in std_logic_vector(N_bits_col-1 downto 0); data_A : in std_logic; data_B : out std_logic ); end entity video_ram; architecture video_ram_arch of video_ram is --Declaracion de componentes a utilizar (se utiliza la dual port ram) component dual_port_ram is generic( data_width : natural := 1; addr_width : natural := 18 ); port( clock: in std_logic; write_enable : in std_logic; barrido : in std_logic; addr_A : in std_logic_vector(addr_width-1 downto 0); addr_B : in std_logic_vector(addr_width-1 downto 0); data_A : in std_logic_vector(data_width-1 downto 0); data_B : out std_logic_vector(data_width-1 downto 0) ); end component; --Senales auxiliares signal address_A :std_logic_vector(N_bits_row+N_bits_col -1 downto 0):= (others => '0'); signal address_B :std_logic_vector(N_bits_row+N_bits_col -1 downto 0):= (others => '0'); begin address_A <= A_row & A_col; --La dirección A es la concantenacion de fila y columna ---CREO Q HAY Q OPTIMIZAR ESTO address_B <= B_row & B_col; --La dirección B es la concantenacion de fila y columna ---mirar gen_dirs.vhd --Instanciación de los componentes a utilizar video_dual_port_ram: dual_port_ram generic map( data_width => 1, addr_width => 5---N_bits_row + N_bits_col ---TESTEO ) port map( clock =>clock, write_enable =>write_enable, barrido => barrido, addr_A =>"00000",---address_A, addr_B =>"00000",---address_B, data_A(0) =>data_A, data_B(0) =>data_B ); end video_ram_arch;
gpl-3.0
bd9ff34934aa6dd61490926b28a9e1ca
0.62522
2.845
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/sim/zybo_zynq_design_rst_ps7_0_100M_0.vhd
2
7,328
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_12; USE proc_sys_reset_v5_0_12.proc_sys_reset; ENTITY zybo_zynq_design_rst_ps7_0_100M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END zybo_zynq_design_rst_ps7_0_100M_0; ARCHITECTURE zybo_zynq_design_rst_ps7_0_100M_0_arch OF zybo_zynq_design_rst_ps7_0_100M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zybo_zynq_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END zybo_zynq_design_rst_ps7_0_100M_0_arch;
mit
5e29c0811db58d0de8b6d9bf21fd235c
0.726255
3.636725
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/moving-avg/saved.vhdl
1
8,360
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- This design implements an FIR Moving Average filter -- which averages L points -- -- y[n] = ( x[n] + x[n-1] + .. + x[n-L-1] ) / L -- = summation( x[n-k], k = 0 to L-1 ) / L -- -- L= Number of points to be averaged or length of filter -- N = L-1 = order of the filter -- -- To design above FIR filer using R adders (resources), -- we modify the difference equation in two ways below: -- -- 1. y[n] = summation( summation( x[ n - r x M - s], s = 0 to M-1 ), r = 0 to R-1 ) / L -- -- where, -- M = L/R = Samples to be processed per resource (adder) -- r = resource id = 0 to R-1 -- s = sample id = 0 to M-1 -- -- This allocates resource id -- 0 with sub-sequence : x[n] x[n-1] ... x[n-M+1] -- 1 with sub-sequence : x[n-M] x[n-M-1] ... x[n-2M+1] -- 2 with sub-sequence : x[n-2M] x[n-2M-1] ... x[n-3M+1] -- ... -- R-1 with sub-sequence : x[n-(R-1)M] x[n-(R-1)M-1] ... x[n-RM+1] = x[n-L+1] -- -- 2. y[n] = summation( summation( x[ n - R x s - r], s = 0 to M-1 ), r = 0 to R-1 ) / L -- -- where, -- M = L/R = Samples to be processed per resource (adder) -- r = resource id = 0 to R-1 -- s = sample id = 0 to M-1 -- -- This allocates rth resource id with subsequence -- m = 0 m = 1 m = M-1 -- r = 0 : x[n-1] x[n-1-R] ... x[n-1-RM+R] -- r = 1 : x[n-2] x[n-2-R] ... x[n-2-RM+R] -- r = 2 : x[n-3] x[n-3-R] ... x[n-3-RM+R] -- .. -- r = R-1 : x[n-R] x[n-R-R] ... x[n-R-RM+R] = x[n-RM]= x[n-L] -- -- While we can implement any of above two equations, -- in our design we implement the second of the above -- two equations entity fir is generic( L : natural := 16; -- L = Filter length or number of points to be averaged L_BW : natural := 4; -- L_BW = Ceil(Log2(L)) R : natural := 4; -- R = Number of resources (adders and multiplexers) R_BW : natural := 2; -- R_BW = Ceil(Log2(R)) M : natural := 4; -- M = L/R = Samples to be processed per resource (adder) M_BW : natural := 2; -- M_BW = Ceil(Log2(M)) = number of select bits for M samples W : natural := 16 ); -- W = Bit width of input and output sample data (signed) port (clk : in std_logic; -- clock reset_n : in std_logic; -- active low asynchronous reset fir_en : in std_logic; -- handshake signal fir_in : in std_logic_vector( W-1 downto 0 ); -- sample inout x[n] fir_out : out std_logic_vector( W-1 downto 0 ); -- sample output y[n] fir_rdy : out std_logic -- handshake signal ); end fir; architecture rtl of fir is type t_reg_x is array ( 0 to L-1 ) of signed( W-1 downto 0 ); signal reg_x : t_reg_x := ( others => ( others => '0' ) ); -- R outputs of R muxes (one mux output per resource) type t_array_mux_out_x is array ( 0 to R-1 ) of signed( W-1 downto 0 ); signal sig_array_mux_out_x : t_array_mux_out_x := ( others => ( others => '0') ); -- Each of the R muxes has M data inputs requiring total of L=MR data inputs --type t_array_mux_in_x is array ( 0 to L-1 ) of signed( W-1 downto 0 ); --signal sig_array_mux_in_x : t_array_mux_in_x := ( others => ( others => '0') ); type t_mux_in is array ( 0 to R-1, 0 to M-1 ) of signed( W-1 downto 0 ); signal sig_array_mux_in_x : t_mux_in := ( others => ( others => ( others => '0') ) ); -- M_BW-bit select signal for each mux where M_BW = Ceil(Log2(M)), M = L/R signal sig_mux_sel_cnt : unsigned( M_BW-1 downto 0 ) := ( others => '0' ); signal sig_mux_sel_cnt_next : unsigned( M_BW-1 downto 0 ) := ( others => '0' ); -- R-1 signed adders to add R mux outputs. -- i.e. 0, 1..., (R-2)th signed adders -- Note that we set bit size of each adder output equal to the -- maximum bit-size required to accumulate addition of R signed -- numbers which is W+R_BW bits where R_BW = Ceil(Log2(R)) type t_array_signed_adders is array ( 0 to R-2 ) of signed( W+R_BW-1 downto 0 ); signal sig_array_signed_adders: t_array_signed_adders := ( others => ( others => '0' ) ); -- (R-1)th signed adder is used to accumulate result of -- R-1 signed adders i.e output of the (R-2)th signed adder signal sig_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' ); -- add/sub of L = MR signed numbers each of W bit-width -- requires total W+L_BW bits where L_BW = Ceil(log2(L)) signal reg_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' ); signal sig_y_out : signed( W+L_BW-1 downto 0 ) := ( others => '0' ); begin -- Generate x[n-1],x[n-2]...x[n-L+1], x[n-L] process ( clk, reset_n ) begin if ( reset_n = '0' ) then for i in 0 to (L-1) loop reg_x(i) <= ( others => '0'); end loop; elsif ( rising_edge(clk) ) then if( fir_en = '1' ) then reg_x(0) <= signed(fir_in); for i in 1 to (L-1) loop reg_x(i) <= reg_x(i-1); end loop; end if; end if; end process; -- Allocate following data lines as inputs to the rth multiplexer: -- j = 0 j = 1 j = M-1 -- i = 0 : x[n-1] x[n-1-R] ... x[n-1-RM+R] -- i = 1 : x[n-2] x[n-2-R] ... x[n-2-RM+R] -- i = 2 : x[n-3] x[n-3-R] ... x[n-3-RM+R] -- .. -- i = R-1 : x[n-R] x[n-R-R] ... x[n-R-RM+R] = x[n-RM]= x[n-L] process( reg_x ) begin for i in 0 to R-1 loop for j in 0 to M-1 loop sig_array_mux_in_x( i, j ) <= reg_x( i + j*R ); end loop; end loop; end process; -- Generate select signal for the muxes using a counter (mod M) process ( clk, reset_n ) begin if ( reset_n = '0' ) then sig_mux_sel_cnt <= to_unsigned( M-1, sig_mux_sel_cnt'LENGTH ); elsif ( rising_edge( clk ) ) then if ( fir_en = '1' ) then sig_mux_sel_cnt <= sig_mux_sel_cnt_next; end if; end if; end process; sig_mux_sel_cnt_next <= ( others => '0' ) when sig_mux_sel_cnt = ( M-1 ) else ( sig_mux_sel_cnt + 1 ); -- Generate the R muxes process ( sig_array_mux_in_x, sig_mux_sel_cnt ) begin for i in 0 to R-1 loop sig_array_mux_out_x( i ) <= sig_array_mux_in_x( i, to_integer( sig_mux_sel_cnt ) ); end loop; end process; -- Generate R-1 signed adders for R muxes. -- i.e. 0, 1..., (R-2)th signed adders -- A[0] = M[0]+M[1] -- A[1] = A[0]+M[2] -- A[2] = A[1]+M[3] -- .... -- A[R-2] = A[R-3]+M[R-1] -- -- Note: The last signed adder to be used for -- accumulation is generated separately comb_adders : process ( sig_array_mux_out_x ) begin sig_array_signed_adders(0) <= resize( sig_array_mux_out_x(0), sig_array_signed_adders(0)'LENGTH ) + resize( sig_array_mux_out_x(1), sig_array_signed_adders(0)'LENGTH ); for i in 1 to R-2 loop sig_array_signed_adders(i)<= resize( sig_array_signed_adders(i-1), sig_array_signed_adders(i)'LENGTH ) + resize( sig_array_mux_out_x(i+1), sig_array_signed_adders(i)'LENGTH ); end loop; end process comb_adders; -- Generate Y[n] i.e. Rth signed adder which accumulates -- result of R-1 signed adders i.e the output of -- (R-1)th signed adder -- A[R-1] = A[R-1] + A[R-2] -- Y[n] = Y[n-1] + A[R-2]; sig_y_sum <= reg_y_sum + resize( sig_array_signed_adders( R-2 ), sig_y_sum'LENGTH ) ; -- Generate Y[n-1] process( clk, reset_n ) begin if ( reset_n = '0' ) then reg_y_sum <= ( others => '0'); elsif ( rising_edge(clk) ) then if( fir_en = '1' ) then reg_y_sum <= sig_y_sum; end if; end if; end process; -- y[n] = Y[n]/L = Y[n] >> L_BW, where L_BW=Ceil(log2(L)) sig_y_out <= sig_y_sum srl L_BW; process ( clk, reset_n ) begin if ( reset_n = '0' ) then fir_out <= ( others => '0' ); elsif ( rising_edge( clk ) ) then if( fir_en = '1' ) then fir_out <= std_logic_vector( sig_y_out( W-1 downto 0 ) ); end if; end if; end process; end rtl;
mit
12e122c4a4e8745847a15cfde4cdfe4b
0.520335
2.593052
false
false
false
false
mrozo/programmable-digital-circuits
rs232monitor/counter.vhd
1
998
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.ALL; entity counter is Generic ( width : integer := 8 ); Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; clear : in STD_LOGIC; state : out STD_LOGIC_VECTOR ((width-1) downto 0) := (others => '0') ); end counter; architecture Behavioral of counter is signal internalState : STD_LOGIC_VECTOR ((width-1) downto 0) := (others => '0'); begin process(rst, clear, clk) begin if(rst='1') then state <= (others => '0'); internalState <= (others => '0'); elsif(rising_edge(clk)) then if(clear='1') then state <= (others => '0'); internalState <= (others => '0'); else state <= internalState; internalState <= std_logic_vector(unsigned(internalState) + 1); end if; end if; end process; end Behavioral;
bsd-3-clause
99a5ffb5748ab49da5115a95a2afcd5f
0.512024
3.589928
false
false
false
false
kuba-moo/VHDL-lib
bus_tail_strip.vhd
1
2,041
-- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- -- Copyright (C) 2014 Jakub Kicinski <[email protected]> library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- Remove last @N_BYTES from data flying through Bus entity bus_tail_strip is generic (N_BYTES : integer); port (Clk : in std_logic; Rst : in std_logic; PktIn : in std_logic; DataIn : in std_logic_vector(7 downto 0); PktOut : out std_logic; DataOut : out std_logic_vector(7 downto 0)); end bus_tail_strip; -- Operation: -- Delay all signals and "and" incoming @PktIn with @PktOut to cut it early. -- NOTE: input is registered which may not be necessary. Remove clocking of -- delay*(0) to stop registering input. architecture Behavioral of bus_tail_strip is type byte_vec is array (0 to N_BYTES) of std_logic_vector(7 downto 0); signal delayByte : byte_vec; signal delayPkt : std_logic_vector(0 to N_BYTES); begin delayByte(0) <= DataIn when rising_edge(Clk); delayPkt(0) <= PktIn when rising_edge(Clk); delay_path : for i in 0 to N_BYTES - 1 generate delayByte(i + 1) <= delayByte(i) when rising_edge(Clk); delayPkt(i + 1) <= delayPkt(i) when rising_edge(Clk); end generate delay_path; DataOut <= delayByte(N_BYTES); PktOut <= delayPkt(0) and delayPkt(N_BYTES); end Behavioral;
gpl-3.0
8ba597561f9c6b18d663a5a6e079397c
0.680549
3.638146
false
false
false
false
MartinCura/SistDig-TP4
src/ext_ram/pos_loader.vhd
1
2,174
-- Loader de posiciones (x,y,z) desde la RAM externa library ieee; use ieee.std_logic_1164.all; entity pos_loader is port ( clock: in std_logic; reset: in std_logic; enable: in std_logic; start: in std_logic; data_in: in std_logic_vector(15 downto 0); go_ram: out std_logic; busy_ram: in std_logic; RxRdy_ram: in std_logic; RxRdy_out: out std_logic; x, y, z: out std_logic_vector(15 downto 0) ); end; architecture pos_loader_arq of pos_loader is -- Para indicar qué coordenada se está cargando type t_estado is (IDLE, X_st, Y_st, Z_st); signal estado : t_estado := IDLE; begin process(clock, reset, start, RxRdy_ram, busy_ram) begin -- reset if reset = '1' then go_ram <= '0'; estado <= IDLE; elsif rising_edge(clock) then RxRdy_out <= '0'; go_ram <= '0'; if enable = '1' then case estado is when IDLE => if start = '1' and busy_ram = '0' then -- pido X go_ram <= '1'; estado <= X_st; end if; when X_st => if RxRdy_ram = '1' then -- Ya X, pido Y x <= data_in; go_ram <= '1'; estado <= Y_st; end if; when Y_st => if RxRdy_ram = '1' then -- Ya Y, pido Z y <= data_in; go_ram <= '1'; estado <= Z_st; end if; when Z_st => if RxRdy_ram = '1' then -- Ya Z, vuelvo a IDLE z <= data_in; RxRdy_out <= '1'; -- Posición lista go_ram <= '1'; estado <= X_st;--- end if; end case; end if; end if; end process; end;
gpl-3.0
edd11c8c1a69d3d11405343fac682c8d
0.386458
4.111742
false
false
false
false
natsutan/NPU
fpga_implement/npu8/npu8.cache/ip/b68c3a7a323700c9/mul17_16_sim_netlist.vhdl
1
632,253
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 -- Date : Sat Jan 21 16:36:06 2017 -- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul17_16_sim_netlist.vhdl -- Design : mul17_16 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. 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library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 16 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); CE : in STD_LOGIC; SCLR : in STD_LOGIC; ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 ); P : out STD_LOGIC_VECTOR ( 16 downto 0 ); PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 ) ); attribute C_A_TYPE : integer; attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 17; attribute C_B_TYPE : integer; attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_OPTIMIZE_GOAL : integer; attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 32; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is signal \<const0>\ : STD_LOGIC; signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE of i_mult : label is 1; attribute C_A_WIDTH of i_mult : label is 17; attribute C_B_TYPE of i_mult : label is 1; attribute C_B_VALUE of i_mult : label is "10000001"; attribute C_B_WIDTH of i_mult : label is 16; attribute C_CCM_IMP of i_mult : label is 0; attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0; attribute C_HAS_CE of i_mult : label is 0; attribute C_HAS_SCLR of i_mult : label is 0; attribute C_HAS_ZERO_DETECT of i_mult : label is 0; attribute C_LATENCY of i_mult : label is 4; attribute C_MODEL_TYPE of i_mult : label is 0; attribute C_MULT_TYPE of i_mult : label is 0; attribute C_OUT_HIGH of i_mult : label is 32; attribute C_OUT_LOW of i_mult : label is 16; attribute C_ROUND_OUTPUT of i_mult : label is 0; attribute C_ROUND_PT of i_mult : label is 0; attribute C_VERBOSITY of i_mult : label is 0; attribute C_XDEVICEFAMILY of i_mult : label is "kintexu"; attribute c_optimize_goal of i_mult : label is 1; attribute downgradeipidentifiedwarnings of i_mult : label is "yes"; begin PCASC(47) <= \<const0>\; PCASC(46) <= \<const0>\; PCASC(45) <= \<const0>\; PCASC(44) <= \<const0>\; PCASC(43) <= \<const0>\; PCASC(42) <= \<const0>\; PCASC(41) <= \<const0>\; PCASC(40) <= \<const0>\; PCASC(39) <= \<const0>\; PCASC(38) <= \<const0>\; PCASC(37) <= \<const0>\; PCASC(36) <= \<const0>\; PCASC(35) <= \<const0>\; PCASC(34) <= \<const0>\; PCASC(33) <= \<const0>\; PCASC(32) <= \<const0>\; PCASC(31) <= \<const0>\; PCASC(30) <= \<const0>\; PCASC(29) <= \<const0>\; PCASC(28) <= \<const0>\; PCASC(27) <= \<const0>\; PCASC(26) <= \<const0>\; PCASC(25) <= \<const0>\; PCASC(24) <= \<const0>\; PCASC(23) <= \<const0>\; PCASC(22) <= \<const0>\; PCASC(21) <= \<const0>\; PCASC(20) <= \<const0>\; PCASC(19) <= \<const0>\; PCASC(18) <= \<const0>\; PCASC(17) <= \<const0>\; PCASC(16) <= \<const0>\; PCASC(15) <= \<const0>\; PCASC(14) <= \<const0>\; PCASC(13) <= \<const0>\; PCASC(12) <= \<const0>\; PCASC(11) <= \<const0>\; PCASC(10) <= \<const0>\; PCASC(9) <= \<const0>\; PCASC(8) <= \<const0>\; PCASC(7) <= \<const0>\; PCASC(6) <= \<const0>\; PCASC(5) <= \<const0>\; PCASC(4) <= \<const0>\; PCASC(3) <= \<const0>\; PCASC(2) <= \<const0>\; PCASC(1) <= \<const0>\; PCASC(0) <= \<const0>\; ZERO_DETECT(1) <= \<const0>\; ZERO_DETECT(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv port map ( A(16 downto 0) => A(16 downto 0), B(15 downto 0) => B(15 downto 0), CE => '0', CLK => CLK, P(16 downto 0) => P(16 downto 0), PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 16 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); P : out STD_LOGIC_VECTOR ( 16 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mul17_16,mult_gen_v12_0_12,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE : integer; attribute C_A_TYPE of U0 : label is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of U0 : label is 17; attribute C_B_TYPE : integer; attribute C_B_TYPE of U0 : label is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of U0 : label is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of U0 : label is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of U0 : label is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of U0 : label is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of U0 : label is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of U0 : label is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of U0 : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of U0 : label is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of U0 : label is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of U0 : label is 32; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of U0 : label is 16; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of U0 : label is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of U0 : label is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of U0 : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "kintexu"; attribute c_optimize_goal : integer; attribute c_optimize_goal of U0 : label is 1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 port map ( A(16 downto 0) => A(16 downto 0), B(15 downto 0) => B(15 downto 0), CE => '1', CLK => CLK, P(16 downto 0) => P(16 downto 0), PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE;
bsd-3-clause
bd063dd1bbbd0e792105bfa87e19489b
0.950336
1.819438
false
false
false
false
drhodes/jade2hdl
test-data/vhdl/AND23-with-clock/AND23.vhdl
1
2,500
library ieee; use ieee.std_logic_1164.all; ENTITY AND2 IS PORT (in1 : IN std_logic; in2 : IN std_logic; out1 : OUT std_logic) ; END ENTITY AND2 ; ARCHITECTURE Behavioral OF AND2 IS BEGIN out1 <= in1 AND in2 ; END ARCHITECTURE Behavioral ; ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity AND23 IS port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; output : out std_logic); end AND23; architecture struct of AND23 is -- each node goes here. signal w1, w2 : std_logic; -- each submodule is wired up here. begin u1 : entity work.AND2 port map (in1 => a, in2 => b, out1 => w1); u2 : entity work.AND2 port map (in1 => c, in2 => d, out1 => w2); u3 : entity work.AND2 port map (in1 => w1, in2 => w2, out1 => output); end struct; ------------------------------------------------------------------ -- This will probably be a combinational test. library STD; use STD.textio.all; -- basic I/O library IEEE; use IEEE.std_logic_1164.all; -- basic logic types use IEEE.std_logic_textio.all; -- I/O for logic types use ieee.numeric_std.all; entity AND23_TB is end AND23_TB; architecture behaviour of AND23_TB is signal clk : std_logic := '0'; signal sigterm : std_logic := '0'; signal counter : unsigned(7 downto 0) := x"00"; signal a, b, c, d, result : std_logic; begin u1 : entity work.AND23 port map (a => a, b => b, c => c, d => d, output => result); process begin --wait for 99 ns; clkloop : loop clk <= not clk; if sigterm = '1' then exit; end if; wait for 50 ns; end loop clkloop; wait; end process; process (clk) begin a <= counter(0); b <= counter(1); c <= counter(2); d <= counter(3); if rising_edge(clk) then -- report "counter is: " & to_hstring(counter); -- report "counter is: " & integer'image(to_integer(unsigned(counter))); -- to get decimal report "inputs: (a, b, c, d) = " & " (" & to_string(a) & ", " & to_string(b) & ", " & to_string(c) & ", " & to_string(d) & ") " & to_string(result) & " counter: " & integer'image(to_integer(unsigned(counter))); if counter = x"F" then sigterm <= '1'; end if; counter <= counter + 1; end if; end process; end behaviour;
bsd-3-clause
b09579da66344120a5424c3c77ab785c
0.5352
3.355705
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd/gcd.cache/ip/2018.2/0141074d64e361c1/gcd_block_design_processing_system7_0_0_sim_netlist.vhdl
1
206,350
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 15:49:39 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_0_sim_netlist.vhdl -- Design : gcd_block_design_processing_system7_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "gcd_block_design_processing_system7_0_0.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_block_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "gcd_block_design_processing_system7_0_0.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW"; attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"; attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => IRQ_F2P(0), IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;
mit
83bda871ebb66d406202f705683341e8
0.639777
2.766976
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/aluseq/top.vhdl
1
6,692
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top is generic( W : natural := 4); -- Width of data port (clk : in std_logic; rst : in std_logic; -- active high sync to clock i_data_a : in std_logic_vector(W-1 downto 0); -- input data A i_data_b : in std_logic_vector(W-1 downto 0); -- input data B i_data_carry : in std_logic; -- carry in or borrow in i_ctrl : in std_logic_vector(3 downto 0); -- control signals o_data_c : out std_logic_vector(W-1 downto 0); -- output data C o_data_carry : out std_logic; -- carry out or borrow out o_data_comp : out std_logic_vector(1 downto 0); -- output comparison o_valid : out std_logic -- valid output ); end top; architecture rtl of top is -- 1: FETCH signal reg_i_instr_1 : std_logic_vector( i_ctrl'RANGE ) := ( others => '0' ); signal reg_i_data_a_1 : std_logic_vector( i_data_a'RANGE ) := ( others => '0' ); signal reg_i_data_b_1 : std_logic_vector( i_data_b'RANGE ) := ( others => '0' ); signal reg_i_data_carry_1 : std_logic := '0'; -- 2: DECODE signal reg_i_instr_2 : std_logic_vector( i_ctrl'RANGE ) := ( others => '0' ); signal reg_i_data_a_2 : std_logic_vector( i_data_a'RANGE ) := ( others => '0' ); signal reg_i_data_b_2 : std_logic_vector( i_data_b'RANGE ) := ( others => '0' ); signal reg_i_data_carry_2 : std_logic := '0'; -- 3: Execute signal reg_i_instr_3 : std_logic_vector( i_ctrl'RANGE ) := ( others => '0' ); signal reg_i_data_a_3 : std_logic_vector( i_data_a'RANGE ) := ( others => '0' ); signal reg_i_data_b_3 : std_logic_vector( i_data_b'RANGE ) := ( others => '0' ); signal reg_i_data_carry_3 : std_logic := '0'; -- Output signals of ALU signal sig_data_c : std_logic_vector( o_data_c'RANGE ) := ( others=> '0' ); signal sig_data_carry : std_logic := '0'; signal sig_data_comp : std_logic_vector( o_data_comp'RANGE ) := ( others=> '0' ); signal sig_valid : std_logic := '0'; signal reg_valid : std_logic := '0'; -- Declare component ALU component alu is generic( W : natural := 4 ); port (i_data_a : in std_logic_vector(W-1 downto 0); -- input data A i_data_b : in std_logic_vector(W-1 downto 0); -- input data B i_data_carry : in std_logic; -- carry in or borrow in i_ctrl : in std_logic_vector(3 downto 0); -- control signals o_data_c : out std_logic_vector(W-1 downto 0); -- output data C o_data_carry : out std_logic; -- carry out or borrow out o_data_comp : out std_logic_vector(1 downto 0) -- output comparison ); end component alu; begin -- Instruction pipeline (1: FETCH, 2: DECODE, 3: EXECUTE) mem_instr: process(clk) begin if rising_edge(clk) then if( rst = '1' ) then -- 1: FETCH reg_i_instr_1 <= ( others => '0' ); -- NOP -- 2: DECODE reg_i_instr_2 <= ( others => '0' ); -- NOP -- 2: DECODE reg_i_instr_3 <= ( others => '0' ); -- NOP else -- 1: FETCH reg_i_instr_1 <= i_ctrl; -- 2: DECODE reg_i_instr_2 <= reg_i_instr_1; -- 3: Execute reg_i_instr_3 <= reg_i_instr_2; end if; end if; end process mem_instr; -- Operand pipeline (1: FETCH, 2: DECODE, 3: EXECUTE) mem_operands: process(clk) begin if rising_edge(clk) then if( rst = '1' ) then -- 1: FETCH reg_i_data_a_1 <= ( others => '0' ); reg_i_data_b_1 <= ( others => '0' ); reg_i_data_carry_1 <= '0'; -- 2: DECODE reg_i_data_a_2 <= ( others => '0' ); reg_i_data_b_2 <= ( others => '0' ); reg_i_data_carry_2 <= '0'; -- 2: Execute reg_i_data_a_3 <= ( others => '0' ); reg_i_data_b_3 <= ( others => '0' ); reg_i_data_carry_3 <= '0'; else -- 1: FETCH reg_i_data_a_1 <= i_data_a; reg_i_data_b_1 <= i_data_b; reg_i_data_carry_1 <= i_data_carry; -- 2: DECODE reg_i_data_a_2 <= reg_i_data_a_1; reg_i_data_b_2 <= reg_i_data_b_1; reg_i_data_carry_2 <= reg_i_data_carry_1; -- 2: EXECUTE reg_i_data_a_3 <= reg_i_data_a_2; reg_i_data_b_3 <= reg_i_data_b_2; reg_i_data_carry_3 <= reg_i_data_carry_2; end if; end if; end process mem_operands; -- 2: DECODE -- Check if fetched instruction is a valid instruction sig_valid <= '1' when reg_i_instr_2 = "0001" OR reg_i_instr_2 = "0010" OR reg_i_instr_2 = "0011" OR reg_i_instr_2 = "0100" OR reg_i_instr_2 = "0101" OR reg_i_instr_2 = "0110" OR reg_i_instr_2 = "0111" else '0'; -- 2: DECODE mem_valid: process(clk) begin if rising_edge(clk) then if( rst = '1') then reg_valid <= '0'; else reg_valid <= sig_valid; end if; end if; end process mem_valid; -- 2: DECODE o_valid <= reg_valid; -- 3: EXECUTE alu_inst: alu generic map( W => W ) port map( i_data_a => reg_i_data_a_3, i_data_b => reg_i_data_b_3, i_data_carry => reg_i_data_carry_3, i_ctrl => reg_i_instr_3, o_data_c => sig_data_c, o_data_carry => sig_data_carry, o_data_comp => sig_data_comp ); -- 3: EXECUTE mem_outputs: process(clk) begin if rising_edge(clk) then if( rst = '1') then o_data_c <= ( others => '0' ); o_data_carry <= '0'; o_data_comp <= ( others => '0' ); else if( reg_valid = '1' ) then o_data_c <= sig_data_c; o_data_carry <= sig_data_carry; o_data_comp <= sig_data_comp; else o_data_c <= ( others => '0' ); o_data_carry <= '0'; o_data_comp <= ( others => '0' ); end if; end if; end if; end process mem_outputs; end rtl;
mit
e4b0986817e79f3c4f9ac275ce8efc68
0.465631
3.198853
false
false
false
false
MartinCura/SistDig-TP4
old/testers/tester_ram_interna.vhd
1
3,454
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.cordic_lib.all; library floatfixlib; use floatfixlib.float_pkg.all; entity tester_ram_interna is generic( N_BITS_COORD : integer := 32 --- REVISAR ); port( clk_i: in std_logic; -- Clock general rst_i: in std_logic := '0'; -- Botón de reset pos_leida: out t_pos; ena_o: out std_logic := '0'; ram_int_refresh: out std_logic := '0' ); attribute loc: string; attribute loc of clk_i: signal is "B8"; end; architecture tester_ram_interna_arq of tester_ram_interna is signal RxRdy: std_logic := '0'; -- Dato listo para leerse signal Dout_uart: std_logic_vector(15 downto 0) := (others => '0'); signal Dout_memint: t_pos_mem := (others => (others => '0')); signal pos_leida_aux: t_pos := (others => CERO); type memo_t is array(0 to 39) of std_logic_vector(15 downto 0); constant testmemo : memo_t := ( "0000000000000000", "0000000000000100", "0000000000001100", "0000000001100000", "0000000000000010", "0000000000000001", "1000001100000000", "1000000000010000", "0100000000010000", "1111111111111111", "1111111111111110", "1111101111101111", "0000000000000010", "1000000000000011", "0000000000000011", "0000000001100000", "0000000000000010", "0000000000000001", "1000001100000000", "1000000000010000", "0100000000010000", "1111111111111111", "1111111111111110", "1111111111111110", "1111101111101111", "0000000000000010", "1000000000000011", "0000000000000011", "0000000001100000", "0000000000000010", "0100000000010000", "1111111111111111", "1111111111111110", "1111101111101111", "0000000000000010", "1000000000000011", "0000000000000011", "0000000001100000", "0000000000000001", "0000000000000010" ); begin process(clk_i) variable i : natural := 0; variable j : natural := 0; variable n : natural := 0; begin if rising_edge(clk_i) then i := i + 1; if i > 32 then i := 0; Dout_uart <= testmemo(j); RxRdy <= '1'; j := j + 1; if j >= testmemo'length then j := 0; end if; end if; --- else RxRdy <= '0'; if n < 150 then report "pos_leida 1 " & integer'image(to_integer(signed(pos_leida_aux(1))))-- & " ena_o " & ena_o severity note; report "pos_leida 2 " & integer'image(to_integer(signed(pos_leida_aux(2))))-- & " ena_o " & ena_o severity note; report "pos_leida 3 " & integer'image(to_integer(signed(pos_leida_aux(3))))-- & " ena_o " & ena_o severity note; n := n + 1; end if; end if; end process; --- Se guarda un dato de lectura listo en memoria [interna]. Continuamente se leen y guardan en vector pos_leida ram_int: entity work.ram_interna generic map( N_BITS => N_BITS_COORD---, ---CANT_P => 50---0 ) port map( clk => clk_i, rst => rst_i, Rx => RxRdy, Din => Dout_uart, Dout => Dout_memint, Rdy => ena_o, barrido => ram_int_refresh ); ---pos_leida_aux(i) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_leida_aux(i)),N_BITS_COORD)); pos_leida_aux(1) <= to_float(Dout_memint(1)); pos_leida_aux(2) <= to_float(Dout_memint(2)); pos_leida_aux(3) <= to_float(Dout_memint(3)); pos_leida <= pos_leida_aux; end;
gpl-3.0
4349a06740a78e6c881bd006cd4c273c
0.607877
3.00784
false
false
false
false
besm6/micro-besm
tests/2910/vhdl/funct_block_alg_beh/components/mux/test_vectors_mux.vhdl
1
4,973
-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Feb 19, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD -- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD -------------------------------------------------------------------------------- --library ZYCAD; use work.types.all; use work.MVL7_functions.all; use work.synthesis_types.all; entity E is end; architecture AA of E is component cmux port ( R_sel : in MVL7; D_sel : in MVL7; uPC_sel : in MVL7; stack_sel : in MVL7; OEBAR : in MVL7; sp : in INTEGER range 0 to 5; D : in MVL7_VECTOR(11 downto 0); RE : in MVL7_VECTOR(11 downto 0); uPC : in MVL7_VECTOR(11 downto 0); Y : out MVL7_VECTOR(11 downto 0) ); end component; signal R_sel : MVL7; signal D_sel : MVL7; signal uPC_sel : MVL7; signal stack_sel : MVL7; signal OEBAR : MVL7; signal sp : INTEGER range 0 to 5; signal D : MVL7_VECTOR(11 downto 0); signal RE : MVL7_VECTOR(11 downto 0); signal uPC : MVL7_VECTOR(11 downto 0); signal Y : MVL7_VECTOR(11 downto 0); for all : cmux use entity work.multiplexer(multiplexer); begin CMUX1 : cmux port map( R_sel, D_sel, uPC_sel, stack_sel, OEBAR, sp, D, RE, uPC, Y ); process begin --------------------- R_sel <= '1'; D_sel <= '0'; uPC_sel <= '0'; stack_sel <= '0'; OEBAR <= '0'; sp <= 2; RE <= "000000000000"; D <= "111111111111"; uPC <= "111111111111"; wait for 1 ns; assert (Y = "000000000000") report "Assert 0 : < Y /= 000000000000 >" severity warning; wait for 1 ns; --------------------- R_sel <= '1'; D_sel <= '0'; uPC_sel <= '0'; stack_sel <= '0'; OEBAR <= '0'; sp <= 1; RE <= "111111111111"; D <= "000000000000"; uPC <= "000000000000"; wait for 1 ns; assert (Y = "111111111111") report "Assert 1 : < Y /= 111111111111 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '1'; uPC_sel <= '0'; stack_sel <= '0'; OEBAR <= '0'; sp <= 2; RE <= "111111111111"; D <= "000000000000"; uPC <= "111111111111"; wait for 1 ns; assert (Y = "000000000000") report "Assert 2 : < Y /= 000000000000 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '1'; uPC_sel <= '0'; stack_sel <= '0'; OEBAR <= '0'; sp <= 1; RE <= "000000000000"; D <= "111111111111"; uPC <= "000000000000"; wait for 1 ns; assert (Y = "111111111111") report "Assert 3 : < Y /= 111111111111 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '0'; uPC_sel <= '1'; stack_sel <= '0'; OEBAR <= '0'; sp <= 2; RE <= "111111111111"; D <= "111111111111"; uPC <= "000000000000"; wait for 1 ns; assert (Y = "000000000000") report "Assert 4 : < Y /= 000000000000 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '0'; uPC_sel <= '1'; stack_sel <= '0'; OEBAR <= '0'; sp <= 1; RE <= "000000000000"; D <= "000000000000"; uPC <= "111111111111"; wait for 1 ns; assert (Y = "111111111111") report "Assert 5 : < Y /= 111111111111 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '0'; uPC_sel <= '1'; stack_sel <= '0'; OEBAR <= '0'; sp <= 1; RE <= "111111111111"; D <= "111111111111"; uPC <= "000000000000"; wait for 1 ns; assert (Y = "000000000000") report "Assert 6 : < Y /= 000000000000 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '0'; uPC_sel <= '1'; stack_sel <= '0'; OEBAR <= '0'; sp <= 2; RE <= "000000000000"; D <= "000000000000"; uPC <= "111111111111"; wait for 1 ns; assert (Y = "111111111111") report "Assert 7 : < Y /= 111111111111 >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '1'; uPC_sel <= '0'; stack_sel <= '0'; OEBAR <= '1'; sp <= 2; RE <= "111111111111"; D <= "000000000000"; uPC <= "111111111111"; wait for 1 ns; assert (Y = "ZZZZZZZZZZZZ") report "Assert 8 : < Y /= ZZZZZZZZZZZZ >" severity warning; wait for 1 ns; --------------------- R_sel <= '0'; D_sel <= '1'; uPC_sel <= '0'; stack_sel <= '0'; OEBAR <= '1'; sp <= 1; RE <= "000000000000"; D <= "111111111111"; uPC <= "000000000000"; wait for 1 ns; assert (Y = "ZZZZZZZZZZZZ") report "Assert 9 : < Y /= ZZZZZZZZZZZZ >" severity warning; wait for 1 ns; --------------------- end process; end AA;
mit
36833d14a591abc80159cb28702fec81
0.506937
2.937389
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd/gcd.cache/ip/2018.2/e50e3d2e678dd930/gcd_block_design_auto_pc_0_sim_netlist.vhdl
1
517,973
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 15:50:55 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_auto_pc_0_sim_netlist.vhdl -- Design : gcd_block_design_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[5]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113"; begin Q(0) <= \^q\(0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0); \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => \axaddr_incr[0]_i_1_n_0\ ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => \axaddr_incr[10]_i_1_n_0\ ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \next\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => \axaddr_incr[11]_i_2_n_0\ ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => \axaddr_incr[1]_i_1_n_0\ ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => \axaddr_incr[2]_i_1_n_0\ ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => \axaddr_incr[3]_i_1_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0102" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"262A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"060A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), I3 => \next\, O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => \axaddr_incr[4]_i_1_n_0\ ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => \axaddr_incr[5]_i_1_n_0\ ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => \axaddr_incr[6]_i_1_n_0\ ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => \axaddr_incr[7]_i_1_n_0\ ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => \axaddr_incr[8]_i_1_n_0\ ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => \axaddr_incr[9]_i_1_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[0]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[10]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[11]_i_2_n_0\, Q => \^axaddr_incr_reg[11]_0\(10), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[1]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[2]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[3]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[4]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[5]_i_1_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[6]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[7]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[8]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[9]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \^q\(0), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[2]_0\, I4 => E(0), I5 => \m_payload_i_reg[46]\(9), O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), I5 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \^q\(0), I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \state_reg[1]\(0), Q => \^q\(0), R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(7), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => \m_payload_i_reg[46]\(7), I3 => \m_payload_i_reg[46]\(4), O => \m_axi_awaddr[5]\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[2]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; \m_axi_araddr[5]\ : out STD_LOGIC; \m_axi_araddr[3]\ : out STD_LOGIC; \m_axi_araddr[2]\ : out STD_LOGIC; \m_axi_araddr[1]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC; signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0201020202020202" ) port map ( I0 => Q(0), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[1]\, I1 => Q(6), I2 => Q(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => Q(3), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A262A2A2A2A2A2A" ) port map ( I0 => Q(2), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A060A0A0A0A0A0A" ) port map ( I0 => Q(1), I1 => Q(5), I2 => Q(6), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[1]\, R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1) => \axaddr_incr_reg_n_0_[1]\, DI(0) => \^axaddr_incr_reg[11]_0\(0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(1) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(8), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(9), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[0]_0\, I4 => E(0), I5 => Q(10), O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => \next_pending_r_i_4__0_n_0\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => Q(7), O => \m_axi_araddr[11]\ ); \m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[1]\, I2 => Q(7), I3 => Q(1), O => \m_axi_araddr[1]\ ); \m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => Q(7), I3 => Q(2), O => \m_axi_araddr[2]\ ); \m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => Q(7), I3 => Q(3), O => \m_axi_araddr[3]\ ); \m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => Q(7), I3 => Q(4), O => \m_axi_araddr[5]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__0_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[47]_0\, O => \^incr_next_pending\ ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \next_pending_r_i_4__0_n_0\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, O => \next_pending_r_i_2__0_n_0\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \next_pending_r_i_4__0_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_i : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[7]_0\ : in STD_LOGIC; s_axburst_eq1_reg : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4"; begin Q(1 downto 0) <= \^q\(1 downto 0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AAEA" ) port map ( I0 => sel_first, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(0), I2 => \^m_payload_i_reg[0]_0\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"00CA" ) port map ( I0 => si_rs_arvalid, I1 => m_axi_arready, I2 => \^q\(0), I3 => \^q\(1), O => E(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00005140" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => m_axi_arready, I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[7]_0\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => si_rs_arvalid, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => m_axi_arready, O => r_push_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8FFF8F8F" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => s_ready_i0 ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFFFFCCCECCCE" ) port map ( I0 => si_rs_arvalid, I1 => areset_d1, I2 => \^m_payload_i_reg[0]\, I3 => \^m_payload_i_reg[0]_0\, I4 => m_axi_arready, I5 => sel_first_reg_2, O => sel_first_i ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"003030303E3E3E3E" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(1), I2 => \^q\(0), I3 => m_axi_arready, I4 => s_axburst_eq1_reg, I5 => \cnt_read_reg[2]_rep__0\, O => \next_state__0\(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00AAB000" ) port map ( I0 => \cnt_read_reg[2]_rep__0\, I1 => s_axburst_eq1_reg, I2 => m_axi_arready, I3 => \^m_payload_i_reg[0]_0\, I4 => \^m_payload_i_reg[0]\, O => \next_state__0\(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \wrap_boundary_axaddr_r_reg[11]\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; si_rs_bready : in STD_LOGIC; bvalid_i_reg_0 : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"EEFEFFFFFFFFEEFE" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \bresp_cnt_reg[7]\(6), I2 => \bresp_cnt_reg[7]\(0), I3 => \memory_reg[3][0]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF6FFFF" ) port map ( I0 => \bresp_cnt_reg[7]\(1), I1 => \memory_reg[3][1]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(4), I3 => \bresp_cnt_reg[7]\(5), I4 => mhandshake_r, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000D00DD00DD00D" ) port map ( I0 => \memory_reg[3][0]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(0), I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \^cnt_read_reg[1]_rep__0_0\, I5 => \^cnt_read_reg[0]_rep__0_0\, O => \bresp_cnt[7]_i_5_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bready, I3 => bvalid_i_reg_0, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => shandshake_r, I3 => Q(1), I4 => Q(0), I5 => bvalid_i_reg_0, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => shandshake_r, I2 => Q(0), O => D(0) ); \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000041004141" ) port map ( I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\, I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, I5 => \memory_reg[3][0]_srl4_i_3_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFFFFFFFFFB" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(5), I3 => \bresp_cnt_reg[7]\(4), I4 => \memory_reg[3][1]_srl4_n_0\, I5 => \bresp_cnt_reg[7]\(1), O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); mhandshake : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A69A" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => shandshake_r, I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(0), I3 => \^q\(1), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal wr_en0 : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19"; begin \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; \cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => s_ready_i_reg, I3 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9AAAA6A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAA6AA9AAAAAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"99AA99AA99AA55A6" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_1\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_2\, I3 => \cnt_read[4]_i_3__0_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_2\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read[4]_i_5_n_0\, I3 => \cnt_read_reg[4]_rep__0_0\, I4 => si_rs_rready, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6000E000FFFFFFFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, I5 => m_axi_rvalid, O => \cnt_read[4]_i_5_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__3_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_1\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"9FFF1FFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA0AAA0AAAAAAA" ) port map ( I0 => m_axi_rvalid, I1 => \cnt_read_reg[0]_rep__3_n_0\, I2 => \^cnt_read_reg[4]_rep__2_0\, I3 => \^cnt_read_reg[4]_rep__2_1\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[2]_rep__2_n_0\, O => wr_en0 ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"40C0C000" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[2]_rep__2_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); s_ready_i_reg : in STD_LOGIC; r_push_r : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"DB24" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7F0080FEFF0100" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9A999AAA" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA2AAA2AAA" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => r_push_r, I4 => \^m_valid_i_reg\, I5 => si_rs_rready, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => r_push_r, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => \cnt_read_reg[0]_rep__1_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"80808080FF808080" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read_reg[3]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2\, I5 => \cnt_read_reg[0]_rep__3\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__1_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"BFEEAAAAAAAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__3_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => \cnt_read_reg[1]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[4]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \axlen_cnt_reg[7]_1\ : out STD_LOGIC; \next\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axburst_eq0_reg : out STD_LOGIC; incr_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[7]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wrap_next_pending : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[7]\ : STD_LOGIC; signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \^next\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \state[0]_i_1_n_0\ : STD_LOGIC; signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\; \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; \next\ <= \^next\; sel_first_i <= \^sel_first_i\; \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(2), I2 => \^axlen_cnt_reg[7]_0\, I3 => si_rs_awvalid, I4 => \^axlen_cnt_reg[7]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0400FFFF04000400" ) port map ( I0 => \^q\(1), I1 => si_rs_awvalid, I2 => \^q\(0), I3 => \m_payload_i_reg[46]\(1), I4 => \axlen_cnt_reg[0]_0\(0), I5 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[0]\(0) ); \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^next\, O => \axaddr_wrap_reg[11]\(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF04" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]\, I3 => \^next\, I4 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[7]_1\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"88008888A800A8A8" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, I2 => m_axi_awready, I3 => \cnt_read_reg[0]_rep__0\, I4 => \cnt_read_reg[1]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF404" ) port map ( I0 => \^e\(0), I1 => next_pending_r_reg, I2 => \^next\, I3 => \axlen_cnt_reg[7]_2\, I4 => \m_payload_i_reg[47]\, O => \^incr_next_pending\ ); next_pending_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F3F3FFFF51000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \^next\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => \^incr_next_pending\, I1 => \^sel_first_i\, I2 => \m_payload_i_reg[46]\(0), I3 => wrap_next_pending, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => \^incr_next_pending\, I1 => \m_payload_i_reg[46]\(0), I2 => \^sel_first_i\, I3 => wrap_next_pending, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first_0, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF04FFFFFF04FF04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, I3 => areset_d1, I4 => \^next\, I5 => sel_first_reg_1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => \state[0]_i_2_n_0\, I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), O => \state[0]_i_1_n_0\ ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00F000F055750000" ) port map ( I0 => m_axi_awready, I1 => s_axburst_eq1_reg_0, I2 => \cnt_read_reg[1]_rep__0\, I3 => \cnt_read_reg[0]_rep__0\, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \state[0]_i_2_n_0\ ); \state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0C0CAE0000000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]\, I5 => \^axlen_cnt_reg[7]_0\, O => \state[1]_i_1__0_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^axlen_cnt_reg[7]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^axlen_cnt_reg[7]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is port ( wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \next\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); sel_first_reg_3 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin sel_first_reg_0 <= \^sel_first_reg_0\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(0), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(0), I3 => \next\, I4 => \m_payload_i_reg[47]\(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(10), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(10), I3 => \next\, I4 => \m_payload_i_reg[47]\(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(11), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(11), I3 => \next\, I4 => \m_payload_i_reg[47]\(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4_n_0\, I1 => wrap_cnt_r(3), I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(1), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(1), I3 => \next\, I4 => \m_payload_i_reg[47]\(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(2), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(2), I3 => \next\, I4 => \m_payload_i_reg[47]\(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(3), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(3), I3 => \next\, I4 => \m_payload_i_reg[47]\(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[47]\(13), I2 => \m_payload_i_reg[47]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(4), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(4), I3 => \next\, I4 => \m_payload_i_reg[47]\(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(5), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(5), I3 => \next\, I4 => \m_payload_i_reg[47]\(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(6), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(6), I3 => \next\, I4 => \m_payload_i_reg[47]\(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(7), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(7), I3 => \next\, I4 => \m_payload_i_reg[47]\(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(8), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(8), I3 => \next\, I4 => \m_payload_i_reg[47]\(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(9), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(9), I3 => \next\, I4 => \m_payload_i_reg[47]\(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => \m_payload_i_reg[47]\(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => \m_payload_i_reg[47]\(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => \m_payload_i_reg[47]\(17), O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => \m_payload_i_reg[47]\(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(2), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(3), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[47]\(5), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(5), I3 => \m_payload_i_reg[47]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(9) ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]_0\, I1 => next_pending_r_reg_n_0, I2 => \next\, I3 => \next_pending_r_i_2__1_n_0\, I4 => E(0), O => \^wrap_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_awvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^wrap_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => wrap_cnt(1) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cnt(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is port ( sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); sel_first_i : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; sel_first_reg_5 : in STD_LOGIC; sel_first_reg_6 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4__0_n_0\, I1 => \wrap_cnt_r_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => Q(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => Q(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => Q(17), O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => Q(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(1), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[1]\, I3 => Q(14), I4 => sel_first_reg_6, O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(2), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[2]\, I3 => Q(14), I4 => sel_first_reg_5, O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(3), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[3]\, I3 => Q(14), I4 => sel_first_reg_4, O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(5), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[5]\, I3 => Q(14), I4 => sel_first_reg_3, O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(9) ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => \next_pending_r_i_2__2_n_0\, I4 => E(0), O => wrap_next_pending ); \next_pending_r_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_arvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__2_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_n_0, R => '0' ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq1_reg ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1__0_n_0\ ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1__0_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[0]\ : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2__0_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2__0_n_0\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2__0_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_0\(0) ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2__0_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_0\(1) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^axaddr_offset_r_reg[3]\, R => \^m_valid_i_reg_0\ ); next_pending_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r_reg[3]\(0) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => \wrap_cnt_r_reg[3]\(1) ); \wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_1\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2__0_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5__0_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5__0_n_0\ ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset_0\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_0\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3__0_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(1), O => \^axaddr_offset\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2_n_0\ ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(2), O => \^axaddr_offset\(1) ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => D(1) ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5_n_0\ ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2_n_0\ ); \wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[4]_rep__0\, O => \cnt_read_reg[2]_rep__0\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \cnt_read_reg[4]_rep__0\, I3 => \^skid_buffer_reg[0]_0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \cnt_read_reg[4]_rep__0\, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_5, bvalid_i_reg_0 => \^si_rs_bvalid\, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(1), I1 => \bresp_cnt_reg__0\(0), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_6_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_6_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_6_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_5, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACEAAAA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[0]\, I1 => m_axi_bresp(0), I2 => m_axi_bresp(1), I3 => \s_bresp_acc_reg_n_0_[1]\, I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EC" ) port map ( I0 => m_axi_bresp(1), I1 => \s_bresp_acc_reg_n_0_[1]\, I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^si_rs_bvalid\, I1 => si_rs_bready, O => shandshake ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \m_payload_i_reg[47]_1\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_16 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd port map ( E(0) => E(0), Q(0) => Q(0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14, \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_15, \m_axi_awaddr[5]\ => incr_cmd_0_n_16, \m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17), \m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12), \m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \next\ => \next\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(0) => \state_reg[1]_0\(0) ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[47]\(15), I2 => s_axburst_eq0, O => \state_reg[1]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), aclk => aclk, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15), \m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_15, sel_first_reg_3 => incr_cmd_0_n_16, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is port ( sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; signal wrap_cmd_0_n_6 : STD_LOGIC; signal wrap_cmd_0_n_7 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17"; begin incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(10 downto 8) => Q(18 downto 16), Q(7 downto 5) => Q(14 downto 12), Q(4) => Q(5), Q(3 downto 0) => Q(3 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_11, \m_axi_araddr[1]\ => incr_cmd_0_n_15, \m_axi_araddr[2]\ => incr_cmd_0_n_14, \m_axi_araddr[3]\ => incr_cmd_0_n_13, \m_axi_araddr[5]\ => incr_cmd_0_n_12, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]_0\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_6, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_7, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(18 downto 14) => Q(19 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), s_axburst_eq0_reg => wrap_cmd_0_n_6, s_axburst_eq1_reg => wrap_cmd_0_n_7, sel_first_i => sel_first_i, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_11, sel_first_reg_3 => incr_cmd_0_n_12, sel_first_reg_4 => incr_cmd_0_n_13, sel_first_reg_5 => incr_cmd_0_n_14, sel_first_reg_6 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_1 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_4 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \state_reg[1]_rep_0\, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1, \cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_4 ); transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2, \cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]_0\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_2\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \wrap_second_len_r_reg[1]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_4\ : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \state_reg[1]_rep_2\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice is signal \ar.ar_pipe_n_2\ : STD_LOGIC; signal \aw.aw_pipe_n_1\ : STD_LOGIC; signal \aw.aw_pipe_n_90\ : STD_LOGIC; begin \ar.ar_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset_0(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\, \axaddr_offset_r_reg[3]\ => si_rs_arvalid, \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \ar.ar_pipe_n_2\, m_valid_i_reg_1(0) => m_valid_i_reg(0), next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_ready_i0 => s_ready_i0, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_2\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\, \wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0) ); \aw.aw_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 port map ( D(1 downto 0) => D(1 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\, \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \aw.aw_pipe_n_1\, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_0\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \b.b_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \r.r_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), \cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\, r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); r_rlast : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_10 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal ar_cmd_fsm_0_n_8 : STD_LOGIC; signal ar_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_10 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_3 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push_r_reg\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm port map ( D(0) => ar_cmd_fsm_0_n_6, E(0) => ar_cmd_fsm_0_n_8, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[46]\(0) => Q(18), \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, m_valid_i0 => m_valid_i0, r_push_r_reg => \^r_push_r_reg\, s_axburst_eq1_reg => cmd_translator_0_n_10, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => s_ready_i0, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_9, sel_first_reg_0 => ar_cmd_fsm_0_n_10, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => cmd_translator_0_n_0, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(19 downto 0) => Q(19 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]\ => cmd_translator_0_n_3, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_8, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_0, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => ar_cmd_fsm_0_n_10, sel_first_reg_3 => ar_cmd_fsm_0_n_9, sel_first_reg_4(0) => ar_cmd_fsm_0_n_16, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_10, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\ => ar_cmd_fsm_0_n_0, \state_reg[1]_rep\ => \^r_push_r_reg\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0), \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); si_rs_awvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel is signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_14 : STD_LOGIC; signal aw_cmd_fsm_0_n_15 : STD_LOGIC; signal aw_cmd_fsm_0_n_16 : STD_LOGIC; signal aw_cmd_fsm_0_n_2 : STD_LOGIC; signal aw_cmd_fsm_0_n_8 : STD_LOGIC; signal aw_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_12 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \next\ : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm port map ( D(0) => wrap_cnt(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14, \axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8, \axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\, \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\, \axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2, \axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[46]\(2) => Q(18), \m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, s_axburst_eq0_reg => aw_cmd_fsm_0_n_9, s_axburst_eq1_reg => aw_cmd_fsm_0_n_12, s_axburst_eq1_reg_0 => cmd_translator_0_n_12, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_15, sel_first_reg_0 => aw_cmd_fsm_0_n_16, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(0) => cmd_translator_0_n_5, S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12, \m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_16, sel_first_reg_2 => aw_cmd_fsm_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_14, \state_reg[0]_rep\ => aw_cmd_fsm_0_n_2, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8, \state_reg[1]_rep\ => cmd_translator_0_n_12, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0), \wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awready : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_10\ : STD_LOGIC; signal \RD.ar_channel_0_n_11\ : STD_LOGIC; signal \RD.ar_channel_0_n_16\ : STD_LOGIC; signal \RD.ar_channel_0_n_3\ : STD_LOGIC; signal \RD.ar_channel_0_n_4\ : STD_LOGIC; signal \RD.ar_channel_0_n_46\ : STD_LOGIC; signal \RD.ar_channel_0_n_47\ : STD_LOGIC; signal \RD.ar_channel_0_n_48\ : STD_LOGIC; signal \RD.ar_channel_0_n_49\ : STD_LOGIC; signal \RD.ar_channel_0_n_5\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_132 : STD_LOGIC; signal SI_REG_n_133 : STD_LOGIC; signal SI_REG_n_134 : STD_LOGIC; signal SI_REG_n_135 : STD_LOGIC; signal SI_REG_n_136 : STD_LOGIC; signal SI_REG_n_137 : STD_LOGIC; signal SI_REG_n_138 : STD_LOGIC; signal SI_REG_n_139 : STD_LOGIC; signal SI_REG_n_140 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_149 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_155 : STD_LOGIC; signal SI_REG_n_156 : STD_LOGIC; signal SI_REG_n_157 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_181 : STD_LOGIC; signal SI_REG_n_182 : STD_LOGIC; signal SI_REG_n_26 : STD_LOGIC; signal SI_REG_n_64 : STD_LOGIC; signal SI_REG_n_8 : STD_LOGIC; signal SI_REG_n_82 : STD_LOGIC; signal \WR.aw_channel_0_n_0\ : STD_LOGIC; signal \WR.aw_channel_0_n_10\ : STD_LOGIC; signal \WR.aw_channel_0_n_15\ : STD_LOGIC; signal \WR.aw_channel_0_n_3\ : STD_LOGIC; signal \WR.aw_channel_0_n_4\ : STD_LOGIC; signal \WR.aw_channel_0_n_47\ : STD_LOGIC; signal \WR.aw_channel_0_n_48\ : STD_LOGIC; signal \WR.aw_channel_0_n_49\ : STD_LOGIC; signal \WR.aw_channel_0_n_50\ : STD_LOGIC; signal \WR.aw_channel_0_n_9\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw.aw_pipe/p_1_in\ : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel port map ( D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), E(0) => \ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(31 downto 20) => s_arid(11 downto 0), Q(19 downto 16) => si_rs_arlen(3 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_82, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_46\, S(2) => \RD.ar_channel_0_n_47\, S(1) => \RD.ar_channel_0_n_48\, S(0) => \RD.ar_channel_0_n_49\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_161, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_165, \cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\, \m_payload_i_reg[3]\(3) => SI_REG_n_132, \m_payload_i_reg[3]\(2) => SI_REG_n_133, \m_payload_i_reg[3]\(1) => SI_REG_n_134, \m_payload_i_reg[3]\(0) => SI_REG_n_135, \m_payload_i_reg[47]\ => SI_REG_n_64, \m_payload_i_reg[47]_0\ => SI_REG_n_167, \m_payload_i_reg[5]\ => SI_REG_n_166, \m_payload_i_reg[6]\(6) => SI_REG_n_176, \m_payload_i_reg[6]\(5) => SI_REG_n_177, \m_payload_i_reg[6]\(4) => SI_REG_n_178, \m_payload_i_reg[6]\(3) => SI_REG_n_179, \m_payload_i_reg[6]\(2) => SI_REG_n_180, \m_payload_i_reg[6]\(1) => SI_REG_n_181, \m_payload_i_reg[6]\(0) => SI_REG_n_182, \m_payload_i_reg[7]\(3) => SI_REG_n_136, \m_payload_i_reg[7]\(2) => SI_REG_n_137, \m_payload_i_reg[7]\(1) => SI_REG_n_138, \m_payload_i_reg[7]\(0) => SI_REG_n_139, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push_r_reg => \RD.ar_channel_0_n_3\, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => \ar.ar_pipe/s_ready_i0\, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\, \wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\, \wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0), \wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157 ); \RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_168, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\ ); SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_26, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_132, \axaddr_incr_reg[3]\(2) => SI_REG_n_133, \axaddr_incr_reg[3]\(1) => SI_REG_n_134, \axaddr_incr_reg[3]\(0) => SI_REG_n_135, \axaddr_incr_reg[7]\(3) => SI_REG_n_136, \axaddr_incr_reg[7]\(2) => SI_REG_n_137, \axaddr_incr_reg[7]\(1) => SI_REG_n_138, \axaddr_incr_reg[7]\(0) => SI_REG_n_139, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\ => SI_REG_n_154, \axaddr_offset_r_reg[2]_0\ => SI_REG_n_166, \axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\, \axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\, \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\, \axlen_cnt_reg[3]\ => SI_REG_n_8, \axlen_cnt_reg[3]_0\ => SI_REG_n_64, b_push => b_push, \cnt_read_reg[2]_rep__0\ => SI_REG_n_168, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\, \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\, next_pending_r_reg => SI_REG_n_155, next_pending_r_reg_0 => SI_REG_n_167, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0), \s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_82, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), s_ready_i0 => \ar.ar_pipe/s_ready_i0\, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \WR.aw_channel_0_n_4\, \state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_0\, \state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182, \wrap_cnt_r_reg[2]\ => SI_REG_n_149, \wrap_cnt_r_reg[2]_0\ => SI_REG_n_161, \wrap_cnt_r_reg[3]\ => SI_REG_n_153, \wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157, \wrap_cnt_r_reg[3]_1\ => SI_REG_n_165, \wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\, \wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\, \wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0) ); \WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, Q(31 downto 20) => s_awid(11 downto 0), Q(19 downto 16) => si_rs_awlen(3 downto 0), Q(15) => si_rs_awburst(1), Q(14) => SI_REG_n_26, Q(13 downto 12) => si_rs_awsize(1 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_149, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_153, \axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\, \axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[47]\ => SI_REG_n_8, \m_payload_i_reg[47]_0\ => SI_REG_n_155, \m_payload_i_reg[5]\ => SI_REG_n_154, \m_payload_i_reg[6]\(6) => SI_REG_n_169, \m_payload_i_reg[6]\(5) => SI_REG_n_170, \m_payload_i_reg[6]\(4) => SI_REG_n_171, \m_payload_i_reg[6]\(3) => SI_REG_n_172, \m_payload_i_reg[6]\(2) => SI_REG_n_173, \m_payload_i_reg[6]\(1) => SI_REG_n_174, \m_payload_i_reg[6]\(0) => SI_REG_n_175, si_rs_awvalid => si_rs_awvalid, \state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\, \wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1) ); \WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0) ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_block_design_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
mit
872b3972ed5047c5371806e561fe81c0
0.536412
2.550762
false
false
false
false
Feuerwerk/fpgaNES
biquad.vhd
1
6,919
/* This file is part of fpgaNES. fpgaNES is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. fpgaNES is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with fpgaNES. If not, see <http://www.gnu.org/licenses/>. from https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use */ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------- -- -- b0 + b1*Z^-1 + b2*Z^-2 -- H[z] = ------------------------- -- 1 + a1*Z^-1 + a2*Z^-2 -- ------------------------------------------------------------------------- entity biquad is generic ( B0 : std_logic_vector(31 downto 0) := B"01_10_0011_0001_0111_0110_0101_0111_0111"; -- b0 ~ +1.548303 B1 : std_logic_vector(31 downto 0) := B"01_10_0011_0001_0111_0110_0101_0111_0111"; -- b1 ~ +1.548303 B2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b2 0.0 A1 : std_logic_vector(31 downto 0) := B"00_10_0011_0001_0111_0110_0101_0111_0111"; -- a1 ~ +0.548303 A2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000" -- a2 0.0 ); port ( i_clk : in std_logic; i_reset_n : in std_logic := '1'; i_sample_trig : in std_logic; i_x : in std_logic_vector(17 downto 0); o_filter_done : out std_logic; o_q : out std_logic_vector(17 downto 0) ); end biquad; architecture behavioral of biquad is -- define each pre gain sample flip flop signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(17 downto 0) := (others => '0'); -- define each post gain 32 but truncated sample signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(17 downto 0) := (others => '0'); -- define output double reg signal Y_out_double : std_logic_vector(17 downto 0) := (others => '0'); -- state machine signals type state_type is (idle, run); signal state_reg : state_type := idle; signal state_next : state_type; -- counter signals signal q_reg : unsigned(2 downto 0) := (others => '0'); signal q_next : unsigned(2 downto 0); signal q_reset, q_add : std_logic; -- data path flags signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic; begin -- process to shift samples process (i_clk) begin if rising_edge(i_clk) then if i_reset_n = '0' then ZFF_X0 <= (others => '0'); ZFF_X1 <= (others => '0'); ZFF_X2 <= (others => '0'); ZFF_Y1 <= (others => '0'); ZFF_Y2 <= (others => '0'); elsif i_sample_trig = '1' then ZFF_X0 <= i_x(17) & i_x(17 downto 1); ZFF_X1 <= ZFF_X0; ZFF_X2 <= ZFF_X1; ZFF_Y1 <= Y_out_double; ZFF_Y2 <= ZFF_Y1; end if; end if; end process; -- STATE UPDATE AND TIMING process (i_clk) begin if rising_edge(i_clk) then if i_reset_n = '0' then state_reg <= idle; q_reg <= (others => '0'); -- reset counter else state_reg <= state_next; -- update the state q_reg <= q_next; end if; end if; end process; -- COUNTER FOR TIMING q_next <= (others => '0') when q_reset = '1' else -- resets the counter q_reg + 1 when q_add = '1' else -- increment count if commanded q_reg; -- process for control of data path flags process (q_reg, state_reg, i_sample_trig) begin -- defaults q_reset <= '0'; q_add <= '0'; mul_coefs <= '0'; trunc_prods <= '0'; sum_stg_a <= '0'; trunc_out <= '0'; o_filter_done <= '0'; case state_reg is when idle => if i_sample_trig = '1' then state_next <= run; else state_next <= idle; end if; when run => if q_reg < "001" then q_add <= '1'; state_next <= run; elsif q_reg < "011" then mul_coefs <= '1'; q_add <= '1'; state_next <= run; elsif q_reg < "100" then trunc_prods <= '1'; q_add <= '1'; state_next <= run; elsif q_reg < "101" then sum_stg_a <= '1'; q_add <= '1'; state_next <= run; elsif q_reg < "110" then trunc_out <= '1'; q_add <= '1'; state_next <= run; else q_reset <= '1'; o_filter_done <= '1'; state_next <= idle; end if; end case; end process; -- truncate the output to summation block process (i_clk) variable pgZFF_X0_quad : std_logic_vector(49 downto 0) := (others => '0'); variable pgZFF_X1_quad : std_logic_vector(49 downto 0) := (others => '0'); variable pgZFF_X2_quad : std_logic_vector(49 downto 0) := (others => '0'); variable pgZFF_Y1_quad : std_logic_vector(49 downto 0) := (others => '0'); variable pgZFF_Y2_quad : std_logic_vector(49 downto 0) := (others => '0'); begin if rising_edge(i_clk) then if i_reset_n = '0' then pgZFF_X0_quad := (others => '0'); pgZFF_X1_quad := (others => '0'); pgZFF_X2_quad := (others => '0'); pgZFF_Y1_quad := (others => '0'); pgZFF_Y2_quad := (others => '0'); else if mul_coefs = '1' then -- add gain factors to numerator of biquad (feed forward path) pgZFF_X0_quad := std_logic_vector(signed(B0) * signed(ZFF_X0)); pgZFF_X1_quad := std_logic_vector(signed(B1) * signed(ZFF_X1)); pgZFF_X2_quad := std_logic_vector(signed(B2) * signed(ZFF_X2)); -- add gain factors to denominator of biquad (feed back path) pgZFF_Y1_quad := std_logic_vector(signed(A1) * signed(ZFF_Y1)); pgZFF_Y2_quad := std_logic_vector(signed(A2) * signed(ZFF_Y2)); end if; if trunc_prods = '1' then pgZFF_X0 <= pgZFF_X0_quad(47 downto 30); pgZFF_X2 <= pgZFF_X2_quad(47 downto 30); pgZFF_X1 <= pgZFF_X1_quad(47 downto 30); pgZFF_Y1 <= pgZFF_Y1_quad(47 downto 30); pgZFF_Y2 <= pgZFF_Y2_quad(47 downto 30); end if; end if; end if; end process; -- sum all post gain feedback and feedfoward paths -- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2 process (i_clk) begin if rising_edge(i_clk) then if sum_stg_a = '1' then Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); end if; end if; end process; -- output truncation block process (i_clk) begin if rising_edge(i_clk) then if trunc_out = '1' then o_q <= Y_out_double(17 downto 0); end if; end if; end process; end behavioral;
gpl-3.0
0b32685068d453566ea7a2183136ce08
0.575372
2.791045
false
false
false
false
elionne/easy_bitcoin_wallet
vowels.vhdl
1
1,438
library IEEE; use ieee.std_logic_1164.all; entity vowels is port ( length_in : in natural; length_out : out natural; enable : in std_logic; reset : in std_logic; load_index : in natural; current_index: out natural; clk : in std_logic; char : out character := 'a'; finished : out std_logic := '1' ); end vowels; architecture arch_vowels of vowels is type vowel_list is array (0 to 4) of character; subtype vowel_index is integer range 0 to 4; signal vowels : vowel_list := ('a','e', 'i', 'o', 'u'); signal current_vowel : character := 'a'; begin process(clk) variable index : vowel_index := 0; begin if rising_edge(clk) then if reset = '1' then index := load_index; current_vowel <= vowels(index); finished <= '0'; end if; if enable = '1' and reset = '0' then if current_vowel = vowels(vowels'right) then finished <= '1'; else finished <= '0'; current_vowel <= vowels(index); current_index <= index; if index < vowel_index'high then length_out <= length_in + 1; index := index + 1; end if; end if; end if; end if; end process; char <= current_vowel; end arch_vowels;
mit
b79d9935e5ba278df2c1e90bcb52f684
0.508345
3.640506
false
false
false
false
besm6/micro-besm
tests/2910/vhdl/funct_block_alg_beh/components/upc/MVL7_functions.vhd
5
12,874
--*************************************************************************** -- VHDL BIT_VECTOR Operations for MVL7 type -- -- Copyright (c) 1990 UCI CADLAB, Dept. of ICS -- Author : Sanjiv Narayan ([email protected]) -- -- Updated 7/8/91 by Sanjiv and Frank -- -- updated by Champaka Ramachandran 16/10/92 -- --*************************************************************************** use work.TYPES.all; package MVL7_functions is function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR; function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR; function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function I2B( Number : integer ; len : integer ) return MVL7_VECTOR; function B2I( v2 : MVL7_VECTOR ) return integer; function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR; function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR; function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7; function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7; function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR; function SUM( v2 : MVL7_VECTOR ) return integer; function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR; function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR; function INC( x : MVL7_VECTOR ) return MVL7_VECTOR; function CARRY_ADD( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; function "-"( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; -- truth table for "WiredOr" function constant tbl_WIREDOR: MVL7_TABLE := -- ----------------------------------------------- -- | X 0 1 Z W L H | | -- ----------------------------------------------- (('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X | ('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 | ('1', '1', '1', '1', '1', '1', '1'), -- | 1 | ('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z | ('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W | ('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L | ('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H | -- function WiredOr (V: MVL7_VECTOR) return MVL7; end; package body MVL7_functions is --*************************************************************************** function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable shift_val: MVL7_VECTOR (v1'high downto v1'low); variable I: integer; begin v1 := v2; for I in v1'high downto (v1'low + 1) loop shift_val(I) := v1(I - 1); end loop ; shift_val(v1'low) := fill; return shift_val; end; --*************************************************************************** function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHL(v1,'0'); end loop ; return v1; end; --*************************************************************************** function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHL(v1,'1'); end loop ; return v1; end; --*************************************************************************** function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable shift_val: MVL7_VECTOR (v1'high downto v1'low); begin v1 := v2; for I in v1'low to (v1'high - 1) loop shift_val(I) := v1(I + 1); end loop ; shift_val(v1'high) := fill; return shift_val; end; --*************************************************************************** function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHR(v1,'0'); end loop ; return v1; end; --*************************************************************************** function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHR(v1,'1'); end loop ; return v1; end; --*************************************************************************** function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for i in 1 to dist loop v1 := SHR(v1,v1(v1'low)); end loop ; return v1; end; --*************************************************************************** function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for i in 1 to dist loop v1 := SHL(v1,v1(v1'high)); end loop ; return v1; end; --*************************************************************************** function I2B( Number : integer ; len : integer ) return MVL7_VECTOR is variable temp: MVL7_VECTOR (len - 1 downto 0); variable NUM: integer:=0; variable QUOTIENT: integer:=0; begin QUOTIENT := Number; for I in 0 to len - 1 loop NUM := 0; while QUOTIENT > 1 loop QUOTIENT := QUOTIENT - 2; NUM := NUM + 1; end loop ; case QUOTIENT is when 1 => temp(I) := '1'; when 0 => temp(I) := '0'; when others => null; end case; QUOTIENT := NUM; end loop ; return temp; end; --*************************************************************************** function B2I( v2 : MVL7_VECTOR ) return integer is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable SUM: integer:=0; begin v1 := v2; for N in v1'low to v1'high loop if v1(N) = '1' then SUM := SUM + (2 ** (N - v1'low)); end if; end loop ; return SUM; end; --*************************************************************************** function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable temp: MVL7_VECTOR (v1'high downto v1'low); variable I: INTEGER; begin v1 := v2; for I in v1'low to v1'high loop if v1(I) = '0' then temp(i) := '1'; else temp(i) := '0'; end if; end loop ; return temp; end; --*************************************************************************** function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable temp: MVL7_VECTOR (v1'high downto v1'low); begin v1 := v2; temp := comp(v1); temp := INC(temp); return temp; end; --*************************************************************************** function "-" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable SUM: MVL7_VECTOR (v1'high downto v1'low); begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7 vector -: operands of unequal lengths" severity FAILURE; SUM := I2B(B2I(v1) - B2I(v2),SUM'length); return (SUM); end; --*************************************************************************** function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR is variable v: MVL7_VECTOR (x'high downto x'low); begin v := x; return I2B(B2I(v) - 1,v'length); end; --*************************************************************************** function CARRY_ADD( x1: MVL7_VECTOR ; x2: MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable SUM: MVL7_VECTOR (x1'high - x1'low + 1 downto 0); -- + 1 is for carry begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7vector carry add:operands of unequal lengths" severity FAILURE; SUM := I2B(B2I(v1) + B2I(v2),SUM'length); return (SUM); end; --*************************************************************************** function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable SUM: MVL7_VECTOR (v1'high downto v1'low); begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7 vector +: operands of unequal lengths" severity FAILURE; SUM := I2B(B2I(v1) + B2I(v2),SUM'length); return (SUM); end; --*************************************************************************** function INC( x : MVL7_VECTOR ) return MVL7_VECTOR is variable v: MVL7_VECTOR (x'high downto x'low); begin v := x; return I2B(B2I(v) + 1,v'length); end; --*************************************************************************** function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7 is begin if ((SUM(v1) mod 2) = 1) then return '0'; else return '1'; end if; end; --*************************************************************************** function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7 is begin if ((SUM(v1) mod 2) = 1) then return '1'; else return '0'; end if; end; --*************************************************************************** function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable temp: MVL7_VECTOR (v1'high downto v1'low); begin v1 := v2; for I in v1'high downto v1'low loop temp(I) := v1(v1'high - I + v1'low); end loop ; return temp; end; --*************************************************************************** function SUM( v2 : MVL7_VECTOR ) return integer is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable count: integer:=0; begin v1 := v2; for I in v1'high downto v1'low loop if (v1(I) = '1') then count := count + 1; end if; end loop ; return count; end; --*************************************************************************** function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR is begin return I2B(B2I(v),width); end; --*************************************************************************** function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable PROD: MVL7_VECTOR (v1'high downto v1'low); begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7 vector MUL: operands of unequal lengths" severity FAILURE; PROD := I2B(B2I(v1) * B2I(v2),PROD'length); return (PROD); end; --*************************************************************************** function WiredOr (V: MVL7_VECTOR) return MVL7 is variable result: MVL7; begin result := 'Z'; for i in V'range loop result := tbl_WIREDOr(result, V(i)); exit when result = '1'; end loop; return result; end WiredOr; --*************************************************************************** end;
mit
6e298b1309774d3164b66f5a4c04cc07
0.458754
3.56423
false
false
false
false
MartinCura/SistDig-TP4
src/cordic/cordic_bkp.vhd
1
8,330
-- Algoritmo CORDIC -- (Rehecho de forma iterativa) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.MATH_REAL.all; library work; use work.cordic_lib.all; entity cordic is generic ( P : natural := 16 -- Cantidad de iteraciones, determina la precisión ); port ( clk : in std_logic; rst : in std_logic; load : in std_logic; x_in, y_in : in t_coord; angle : in t_num; x_rot, y_rot : out t_coord; rotRdy : out std_logic ); end entity cordic; architecture cordic_arq of cordic is type t_angles is array (0 to 27) of real; constant ANGLES : t_angles := ( -- 28 primeros valores de atan(2^-i) 0.785398163397448279, 0.463647609000806094, 0.244978663126864143, 0.124354994546761438, 0.062418809995957350, 0.031239833430268277, 0.015623728620476831, 0.007812341060101111, 0.003906230131966972, 0.001953122516478819, 0.000976562189559319, 0.000488281211194898, 0.000244140620149362, 0.000122070311893670, 0.000061035156174209, 0.000030517578115526, 0.000015258789061316, 0.000007629394531102, 0.000003814697265606, 0.000001907348632810, 0.000000953674316406, 0.000000476837158203, 0.000000238418579102, 0.000000119209289551, 0.000000059604644775, 0.000000029802322388, 0.000000014901161194, 0.000000007450580597 ); type t_angles_deg is array(0 to 27) of unsigned(N_BITS-1 downto 0); constant ANGLES_DEG : t_angles := to_unsigned(integer(round( ANGLES * real(2**N_BITS) / (2.0*MATH_PI) )), N_BITS); ---constant ANGLES_DEG : t_angles := ANGLES(0 to 27) * real(2**N_BITS) / (2.0*MATH_PI); ---chequear; si no, copiar lo otro constant N_K : natural := N_BITS / 2; type t_kvalues is array (0 to 25) of real; constant K_VALUES: t_kvalues := ( -- 26 primeros cumprod(1 ./ abs(1 + 1j*2.^(-(0:25)))) 0.707106781186547462, 0.632455532033675771, 0.613571991077896284, 0.608833912517752429, 0.607648256256168140, 0.607351770141295932, 0.607277644093526026, 0.607259112298892734, 0.607254479332562269, 0.607253321089875175, 0.607253031529134346, 0.607252959138944837, 0.607252941041397154, 0.607252936517010178, 0.607252935385913406, 0.607252935103139269, 0.607252935032445706, 0.607252935014772288, 0.607252935010353934, 0.607252935009249373, 0.607252935008973260, 0.607252935008904204, 0.607252935008886885, 0.607252935008882666, 0.607252935008881555, 0.607252935008881223 );----///2**Nk signal x_in_e, x_in_n, x0, x_1, x_2, x_2_sh, x_3, x_4 : t_coord_e := (others => '0'); signal y_in_e, y_in_n, y0, y_1, y_2, y_2_sh, y_3, y_4 : t_coord_e := (others => '0'); signal x_5, y_5 : std_logic_vector((N_EXTR+N_K)-1 downto 0) := (others => '0'); signal angle0, angle_1, angle_2, angle_3 : t_num := (others => '0'); subtype natural_i is natural range 0 to 31; signal i : natural_i := P; signal cuadrante : std_logic_vector(1 downto 0) := "00"; signal angle_i : unsigned(N_BITS-1 downto 0) := (others => '0'); signal sigma : std_logic := '0'; signal ena_reg : std_logic := '0'; type t_estado is (IDLE, LOAD, ROTA, RDY); signal estado : t_estado : IDLE; begin -- Extiendo coordenadas x_in_e <= (N_EXTR-N_BITS-1 downto 0 => x_in(N_BITS-1)) & x_in; y_in_e <= (N_EXTR-N_BITS-1 downto 0 => y_in(N_BITS-1)) & y_in; -- Versiones negativas x_in_n <= std_logic_vector(signed(not x_in_e) + 1); y_in_n <= std_logic_vector(signed(not y_in_e) + 1); -- Iterador process(clk, rst, load) begin if rst = '1' then i <= P; estado <= IDLE; elsif rising_edge(clk) then if load = '1' then -- Cargo nueva posición para rotar estado <= LOAD; i <= 0; elsif i < P-2 then -- Sigo rotando estado <= ROTA; i <= i + 1; elsif i = P-2 then -- Terminé de rotar posición estado <= RDY; i <= i + 1; else estado <= IDLE; end if; end if; end process; ena_reg <= (estado = LOAD or estado = ROTA) or load = '1'; ---Chequear sintaxis -- Averiguo cuadrante con los 2 MSBs del ángulo cuadrante <= angle(N_BITS-1 downto N_BITS-2); -- Rotación inicial (pongo en el cuadrante correcto) x0 <= x_in_e when cuadrante = "00" else y_in_n when cuadrante = "01" else x_in_n when cuadrante = "10" else y_in_e when cuadrante = "11"; y0 <= y_in_e when cuadrante = "00" else x_in_e when cuadrante = "01" else y_in_n when cuadrante = "10" else x_in_n when cuadrante = "11"; angle0 <= "00" & angle(N_BITS-3 downto 0); -- Uso pos nueva si cargando o sigo rotando x_1 <= x0 when load = '1' else x_3; y_1 <= y0 when load = '1' else y_3; angle_1 <= angle0 when load = '1' else angle_3; -- ... reg_x: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => ena_reg, d => x_1, q => x_2 ); reg_y: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => ena_reg, d => y_1, q => y_2 ); reg_angle: entity work.registroNb generic map( N => N_BITS ) port map( clk => clk, rst => rst, ena => ena_reg, d => angle_1, q => angle_2 ); -- ... bshift_x: entity work.barrel_shifterNb generic map( N => N_EXTR ) port map( to_left => '0', M => i, a => x_2, o => x_2_sh ); bshift_y: entity work.barrel_shifterNb generic map( N => N_EXTR ) port map( to_left => '0', M => i, a => y_2, o => y_2_sh ); -- ... x_3 <= std_logic_vector(unsigned(x_2) + unsigned(y_2_sh)) when sigma = '1' else std_logic_vector(unsigned(x_2) - unsigned(y_2_sh)); y_3 <= std_logic_vector(unsigned(y_2) + unsigned(x_2_sh)) when sigma = '0' else std_logic_vector(unsigned(y_2) - unsigned(x_2_sh)); angle_i <= ANGLES_DEG(i);---- when (i < ANGLES'length) else ----(angle(ANGLES'length-1) / (2**(i - ANGLES'length + 1))); ------ Si me paso de la tabla, aproximo angle_3 <= std_logic_vector(unsigned(angle_2) + angle_i) when sigma = '1' else std_logic_vector(unsigned(angle_2) - angle_i); -- Signo del ángulo de rotación restante sigma <= angle_2(N_BITS-1) and (estado = ROTA); -- ... pipe_reg_x: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => '1', d => x_3, q => x_4 ); pipe_reg_y: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => '1', d => y_3, q => y_4 ); -- ... delay_Rdy: entity work.ffd port map( clk => clk, rst => rst, ena => '1', d => (estado = RDY); ---Seguro tenga q reemplazar por auxiliar q => rotRdy ); ---Chequear que funcionen x_5 <= std_logic_vector( signed(x_4) * to_signed(real(2**N_K) * K_VALUES, N_K) ); y_5 <= std_logic_vector( signed(y_4) * to_signed(real(2**N_K) * K_VALUES, N_K) ); -- Salida de la rotación (si rotRdy) x_rot <= x_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1); y_rot <= y_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1); end cordic_arq;
gpl-3.0
9cdc27455d8162df39b3e659d5f76090
0.517366
3.101379
false
false
false
false
MartinCura/SistDig-TP4
src/video_ram/dual_port_ram.vhd
1
1,703
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dual_port_ram is generic ( DATA_WIDTH : natural := 1; ADDRESS_WIDTH : natural := 18 ); port ( clock: in std_logic; write_enable : in std_logic; address_A : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); address_B : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); data_A : in std_logic_vector(DATA_WIDTH-1 downto 0); data_B : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end entity dual_port_ram; architecture dual_port_ram_arq of dual_port_ram is attribute ram_style : string; constant memo_size : natural := 2**ADDRESS_WIDTH; subtype memo_i is integer range 0 to memo_size-1; subtype t_word is std_logic_vector(DATA_WIDTH-1 downto 0); type memo is array(0 to (memo_size-1)) of t_word; signal RAM : memo := (others => (others => '0')); attribute ram_style of ram: signal is "block"; -- DEBUG ---type memo_aux is array(0 to (memo_size-1)) of std_logic; ---signal RAM_aux : memo_aux := (others => '0'); signal address_A_int : memo_i := 0;---integer := 0; signal address_B_int : memo_i := 0;---integer := 0; begin --DEBUG ---ram_test: for i in 0 to memo_size-1 generate --- RAM_aux(i) <= RAM(i)(0); ---end generate; address_A_int <= to_integer(unsigned(address_A)); address_B_int <= to_integer(unsigned(address_B)); process(clock) begin if rising_edge(clock) then if write_enable = '1' then RAM(address_A_int) <= data_A; end if; data_B <= RAM(address_B_int); end if; end process; end;
gpl-3.0
91d89b9b2dc3862b052ea79922484e92
0.591897
3.262452
false
false
false
false
natsutan/NPU
fpga_implement/npu8/npu8.cache/ip/3ff41c2a70d99e06/mul16_16_sim_netlist.vhdl
1
602,012
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 -- Date : Sat Jan 21 17:58:33 2017 -- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul16_16_sim_netlist.vhdl -- Design : mul16_16 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. 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15 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); CE : in STD_LOGIC; SCLR : in STD_LOGIC; ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 ); P : out STD_LOGIC_VECTOR ( 15 downto 0 ); PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 ) ); attribute C_A_TYPE : integer; attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16; attribute C_B_TYPE : integer; attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_OPTIMIZE_GOAL : integer; attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 31; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is signal \<const0>\ : STD_LOGIC; signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE of i_mult : label is 1; attribute C_A_WIDTH of i_mult : label is 16; attribute C_B_TYPE of i_mult : label is 1; attribute C_B_VALUE of i_mult : label is "10000001"; attribute C_B_WIDTH of i_mult : label is 16; attribute C_CCM_IMP of i_mult : label is 0; attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0; attribute C_HAS_CE of i_mult : label is 0; attribute C_HAS_SCLR of i_mult : label is 0; attribute C_HAS_ZERO_DETECT of i_mult : label is 0; attribute C_LATENCY of i_mult : label is 4; attribute C_MODEL_TYPE of i_mult : label is 0; attribute C_MULT_TYPE of i_mult : label is 0; attribute C_OUT_HIGH of i_mult : label is 31; attribute C_OUT_LOW of i_mult : label is 16; attribute C_ROUND_OUTPUT of i_mult : label is 0; attribute C_ROUND_PT of i_mult : label is 0; attribute C_VERBOSITY of i_mult : label is 0; attribute C_XDEVICEFAMILY of i_mult : label is "kintexu"; attribute c_optimize_goal of i_mult : label is 1; attribute downgradeipidentifiedwarnings of i_mult : label is "yes"; begin PCASC(47) <= \<const0>\; PCASC(46) <= \<const0>\; PCASC(45) <= \<const0>\; PCASC(44) <= \<const0>\; PCASC(43) <= \<const0>\; PCASC(42) <= \<const0>\; PCASC(41) <= \<const0>\; PCASC(40) <= \<const0>\; PCASC(39) <= \<const0>\; PCASC(38) <= \<const0>\; PCASC(37) <= \<const0>\; PCASC(36) <= \<const0>\; PCASC(35) <= \<const0>\; PCASC(34) <= \<const0>\; PCASC(33) <= \<const0>\; PCASC(32) <= \<const0>\; PCASC(31) <= \<const0>\; PCASC(30) <= \<const0>\; PCASC(29) <= \<const0>\; PCASC(28) <= \<const0>\; PCASC(27) <= \<const0>\; PCASC(26) <= \<const0>\; PCASC(25) <= \<const0>\; PCASC(24) <= \<const0>\; PCASC(23) <= \<const0>\; PCASC(22) <= \<const0>\; PCASC(21) <= \<const0>\; PCASC(20) <= \<const0>\; PCASC(19) <= \<const0>\; PCASC(18) <= \<const0>\; PCASC(17) <= \<const0>\; PCASC(16) <= \<const0>\; PCASC(15) <= \<const0>\; PCASC(14) <= \<const0>\; PCASC(13) <= \<const0>\; PCASC(12) <= \<const0>\; PCASC(11) <= \<const0>\; PCASC(10) <= \<const0>\; PCASC(9) <= \<const0>\; PCASC(8) <= \<const0>\; PCASC(7) <= \<const0>\; PCASC(6) <= \<const0>\; PCASC(5) <= \<const0>\; PCASC(4) <= \<const0>\; PCASC(3) <= \<const0>\; PCASC(2) <= \<const0>\; PCASC(1) <= \<const0>\; PCASC(0) <= \<const0>\; ZERO_DETECT(1) <= \<const0>\; ZERO_DETECT(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv port map ( A(15 downto 0) => A(15 downto 0), B(15 downto 0) => B(15 downto 0), CE => '0', CLK => CLK, P(15 downto 0) => P(15 downto 0), PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 15 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); P : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mul16_16,mult_gen_v12_0_12,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE : integer; attribute C_A_TYPE of U0 : label is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of U0 : label is 16; attribute C_B_TYPE : integer; attribute C_B_TYPE of U0 : label is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of U0 : label is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of U0 : label is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of U0 : label is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of U0 : label is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of U0 : label is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of U0 : label is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of U0 : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of U0 : label is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of U0 : label is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of U0 : label is 31; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of U0 : label is 16; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of U0 : label is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of U0 : label is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of U0 : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "kintexu"; attribute c_optimize_goal : integer; attribute c_optimize_goal of U0 : label is 1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 port map ( A(15 downto 0) => A(15 downto 0), B(15 downto 0) => B(15 downto 0), CE => '1', CLK => CLK, P(15 downto 0) => P(15 downto 0), PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE;
bsd-3-clause
37d814e0b376853aa59d64edf8a01f45
0.950317
1.820632
false
false
false
false
besm6/micro-besm
tests/2901/vhdl/funct_blocks_alg_beh/components/alu/test_vectors.vhdl
1
11,338
-------------------------------------------------------------------------------- -- -- AM2901 Benchmark -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Jan 1, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD -- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD -------------------------------------------------------------------------------- --library ZYCAD; use work.TYPES.all; use work.MVL7_functions.all; entity E is end; architecture A of E is component alu_inst port ( RE, S : in MVL7_vector(3 downto 0); I : in MVL7_vector(8 downto 0); C0 : in MVL7; C4, OVR, F30, F3, Pbar, Gbar : out MVL7; F : out MVL7_vector(3 downto 0) ); end component; signal RE, S : MVL7_vector(3 downto 0); signal I : MVL7_vector(8 downto 0); signal C0 : MVL7; signal C4, OVR, F30, F3, Pbar, Gbar : MVL7; signal F : MVL7_vector(3 downto 0); for all : alu_inst use entity work.alu(alu); begin alu_inst1 : alu_inst port map( RE, S, I, C0, C4, OVR, F30, F3, Pbar, Gbar, F ); process begin ---------------------------------------------------------------------------- RE <= "0001"; --#1 S <= "0001"; C0 <= '0'; -- Compute RE + S. ( RE = 0001, S = 0001) I <= "000000000"; wait for 1 ns; assert (F = "0010") report "Assert a1 : < F /= '0010'> " severity warning; assert (C4 = '0') report "Assert a2 : < C4 /= '0'> " severity warning; assert (OVR = '0') report "Assert a3 : < OVR /= '0'> " severity warning; assert (F30 = '0') report "Assert a4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert a5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert a6 : < Pbar /= '1'> " severity warning; assert (Gbar = '1') report "Assert a7 : < Gbar /= '1'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "0010"; --#2 S <= "0010"; C0 <= '1'; -- Compute RE + S + 1. ( RE = 0010, S = 0010) I <= "000000000"; wait for 1 ns; assert (F = "0101") report "Assert b1 : < F /= '0101'> " severity warning; assert (C4 = '0') report "Assert b2 : < C4 /= '0'> " severity warning; assert (OVR = '0') report "Assert b3 : < OVR /= '0'> " severity warning; assert (F30 = '0') report "Assert b4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert b5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert b6 : < Pbar /= '1'> " severity warning; assert (Gbar = '1') report "Assert b7 : < Gbar /= '1'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "0100"; --#3 S <= "0100"; C0 <= '0'; -- Compute RE + S. ( RE = 0100, S = 0100) I <= "000000000"; wait for 1 ns; assert (F = "1000") report "Assert c1 : < F /= '1000'> " severity warning; assert (C4 = '0') report "Assert c2 : < C4 /= '0'> " severity warning; assert (OVR = '1') report "Assert c3 : < OVR /= '1'> " severity warning; assert (F30 = '0') report "Assert c4 : < F30 /= '0'> " severity warning; assert (F3 = '1') report "Assert c5 : < F3 /= '1'> " severity warning; assert (Pbar = '1') report "Assert c6 : < Pbar /= '1'> " severity warning; assert (Gbar = '1') report "Assert c7 : < Gbar /= '1'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1000"; --#4 S <= "1000"; C0 <= '0'; -- Compute RE + S. ( RE = 1000, S = 1000) I <= "000000000"; wait for 1 ns; assert (F = "0000") report "Assert d1 : < F /= '0000'> " severity warning; assert (C4 = '1') report "Assert d2 : < C4 /= '1'> " severity warning; assert (OVR = '1') report "Assert d3 : < OVR /= '1'> " severity warning; assert (F30 = '1') report "Assert d4 : < F30 /= '1'> " severity warning; assert (F3 = '0') report "Assert d5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert d6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert d7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "0001"; --#5 S <= "0010"; C0 <= '1'; -- Compute S - RE. ( RE = 0001, S = 0010) I <= "000001000"; wait for 1 ns; assert (F = "0001") report "Assert e1 : < F /= '0001'> " severity warning; assert (C4 = '1') report "Assert e2 : < C4 /= '1'> " severity warning; assert (OVR = '0') report "Assert e3 : < OVR /= '0'> " severity warning; assert (F30 = '0') report "Assert e4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert e5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert e6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert e7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "0001"; --#6 S <= "0010"; C0 <= '0'; -- Compute S - RE -1. ( RE = 0001, S = 0010) I <= "000001000"; wait for 1 ns; assert (F = "0000") report "Assert f1 : < F /= '0000'> " severity warning; assert (C4 = '1') report "Assert f2 : < C4 /= '1'> " severity warning; assert (OVR = '0') report "Assert f3 : < OVR /= '0'> " severity warning; assert (F30 = '1') report "Assert f4 : < F30 /= '1'> " severity warning; assert (F3 = '0') report "Assert f5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert f6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert f7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1000"; --#7 S <= "0001"; C0 <= '1'; -- Compute RE - S. ( RE = 1000, S = 0001) I <= "000010000"; wait for 1 ns; assert (F = "0111") report "Assert g1 : < F /= '0111'> " severity warning; assert (C4 = '1') report "Assert g2 : < C4 /= '1'> " severity warning; assert (OVR = '1') report "Assert g3 : < OVR /= '1'> " severity warning; assert (F30 = '0') report "Assert g4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert g5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert g6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert g7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1000"; --#8 S <= "0001"; C0 <= '0'; -- Compute RE - S - 1. ( RE = 1000, S = 0001) I <= "000010000"; wait for 1 ns; assert (F = "0110") report "Assert h1 : < F /= '0110'> " severity warning; assert (C4 = '1') report "Assert h2 : < C4 /= '1'> " severity warning; assert (OVR = '1') report "Assert h3 : < OVR /= '1'> " severity warning; assert (F30 = '0') report "Assert h4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert h5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert h6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert h7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1010"; --#9 S <= "1001"; C0 <= '0'; -- Compute RE or S. ( RE = 1010, S = 1001) I <= "000011000"; wait for 1 ns; assert (C4 = '0') report "Assert i2 : < C4 /= '0'> " severity warning; assert (OVR = '0') report "Assert i3 : < OVR /= '0'> " severity warning; assert (F = "1011") report "Assert i1 : < F /= '1011'> " severity warning; assert (F30 = '0') report "Assert i4 : < F30 /= '0'> " severity warning; assert (F3 = '1') report "Assert i5 : < F3 /= '1'> " severity warning; assert (Pbar = '1') report "Assert i6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert i7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1010"; --#10 S <= "1001"; C0 <= '0'; -- Compute RE and S. ( RE = 1010, S = 1001) I <= "000100000"; wait for 1 ns; assert (F = "1000") report "Assert j1 : < F /= '1000'> " severity warning; assert (C4 = '0') report "Assert j2 : < C4 /= '0'> " severity warning; assert (OVR = '0') report "Assert j3 : < OVR /= '0'> " severity warning; assert (F30 = '0') report "Assert j4 : < F30 /= '0'> " severity warning; assert (F3 = '1') report "Assert j5 : < F3 /= '1'> " severity warning; assert (Pbar = '1') report "Assert j6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert j7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1010"; --#11 S <= "1001"; C0 <= '0'; -- Compute not(RE) and S. ( RE = 1010, S = 1001) I <= "000101000"; wait for 1 ns; assert (F = "0001") report "Assert k1 : < F /= '0001'> " severity warning; assert (C4 = '0') report "Assert k2 : < C4 /= '0'> " severity warning; assert (OVR = '1') report "Assert k3 : < OVR /= '1'> " severity warning; assert (F30 = '0') report "Assert k4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert k5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert k6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert k7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "1010"; --#12 S <= "1001"; C0 <= '0'; -- Compute RE xor S. ( RE = 1010, S = 1001) I <= "000110000"; wait for 1 ns; assert (F = "0011") report "Assert l1 : < F /= '0011'> " severity warning; assert (C4 = '0') report "Assert l2 : < C4 /= '0'> " severity warning; assert (OVR = '1') report "Assert l3 : < OVR /= '1'> " severity warning; assert (F30 = '0') report "Assert l4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert l5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert l6 : < Pbar /= '1'> " severity warning; assert (Gbar = '0') report "Assert l7 : < Gbar /= '0'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- RE <= "0101"; --#13 S <= "1001"; C0 <= '0'; -- Compute RE xnor S. ( RE = 0101, S = 1001) I <= "000111000"; wait for 1 ns; assert (F = "0011") report "Assert m1 : < F /= '0011'> " severity warning; assert (C4 = '1') report "Assert m2 : < C4 /= '1'> " severity warning; assert (OVR = '0') report "Assert m3 : < OVR /= '0'> " severity warning; assert (F30 = '0') report "Assert m4 : < F30 /= '0'> " severity warning; assert (F3 = '0') report "Assert m5 : < F3 /= '0'> " severity warning; assert (Pbar = '1') report "Assert m6 : < Pbar /= '1'> " severity warning; assert (Gbar = '1') report "Assert m7 : < Gbar /= '1'> " severity warning; wait for 1 ns; ---------------------------------------------------------------------------- end process; end A;
mit
7169d66b9d5599035fcd35f714ba2a29
0.486858
2.822504
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado-hls/array_arith/proj_array_arith/solution1/syn/vhdl/array_arith.vhd
3
9,635
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2018.2 -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity array_arith is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; d_address0 : OUT STD_LOGIC_VECTOR (2 downto 0); d_ce0 : OUT STD_LOGIC; d_we0 : OUT STD_LOGIC; d_d0 : OUT STD_LOGIC_VECTOR (31 downto 0); d_q0 : IN STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of array_arith is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "array_arith,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=21,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=108,HLS_SYN_LUT=122,HLS_VERSION=2018_2}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100"; constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_boolean_1 : BOOLEAN := true; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal acc : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal i_1_fu_61_p2 : STD_LOGIC_VECTOR (2 downto 0); signal i_1_reg_94 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal ap_CS_fsm_state3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none"; signal d_load_reg_105 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none"; signal tmp_2_fu_75_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_reg_110 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none"; signal i_reg_43 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none"; signal tmp_1_fu_67_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_3_fu_86_p1 : STD_LOGIC_VECTOR (63 downto 0); signal exitcond_fu_55_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); begin ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; i_reg_43_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state6)) then i_reg_43 <= i_1_reg_94; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then i_reg_43 <= ap_const_lv3_0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state5)) then acc <= tmp_2_fu_75_p2; tmp_2_reg_110 <= tmp_2_fu_75_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state4)) then d_load_reg_105 <= d_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state2)) then i_1_reg_94 <= i_1_fu_61_p2; end if; end if; end process; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, exitcond_fu_55_p2) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((exitcond_fu_55_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state3; end if; when ap_ST_fsm_state3 => ap_NS_fsm <= ap_ST_fsm_state4; when ap_ST_fsm_state4 => ap_NS_fsm <= ap_ST_fsm_state5; when ap_ST_fsm_state5 => ap_NS_fsm <= ap_ST_fsm_state6; when ap_ST_fsm_state6 => ap_NS_fsm <= ap_ST_fsm_state2; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state3 <= ap_CS_fsm(2); ap_CS_fsm_state4 <= ap_CS_fsm(3); ap_CS_fsm_state5 <= ap_CS_fsm(4); ap_CS_fsm_state6 <= ap_CS_fsm(5); ap_done_assign_proc : process(ap_CS_fsm_state2, exitcond_fu_55_p2) begin if (((exitcond_fu_55_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_CS_fsm_state2, exitcond_fu_55_p2) begin if (((exitcond_fu_55_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; d_address0_assign_proc : process(ap_CS_fsm_state3, ap_CS_fsm_state6, tmp_1_fu_67_p1, tmp_3_fu_86_p1) begin if ((ap_const_logic_1 = ap_CS_fsm_state6)) then d_address0 <= tmp_3_fu_86_p1(3 - 1 downto 0); elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then d_address0 <= tmp_1_fu_67_p1(3 - 1 downto 0); else d_address0 <= "XXX"; end if; end process; d_ce0_assign_proc : process(ap_CS_fsm_state3, ap_CS_fsm_state6) begin if (((ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state3))) then d_ce0 <= ap_const_logic_1; else d_ce0 <= ap_const_logic_0; end if; end process; d_d0 <= tmp_2_reg_110; d_we0_assign_proc : process(ap_CS_fsm_state6) begin if ((ap_const_logic_1 = ap_CS_fsm_state6)) then d_we0 <= ap_const_logic_1; else d_we0 <= ap_const_logic_0; end if; end process; exitcond_fu_55_p2 <= "1" when (i_reg_43 = ap_const_lv3_4) else "0"; i_1_fu_61_p2 <= std_logic_vector(unsigned(i_reg_43) + unsigned(ap_const_lv3_1)); tmp_1_fu_67_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_94),64)); tmp_2_fu_75_p2 <= std_logic_vector(unsigned(d_load_reg_105) + unsigned(acc)); tmp_3_fu_86_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_43),64)); end behav;
mit
f9c40a8201880f91e57b9c2b8522d3f9
0.561287
3.059701
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/alu/top.vhdl
1
4,277
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top is generic( N : natural := 4 ); port (in_data_a : in std_logic_vector(N-1 downto 0); -- input data A in_data_b : in std_logic_vector(N-1 downto 0); -- input data B in_data_carry : in std_logic; -- carry in or borrow in in_ctrl : in std_logic_vector(2 downto 0); -- control signals out_data_c : out std_logic_vector(N-1 downto 0); -- output data C out_data_carry : out std_logic; -- carry out or borrow out out_data_comp : out std_logic_vector(1 downto 0) -- output comparison ); end top; architecture behavioral of top is begin comb_memless_process: process ( in_data_a, in_data_b, in_data_carry, in_ctrl ) variable temp_carry: std_logic_vector(N downto 0) := ( others => '0' ); variable temp_b: std_logic_vector( N-1 downto 0 ) := ( others => '0' ); begin out_data_c <= (others => '0'); out_data_carry <= '0'; out_data_comp <= (others => '0'); case in_ctrl is when "000" => out_data_c <= in_data_a; out_data_carry <= in_data_carry; when "001" => -- ripple carry adder: {sum, cout} = a+b+cin temp_carry(0) := in_data_carry; for i in 0 to N-1 loop -- sum(k) = a(k) xor b(k) xor c(k) out_data_c(i) <= in_data_a(i) xor in_data_b(i) xor temp_carry(i); -- cout(k+1) = a(k).b(k) + b(k).c(k) + c(k).a(k) temp_carry(i+1) := ( in_data_a(i) and in_data_b(i) ) or ( in_data_b(i) and temp_carry(i) ) or ( temp_carry(i) and in_data_a(i) ); end loop; out_data_carry <= temp_carry(N); --sum := signed('0' & in_data_a) + signed('0' & in_data_b) + signed( in_data_carry ); --out_data_c <= std_logic_vector( sum(N-1 downto 0) ); --out_data_carry <= sum(N); when "010" => -- full subtraction: {diff, bout} = a-b-bin temp_carry(0) := in_data_carry; for i in 0 to N-1 loop -- diff(k) = a(k) xor b(k) xor c(k) out_data_c(i) <= in_data_a(i) xor in_data_b(i) xor temp_carry(i); -- bout(k+1) = !a(k).b(k) + b(k).c(k) + c(k).!a(k) temp_carry(i+1) := ( ( NOT in_data_a(i) ) AND in_data_b(i) ) OR ( in_data_b(i) AND temp_carry(i) ) OR ( temp_carry(i) AND ( NOT in_data_a(i) ) ); end loop; out_data_carry <= temp_carry(N); -- 2's complement of n-bits data B (1's complement + 1) --temp_b := std_logic_vector( unsigned( NOT in_data_b ) + 1 ); -- 2's complement of single bit is same single bit --temp_carry(0) := in_data_carry; --for i in 0 to N-1 loop -- out_data_c(i) := in_data_a(i) xor temp_b(i) xor temp_carry(i); -- temp_carry(i+1) := ( in_data_a(i) and temp_b(i) ) or -- ( temp_b(i) and temp_carry(i) ) or -- ( temp_carry(i) and in_data_a(i) ); --end loop; --out_data_carry <= temp_carry(N); when "011" => -- comparator: comp_out = 1 if A > B if( in_data_a > in_data_b ) then out_data_comp <= "01"; else out_data_comp <= "00"; end if; when "100" => -- comparator: comp_out = 1 if A < B if( in_data_a < in_data_b ) then out_data_comp <= "01"; else out_data_comp <= ( others => '0' ); end if; when "101" => -- comparator: comp_out = 1 if A = B if( in_data_a = in_data_b ) then out_data_comp <= "01"; else out_data_comp <= ( others => '0' ); end if; when "110" => -- logical right shift A by B[1:0] out_data_c <= std_logic_vector( unsigned(in_data_a) srl to_integer( unsigned( in_data_b(1 downto 0) ) ) ); when "111" => -- logical left shift A by B out_data_c <= std_logic_vector( unsigned(in_data_a) sll to_integer( unsigned( in_data_b(1 downto 0) ) ) ); when others => -- nothing to be done end case; end process comb_memless_process; end behavioral;
mit
bc78afbe862c8dd6d1bd133687e242f6
0.494272
2.713832
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_gcd_0_0/gcd_zynq_snick_gcd_0_0_sim_netlist.vhdl
1
128,447
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 19:44:40 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_gcd_0_0/gcd_zynq_snick_gcd_0_0_sim_netlist.vhdl -- Design : gcd_zynq_snick_gcd_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg400-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_gcd_0_0_gcd_gcd_bus_s_axi is port ( \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); interrupt : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); CO : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \b_read_reg_102_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); \a_read_reg_107_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); ap_clk : in STD_LOGIC; s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BREADY : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \result_reg_56_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); \p_s_reg_45_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); ap_rst_n : in STD_LOGIC; s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_gcd_0_0_gcd_gcd_bus_s_axi : entity is "gcd_gcd_bus_s_axi"; end gcd_zynq_snick_gcd_0_0_gcd_gcd_bus_s_axi; architecture STRUCTURE of gcd_zynq_snick_gcd_0_0_gcd_gcd_bus_s_axi is signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes"; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^a_read_reg_107_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_start : STD_LOGIC; signal ar_hs : STD_LOGIC; signal \^b_read_reg_102_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal int_a0 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \int_a[15]_i_1_n_0\ : STD_LOGIC; signal \int_a[15]_i_3_n_0\ : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_done1 : STD_LOGIC; signal int_ap_done_i_1_n_0 : STD_LOGIC; signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_start3_out : STD_LOGIC; signal int_ap_start_i_10_n_0 : STD_LOGIC; signal int_ap_start_i_1_n_0 : STD_LOGIC; signal int_ap_start_i_5_n_0 : STD_LOGIC; signal int_ap_start_i_6_n_0 : STD_LOGIC; signal int_ap_start_i_7_n_0 : STD_LOGIC; signal int_ap_start_i_8_n_0 : STD_LOGIC; signal int_ap_start_i_9_n_0 : STD_LOGIC; signal int_ap_start_reg_i_2_n_3 : STD_LOGIC; signal int_ap_start_reg_i_4_n_0 : STD_LOGIC; signal int_ap_start_reg_i_4_n_1 : STD_LOGIC; signal int_ap_start_reg_i_4_n_2 : STD_LOGIC; signal int_ap_start_reg_i_4_n_3 : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_auto_restart_i_1_n_0 : STD_LOGIC; signal int_b0 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \int_b[15]_i_1_n_0\ : STD_LOGIC; signal int_gie_i_1_n_0 : STD_LOGIC; signal int_gie_reg_n_0 : STD_LOGIC; signal \int_ier[0]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_2_n_0\ : STD_LOGIC; signal \int_ier_reg_n_0_[0]\ : STD_LOGIC; signal \int_ier_reg_n_0_[1]\ : STD_LOGIC; signal int_isr6_out : STD_LOGIC; signal \int_isr[0]_i_1_n_0\ : STD_LOGIC; signal \int_isr[1]_i_1_n_0\ : STD_LOGIC; signal \int_isr_reg_n_0_[0]\ : STD_LOGIC; signal int_pResult : STD_LOGIC_VECTOR ( 15 downto 0 ); signal int_pResult_ap_vld : STD_LOGIC; signal int_pResult_ap_vld1 : STD_LOGIC; signal int_pResult_ap_vld_i_1_n_0 : STD_LOGIC; signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP of \^out\ : signal is "yes"; signal p_1_in : STD_LOGIC; signal \rdata[0]_i_1_n_0\ : STD_LOGIC; signal \rdata[0]_i_2_n_0\ : STD_LOGIC; signal \rdata[0]_i_3_n_0\ : STD_LOGIC; signal \rdata[0]_i_4_n_0\ : STD_LOGIC; signal \rdata[10]_i_1_n_0\ : STD_LOGIC; signal \rdata[11]_i_1_n_0\ : STD_LOGIC; signal \rdata[12]_i_1_n_0\ : STD_LOGIC; signal \rdata[13]_i_1_n_0\ : STD_LOGIC; signal \rdata[14]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_1_n_0\ : STD_LOGIC; signal \rdata[1]_i_2_n_0\ : STD_LOGIC; signal \rdata[1]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_4_n_0\ : STD_LOGIC; signal \rdata[1]_i_5_n_0\ : STD_LOGIC; signal \rdata[2]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_2_n_0\ : STD_LOGIC; signal \rdata[3]_i_1_n_0\ : STD_LOGIC; signal \rdata[3]_i_2_n_0\ : STD_LOGIC; signal \rdata[4]_i_1_n_0\ : STD_LOGIC; signal \rdata[5]_i_1_n_0\ : STD_LOGIC; signal \rdata[6]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_2_n_0\ : STD_LOGIC; signal \rdata[8]_i_1_n_0\ : STD_LOGIC; signal \rdata[9]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \^s_axi_gcd_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \^s_axi_gcd_bus_rvalid\ : signal is "yes"; signal waddr : STD_LOGIC; signal \waddr_reg_n_0_[0]\ : STD_LOGIC; signal \waddr_reg_n_0_[1]\ : STD_LOGIC; signal \waddr_reg_n_0_[2]\ : STD_LOGIC; signal \waddr_reg_n_0_[3]\ : STD_LOGIC; signal \waddr_reg_n_0_[4]\ : STD_LOGIC; signal \waddr_reg_n_0_[5]\ : STD_LOGIC; signal NLW_int_ap_start_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); signal NLW_int_ap_start_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_int_ap_start_reg_i_4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_a[15]_i_2\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of int_ap_start_i_3 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_b[15]_i_2\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0"; begin CO(0) <= \^co\(0); SR(0) <= \^sr\(0); \a_read_reg_107_reg[15]\(15 downto 0) <= \^a_read_reg_107_reg[15]\(15 downto 0); \b_read_reg_102_reg[15]\(15 downto 0) <= \^b_read_reg_102_reg[15]\(15 downto 0); \out\(2 downto 0) <= \^out\(2 downto 0); s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0); s_axi_gcd_bus_RVALID(1 downto 0) <= \^s_axi_gcd_bus_rvalid\(1 downto 0); \FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F747" ) port map ( I0 => s_axi_gcd_bus_ARVALID, I1 => \^s_axi_gcd_bus_rvalid\(0), I2 => \^s_axi_gcd_bus_rvalid\(1), I3 => s_axi_gcd_bus_RREADY, O => \FSM_onehot_rstate[1]_i_1_n_0\ ); \FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88F8" ) port map ( I0 => s_axi_gcd_bus_ARVALID, I1 => \^s_axi_gcd_bus_rvalid\(0), I2 => \^s_axi_gcd_bus_rvalid\(1), I3 => s_axi_gcd_bus_RREADY, O => \FSM_onehot_rstate[2]_i_1_n_0\ ); \FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_rstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[1]_i_1_n_0\, Q => \^s_axi_gcd_bus_rvalid\(0), R => \^sr\(0) ); \FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[2]_i_1_n_0\, Q => \^s_axi_gcd_bus_rvalid\(1), R => \^sr\(0) ); \FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"888BFF8B" ) port map ( I0 => s_axi_gcd_bus_BREADY, I1 => \^out\(2), I2 => \^out\(1), I3 => \^out\(0), I4 => s_axi_gcd_bus_AWVALID, O => \FSM_onehot_wstate[1]_i_1_n_0\ ); \FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_gcd_bus_AWVALID, I1 => \^out\(0), I2 => s_axi_gcd_bus_WVALID, I3 => \^out\(1), O => \FSM_onehot_wstate[2]_i_1_n_0\ ); \FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ap_rst_n, O => \^sr\(0) ); \FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_gcd_bus_WVALID, I1 => \^out\(1), I2 => s_axi_gcd_bus_BREADY, I3 => \^out\(2), O => \FSM_onehot_wstate[3]_i_2_n_0\ ); \FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_wstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[1]_i_1_n_0\, Q => \^out\(0), R => \^sr\(0) ); \FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[2]_i_1_n_0\, Q => \^out\(1), R => \^sr\(0) ); \FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[3]_i_2_n_0\, Q => \^out\(2), R => \^sr\(0) ); \ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FA30" ) port map ( I0 => \^co\(0), I1 => ap_start, I2 => Q(0), I3 => Q(2), O => D(0) ); \ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00001000" ) port map ( I0 => Q(1), I1 => Q(3), I2 => Q(0), I3 => ap_start, I4 => Q(2), O => D(1) ); \b_read_reg_102[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => Q(0), I1 => ap_start, O => E(0) ); \int_a[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(0), O => int_a0(0) ); \int_a[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(10), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(10), O => int_a0(10) ); \int_a[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(11), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(11), O => int_a0(11) ); \int_a[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(12), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(12), O => int_a0(12) ); \int_a[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(13), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(13), O => int_a0(13) ); \int_a[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(14), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(14), O => int_a0(14) ); \int_a[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0008" ) port map ( I0 => \waddr_reg_n_0_[4]\, I1 => \int_a[15]_i_3_n_0\, I2 => \waddr_reg_n_0_[2]\, I3 => \waddr_reg_n_0_[3]\, O => \int_a[15]_i_1_n_0\ ); \int_a[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(15), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(15), O => int_a0(15) ); \int_a[15]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00001000" ) port map ( I0 => \waddr_reg_n_0_[0]\, I1 => \waddr_reg_n_0_[5]\, I2 => \^out\(1), I3 => s_axi_gcd_bus_WVALID, I4 => \waddr_reg_n_0_[1]\, O => \int_a[15]_i_3_n_0\ ); \int_a[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(1), O => int_a0(1) ); \int_a[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(2), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(2), O => int_a0(2) ); \int_a[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(3), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(3), O => int_a0(3) ); \int_a[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(4), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(4), O => int_a0(4) ); \int_a[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(5), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(5), O => int_a0(5) ); \int_a[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(6), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(6), O => int_a0(6) ); \int_a[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(7), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(7), O => int_a0(7) ); \int_a[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(8), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(8), O => int_a0(8) ); \int_a[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(9), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(9), O => int_a0(9) ); \int_a_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(0), Q => \^a_read_reg_107_reg[15]\(0), R => \^sr\(0) ); \int_a_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(10), Q => \^a_read_reg_107_reg[15]\(10), R => \^sr\(0) ); \int_a_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(11), Q => \^a_read_reg_107_reg[15]\(11), R => \^sr\(0) ); \int_a_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(12), Q => \^a_read_reg_107_reg[15]\(12), R => \^sr\(0) ); \int_a_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(13), Q => \^a_read_reg_107_reg[15]\(13), R => \^sr\(0) ); \int_a_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(14), Q => \^a_read_reg_107_reg[15]\(14), R => \^sr\(0) ); \int_a_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(15), Q => \^a_read_reg_107_reg[15]\(15), R => \^sr\(0) ); \int_a_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(1), Q => \^a_read_reg_107_reg[15]\(1), R => \^sr\(0) ); \int_a_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(2), Q => \^a_read_reg_107_reg[15]\(2), R => \^sr\(0) ); \int_a_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(3), Q => \^a_read_reg_107_reg[15]\(3), R => \^sr\(0) ); \int_a_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(4), Q => \^a_read_reg_107_reg[15]\(4), R => \^sr\(0) ); \int_a_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(5), Q => \^a_read_reg_107_reg[15]\(5), R => \^sr\(0) ); \int_a_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(6), Q => \^a_read_reg_107_reg[15]\(6), R => \^sr\(0) ); \int_a_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(7), Q => \^a_read_reg_107_reg[15]\(7), R => \^sr\(0) ); \int_a_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(8), Q => \^a_read_reg_107_reg[15]\(8), R => \^sr\(0) ); \int_a_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(9), Q => \^a_read_reg_107_reg[15]\(9), R => \^sr\(0) ); int_ap_done_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"8FFFFFFF88888888" ) port map ( I0 => Q(2), I1 => \^co\(0), I2 => \^s_axi_gcd_bus_rvalid\(0), I3 => s_axi_gcd_bus_ARVALID, I4 => int_ap_done1, I5 => int_ap_done, O => int_ap_done_i_1_n_0 ); int_ap_done_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => s_axi_gcd_bus_ARADDR(1), I3 => s_axi_gcd_bus_ARADDR(0), I4 => s_axi_gcd_bus_ARADDR(3), I5 => s_axi_gcd_bus_ARADDR(2), O => int_ap_done1 ); int_ap_done_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_done_i_1_n_0, Q => int_ap_done, R => \^sr\(0) ); int_ap_idle_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => Q(0), I1 => ap_start, O => ap_idle ); int_ap_idle_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => ap_idle, Q => int_ap_idle, R => \^sr\(0) ); int_ap_ready_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^co\(0), I1 => Q(2), O => ap_done ); int_ap_ready_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => ap_done, Q => int_ap_ready, R => \^sr\(0) ); int_ap_start_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFBFFF80" ) port map ( I0 => int_auto_restart, I1 => Q(2), I2 => \^co\(0), I3 => int_ap_start3_out, I4 => ap_start, O => int_ap_start_i_1_n_0 ); int_ap_start_i_10: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(0), I1 => \p_s_reg_45_reg[15]\(0), I2 => \p_s_reg_45_reg[15]\(2), I3 => \result_reg_56_reg[15]\(2), I4 => \p_s_reg_45_reg[15]\(1), I5 => \result_reg_56_reg[15]\(1), O => int_ap_start_i_10_n_0 ); int_ap_start_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"00000800" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \int_ier[1]_i_2_n_0\, I4 => \waddr_reg_n_0_[3]\, O => int_ap_start3_out ); int_ap_start_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \p_s_reg_45_reg[15]\(15), I1 => \result_reg_56_reg[15]\(15), O => int_ap_start_i_5_n_0 ); int_ap_start_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(12), I1 => \p_s_reg_45_reg[15]\(12), I2 => \p_s_reg_45_reg[15]\(14), I3 => \result_reg_56_reg[15]\(14), I4 => \p_s_reg_45_reg[15]\(13), I5 => \result_reg_56_reg[15]\(13), O => int_ap_start_i_6_n_0 ); int_ap_start_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(9), I1 => \p_s_reg_45_reg[15]\(9), I2 => \p_s_reg_45_reg[15]\(11), I3 => \result_reg_56_reg[15]\(11), I4 => \p_s_reg_45_reg[15]\(10), I5 => \result_reg_56_reg[15]\(10), O => int_ap_start_i_7_n_0 ); int_ap_start_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(6), I1 => \p_s_reg_45_reg[15]\(6), I2 => \p_s_reg_45_reg[15]\(8), I3 => \result_reg_56_reg[15]\(8), I4 => \p_s_reg_45_reg[15]\(7), I5 => \result_reg_56_reg[15]\(7), O => int_ap_start_i_8_n_0 ); int_ap_start_i_9: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(3), I1 => \p_s_reg_45_reg[15]\(3), I2 => \p_s_reg_45_reg[15]\(5), I3 => \result_reg_56_reg[15]\(5), I4 => \p_s_reg_45_reg[15]\(4), I5 => \result_reg_56_reg[15]\(4), O => int_ap_start_i_9_n_0 ); int_ap_start_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_start_i_1_n_0, Q => ap_start, R => \^sr\(0) ); int_ap_start_reg_i_2: unisim.vcomponents.CARRY4 port map ( CI => int_ap_start_reg_i_4_n_0, CO(3 downto 2) => NLW_int_ap_start_reg_i_2_CO_UNCONNECTED(3 downto 2), CO(1) => \^co\(0), CO(0) => int_ap_start_reg_i_2_n_3, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_int_ap_start_reg_i_2_O_UNCONNECTED(3 downto 0), S(3 downto 2) => B"00", S(1) => int_ap_start_i_5_n_0, S(0) => int_ap_start_i_6_n_0 ); int_ap_start_reg_i_4: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => int_ap_start_reg_i_4_n_0, CO(2) => int_ap_start_reg_i_4_n_1, CO(1) => int_ap_start_reg_i_4_n_2, CO(0) => int_ap_start_reg_i_4_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_int_ap_start_reg_i_4_O_UNCONNECTED(3 downto 0), S(3) => int_ap_start_i_7_n_0, S(2) => int_ap_start_i_8_n_0, S(1) => int_ap_start_i_9_n_0, S(0) => int_ap_start_i_10_n_0 ); int_auto_restart_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFFF00200000" ) port map ( I0 => s_axi_gcd_bus_WDATA(7), I1 => \waddr_reg_n_0_[3]\, I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, I4 => s_axi_gcd_bus_WSTRB(0), I5 => int_auto_restart, O => int_auto_restart_i_1_n_0 ); int_auto_restart_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_auto_restart_i_1_n_0, Q => int_auto_restart, R => \^sr\(0) ); \int_b[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(0), O => int_b0(0) ); \int_b[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(10), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(10), O => int_b0(10) ); \int_b[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(11), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(11), O => int_b0(11) ); \int_b[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(12), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(12), O => int_b0(12) ); \int_b[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(13), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(13), O => int_b0(13) ); \int_b[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(14), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(14), O => int_b0(14) ); \int_b[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \waddr_reg_n_0_[3]\, I1 => \waddr_reg_n_0_[4]\, I2 => \int_a[15]_i_3_n_0\, I3 => \waddr_reg_n_0_[2]\, O => \int_b[15]_i_1_n_0\ ); \int_b[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(15), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(15), O => int_b0(15) ); \int_b[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(1), O => int_b0(1) ); \int_b[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(2), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(2), O => int_b0(2) ); \int_b[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(3), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(3), O => int_b0(3) ); \int_b[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(4), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(4), O => int_b0(4) ); \int_b[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(5), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(5), O => int_b0(5) ); \int_b[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(6), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(6), O => int_b0(6) ); \int_b[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(7), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(7), O => int_b0(7) ); \int_b[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(8), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(8), O => int_b0(8) ); \int_b[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(9), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(9), O => int_b0(9) ); \int_b_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(0), Q => \^b_read_reg_102_reg[15]\(0), R => \^sr\(0) ); \int_b_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(10), Q => \^b_read_reg_102_reg[15]\(10), R => \^sr\(0) ); \int_b_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(11), Q => \^b_read_reg_102_reg[15]\(11), R => \^sr\(0) ); \int_b_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(12), Q => \^b_read_reg_102_reg[15]\(12), R => \^sr\(0) ); \int_b_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(13), Q => \^b_read_reg_102_reg[15]\(13), R => \^sr\(0) ); \int_b_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(14), Q => \^b_read_reg_102_reg[15]\(14), R => \^sr\(0) ); \int_b_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(15), Q => \^b_read_reg_102_reg[15]\(15), R => \^sr\(0) ); \int_b_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(1), Q => \^b_read_reg_102_reg[15]\(1), R => \^sr\(0) ); \int_b_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(2), Q => \^b_read_reg_102_reg[15]\(2), R => \^sr\(0) ); \int_b_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(3), Q => \^b_read_reg_102_reg[15]\(3), R => \^sr\(0) ); \int_b_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(4), Q => \^b_read_reg_102_reg[15]\(4), R => \^sr\(0) ); \int_b_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(5), Q => \^b_read_reg_102_reg[15]\(5), R => \^sr\(0) ); \int_b_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(6), Q => \^b_read_reg_102_reg[15]\(6), R => \^sr\(0) ); \int_b_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(7), Q => \^b_read_reg_102_reg[15]\(7), R => \^sr\(0) ); \int_b_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(8), Q => \^b_read_reg_102_reg[15]\(8), R => \^sr\(0) ); \int_b_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(9), Q => \^b_read_reg_102_reg[15]\(9), R => \^sr\(0) ); int_gie_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \waddr_reg_n_0_[3]\, I3 => \waddr_reg_n_0_[2]\, I4 => \int_ier[1]_i_2_n_0\, I5 => int_gie_reg_n_0, O => int_gie_i_1_n_0 ); int_gie_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_gie_i_1_n_0, Q => int_gie_reg_n_0, R => \^sr\(0) ); \int_ier[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFBFFFFF00800000" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, I4 => \waddr_reg_n_0_[3]\, I5 => \int_ier_reg_n_0_[0]\, O => \int_ier[0]_i_1_n_0\ ); \int_ier[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFBFFFFF00800000" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, I4 => \waddr_reg_n_0_[3]\, I5 => \int_ier_reg_n_0_[1]\, O => \int_ier[1]_i_1_n_0\ ); \int_ier[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => \waddr_reg_n_0_[1]\, I1 => s_axi_gcd_bus_WVALID, I2 => \^out\(1), I3 => \waddr_reg_n_0_[5]\, I4 => \waddr_reg_n_0_[0]\, I5 => \waddr_reg_n_0_[4]\, O => \int_ier[1]_i_2_n_0\ ); \int_ier_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[0]_i_1_n_0\, Q => \int_ier_reg_n_0_[0]\, R => \^sr\(0) ); \int_ier_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[1]_i_1_n_0\, Q => \int_ier_reg_n_0_[1]\, R => \^sr\(0) ); \int_isr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F7777777F8888888" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => int_isr6_out, I2 => \int_ier_reg_n_0_[0]\, I3 => \^co\(0), I4 => Q(2), I5 => \int_isr_reg_n_0_[0]\, O => \int_isr[0]_i_1_n_0\ ); \int_isr[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => s_axi_gcd_bus_WSTRB(0), I1 => \waddr_reg_n_0_[2]\, I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[3]\, O => int_isr6_out ); \int_isr[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F7777777F8888888" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => int_isr6_out, I2 => \int_ier_reg_n_0_[1]\, I3 => \^co\(0), I4 => Q(2), I5 => p_1_in, O => \int_isr[1]_i_1_n_0\ ); \int_isr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[0]_i_1_n_0\, Q => \int_isr_reg_n_0_[0]\, R => \^sr\(0) ); \int_isr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[1]_i_1_n_0\, Q => p_1_in, R => \^sr\(0) ); int_pResult_ap_vld_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"8FFFFFFF88888888" ) port map ( I0 => Q(2), I1 => \^co\(0), I2 => \^s_axi_gcd_bus_rvalid\(0), I3 => s_axi_gcd_bus_ARVALID, I4 => int_pResult_ap_vld1, I5 => int_pResult_ap_vld, O => int_pResult_ap_vld_i_1_n_0 ); int_pResult_ap_vld_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000001000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(1), I1 => s_axi_gcd_bus_ARADDR(4), I2 => s_axi_gcd_bus_ARADDR(5), I3 => s_axi_gcd_bus_ARADDR(2), I4 => s_axi_gcd_bus_ARADDR(3), I5 => s_axi_gcd_bus_ARADDR(0), O => int_pResult_ap_vld1 ); int_pResult_ap_vld_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => int_pResult_ap_vld_i_1_n_0, Q => int_pResult_ap_vld, R => \^sr\(0) ); \int_pResult_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(0), Q => int_pResult(0), R => \^sr\(0) ); \int_pResult_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(10), Q => int_pResult(10), R => \^sr\(0) ); \int_pResult_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(11), Q => int_pResult(11), R => \^sr\(0) ); \int_pResult_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(12), Q => int_pResult(12), R => \^sr\(0) ); \int_pResult_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(13), Q => int_pResult(13), R => \^sr\(0) ); \int_pResult_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(14), Q => int_pResult(14), R => \^sr\(0) ); \int_pResult_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(15), Q => int_pResult(15), R => \^sr\(0) ); \int_pResult_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(1), Q => int_pResult(1), R => \^sr\(0) ); \int_pResult_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(2), Q => int_pResult(2), R => \^sr\(0) ); \int_pResult_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(3), Q => int_pResult(3), R => \^sr\(0) ); \int_pResult_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(4), Q => int_pResult(4), R => \^sr\(0) ); \int_pResult_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(5), Q => int_pResult(5), R => \^sr\(0) ); \int_pResult_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(6), Q => int_pResult(6), R => \^sr\(0) ); \int_pResult_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(7), Q => int_pResult(7), R => \^sr\(0) ); \int_pResult_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(8), Q => int_pResult(8), R => \^sr\(0) ); \int_pResult_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(9), Q => int_pResult(9), R => \^sr\(0) ); interrupt_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => p_1_in, I1 => \int_isr_reg_n_0_[0]\, I2 => int_gie_reg_n_0, O => interrupt ); \rdata[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata[0]_i_2_n_0\, I1 => s_axi_gcd_bus_ARADDR(2), I2 => \rdata[0]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_gcd_bus_rdata\(0), O => \rdata[0]_i_1_n_0\ ); \rdata[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \int_ier_reg_n_0_[0]\, I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(0), I3 => s_axi_gcd_bus_ARADDR(5), I4 => s_axi_gcd_bus_ARADDR(3), I5 => \rdata[0]_i_4_n_0\, O => \rdata[0]_i_2_n_0\ ); \rdata[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033223000002230" ) port map ( I0 => int_pResult_ap_vld, I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_gie_reg_n_0, I3 => s_axi_gcd_bus_ARADDR(5), I4 => s_axi_gcd_bus_ARADDR(3), I5 => \int_isr_reg_n_0_[0]\, O => \rdata[0]_i_3_n_0\ ); \rdata[0]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(0), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(0), I3 => s_axi_gcd_bus_ARADDR(5), I4 => ap_start, O => \rdata[0]_i_4_n_0\ ); \rdata[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(10), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(10), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(10), O => \rdata[10]_i_1_n_0\ ); \rdata[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(11), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(11), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(11), O => \rdata[11]_i_1_n_0\ ); \rdata[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(12), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(12), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(12), O => \rdata[12]_i_1_n_0\ ); \rdata[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(13), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(13), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(13), O => \rdata[13]_i_1_n_0\ ); \rdata[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(14), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(14), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(14), O => \rdata[14]_i_1_n_0\ ); \rdata[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88888880" ) port map ( I0 => s_axi_gcd_bus_ARVALID, I1 => \^s_axi_gcd_bus_rvalid\(0), I2 => s_axi_gcd_bus_ARADDR(1), I3 => s_axi_gcd_bus_ARADDR(0), I4 => s_axi_gcd_bus_ARADDR(2), O => \rdata[15]_i_1_n_0\ ); \rdata[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^s_axi_gcd_bus_rvalid\(0), I1 => s_axi_gcd_bus_ARVALID, O => ar_hs ); \rdata[15]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(15), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(15), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(15), O => \rdata[15]_i_3_n_0\ ); \rdata[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata[1]_i_2_n_0\, I1 => s_axi_gcd_bus_ARADDR(2), I2 => \rdata[1]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_gcd_bus_rdata\(1), O => \rdata[1]_i_1_n_0\ ); \rdata[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \int_ier_reg_n_0_[1]\, I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(1), I3 => s_axi_gcd_bus_ARADDR(5), I4 => s_axi_gcd_bus_ARADDR(3), I5 => \rdata[1]_i_5_n_0\, O => \rdata[1]_i_2_n_0\ ); \rdata[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(4), I1 => s_axi_gcd_bus_ARADDR(5), I2 => s_axi_gcd_bus_ARADDR(3), I3 => p_1_in, O => \rdata[1]_i_3_n_0\ ); \rdata[1]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => s_axi_gcd_bus_ARADDR(1), I1 => s_axi_gcd_bus_ARADDR(0), O => \rdata[1]_i_4_n_0\ ); \rdata[1]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(1), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(1), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_ap_done, O => \rdata[1]_i_5_n_0\ ); \rdata[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(2), I3 => s_axi_gcd_bus_ARADDR(3), I4 => \rdata[2]_i_2_n_0\, O => \rdata[2]_i_1_n_0\ ); \rdata[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(2), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(2), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_ap_idle, O => \rdata[2]_i_2_n_0\ ); \rdata[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(3), I3 => s_axi_gcd_bus_ARADDR(3), I4 => \rdata[3]_i_2_n_0\, O => \rdata[3]_i_1_n_0\ ); \rdata[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(3), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(3), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_ap_ready, O => \rdata[3]_i_2_n_0\ ); \rdata[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(4), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(4), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(4), O => \rdata[4]_i_1_n_0\ ); \rdata[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(5), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(5), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(5), O => \rdata[5]_i_1_n_0\ ); \rdata[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(6), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(6), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(6), O => \rdata[6]_i_1_n_0\ ); \rdata[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(7), I3 => s_axi_gcd_bus_ARADDR(3), I4 => \rdata[7]_i_2_n_0\, O => \rdata[7]_i_1_n_0\ ); \rdata[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(7), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(7), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_auto_restart, O => \rdata[7]_i_2_n_0\ ); \rdata[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(8), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(8), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(8), O => \rdata[8]_i_1_n_0\ ); \rdata[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(9), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(9), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(9), O => \rdata[9]_i_1_n_0\ ); \rdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[0]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(0), R => '0' ); \rdata_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[10]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(10), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[11]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(11), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[12]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(12), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[13]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(13), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[14]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(14), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[15]_i_3_n_0\, Q => \^s_axi_gcd_bus_rdata\(15), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[1]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(1), R => '0' ); \rdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[2]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(2), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[3]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(3), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[4]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(4), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[5]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(5), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[6]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(6), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[7]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(7), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[8]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(8), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[9]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(9), R => \rdata[15]_i_1_n_0\ ); \waddr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^out\(0), I1 => s_axi_gcd_bus_AWVALID, O => waddr ); \waddr_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(0), Q => \waddr_reg_n_0_[0]\, R => '0' ); \waddr_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(1), Q => \waddr_reg_n_0_[1]\, R => '0' ); \waddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(2), Q => \waddr_reg_n_0_[2]\, R => '0' ); \waddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(3), Q => \waddr_reg_n_0_[3]\, R => '0' ); \waddr_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(4), Q => \waddr_reg_n_0_[4]\, R => '0' ); \waddr_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(5), Q => \waddr_reg_n_0_[5]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_gcd_0_0_gcd is port ( ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_AWREADY : out STD_LOGIC; s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WREADY : out STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_ARREADY : out STD_LOGIC; s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BVALID : out STD_LOGIC; s_axi_gcd_bus_BREADY : in STD_LOGIC; s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); interrupt : out STD_LOGIC ); attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of gcd_zynq_snick_gcd_0_0_gcd : entity is 32; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of gcd_zynq_snick_gcd_0_0_gcd : entity is 6; attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer; attribute C_S_AXI_GCD_BUS_DATA_WIDTH of gcd_zynq_snick_gcd_0_0_gcd : entity is 32; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of gcd_zynq_snick_gcd_0_0_gcd : entity is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of gcd_zynq_snick_gcd_0_0_gcd : entity is 4; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_gcd_0_0_gcd : entity is "gcd"; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of gcd_zynq_snick_gcd_0_0_gcd : entity is "4'b0001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of gcd_zynq_snick_gcd_0_0_gcd : entity is "4'b0010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of gcd_zynq_snick_gcd_0_0_gcd : entity is "4'b0100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of gcd_zynq_snick_gcd_0_0_gcd : entity is "4'b1000"; attribute hls_module : string; attribute hls_module of gcd_zynq_snick_gcd_0_0_gcd : entity is "yes"; end gcd_zynq_snick_gcd_0_0_gcd; architecture STRUCTURE of gcd_zynq_snick_gcd_0_0_gcd is signal \<const0>\ : STD_LOGIC; signal a : STD_LOGIC_VECTOR ( 15 downto 0 ); signal a_assign_fu_78_p21_out : STD_LOGIC_VECTOR ( 15 downto 0 ); signal a_assign_reg_121 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal a_assign_reg_1210 : STD_LOGIC; signal \a_assign_reg_121[11]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[11]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[11]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[11]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_3\ : STD_LOGIC; signal \a_assign_reg_121_reg[15]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[15]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[15]_i_1_n_3\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_3\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_3\ : STD_LOGIC; signal a_read_reg_107 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC; signal ap_CS_fsm_state2 : STD_LOGIC; signal ap_CS_fsm_state3 : STD_LOGIC; signal ap_CS_fsm_state4 : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ap_NS_fsm1 : STD_LOGIC; signal ap_rst_n_inv : STD_LOGIC; signal b : STD_LOGIC_VECTOR ( 15 downto 0 ); signal b_assign_fu_84_p20_out : STD_LOGIC_VECTOR ( 15 downto 0 ); signal b_assign_reg_126 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \b_assign_reg_126[11]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[11]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[11]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[11]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_3\ : STD_LOGIC; signal \b_assign_reg_126_reg[15]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[15]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[15]_i_1_n_3\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_3\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_3\ : STD_LOGIC; signal b_read_reg_102 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 ); signal p_s_reg_45 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \p_s_reg_45[0]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[10]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[11]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[12]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[13]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[14]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[15]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[15]_i_2_n_0\ : STD_LOGIC; signal \p_s_reg_45[1]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[2]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[3]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[4]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[5]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[6]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[7]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[8]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[9]_i_1_n_0\ : STD_LOGIC; signal result_reg_56 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \result_reg_56[15]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal tmp_2_fu_66_p2 : STD_LOGIC; signal tmp_3_fu_72_p2 : STD_LOGIC; signal tmp_3_reg_115 : STD_LOGIC; signal \tmp_3_reg_115[0]_i_10_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_11_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_12_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_13_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_14_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_15_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_16_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_17_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_18_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_3_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_4_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_5_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_6_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_7_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_8_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_9_n_0\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_1_n_1\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_1_n_2\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_1_n_3\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_0\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_1\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_2\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_3\ : STD_LOGIC; signal \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute FSM_ENCODING : string; attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none"; begin s_axi_gcd_bus_BRESP(1) <= \<const0>\; s_axi_gcd_bus_BRESP(0) <= \<const0>\; s_axi_gcd_bus_RDATA(31) <= \<const0>\; s_axi_gcd_bus_RDATA(30) <= \<const0>\; s_axi_gcd_bus_RDATA(29) <= \<const0>\; s_axi_gcd_bus_RDATA(28) <= \<const0>\; s_axi_gcd_bus_RDATA(27) <= \<const0>\; s_axi_gcd_bus_RDATA(26) <= \<const0>\; s_axi_gcd_bus_RDATA(25) <= \<const0>\; s_axi_gcd_bus_RDATA(24) <= \<const0>\; s_axi_gcd_bus_RDATA(23) <= \<const0>\; s_axi_gcd_bus_RDATA(22) <= \<const0>\; s_axi_gcd_bus_RDATA(21) <= \<const0>\; s_axi_gcd_bus_RDATA(20) <= \<const0>\; s_axi_gcd_bus_RDATA(19) <= \<const0>\; s_axi_gcd_bus_RDATA(18) <= \<const0>\; s_axi_gcd_bus_RDATA(17) <= \<const0>\; s_axi_gcd_bus_RDATA(16) <= \<const0>\; s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0); s_axi_gcd_bus_RRESP(1) <= \<const0>\; s_axi_gcd_bus_RRESP(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \a_assign_reg_121[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(11), I1 => p_s_reg_45(11), O => \a_assign_reg_121[11]_i_2_n_0\ ); \a_assign_reg_121[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(10), I1 => p_s_reg_45(10), O => \a_assign_reg_121[11]_i_3_n_0\ ); \a_assign_reg_121[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(9), I1 => p_s_reg_45(9), O => \a_assign_reg_121[11]_i_4_n_0\ ); \a_assign_reg_121[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(8), I1 => p_s_reg_45(8), O => \a_assign_reg_121[11]_i_5_n_0\ ); \a_assign_reg_121[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(15), I1 => p_s_reg_45(15), O => \a_assign_reg_121[15]_i_2_n_0\ ); \a_assign_reg_121[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(14), I1 => p_s_reg_45(14), O => \a_assign_reg_121[15]_i_3_n_0\ ); \a_assign_reg_121[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(13), I1 => p_s_reg_45(13), O => \a_assign_reg_121[15]_i_4_n_0\ ); \a_assign_reg_121[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(12), I1 => p_s_reg_45(12), O => \a_assign_reg_121[15]_i_5_n_0\ ); \a_assign_reg_121[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(3), I1 => p_s_reg_45(3), O => \a_assign_reg_121[3]_i_2_n_0\ ); \a_assign_reg_121[3]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(2), I1 => p_s_reg_45(2), O => \a_assign_reg_121[3]_i_3_n_0\ ); \a_assign_reg_121[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(1), I1 => p_s_reg_45(1), O => \a_assign_reg_121[3]_i_4_n_0\ ); \a_assign_reg_121[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(0), I1 => p_s_reg_45(0), O => \a_assign_reg_121[3]_i_5_n_0\ ); \a_assign_reg_121[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(7), I1 => p_s_reg_45(7), O => \a_assign_reg_121[7]_i_2_n_0\ ); \a_assign_reg_121[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(6), I1 => p_s_reg_45(6), O => \a_assign_reg_121[7]_i_3_n_0\ ); \a_assign_reg_121[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(5), I1 => p_s_reg_45(5), O => \a_assign_reg_121[7]_i_4_n_0\ ); \a_assign_reg_121[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(4), I1 => p_s_reg_45(4), O => \a_assign_reg_121[7]_i_5_n_0\ ); \a_assign_reg_121_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(0), Q => a_assign_reg_121(0), R => '0' ); \a_assign_reg_121_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(10), Q => a_assign_reg_121(10), R => '0' ); \a_assign_reg_121_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(11), Q => a_assign_reg_121(11), R => '0' ); \a_assign_reg_121_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \a_assign_reg_121_reg[7]_i_1_n_0\, CO(3) => \a_assign_reg_121_reg[11]_i_1_n_0\, CO(2) => \a_assign_reg_121_reg[11]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[11]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[11]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => result_reg_56(11 downto 8), O(3 downto 0) => a_assign_fu_78_p21_out(11 downto 8), S(3) => \a_assign_reg_121[11]_i_2_n_0\, S(2) => \a_assign_reg_121[11]_i_3_n_0\, S(1) => \a_assign_reg_121[11]_i_4_n_0\, S(0) => \a_assign_reg_121[11]_i_5_n_0\ ); \a_assign_reg_121_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(12), Q => a_assign_reg_121(12), R => '0' ); \a_assign_reg_121_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(13), Q => a_assign_reg_121(13), R => '0' ); \a_assign_reg_121_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(14), Q => a_assign_reg_121(14), R => '0' ); \a_assign_reg_121_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(15), Q => a_assign_reg_121(15), R => '0' ); \a_assign_reg_121_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \a_assign_reg_121_reg[11]_i_1_n_0\, CO(3) => \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\(3), CO(2) => \a_assign_reg_121_reg[15]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[15]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => result_reg_56(14 downto 12), O(3 downto 0) => a_assign_fu_78_p21_out(15 downto 12), S(3) => \a_assign_reg_121[15]_i_2_n_0\, S(2) => \a_assign_reg_121[15]_i_3_n_0\, S(1) => \a_assign_reg_121[15]_i_4_n_0\, S(0) => \a_assign_reg_121[15]_i_5_n_0\ ); \a_assign_reg_121_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(1), Q => a_assign_reg_121(1), R => '0' ); \a_assign_reg_121_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(2), Q => a_assign_reg_121(2), R => '0' ); \a_assign_reg_121_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(3), Q => a_assign_reg_121(3), R => '0' ); \a_assign_reg_121_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \a_assign_reg_121_reg[3]_i_1_n_0\, CO(2) => \a_assign_reg_121_reg[3]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[3]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[3]_i_1_n_3\, CYINIT => '1', DI(3 downto 0) => result_reg_56(3 downto 0), O(3 downto 0) => a_assign_fu_78_p21_out(3 downto 0), S(3) => \a_assign_reg_121[3]_i_2_n_0\, S(2) => \a_assign_reg_121[3]_i_3_n_0\, S(1) => \a_assign_reg_121[3]_i_4_n_0\, S(0) => \a_assign_reg_121[3]_i_5_n_0\ ); \a_assign_reg_121_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(4), Q => a_assign_reg_121(4), R => '0' ); \a_assign_reg_121_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(5), Q => a_assign_reg_121(5), R => '0' ); \a_assign_reg_121_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(6), Q => a_assign_reg_121(6), R => '0' ); \a_assign_reg_121_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(7), Q => a_assign_reg_121(7), R => '0' ); \a_assign_reg_121_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \a_assign_reg_121_reg[3]_i_1_n_0\, CO(3) => \a_assign_reg_121_reg[7]_i_1_n_0\, CO(2) => \a_assign_reg_121_reg[7]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[7]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[7]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => result_reg_56(7 downto 4), O(3 downto 0) => a_assign_fu_78_p21_out(7 downto 4), S(3) => \a_assign_reg_121[7]_i_2_n_0\, S(2) => \a_assign_reg_121[7]_i_3_n_0\, S(1) => \a_assign_reg_121[7]_i_4_n_0\, S(0) => \a_assign_reg_121[7]_i_5_n_0\ ); \a_assign_reg_121_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(8), Q => a_assign_reg_121(8), R => '0' ); \a_assign_reg_121_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(9), Q => a_assign_reg_121(9), R => '0' ); \a_read_reg_107_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(0), Q => a_read_reg_107(0), R => '0' ); \a_read_reg_107_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(10), Q => a_read_reg_107(10), R => '0' ); \a_read_reg_107_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(11), Q => a_read_reg_107(11), R => '0' ); \a_read_reg_107_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(12), Q => a_read_reg_107(12), R => '0' ); \a_read_reg_107_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(13), Q => a_read_reg_107(13), R => '0' ); \a_read_reg_107_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(14), Q => a_read_reg_107(14), R => '0' ); \a_read_reg_107_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(15), Q => a_read_reg_107(15), R => '0' ); \a_read_reg_107_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(1), Q => a_read_reg_107(1), R => '0' ); \a_read_reg_107_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(2), Q => a_read_reg_107(2), R => '0' ); \a_read_reg_107_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(3), Q => a_read_reg_107(3), R => '0' ); \a_read_reg_107_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(4), Q => a_read_reg_107(4), R => '0' ); \a_read_reg_107_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(5), Q => a_read_reg_107(5), R => '0' ); \a_read_reg_107_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(6), Q => a_read_reg_107(6), R => '0' ); \a_read_reg_107_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(7), Q => a_read_reg_107(7), R => '0' ); \a_read_reg_107_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(8), Q => a_read_reg_107(8), R => '0' ); \a_read_reg_107_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(9), Q => a_read_reg_107(9), R => '0' ); \ap_CS_fsm[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => ap_CS_fsm_state2, I1 => ap_CS_fsm_state4, O => ap_NS_fsm(2) ); \ap_CS_fsm[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ap_CS_fsm_state3, I1 => tmp_2_fu_66_p2, O => a_assign_reg_1210 ); \ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(0), Q => \ap_CS_fsm_reg_n_0_[0]\, S => ap_rst_n_inv ); \ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(1), Q => ap_CS_fsm_state2, R => ap_rst_n_inv ); \ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(2), Q => ap_CS_fsm_state3, R => ap_rst_n_inv ); \ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => a_assign_reg_1210, Q => ap_CS_fsm_state4, R => ap_rst_n_inv ); \b_assign_reg_126[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(11), I1 => result_reg_56(11), O => \b_assign_reg_126[11]_i_2_n_0\ ); \b_assign_reg_126[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(10), I1 => result_reg_56(10), O => \b_assign_reg_126[11]_i_3_n_0\ ); \b_assign_reg_126[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(9), I1 => result_reg_56(9), O => \b_assign_reg_126[11]_i_4_n_0\ ); \b_assign_reg_126[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(8), I1 => result_reg_56(8), O => \b_assign_reg_126[11]_i_5_n_0\ ); \b_assign_reg_126[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(15), I1 => result_reg_56(15), O => \b_assign_reg_126[15]_i_2_n_0\ ); \b_assign_reg_126[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(14), I1 => result_reg_56(14), O => \b_assign_reg_126[15]_i_3_n_0\ ); \b_assign_reg_126[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(13), I1 => result_reg_56(13), O => \b_assign_reg_126[15]_i_4_n_0\ ); \b_assign_reg_126[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(12), I1 => result_reg_56(12), O => \b_assign_reg_126[15]_i_5_n_0\ ); \b_assign_reg_126[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(3), I1 => result_reg_56(3), O => \b_assign_reg_126[3]_i_2_n_0\ ); \b_assign_reg_126[3]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(2), I1 => result_reg_56(2), O => \b_assign_reg_126[3]_i_3_n_0\ ); \b_assign_reg_126[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(1), I1 => result_reg_56(1), O => \b_assign_reg_126[3]_i_4_n_0\ ); \b_assign_reg_126[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(0), I1 => result_reg_56(0), O => \b_assign_reg_126[3]_i_5_n_0\ ); \b_assign_reg_126[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(7), I1 => result_reg_56(7), O => \b_assign_reg_126[7]_i_2_n_0\ ); \b_assign_reg_126[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(6), I1 => result_reg_56(6), O => \b_assign_reg_126[7]_i_3_n_0\ ); \b_assign_reg_126[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(5), I1 => result_reg_56(5), O => \b_assign_reg_126[7]_i_4_n_0\ ); \b_assign_reg_126[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(4), I1 => result_reg_56(4), O => \b_assign_reg_126[7]_i_5_n_0\ ); \b_assign_reg_126_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(0), Q => b_assign_reg_126(0), R => '0' ); \b_assign_reg_126_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(10), Q => b_assign_reg_126(10), R => '0' ); \b_assign_reg_126_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(11), Q => b_assign_reg_126(11), R => '0' ); \b_assign_reg_126_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \b_assign_reg_126_reg[7]_i_1_n_0\, CO(3) => \b_assign_reg_126_reg[11]_i_1_n_0\, CO(2) => \b_assign_reg_126_reg[11]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[11]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[11]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => p_s_reg_45(11 downto 8), O(3 downto 0) => b_assign_fu_84_p20_out(11 downto 8), S(3) => \b_assign_reg_126[11]_i_2_n_0\, S(2) => \b_assign_reg_126[11]_i_3_n_0\, S(1) => \b_assign_reg_126[11]_i_4_n_0\, S(0) => \b_assign_reg_126[11]_i_5_n_0\ ); \b_assign_reg_126_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(12), Q => b_assign_reg_126(12), R => '0' ); \b_assign_reg_126_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(13), Q => b_assign_reg_126(13), R => '0' ); \b_assign_reg_126_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(14), Q => b_assign_reg_126(14), R => '0' ); \b_assign_reg_126_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(15), Q => b_assign_reg_126(15), R => '0' ); \b_assign_reg_126_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \b_assign_reg_126_reg[11]_i_1_n_0\, CO(3) => \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\(3), CO(2) => \b_assign_reg_126_reg[15]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[15]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => p_s_reg_45(14 downto 12), O(3 downto 0) => b_assign_fu_84_p20_out(15 downto 12), S(3) => \b_assign_reg_126[15]_i_2_n_0\, S(2) => \b_assign_reg_126[15]_i_3_n_0\, S(1) => \b_assign_reg_126[15]_i_4_n_0\, S(0) => \b_assign_reg_126[15]_i_5_n_0\ ); \b_assign_reg_126_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(1), Q => b_assign_reg_126(1), R => '0' ); \b_assign_reg_126_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(2), Q => b_assign_reg_126(2), R => '0' ); \b_assign_reg_126_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(3), Q => b_assign_reg_126(3), R => '0' ); \b_assign_reg_126_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \b_assign_reg_126_reg[3]_i_1_n_0\, CO(2) => \b_assign_reg_126_reg[3]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[3]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[3]_i_1_n_3\, CYINIT => '1', DI(3 downto 0) => p_s_reg_45(3 downto 0), O(3 downto 0) => b_assign_fu_84_p20_out(3 downto 0), S(3) => \b_assign_reg_126[3]_i_2_n_0\, S(2) => \b_assign_reg_126[3]_i_3_n_0\, S(1) => \b_assign_reg_126[3]_i_4_n_0\, S(0) => \b_assign_reg_126[3]_i_5_n_0\ ); \b_assign_reg_126_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(4), Q => b_assign_reg_126(4), R => '0' ); \b_assign_reg_126_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(5), Q => b_assign_reg_126(5), R => '0' ); \b_assign_reg_126_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(6), Q => b_assign_reg_126(6), R => '0' ); \b_assign_reg_126_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(7), Q => b_assign_reg_126(7), R => '0' ); \b_assign_reg_126_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \b_assign_reg_126_reg[3]_i_1_n_0\, CO(3) => \b_assign_reg_126_reg[7]_i_1_n_0\, CO(2) => \b_assign_reg_126_reg[7]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[7]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[7]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => p_s_reg_45(7 downto 4), O(3 downto 0) => b_assign_fu_84_p20_out(7 downto 4), S(3) => \b_assign_reg_126[7]_i_2_n_0\, S(2) => \b_assign_reg_126[7]_i_3_n_0\, S(1) => \b_assign_reg_126[7]_i_4_n_0\, S(0) => \b_assign_reg_126[7]_i_5_n_0\ ); \b_assign_reg_126_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(8), Q => b_assign_reg_126(8), R => '0' ); \b_assign_reg_126_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(9), Q => b_assign_reg_126(9), R => '0' ); \b_read_reg_102_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(0), Q => b_read_reg_102(0), R => '0' ); \b_read_reg_102_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(10), Q => b_read_reg_102(10), R => '0' ); \b_read_reg_102_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(11), Q => b_read_reg_102(11), R => '0' ); \b_read_reg_102_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(12), Q => b_read_reg_102(12), R => '0' ); \b_read_reg_102_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(13), Q => b_read_reg_102(13), R => '0' ); \b_read_reg_102_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(14), Q => b_read_reg_102(14), R => '0' ); \b_read_reg_102_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(15), Q => b_read_reg_102(15), R => '0' ); \b_read_reg_102_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(1), Q => b_read_reg_102(1), R => '0' ); \b_read_reg_102_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(2), Q => b_read_reg_102(2), R => '0' ); \b_read_reg_102_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(3), Q => b_read_reg_102(3), R => '0' ); \b_read_reg_102_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(4), Q => b_read_reg_102(4), R => '0' ); \b_read_reg_102_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(5), Q => b_read_reg_102(5), R => '0' ); \b_read_reg_102_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(6), Q => b_read_reg_102(6), R => '0' ); \b_read_reg_102_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(7), Q => b_read_reg_102(7), R => '0' ); \b_read_reg_102_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(8), Q => b_read_reg_102(8), R => '0' ); \b_read_reg_102_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(9), Q => b_read_reg_102(9), R => '0' ); gcd_gcd_bus_s_axi_U: entity work.gcd_zynq_snick_gcd_0_0_gcd_gcd_bus_s_axi port map ( CO(0) => tmp_2_fu_66_p2, D(1 downto 0) => ap_NS_fsm(1 downto 0), E(0) => ap_NS_fsm1, Q(3) => ap_CS_fsm_state4, Q(2) => ap_CS_fsm_state3, Q(1) => ap_CS_fsm_state2, Q(0) => \ap_CS_fsm_reg_n_0_[0]\, SR(0) => ap_rst_n_inv, \a_read_reg_107_reg[15]\(15 downto 0) => a(15 downto 0), ap_clk => ap_clk, ap_rst_n => ap_rst_n, \b_read_reg_102_reg[15]\(15 downto 0) => b(15 downto 0), interrupt => interrupt, \out\(2) => s_axi_gcd_bus_BVALID, \out\(1) => s_axi_gcd_bus_WREADY, \out\(0) => s_axi_gcd_bus_AWREADY, \p_s_reg_45_reg[15]\(15 downto 0) => p_s_reg_45(15 downto 0), \result_reg_56_reg[15]\(15 downto 0) => result_reg_56(15 downto 0), s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0), s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID, s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0), s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY, s_axi_gcd_bus_RDATA(15 downto 0) => \^s_axi_gcd_bus_rdata\(15 downto 0), s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY, s_axi_gcd_bus_RVALID(1) => s_axi_gcd_bus_RVALID, s_axi_gcd_bus_RVALID(0) => s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_WDATA(15 downto 0) => s_axi_gcd_bus_WDATA(15 downto 0), s_axi_gcd_bus_WSTRB(1 downto 0) => s_axi_gcd_bus_WSTRB(1 downto 0), s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID ); \p_s_reg_45[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(0), I1 => b_read_reg_102(0), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[0]_i_1_n_0\ ); \p_s_reg_45[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(10), I1 => b_read_reg_102(10), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[10]_i_1_n_0\ ); \p_s_reg_45[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(11), I1 => b_read_reg_102(11), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[11]_i_1_n_0\ ); \p_s_reg_45[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(12), I1 => b_read_reg_102(12), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[12]_i_1_n_0\ ); \p_s_reg_45[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(13), I1 => b_read_reg_102(13), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[13]_i_1_n_0\ ); \p_s_reg_45[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(14), I1 => b_read_reg_102(14), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[14]_i_1_n_0\ ); \p_s_reg_45[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"74" ) port map ( I0 => tmp_3_reg_115, I1 => ap_CS_fsm_state4, I2 => ap_CS_fsm_state2, O => \p_s_reg_45[15]_i_1_n_0\ ); \p_s_reg_45[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(15), I1 => b_read_reg_102(15), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[15]_i_2_n_0\ ); \p_s_reg_45[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(1), I1 => b_read_reg_102(1), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[1]_i_1_n_0\ ); \p_s_reg_45[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(2), I1 => b_read_reg_102(2), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[2]_i_1_n_0\ ); \p_s_reg_45[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(3), I1 => b_read_reg_102(3), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[3]_i_1_n_0\ ); \p_s_reg_45[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(4), I1 => b_read_reg_102(4), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[4]_i_1_n_0\ ); \p_s_reg_45[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(5), I1 => b_read_reg_102(5), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[5]_i_1_n_0\ ); \p_s_reg_45[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(6), I1 => b_read_reg_102(6), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[6]_i_1_n_0\ ); \p_s_reg_45[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(7), I1 => b_read_reg_102(7), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[7]_i_1_n_0\ ); \p_s_reg_45[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(8), I1 => b_read_reg_102(8), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[8]_i_1_n_0\ ); \p_s_reg_45[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(9), I1 => b_read_reg_102(9), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[9]_i_1_n_0\ ); \p_s_reg_45_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[0]_i_1_n_0\, Q => p_s_reg_45(0), R => '0' ); \p_s_reg_45_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[10]_i_1_n_0\, Q => p_s_reg_45(10), R => '0' ); \p_s_reg_45_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[11]_i_1_n_0\, Q => p_s_reg_45(11), R => '0' ); \p_s_reg_45_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[12]_i_1_n_0\, Q => p_s_reg_45(12), R => '0' ); \p_s_reg_45_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[13]_i_1_n_0\, Q => p_s_reg_45(13), R => '0' ); \p_s_reg_45_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[14]_i_1_n_0\, Q => p_s_reg_45(14), R => '0' ); \p_s_reg_45_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[15]_i_2_n_0\, Q => p_s_reg_45(15), R => '0' ); \p_s_reg_45_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[1]_i_1_n_0\, Q => p_s_reg_45(1), R => '0' ); \p_s_reg_45_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[2]_i_1_n_0\, Q => p_s_reg_45(2), R => '0' ); \p_s_reg_45_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[3]_i_1_n_0\, Q => p_s_reg_45(3), R => '0' ); \p_s_reg_45_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[4]_i_1_n_0\, Q => p_s_reg_45(4), R => '0' ); \p_s_reg_45_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[5]_i_1_n_0\, Q => p_s_reg_45(5), R => '0' ); \p_s_reg_45_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[6]_i_1_n_0\, Q => p_s_reg_45(6), R => '0' ); \p_s_reg_45_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[7]_i_1_n_0\, Q => p_s_reg_45(7), R => '0' ); \p_s_reg_45_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[8]_i_1_n_0\, Q => p_s_reg_45(8), R => '0' ); \p_s_reg_45_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[9]_i_1_n_0\, Q => p_s_reg_45(9), R => '0' ); \result_reg_56[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(0), I1 => a_read_reg_107(0), I2 => ap_CS_fsm_state4, O => p_1_in(0) ); \result_reg_56[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(10), I1 => a_read_reg_107(10), I2 => ap_CS_fsm_state4, O => p_1_in(10) ); \result_reg_56[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(11), I1 => a_read_reg_107(11), I2 => ap_CS_fsm_state4, O => p_1_in(11) ); \result_reg_56[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(12), I1 => a_read_reg_107(12), I2 => ap_CS_fsm_state4, O => p_1_in(12) ); \result_reg_56[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(13), I1 => a_read_reg_107(13), I2 => ap_CS_fsm_state4, O => p_1_in(13) ); \result_reg_56[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(14), I1 => a_read_reg_107(14), I2 => ap_CS_fsm_state4, O => p_1_in(14) ); \result_reg_56[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => tmp_3_reg_115, I1 => ap_CS_fsm_state4, I2 => ap_CS_fsm_state2, O => \result_reg_56[15]_i_1_n_0\ ); \result_reg_56[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(15), I1 => a_read_reg_107(15), I2 => ap_CS_fsm_state4, O => p_1_in(15) ); \result_reg_56[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(1), I1 => a_read_reg_107(1), I2 => ap_CS_fsm_state4, O => p_1_in(1) ); \result_reg_56[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(2), I1 => a_read_reg_107(2), I2 => ap_CS_fsm_state4, O => p_1_in(2) ); \result_reg_56[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(3), I1 => a_read_reg_107(3), I2 => ap_CS_fsm_state4, O => p_1_in(3) ); \result_reg_56[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(4), I1 => a_read_reg_107(4), I2 => ap_CS_fsm_state4, O => p_1_in(4) ); \result_reg_56[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(5), I1 => a_read_reg_107(5), I2 => ap_CS_fsm_state4, O => p_1_in(5) ); \result_reg_56[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(6), I1 => a_read_reg_107(6), I2 => ap_CS_fsm_state4, O => p_1_in(6) ); \result_reg_56[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(7), I1 => a_read_reg_107(7), I2 => ap_CS_fsm_state4, O => p_1_in(7) ); \result_reg_56[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(8), I1 => a_read_reg_107(8), I2 => ap_CS_fsm_state4, O => p_1_in(8) ); \result_reg_56[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(9), I1 => a_read_reg_107(9), I2 => ap_CS_fsm_state4, O => p_1_in(9) ); \result_reg_56_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(0), Q => result_reg_56(0), R => '0' ); \result_reg_56_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(10), Q => result_reg_56(10), R => '0' ); \result_reg_56_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(11), Q => result_reg_56(11), R => '0' ); \result_reg_56_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(12), Q => result_reg_56(12), R => '0' ); \result_reg_56_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(13), Q => result_reg_56(13), R => '0' ); \result_reg_56_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(14), Q => result_reg_56(14), R => '0' ); \result_reg_56_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(15), Q => result_reg_56(15), R => '0' ); \result_reg_56_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(1), Q => result_reg_56(1), R => '0' ); \result_reg_56_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(2), Q => result_reg_56(2), R => '0' ); \result_reg_56_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(3), Q => result_reg_56(3), R => '0' ); \result_reg_56_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(4), Q => result_reg_56(4), R => '0' ); \result_reg_56_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(5), Q => result_reg_56(5), R => '0' ); \result_reg_56_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(6), Q => result_reg_56(6), R => '0' ); \result_reg_56_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(7), Q => result_reg_56(7), R => '0' ); \result_reg_56_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(8), Q => result_reg_56(8), R => '0' ); \result_reg_56_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(9), Q => result_reg_56(9), R => '0' ); \tmp_3_reg_115[0]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(8), I1 => p_s_reg_45(8), I2 => result_reg_56(9), I3 => p_s_reg_45(9), O => \tmp_3_reg_115[0]_i_10_n_0\ ); \tmp_3_reg_115[0]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(6), I1 => p_s_reg_45(6), I2 => p_s_reg_45(7), I3 => result_reg_56(7), O => \tmp_3_reg_115[0]_i_11_n_0\ ); \tmp_3_reg_115[0]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(4), I1 => p_s_reg_45(4), I2 => p_s_reg_45(5), I3 => result_reg_56(5), O => \tmp_3_reg_115[0]_i_12_n_0\ ); \tmp_3_reg_115[0]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(2), I1 => p_s_reg_45(2), I2 => p_s_reg_45(3), I3 => result_reg_56(3), O => \tmp_3_reg_115[0]_i_13_n_0\ ); \tmp_3_reg_115[0]_i_14\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(0), I1 => p_s_reg_45(0), I2 => p_s_reg_45(1), I3 => result_reg_56(1), O => \tmp_3_reg_115[0]_i_14_n_0\ ); \tmp_3_reg_115[0]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(6), I1 => p_s_reg_45(6), I2 => result_reg_56(7), I3 => p_s_reg_45(7), O => \tmp_3_reg_115[0]_i_15_n_0\ ); \tmp_3_reg_115[0]_i_16\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(4), I1 => p_s_reg_45(4), I2 => result_reg_56(5), I3 => p_s_reg_45(5), O => \tmp_3_reg_115[0]_i_16_n_0\ ); \tmp_3_reg_115[0]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(2), I1 => p_s_reg_45(2), I2 => result_reg_56(3), I3 => p_s_reg_45(3), O => \tmp_3_reg_115[0]_i_17_n_0\ ); \tmp_3_reg_115[0]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(0), I1 => p_s_reg_45(0), I2 => result_reg_56(1), I3 => p_s_reg_45(1), O => \tmp_3_reg_115[0]_i_18_n_0\ ); \tmp_3_reg_115[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(14), I1 => p_s_reg_45(14), I2 => result_reg_56(15), I3 => p_s_reg_45(15), O => \tmp_3_reg_115[0]_i_3_n_0\ ); \tmp_3_reg_115[0]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(12), I1 => p_s_reg_45(12), I2 => p_s_reg_45(13), I3 => result_reg_56(13), O => \tmp_3_reg_115[0]_i_4_n_0\ ); \tmp_3_reg_115[0]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(10), I1 => p_s_reg_45(10), I2 => p_s_reg_45(11), I3 => result_reg_56(11), O => \tmp_3_reg_115[0]_i_5_n_0\ ); \tmp_3_reg_115[0]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(8), I1 => p_s_reg_45(8), I2 => p_s_reg_45(9), I3 => result_reg_56(9), O => \tmp_3_reg_115[0]_i_6_n_0\ ); \tmp_3_reg_115[0]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(14), I1 => p_s_reg_45(14), I2 => p_s_reg_45(15), I3 => result_reg_56(15), O => \tmp_3_reg_115[0]_i_7_n_0\ ); \tmp_3_reg_115[0]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(12), I1 => p_s_reg_45(12), I2 => result_reg_56(13), I3 => p_s_reg_45(13), O => \tmp_3_reg_115[0]_i_8_n_0\ ); \tmp_3_reg_115[0]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(10), I1 => p_s_reg_45(10), I2 => result_reg_56(11), I3 => p_s_reg_45(11), O => \tmp_3_reg_115[0]_i_9_n_0\ ); \tmp_3_reg_115_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => tmp_3_fu_72_p2, Q => tmp_3_reg_115, R => '0' ); \tmp_3_reg_115_reg[0]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \tmp_3_reg_115_reg[0]_i_2_n_0\, CO(3) => tmp_3_fu_72_p2, CO(2) => \tmp_3_reg_115_reg[0]_i_1_n_1\, CO(1) => \tmp_3_reg_115_reg[0]_i_1_n_2\, CO(0) => \tmp_3_reg_115_reg[0]_i_1_n_3\, CYINIT => '0', DI(3) => \tmp_3_reg_115[0]_i_3_n_0\, DI(2) => \tmp_3_reg_115[0]_i_4_n_0\, DI(1) => \tmp_3_reg_115[0]_i_5_n_0\, DI(0) => \tmp_3_reg_115[0]_i_6_n_0\, O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \tmp_3_reg_115[0]_i_7_n_0\, S(2) => \tmp_3_reg_115[0]_i_8_n_0\, S(1) => \tmp_3_reg_115[0]_i_9_n_0\, S(0) => \tmp_3_reg_115[0]_i_10_n_0\ ); \tmp_3_reg_115_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \tmp_3_reg_115_reg[0]_i_2_n_0\, CO(2) => \tmp_3_reg_115_reg[0]_i_2_n_1\, CO(1) => \tmp_3_reg_115_reg[0]_i_2_n_2\, CO(0) => \tmp_3_reg_115_reg[0]_i_2_n_3\, CYINIT => '0', DI(3) => \tmp_3_reg_115[0]_i_11_n_0\, DI(2) => \tmp_3_reg_115[0]_i_12_n_0\, DI(1) => \tmp_3_reg_115[0]_i_13_n_0\, DI(0) => \tmp_3_reg_115[0]_i_14_n_0\, O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\(3 downto 0), S(3) => \tmp_3_reg_115[0]_i_15_n_0\, S(2) => \tmp_3_reg_115[0]_i_16_n_0\, S(1) => \tmp_3_reg_115[0]_i_17_n_0\, S(0) => \tmp_3_reg_115[0]_i_18_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_gcd_0_0 is port ( s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_AWREADY : out STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WREADY : out STD_LOGIC; s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BVALID : out STD_LOGIC; s_axi_gcd_bus_BREADY : in STD_LOGIC; s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_ARREADY : out STD_LOGIC; s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of gcd_zynq_snick_gcd_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of gcd_zynq_snick_gcd_0_0 : entity is "gcd_zynq_snick_gcd_0_0,gcd,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of gcd_zynq_snick_gcd_0_0 : entity is "yes"; attribute IP_DEFINITION_SOURCE : string; attribute IP_DEFINITION_SOURCE of gcd_zynq_snick_gcd_0_0 : entity is "HLS"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of gcd_zynq_snick_gcd_0_0 : entity is "gcd,Vivado 2018.2"; attribute hls_module : string; attribute hls_module of gcd_zynq_snick_gcd_0_0 : entity is "yes"; end gcd_zynq_snick_gcd_0_0; architecture STRUCTURE of gcd_zynq_snick_gcd_0_0 is attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of inst : label is 6; attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer; attribute C_S_AXI_GCD_BUS_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of inst : label is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of inst : label is "4'b0001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of inst : label is "4'b0010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of inst : label is "4'b0100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of inst : label is "4'b1000"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST"; attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}"; attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT"; attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_gcd_bus_RREADY : signal is "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB"; begin inst: entity work.gcd_zynq_snick_gcd_0_0_gcd port map ( ap_clk => ap_clk, ap_rst_n => ap_rst_n, interrupt => interrupt, s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0), s_axi_gcd_bus_ARREADY => s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID, s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0), s_axi_gcd_bus_AWREADY => s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY, s_axi_gcd_bus_BRESP(1 downto 0) => s_axi_gcd_bus_BRESP(1 downto 0), s_axi_gcd_bus_BVALID => s_axi_gcd_bus_BVALID, s_axi_gcd_bus_RDATA(31 downto 0) => s_axi_gcd_bus_RDATA(31 downto 0), s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY, s_axi_gcd_bus_RRESP(1 downto 0) => s_axi_gcd_bus_RRESP(1 downto 0), s_axi_gcd_bus_RVALID => s_axi_gcd_bus_RVALID, s_axi_gcd_bus_WDATA(31 downto 0) => s_axi_gcd_bus_WDATA(31 downto 0), s_axi_gcd_bus_WREADY => s_axi_gcd_bus_WREADY, s_axi_gcd_bus_WSTRB(3 downto 0) => s_axi_gcd_bus_WSTRB(3 downto 0), s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID ); end STRUCTURE;
mit
64730381438ab0e6139a3e55ee4dee4b
0.512351
2.503108
false
false
false
false
besm6/micro-besm
tests/2910/vhdl/funct_block_alg_beh/components/reg/test_vectors_reg.vhdl
1
8,642
-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Feb 19, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD -- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD -------------------------------------------------------------------------------- --library ZYCAD; use work.types.all; use work.MVL7_functions.all; use work.synthesis_types.all; entity E is end; architecture AA of E is component creg port ( RLD_BAR : in MVL7; load : in MVL7; decr : in MVL7; clk : in clock; D : in MVL7_VECTOR(11 downto 0); RE : inout MVL7_VECTOR(11 downto 0); Rzero_bar : out MVL7 ); end component; signal RLD_BAR : MVL7; signal load : MVL7; signal decr : MVL7; signal clk : clock; signal D : MVL7_VECTOR(11 downto 0); signal RE : MVL7_VECTOR(11 downto 0); signal Rzero_bar : MVL7; for all : creg use entity work.reg(reg); begin CREG1 : creg port map( RLD_BAR, load, decr, clk, D, RE, Rzero_bar ); process begin -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '1'; load <= '1'; decr <= '0'; D <= "000000000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (Rzero_bar = '0') report "Assert 0 : < Rzero_bar /= 0 >" severity warning; assert (RE = "000000000000") report "Assert 1 : < RE /= 000000000000 >" severity warning; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '1'; load <= '1'; decr <= '0'; D <= "111111111111"; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (Rzero_bar = '1') report "Assert 2 : < Rzero_bar /= 1 >" severity warning; assert (RE = "111111111111") report "Assert 3 : < RE /= 111111111111 >" severity warning; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; load <= '0'; decr <= '0'; D <= "000000000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (Rzero_bar = '0') report "Assert 4 : < Rzero_bar /= 0 >" severity warning; assert (RE = "000000000000") report "Assert 5 : < RE /= 000000000000 >" severity warning; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '1'; load <= '0'; decr <= '0'; D <= "111111111111"; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (Rzero_bar = '0') report "Assert 6 : < Rzero_bar /= 0 >" severity warning; assert (RE = "000000000000") report "Assert 7 : < RE /= 000000000000 >" severity warning; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; load <= '0'; decr <= '0'; D <= "111111111111"; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (Rzero_bar = '1') report "Assert 8 : < Rzero_bar /= 1 >" severity warning; assert (RE = "111111111111") report "Assert 9 : < RE /= 111111111111 >" severity warning; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '1'; load <= '0'; decr <= '0'; D <= "000000000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (Rzero_bar = '1') report "Assert 10 : < Rzero_bar /= 1 >" severity warning; assert (RE = "111111111111") report "Assert 11 : < RE /= 111111111111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111111111"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111111111110") report "Assert 12 : < RE /= 111111111110 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111111110"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111111111101") report "Assert 13 : < RE /= 111111111101 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111111100"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111111111011") report "Assert 14 : < RE /= 111111111011 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111111000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111111110111") report "Assert 15 : < RE /= 111111110111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111110000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111111101111") report "Assert 16 : < RE /= 111111101111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111100000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111111011111") report "Assert 17 : < RE /= 111111011111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111111000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111110111111") report "Assert 18 : < RE /= 111110111111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111110000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111101111111") report "Assert 19 : < RE /= 111101111111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111100000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "111011111111") report "Assert 20 : < RE /= 111011111111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "111000000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "110111111111") report "Assert 21 : < RE /= 110111111111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "110000000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "101111111111") report "Assert 22 : < RE /= 101111111111 >" severity warning; wait for 1 ns; -------------------- -------------------- clk <= '0'; wait for 1 ns; RLD_BAR <= '0'; D <= "100000000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; wait for 1 ns; -------------------- clk <= '0'; wait for 1 ns; decr <= '1'; RLD_BAR <= '1'; wait for 4 ns; clk <= '1'; wait for 4 ns; assert (RE = "011111111111") report "Assert 23 : < RE /= 011111111111 >" severity warning; wait for 1 ns; -------------------- -------------------- end process; end AA;
mit
f160035f94bcc2b589d7f246fbb00ebb
0.48947
2.818656
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
tutorials/xilinx/hls/ug871-design-files/Using_IP_with_Zynq/lab1/hls_macc/vhls_prj/solution1/syn/vhdl/hls_macc.vhd
3
13,090
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2018.2 -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity hls_macc is generic ( C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH : INTEGER := 6; C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWVALID : IN STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWREADY : OUT STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH-1 downto 0); s_axi_HLS_MACC_PERIPH_BUS_WVALID : IN STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WREADY : OUT STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH-1 downto 0); s_axi_HLS_MACC_PERIPH_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH/8-1 downto 0); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : IN STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARREADY : OUT STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH-1 downto 0); s_axi_HLS_MACC_PERIPH_BUS_RVALID : OUT STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : IN STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH-1 downto 0); s_axi_HLS_MACC_PERIPH_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_HLS_MACC_PERIPH_BUS_BVALID : OUT STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BREADY : IN STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC ); end; architecture behav of hls_macc is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "hls_macc,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.115000,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=510,HLS_SYN_LUT=371,HLS_VERSION=2018_2}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (8 downto 0) := "000000010"; constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (8 downto 0) := "000000100"; constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (8 downto 0) := "000001000"; constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (8 downto 0) := "000010000"; constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (8 downto 0) := "000100000"; constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (8 downto 0) := "001000000"; constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (8 downto 0) := "010000000"; constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (8 downto 0) := "100000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_boolean_1 : BOOLEAN := true; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal ap_ready : STD_LOGIC; signal a : STD_LOGIC_VECTOR (31 downto 0); signal b : STD_LOGIC_VECTOR (31 downto 0); signal accum_ap_vld : STD_LOGIC; signal accum_clr : STD_LOGIC_VECTOR (0 downto 0); signal acc_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal accum_clr_read_reg_85 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_57_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_100 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none"; signal tmp_2_fu_74_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_reg_105 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none"; signal ap_CS_fsm_state9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none"; signal p_acc_reg_load_fu_67_p3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0); component hls_macc_mul_32s_bkb IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component hls_macc_HLS_MACC_PERIPH_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; a : OUT STD_LOGIC_VECTOR (31 downto 0); b : OUT STD_LOGIC_VECTOR (31 downto 0); accum : IN STD_LOGIC_VECTOR (31 downto 0); accum_ap_vld : IN STD_LOGIC; accum_clr : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; begin hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U : component hls_macc_HLS_MACC_PERIPH_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, AWREADY => s_axi_HLS_MACC_PERIPH_BUS_AWREADY, AWADDR => s_axi_HLS_MACC_PERIPH_BUS_AWADDR, WVALID => s_axi_HLS_MACC_PERIPH_BUS_WVALID, WREADY => s_axi_HLS_MACC_PERIPH_BUS_WREADY, WDATA => s_axi_HLS_MACC_PERIPH_BUS_WDATA, WSTRB => s_axi_HLS_MACC_PERIPH_BUS_WSTRB, ARVALID => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, ARREADY => s_axi_HLS_MACC_PERIPH_BUS_ARREADY, ARADDR => s_axi_HLS_MACC_PERIPH_BUS_ARADDR, RVALID => s_axi_HLS_MACC_PERIPH_BUS_RVALID, RREADY => s_axi_HLS_MACC_PERIPH_BUS_RREADY, RDATA => s_axi_HLS_MACC_PERIPH_BUS_RDATA, RRESP => s_axi_HLS_MACC_PERIPH_BUS_RRESP, BVALID => s_axi_HLS_MACC_PERIPH_BUS_BVALID, BREADY => s_axi_HLS_MACC_PERIPH_BUS_BREADY, BRESP => s_axi_HLS_MACC_PERIPH_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, a => a, b => b, accum => tmp_2_reg_105, accum_ap_vld => accum_ap_vld, accum_clr => accum_clr); hls_macc_mul_32s_bkb_U1 : component hls_macc_mul_32s_bkb generic map ( ID => 1, NUM_STAGE => 7, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst_n_inv, din0 => b, din1 => a, ce => ap_const_logic_1, dout => grp_fu_57_p2); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state8)) then acc_reg <= tmp_2_fu_74_p2; tmp_2_reg_105 <= tmp_2_fu_74_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then accum_clr_read_reg_85 <= accum_clr; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state7)) then tmp_1_reg_100 <= grp_fu_57_p2; end if; end if; end process; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => ap_NS_fsm <= ap_ST_fsm_state3; when ap_ST_fsm_state3 => ap_NS_fsm <= ap_ST_fsm_state4; when ap_ST_fsm_state4 => ap_NS_fsm <= ap_ST_fsm_state5; when ap_ST_fsm_state5 => ap_NS_fsm <= ap_ST_fsm_state6; when ap_ST_fsm_state6 => ap_NS_fsm <= ap_ST_fsm_state7; when ap_ST_fsm_state7 => ap_NS_fsm <= ap_ST_fsm_state8; when ap_ST_fsm_state8 => ap_NS_fsm <= ap_ST_fsm_state9; when ap_ST_fsm_state9 => ap_NS_fsm <= ap_ST_fsm_state1; when others => ap_NS_fsm <= "XXXXXXXXX"; end case; end process; accum_ap_vld_assign_proc : process(ap_CS_fsm_state9) begin if ((ap_const_logic_1 = ap_CS_fsm_state9)) then accum_ap_vld <= ap_const_logic_1; else accum_ap_vld <= ap_const_logic_0; end if; end process; ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state7 <= ap_CS_fsm(6); ap_CS_fsm_state8 <= ap_CS_fsm(7); ap_CS_fsm_state9 <= ap_CS_fsm(8); ap_done_assign_proc : process(ap_CS_fsm_state9) begin if ((ap_const_logic_1 = ap_CS_fsm_state9)) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_CS_fsm_state9) begin if ((ap_const_logic_1 = ap_CS_fsm_state9)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; p_acc_reg_load_fu_67_p3 <= ap_const_lv32_0 when (accum_clr_read_reg_85(0) = '1') else acc_reg; tmp_2_fu_74_p2 <= std_logic_vector(unsigned(p_acc_reg_load_fu_67_p3) + unsigned(tmp_1_reg_100)); end behav;
mit
59548bc5850c4e99776b251b889c0980
0.567456
3.120381
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_hls_macc_0_0/zybo_zynq_design_hls_macc_0_0_sim_netlist.vhdl
1
191,631
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Sun Sep 22 02:34:40 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_hls_macc_0_0/zybo_zynq_design_hls_macc_0_0_sim_netlist.vhdl -- Design : zybo_zynq_design_hls_macc_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zybo_zynq_design_hls_macc_0_0_hls_macc_HLS_MACC_PERIPH_BUS_s_axi is port ( \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); interrupt : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \a_reg0_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); \buff2_reg__0\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); \accum_clr_read_reg_85_reg[0]\ : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); ap_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); \ap_CS_fsm_reg[4]\ : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_BREADY : in STD_LOGIC; ap_rst_n : in STD_LOGIC; accum_clr_read_reg_85 : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); \acc_reg_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zybo_zynq_design_hls_macc_0_0_hls_macc_HLS_MACC_PERIPH_BUS_s_axi : entity is "hls_macc_HLS_MACC_PERIPH_BUS_s_axi"; end zybo_zynq_design_hls_macc_0_0_hls_macc_HLS_MACC_PERIPH_BUS_s_axi; architecture STRUCTURE of zybo_zynq_design_hls_macc_0_0_hls_macc_HLS_MACC_PERIPH_BUS_s_axi is signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes"; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^a_reg0_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal accum_clr : STD_LOGIC; signal ap_NS_fsm1 : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_start : STD_LOGIC; signal ar_hs : STD_LOGIC; signal \^buff2_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal int_a0 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \int_a[31]_i_1_n_0\ : STD_LOGIC; signal \int_a[31]_i_3_n_0\ : STD_LOGIC; signal int_accum : STD_LOGIC_VECTOR ( 31 downto 0 ); signal int_accum_ap_vld : STD_LOGIC; signal int_accum_ap_vld1 : STD_LOGIC; signal int_accum_ap_vld_i_1_n_0 : STD_LOGIC; signal \int_accum_clr[0]_i_1_n_0\ : STD_LOGIC; signal \int_accum_clr[0]_i_3_n_0\ : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_done1 : STD_LOGIC; signal int_ap_done_i_1_n_0 : STD_LOGIC; signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_start3_out : STD_LOGIC; signal int_ap_start_i_1_n_0 : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_auto_restart_i_1_n_0 : STD_LOGIC; signal int_b0 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \int_b[31]_i_1_n_0\ : STD_LOGIC; signal int_gie_i_1_n_0 : STD_LOGIC; signal int_gie_reg_n_0 : STD_LOGIC; signal \int_ier[0]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_2_n_0\ : STD_LOGIC; signal \int_ier_reg_n_0_[0]\ : STD_LOGIC; signal int_isr6_out : STD_LOGIC; signal \int_isr[0]_i_1_n_0\ : STD_LOGIC; signal \int_isr[1]_i_1_n_0\ : STD_LOGIC; signal \int_isr_reg_n_0_[0]\ : STD_LOGIC; signal \int_isr_reg_n_0_[1]\ : STD_LOGIC; signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP of \^out\ : signal is "yes"; signal p_0_in : STD_LOGIC; signal p_0_in11_in : STD_LOGIC; signal \rdata[0]_i_1_n_0\ : STD_LOGIC; signal \rdata[0]_i_3_n_0\ : STD_LOGIC; signal \rdata[0]_i_4_n_0\ : STD_LOGIC; signal \rdata[0]_i_5_n_0\ : STD_LOGIC; signal \rdata[10]_i_1_n_0\ : STD_LOGIC; signal \rdata[11]_i_1_n_0\ : STD_LOGIC; signal \rdata[12]_i_1_n_0\ : STD_LOGIC; signal \rdata[13]_i_1_n_0\ : STD_LOGIC; signal \rdata[14]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_1_n_0\ : STD_LOGIC; signal \rdata[16]_i_1_n_0\ : STD_LOGIC; signal \rdata[17]_i_1_n_0\ : STD_LOGIC; signal \rdata[18]_i_1_n_0\ : STD_LOGIC; signal \rdata[19]_i_1_n_0\ : STD_LOGIC; signal \rdata[1]_i_1_n_0\ : STD_LOGIC; signal \rdata[1]_i_2_n_0\ : STD_LOGIC; signal \rdata[1]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_4_n_0\ : STD_LOGIC; signal \rdata[1]_i_5_n_0\ : STD_LOGIC; signal \rdata[20]_i_1_n_0\ : STD_LOGIC; signal \rdata[21]_i_1_n_0\ : STD_LOGIC; signal \rdata[22]_i_1_n_0\ : STD_LOGIC; signal \rdata[23]_i_1_n_0\ : STD_LOGIC; signal \rdata[24]_i_1_n_0\ : STD_LOGIC; signal \rdata[25]_i_1_n_0\ : STD_LOGIC; signal \rdata[26]_i_1_n_0\ : STD_LOGIC; signal \rdata[27]_i_1_n_0\ : STD_LOGIC; signal \rdata[28]_i_1_n_0\ : STD_LOGIC; signal \rdata[29]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_2_n_0\ : STD_LOGIC; signal \rdata[30]_i_1_n_0\ : STD_LOGIC; signal \rdata[31]_i_1_n_0\ : STD_LOGIC; signal \rdata[31]_i_3_n_0\ : STD_LOGIC; signal \rdata[3]_i_1_n_0\ : STD_LOGIC; signal \rdata[3]_i_2_n_0\ : STD_LOGIC; signal \rdata[4]_i_1_n_0\ : STD_LOGIC; signal \rdata[5]_i_1_n_0\ : STD_LOGIC; signal \rdata[6]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_2_n_0\ : STD_LOGIC; signal \rdata[8]_i_1_n_0\ : STD_LOGIC; signal \rdata[9]_i_1_n_0\ : STD_LOGIC; signal \rdata_reg[0]_i_2_n_0\ : STD_LOGIC; signal \^s_axi_hls_macc_periph_bus_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_hls_macc_periph_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \^s_axi_hls_macc_periph_bus_rvalid\ : signal is "yes"; signal waddr : STD_LOGIC; signal \waddr_reg_n_0_[0]\ : STD_LOGIC; signal \waddr_reg_n_0_[1]\ : STD_LOGIC; signal \waddr_reg_n_0_[2]\ : STD_LOGIC; signal \waddr_reg_n_0_[3]\ : STD_LOGIC; signal \waddr_reg_n_0_[4]\ : STD_LOGIC; signal \waddr_reg_n_0_[5]\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \accum_clr_read_reg_85[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \ap_CS_fsm[0]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_2\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \int_a[15]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_a[16]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_a[17]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_a[18]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_a[19]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \int_a[20]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[21]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[22]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_a[23]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_a[24]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \int_a[25]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \int_a[26]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \int_a[27]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \int_a[28]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \int_a[29]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \int_a[30]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \int_a[31]_i_2\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of int_ap_start_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of int_ap_start_i_2 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_b[15]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_b[16]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[17]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[18]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_b[19]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \int_b[20]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_b[21]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_b[22]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[23]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[24]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \int_b[25]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \int_b[26]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \int_b[27]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \int_b[28]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \int_b[29]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \int_b[30]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \int_b[31]_i_2\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0"; begin SR(0) <= \^sr\(0); \a_reg0_reg[31]\(31 downto 0) <= \^a_reg0_reg[31]\(31 downto 0); \buff2_reg__0\(31 downto 0) <= \^buff2_reg__0\(31 downto 0); \out\(2 downto 0) <= \^out\(2 downto 0); s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0) <= \^s_axi_hls_macc_periph_bus_rdata\(31 downto 0); s_axi_HLS_MACC_PERIPH_BUS_RVALID(1 downto 0) <= \^s_axi_hls_macc_periph_bus_rvalid\(1 downto 0); \FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F747" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I1 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I2 => \^s_axi_hls_macc_periph_bus_rvalid\(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_RREADY, O => \FSM_onehot_rstate[1]_i_1_n_0\ ); \FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I1 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I2 => s_axi_HLS_MACC_PERIPH_BUS_RREADY, I3 => \^s_axi_hls_macc_periph_bus_rvalid\(1), O => \FSM_onehot_rstate[2]_i_1_n_0\ ); \FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_rstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[1]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rvalid\(0), R => \^sr\(0) ); \FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[2]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rvalid\(1), R => \^sr\(0) ); \FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"888BFF8B" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_BREADY, I1 => \^out\(2), I2 => \^out\(1), I3 => \^out\(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, O => \FSM_onehot_wstate[1]_i_1_n_0\ ); \FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, I1 => \^out\(0), I2 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I3 => \^out\(1), O => \FSM_onehot_wstate[2]_i_1_n_0\ ); \FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ap_rst_n, O => \^sr\(0) ); \FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I1 => \^out\(1), I2 => s_axi_HLS_MACC_PERIPH_BUS_BREADY, I3 => \^out\(2), O => \FSM_onehot_wstate[3]_i_2_n_0\ ); \FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_wstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[1]_i_1_n_0\, Q => \^out\(0), R => \^sr\(0) ); \FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[2]_i_1_n_0\, Q => \^out\(1), R => \^sr\(0) ); \FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[3]_i_2_n_0\, Q => \^out\(2), R => \^sr\(0) ); \accum_clr_read_reg_85[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => accum_clr, I1 => Q(0), I2 => ap_start, I3 => accum_clr_read_reg_85, O => \accum_clr_read_reg_85_reg[0]\ ); \ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AE" ) port map ( I0 => Q(4), I1 => Q(0), I2 => ap_start, O => D(0) ); \ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => ap_NS_fsm1, I1 => \ap_CS_fsm_reg[4]\, I2 => Q(1), I3 => Q(4), I4 => Q(2), I5 => Q(3), O => D(1) ); \ap_CS_fsm[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => Q(0), I1 => ap_start, O => ap_NS_fsm1 ); \int_a[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(0), O => int_a0(0) ); \int_a[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(10), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(10), O => int_a0(10) ); \int_a[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(11), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(11), O => int_a0(11) ); \int_a[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(12), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(12), O => int_a0(12) ); \int_a[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(13), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(13), O => int_a0(13) ); \int_a[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(14), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(14), O => int_a0(14) ); \int_a[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(15), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(15), O => int_a0(15) ); \int_a[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(16), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(16), O => int_a0(16) ); \int_a[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(17), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(17), O => int_a0(17) ); \int_a[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(18), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(18), O => int_a0(18) ); \int_a[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(19), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(19), O => int_a0(19) ); \int_a[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(1), O => int_a0(1) ); \int_a[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(20), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(20), O => int_a0(20) ); \int_a[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(21), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(21), O => int_a0(21) ); \int_a[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(22), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(22), O => int_a0(22) ); \int_a[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(23), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(23), O => int_a0(23) ); \int_a[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(24), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(24), O => int_a0(24) ); \int_a[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(25), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(25), O => int_a0(25) ); \int_a[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(26), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(26), O => int_a0(26) ); \int_a[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(27), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(27), O => int_a0(27) ); \int_a[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(28), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(28), O => int_a0(28) ); \int_a[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(29), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(29), O => int_a0(29) ); \int_a[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(2), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(2), O => int_a0(2) ); \int_a[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(30), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(30), O => int_a0(30) ); \int_a[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"10" ) port map ( I0 => \waddr_reg_n_0_[2]\, I1 => \waddr_reg_n_0_[3]\, I2 => \int_a[31]_i_3_n_0\, O => \int_a[31]_i_1_n_0\ ); \int_a[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(31), O => int_a0(31) ); \int_a[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000002000" ) port map ( I0 => \waddr_reg_n_0_[4]\, I1 => \waddr_reg_n_0_[5]\, I2 => \^out\(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I4 => \waddr_reg_n_0_[0]\, I5 => \waddr_reg_n_0_[1]\, O => \int_a[31]_i_3_n_0\ ); \int_a[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(3), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(3), O => int_a0(3) ); \int_a[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(4), O => int_a0(4) ); \int_a[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(5), O => int_a0(5) ); \int_a[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(6), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(6), O => int_a0(6) ); \int_a[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(7), O => int_a0(7) ); \int_a[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(8), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(8), O => int_a0(8) ); \int_a[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(9), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(9), O => int_a0(9) ); \int_a_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(0), Q => \^buff2_reg__0\(0), R => \^sr\(0) ); \int_a_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(10), Q => \^buff2_reg__0\(10), R => \^sr\(0) ); \int_a_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(11), Q => \^buff2_reg__0\(11), R => \^sr\(0) ); \int_a_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(12), Q => \^buff2_reg__0\(12), R => \^sr\(0) ); \int_a_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(13), Q => \^buff2_reg__0\(13), R => \^sr\(0) ); \int_a_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(14), Q => \^buff2_reg__0\(14), R => \^sr\(0) ); \int_a_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(15), Q => \^buff2_reg__0\(15), R => \^sr\(0) ); \int_a_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(16), Q => \^buff2_reg__0\(16), R => \^sr\(0) ); \int_a_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(17), Q => \^buff2_reg__0\(17), R => \^sr\(0) ); \int_a_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(18), Q => \^buff2_reg__0\(18), R => \^sr\(0) ); \int_a_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(19), Q => \^buff2_reg__0\(19), R => \^sr\(0) ); \int_a_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(1), Q => \^buff2_reg__0\(1), R => \^sr\(0) ); \int_a_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(20), Q => \^buff2_reg__0\(20), R => \^sr\(0) ); \int_a_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(21), Q => \^buff2_reg__0\(21), R => \^sr\(0) ); \int_a_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(22), Q => \^buff2_reg__0\(22), R => \^sr\(0) ); \int_a_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(23), Q => \^buff2_reg__0\(23), R => \^sr\(0) ); \int_a_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(24), Q => \^buff2_reg__0\(24), R => \^sr\(0) ); \int_a_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(25), Q => \^buff2_reg__0\(25), R => \^sr\(0) ); \int_a_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(26), Q => \^buff2_reg__0\(26), R => \^sr\(0) ); \int_a_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(27), Q => \^buff2_reg__0\(27), R => \^sr\(0) ); \int_a_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(28), Q => \^buff2_reg__0\(28), R => \^sr\(0) ); \int_a_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(29), Q => \^buff2_reg__0\(29), R => \^sr\(0) ); \int_a_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(2), Q => \^buff2_reg__0\(2), R => \^sr\(0) ); \int_a_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(30), Q => \^buff2_reg__0\(30), R => \^sr\(0) ); \int_a_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(31), Q => \^buff2_reg__0\(31), R => \^sr\(0) ); \int_a_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(3), Q => \^buff2_reg__0\(3), R => \^sr\(0) ); \int_a_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(4), Q => \^buff2_reg__0\(4), R => \^sr\(0) ); \int_a_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(5), Q => \^buff2_reg__0\(5), R => \^sr\(0) ); \int_a_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(6), Q => \^buff2_reg__0\(6), R => \^sr\(0) ); \int_a_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(7), Q => \^buff2_reg__0\(7), R => \^sr\(0) ); \int_a_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(8), Q => \^buff2_reg__0\(8), R => \^sr\(0) ); \int_a_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(9), Q => \^buff2_reg__0\(9), R => \^sr\(0) ); int_accum_ap_vld_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"BFFFAAAA" ) port map ( I0 => Q(4), I1 => int_accum_ap_vld1, I2 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I3 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I4 => int_accum_ap_vld, O => int_accum_ap_vld_i_1_n_0 ); int_accum_ap_vld_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000001000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), O => int_accum_ap_vld1 ); int_accum_ap_vld_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => int_accum_ap_vld_i_1_n_0, Q => int_accum_ap_vld, R => \^sr\(0) ); \int_accum_clr[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => p_0_in11_in, I3 => accum_clr, O => \int_accum_clr[0]_i_1_n_0\ ); \int_accum_clr[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00400000" ) port map ( I0 => \waddr_reg_n_0_[2]\, I1 => \waddr_reg_n_0_[5]\, I2 => \int_accum_clr[0]_i_3_n_0\, I3 => \waddr_reg_n_0_[4]\, I4 => \waddr_reg_n_0_[3]\, O => p_0_in11_in ); \int_accum_clr[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0008" ) port map ( I0 => \^out\(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I2 => \waddr_reg_n_0_[0]\, I3 => \waddr_reg_n_0_[1]\, O => \int_accum_clr[0]_i_3_n_0\ ); \int_accum_clr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_accum_clr[0]_i_1_n_0\, Q => accum_clr, R => \^sr\(0) ); \int_accum_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(0), Q => int_accum(0), R => \^sr\(0) ); \int_accum_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(10), Q => int_accum(10), R => \^sr\(0) ); \int_accum_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(11), Q => int_accum(11), R => \^sr\(0) ); \int_accum_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(12), Q => int_accum(12), R => \^sr\(0) ); \int_accum_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(13), Q => int_accum(13), R => \^sr\(0) ); \int_accum_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(14), Q => int_accum(14), R => \^sr\(0) ); \int_accum_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(15), Q => int_accum(15), R => \^sr\(0) ); \int_accum_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(16), Q => int_accum(16), R => \^sr\(0) ); \int_accum_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(17), Q => int_accum(17), R => \^sr\(0) ); \int_accum_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(18), Q => int_accum(18), R => \^sr\(0) ); \int_accum_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(19), Q => int_accum(19), R => \^sr\(0) ); \int_accum_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(1), Q => int_accum(1), R => \^sr\(0) ); \int_accum_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(20), Q => int_accum(20), R => \^sr\(0) ); \int_accum_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(21), Q => int_accum(21), R => \^sr\(0) ); \int_accum_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(22), Q => int_accum(22), R => \^sr\(0) ); \int_accum_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(23), Q => int_accum(23), R => \^sr\(0) ); \int_accum_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(24), Q => int_accum(24), R => \^sr\(0) ); \int_accum_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(25), Q => int_accum(25), R => \^sr\(0) ); \int_accum_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(26), Q => int_accum(26), R => \^sr\(0) ); \int_accum_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(27), Q => int_accum(27), R => \^sr\(0) ); \int_accum_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(28), Q => int_accum(28), R => \^sr\(0) ); \int_accum_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(29), Q => int_accum(29), R => \^sr\(0) ); \int_accum_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(2), Q => int_accum(2), R => \^sr\(0) ); \int_accum_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(30), Q => int_accum(30), R => \^sr\(0) ); \int_accum_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(31), Q => int_accum(31), R => \^sr\(0) ); \int_accum_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(3), Q => int_accum(3), R => \^sr\(0) ); \int_accum_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(4), Q => int_accum(4), R => \^sr\(0) ); \int_accum_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(5), Q => int_accum(5), R => \^sr\(0) ); \int_accum_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(6), Q => int_accum(6), R => \^sr\(0) ); \int_accum_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(7), Q => int_accum(7), R => \^sr\(0) ); \int_accum_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(8), Q => int_accum(8), R => \^sr\(0) ); \int_accum_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(9), Q => int_accum(9), R => \^sr\(0) ); int_ap_done_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"BFFFAAAA" ) port map ( I0 => Q(4), I1 => int_ap_done1, I2 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I3 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I4 => int_ap_done, O => int_ap_done_i_1_n_0 ); int_ap_done_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), O => int_ap_done1 ); int_ap_done_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_done_i_1_n_0, Q => int_ap_done, R => \^sr\(0) ); int_ap_idle_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => Q(0), I1 => ap_start, O => ap_idle ); int_ap_idle_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => ap_idle, Q => int_ap_idle, R => \^sr\(0) ); int_ap_ready_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => Q(4), Q => int_ap_ready, R => \^sr\(0) ); int_ap_start_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FBF8" ) port map ( I0 => int_auto_restart, I1 => Q(4), I2 => int_ap_start3_out, I3 => ap_start, O => int_ap_start_i_1_n_0 ); int_ap_start_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"04000000" ) port map ( I0 => \waddr_reg_n_0_[3]\, I1 => \int_ier[1]_i_2_n_0\, I2 => \waddr_reg_n_0_[2]\, I3 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), O => int_ap_start3_out ); int_ap_start_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_start_i_1_n_0, Q => ap_start, R => \^sr\(0) ); int_auto_restart_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFBFF00000800" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \int_ier[1]_i_2_n_0\, I4 => \waddr_reg_n_0_[3]\, I5 => int_auto_restart, O => int_auto_restart_i_1_n_0 ); int_auto_restart_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_auto_restart_i_1_n_0, Q => int_auto_restart, R => \^sr\(0) ); \int_b[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(0), O => int_b0(0) ); \int_b[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(10), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(10), O => int_b0(10) ); \int_b[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(11), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(11), O => int_b0(11) ); \int_b[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(12), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(12), O => int_b0(12) ); \int_b[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(13), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(13), O => int_b0(13) ); \int_b[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(14), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(14), O => int_b0(14) ); \int_b[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(15), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(15), O => int_b0(15) ); \int_b[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(16), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(16), O => int_b0(16) ); \int_b[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(17), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(17), O => int_b0(17) ); \int_b[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(18), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(18), O => int_b0(18) ); \int_b[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(19), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(19), O => int_b0(19) ); \int_b[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(1), O => int_b0(1) ); \int_b[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(20), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(20), O => int_b0(20) ); \int_b[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(21), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(21), O => int_b0(21) ); \int_b[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(22), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(22), O => int_b0(22) ); \int_b[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(23), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(23), O => int_b0(23) ); \int_b[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(24), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(24), O => int_b0(24) ); \int_b[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(25), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(25), O => int_b0(25) ); \int_b[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(26), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(26), O => int_b0(26) ); \int_b[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(27), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(27), O => int_b0(27) ); \int_b[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(28), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(28), O => int_b0(28) ); \int_b[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(29), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(29), O => int_b0(29) ); \int_b[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(2), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(2), O => int_b0(2) ); \int_b[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(30), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(30), O => int_b0(30) ); \int_b[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \waddr_reg_n_0_[2]\, I1 => \waddr_reg_n_0_[3]\, I2 => \int_a[31]_i_3_n_0\, O => \int_b[31]_i_1_n_0\ ); \int_b[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(31), O => int_b0(31) ); \int_b[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(3), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(3), O => int_b0(3) ); \int_b[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(4), O => int_b0(4) ); \int_b[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(5), O => int_b0(5) ); \int_b[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(6), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(6), O => int_b0(6) ); \int_b[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(7), O => int_b0(7) ); \int_b[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(8), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(8), O => int_b0(8) ); \int_b[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(9), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(9), O => int_b0(9) ); \int_b_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(0), Q => \^a_reg0_reg[31]\(0), R => \^sr\(0) ); \int_b_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(10), Q => \^a_reg0_reg[31]\(10), R => \^sr\(0) ); \int_b_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(11), Q => \^a_reg0_reg[31]\(11), R => \^sr\(0) ); \int_b_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(12), Q => \^a_reg0_reg[31]\(12), R => \^sr\(0) ); \int_b_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(13), Q => \^a_reg0_reg[31]\(13), R => \^sr\(0) ); \int_b_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(14), Q => \^a_reg0_reg[31]\(14), R => \^sr\(0) ); \int_b_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(15), Q => \^a_reg0_reg[31]\(15), R => \^sr\(0) ); \int_b_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(16), Q => \^a_reg0_reg[31]\(16), R => \^sr\(0) ); \int_b_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(17), Q => \^a_reg0_reg[31]\(17), R => \^sr\(0) ); \int_b_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(18), Q => \^a_reg0_reg[31]\(18), R => \^sr\(0) ); \int_b_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(19), Q => \^a_reg0_reg[31]\(19), R => \^sr\(0) ); \int_b_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(1), Q => \^a_reg0_reg[31]\(1), R => \^sr\(0) ); \int_b_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(20), Q => \^a_reg0_reg[31]\(20), R => \^sr\(0) ); \int_b_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(21), Q => \^a_reg0_reg[31]\(21), R => \^sr\(0) ); \int_b_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(22), Q => \^a_reg0_reg[31]\(22), R => \^sr\(0) ); \int_b_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(23), Q => \^a_reg0_reg[31]\(23), R => \^sr\(0) ); \int_b_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(24), Q => \^a_reg0_reg[31]\(24), R => \^sr\(0) ); \int_b_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(25), Q => \^a_reg0_reg[31]\(25), R => \^sr\(0) ); \int_b_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(26), Q => \^a_reg0_reg[31]\(26), R => \^sr\(0) ); \int_b_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(27), Q => \^a_reg0_reg[31]\(27), R => \^sr\(0) ); \int_b_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(28), Q => \^a_reg0_reg[31]\(28), R => \^sr\(0) ); \int_b_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(29), Q => \^a_reg0_reg[31]\(29), R => \^sr\(0) ); \int_b_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(2), Q => \^a_reg0_reg[31]\(2), R => \^sr\(0) ); \int_b_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(30), Q => \^a_reg0_reg[31]\(30), R => \^sr\(0) ); \int_b_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(31), Q => \^a_reg0_reg[31]\(31), R => \^sr\(0) ); \int_b_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(3), Q => \^a_reg0_reg[31]\(3), R => \^sr\(0) ); \int_b_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(4), Q => \^a_reg0_reg[31]\(4), R => \^sr\(0) ); \int_b_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(5), Q => \^a_reg0_reg[31]\(5), R => \^sr\(0) ); \int_b_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(6), Q => \^a_reg0_reg[31]\(6), R => \^sr\(0) ); \int_b_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(7), Q => \^a_reg0_reg[31]\(7), R => \^sr\(0) ); \int_b_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(8), Q => \^a_reg0_reg[31]\(8), R => \^sr\(0) ); \int_b_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(9), Q => \^a_reg0_reg[31]\(9), R => \^sr\(0) ); int_gie_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFBFFFFF00800000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[3]\, I4 => \waddr_reg_n_0_[2]\, I5 => int_gie_reg_n_0, O => int_gie_i_1_n_0 ); int_gie_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_gie_i_1_n_0, Q => int_gie_reg_n_0, R => \^sr\(0) ); \int_ier[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \waddr_reg_n_0_[3]\, I4 => \int_ier[1]_i_2_n_0\, I5 => \int_ier_reg_n_0_[0]\, O => \int_ier[0]_i_1_n_0\ ); \int_ier[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \waddr_reg_n_0_[3]\, I4 => \int_ier[1]_i_2_n_0\, I5 => p_0_in, O => \int_ier[1]_i_1_n_0\ ); \int_ier[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => \waddr_reg_n_0_[5]\, I1 => \^out\(1), I2 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I3 => \waddr_reg_n_0_[0]\, I4 => \waddr_reg_n_0_[1]\, I5 => \waddr_reg_n_0_[4]\, O => \int_ier[1]_i_2_n_0\ ); \int_ier_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[0]_i_1_n_0\, Q => \int_ier_reg_n_0_[0]\, R => \^sr\(0) ); \int_ier_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[1]_i_1_n_0\, Q => p_0_in, R => \^sr\(0) ); \int_isr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F777F888" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => int_isr6_out, I2 => Q(4), I3 => \int_ier_reg_n_0_[0]\, I4 => \int_isr_reg_n_0_[0]\, O => \int_isr[0]_i_1_n_0\ ); \int_isr[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I1 => \waddr_reg_n_0_[3]\, I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, O => int_isr6_out ); \int_isr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F777F888" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => int_isr6_out, I2 => p_0_in, I3 => Q(4), I4 => \int_isr_reg_n_0_[1]\, O => \int_isr[1]_i_1_n_0\ ); \int_isr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[0]_i_1_n_0\, Q => \int_isr_reg_n_0_[0]\, R => \^sr\(0) ); \int_isr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[1]_i_1_n_0\, Q => \int_isr_reg_n_0_[1]\, R => \^sr\(0) ); interrupt_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \int_isr_reg_n_0_[1]\, I1 => \int_isr_reg_n_0_[0]\, I2 => int_gie_reg_n_0, O => interrupt ); \rdata[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata_reg[0]_i_2_n_0\, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), I2 => \rdata[0]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_hls_macc_periph_bus_rdata\(0), O => \rdata[0]_i_1_n_0\ ); \rdata[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033223000002230" ) port map ( I0 => int_accum_ap_vld, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_gie_reg_n_0, I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => \int_isr_reg_n_0_[0]\, O => \rdata[0]_i_3_n_0\ ); \rdata[0]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(0), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => ap_start, O => \rdata[0]_i_4_n_0\ ); \rdata[0]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_reg0_reg[31]\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => accum_clr, I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => \int_ier_reg_n_0_[0]\, O => \rdata[0]_i_5_n_0\ ); \rdata[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(10), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(10), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(10), O => \rdata[10]_i_1_n_0\ ); \rdata[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(11), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(11), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(11), O => \rdata[11]_i_1_n_0\ ); \rdata[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(12), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(12), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(12), O => \rdata[12]_i_1_n_0\ ); \rdata[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(13), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(13), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(13), O => \rdata[13]_i_1_n_0\ ); \rdata[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(14), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(14), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(14), O => \rdata[14]_i_1_n_0\ ); \rdata[15]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(15), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(15), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(15), O => \rdata[15]_i_1_n_0\ ); \rdata[16]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(16), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(16), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(16), O => \rdata[16]_i_1_n_0\ ); \rdata[17]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(17), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(17), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(17), O => \rdata[17]_i_1_n_0\ ); \rdata[18]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(18), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(18), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(18), O => \rdata[18]_i_1_n_0\ ); \rdata[19]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(19), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(19), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(19), O => \rdata[19]_i_1_n_0\ ); \rdata[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata[1]_i_2_n_0\, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), I2 => \rdata[1]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_hls_macc_periph_bus_rdata\(1), O => \rdata[1]_i_1_n_0\ ); \rdata[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => p_0_in, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => \rdata[1]_i_5_n_0\, O => \rdata[1]_i_2_n_0\ ); \rdata[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I3 => \int_isr_reg_n_0_[1]\, O => \rdata[1]_i_3_n_0\ ); \rdata[1]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), O => \rdata[1]_i_4_n_0\ ); \rdata[1]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_ap_done, O => \rdata[1]_i_5_n_0\ ); \rdata[20]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(20), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(20), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(20), O => \rdata[20]_i_1_n_0\ ); \rdata[21]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(21), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(21), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(21), O => \rdata[21]_i_1_n_0\ ); \rdata[22]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(22), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(22), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(22), O => \rdata[22]_i_1_n_0\ ); \rdata[23]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(23), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(23), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(23), O => \rdata[23]_i_1_n_0\ ); \rdata[24]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(24), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(24), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(24), O => \rdata[24]_i_1_n_0\ ); \rdata[25]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(25), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(25), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(25), O => \rdata[25]_i_1_n_0\ ); \rdata[26]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(26), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(26), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(26), O => \rdata[26]_i_1_n_0\ ); \rdata[27]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(27), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(27), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(27), O => \rdata[27]_i_1_n_0\ ); \rdata[28]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(28), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(28), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(28), O => \rdata[28]_i_1_n_0\ ); \rdata[29]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(29), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(29), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(29), O => \rdata[29]_i_1_n_0\ ); \rdata[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(2), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I4 => \rdata[2]_i_2_n_0\, O => \rdata[2]_i_1_n_0\ ); \rdata[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(2), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(2), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_ap_idle, O => \rdata[2]_i_2_n_0\ ); \rdata[30]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(30), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(30), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(30), O => \rdata[30]_i_1_n_0\ ); \rdata[31]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88888880" ) port map ( I0 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), O => \rdata[31]_i_1_n_0\ ); \rdata[31]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I1 => \^s_axi_hls_macc_periph_bus_rvalid\(0), O => ar_hs ); \rdata[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(31), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(31), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(31), O => \rdata[31]_i_3_n_0\ ); \rdata[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(3), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I4 => \rdata[3]_i_2_n_0\, O => \rdata[3]_i_1_n_0\ ); \rdata[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(3), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(3), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_ap_ready, O => \rdata[3]_i_2_n_0\ ); \rdata[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(4), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(4), O => \rdata[4]_i_1_n_0\ ); \rdata[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(5), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(5), O => \rdata[5]_i_1_n_0\ ); \rdata[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(6), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(6), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(6), O => \rdata[6]_i_1_n_0\ ); \rdata[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(7), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I4 => \rdata[7]_i_2_n_0\, O => \rdata[7]_i_1_n_0\ ); \rdata[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(7), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_auto_restart, O => \rdata[7]_i_2_n_0\ ); \rdata[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(8), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(8), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(8), O => \rdata[8]_i_1_n_0\ ); \rdata[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(9), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(9), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(9), O => \rdata[9]_i_1_n_0\ ); \rdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[0]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(0), R => '0' ); \rdata_reg[0]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \rdata[0]_i_4_n_0\, I1 => \rdata[0]_i_5_n_0\, O => \rdata_reg[0]_i_2_n_0\, S => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3) ); \rdata_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[10]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(10), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[11]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(11), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[12]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(12), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[13]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(13), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[14]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(14), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[15]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(15), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[16]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[16]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(16), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[17]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[17]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(17), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[18]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[18]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(18), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[19]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[19]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(19), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[1]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(1), R => '0' ); \rdata_reg[20]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[20]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(20), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[21]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[21]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(21), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[22]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[22]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(22), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[23]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[23]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(23), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[24]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[24]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(24), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[25]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[25]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(25), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[26]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[26]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(26), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[27]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[27]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(27), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[28]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[28]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(28), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[29]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[29]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(29), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[2]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(2), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[30]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[30]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(30), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[31]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[31]_i_3_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(31), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[3]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(3), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[4]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(4), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[5]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(5), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[6]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(6), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[7]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(7), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[8]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(8), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[9]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(9), R => \rdata[31]_i_1_n_0\ ); \waddr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^out\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, O => waddr ); \waddr_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(0), Q => \waddr_reg_n_0_[0]\, R => '0' ); \waddr_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(1), Q => \waddr_reg_n_0_[1]\, R => '0' ); \waddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(2), Q => \waddr_reg_n_0_[2]\, R => '0' ); \waddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(3), Q => \waddr_reg_n_0_[3]\, R => '0' ); \waddr_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(4), Q => \waddr_reg_n_0_[4]\, R => '0' ); \waddr_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5), Q => \waddr_reg_n_0_[5]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb_MulnS_0 is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); ap_clk : in STD_LOGIC; \int_a_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \int_b_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb_MulnS_0 : entity is "hls_macc_mul_32s_bkb_MulnS_0"; end zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb_MulnS_0; architecture STRUCTURE of zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb_MulnS_0 is signal a_reg0 : STD_LOGIC_VECTOR ( 31 downto 17 ); signal b_reg0 : STD_LOGIC_VECTOR ( 16 downto 0 ); signal buff1_reg_n_100 : STD_LOGIC; signal buff1_reg_n_101 : STD_LOGIC; signal buff1_reg_n_102 : STD_LOGIC; signal buff1_reg_n_103 : STD_LOGIC; signal buff1_reg_n_104 : STD_LOGIC; signal buff1_reg_n_105 : STD_LOGIC; signal buff1_reg_n_106 : STD_LOGIC; signal buff1_reg_n_107 : STD_LOGIC; signal buff1_reg_n_108 : STD_LOGIC; signal buff1_reg_n_109 : STD_LOGIC; signal buff1_reg_n_110 : STD_LOGIC; signal buff1_reg_n_111 : STD_LOGIC; signal buff1_reg_n_112 : STD_LOGIC; signal buff1_reg_n_113 : STD_LOGIC; signal buff1_reg_n_114 : STD_LOGIC; signal buff1_reg_n_115 : STD_LOGIC; signal buff1_reg_n_116 : STD_LOGIC; signal buff1_reg_n_117 : STD_LOGIC; signal buff1_reg_n_118 : STD_LOGIC; signal buff1_reg_n_119 : STD_LOGIC; signal buff1_reg_n_120 : STD_LOGIC; signal buff1_reg_n_121 : STD_LOGIC; signal buff1_reg_n_122 : STD_LOGIC; signal buff1_reg_n_123 : STD_LOGIC; signal buff1_reg_n_124 : STD_LOGIC; signal buff1_reg_n_125 : STD_LOGIC; signal buff1_reg_n_126 : STD_LOGIC; signal buff1_reg_n_127 : STD_LOGIC; signal buff1_reg_n_128 : STD_LOGIC; signal buff1_reg_n_129 : STD_LOGIC; signal buff1_reg_n_130 : STD_LOGIC; signal buff1_reg_n_131 : STD_LOGIC; signal buff1_reg_n_132 : STD_LOGIC; signal buff1_reg_n_133 : STD_LOGIC; signal buff1_reg_n_134 : STD_LOGIC; signal buff1_reg_n_135 : STD_LOGIC; signal buff1_reg_n_136 : STD_LOGIC; signal buff1_reg_n_137 : STD_LOGIC; signal buff1_reg_n_138 : STD_LOGIC; signal buff1_reg_n_139 : STD_LOGIC; signal buff1_reg_n_140 : STD_LOGIC; signal buff1_reg_n_141 : STD_LOGIC; signal buff1_reg_n_142 : STD_LOGIC; signal buff1_reg_n_143 : STD_LOGIC; signal buff1_reg_n_144 : STD_LOGIC; signal buff1_reg_n_145 : STD_LOGIC; signal buff1_reg_n_146 : STD_LOGIC; signal buff1_reg_n_147 : STD_LOGIC; signal buff1_reg_n_148 : STD_LOGIC; signal buff1_reg_n_149 : STD_LOGIC; signal buff1_reg_n_150 : STD_LOGIC; signal buff1_reg_n_151 : STD_LOGIC; signal buff1_reg_n_152 : STD_LOGIC; signal buff1_reg_n_153 : STD_LOGIC; signal buff1_reg_n_58 : STD_LOGIC; signal buff1_reg_n_59 : STD_LOGIC; signal buff1_reg_n_60 : STD_LOGIC; signal buff1_reg_n_61 : STD_LOGIC; signal buff1_reg_n_62 : STD_LOGIC; signal buff1_reg_n_63 : STD_LOGIC; signal buff1_reg_n_64 : STD_LOGIC; signal buff1_reg_n_65 : STD_LOGIC; signal buff1_reg_n_66 : STD_LOGIC; signal buff1_reg_n_67 : STD_LOGIC; signal buff1_reg_n_68 : STD_LOGIC; signal buff1_reg_n_69 : STD_LOGIC; signal buff1_reg_n_70 : STD_LOGIC; signal buff1_reg_n_71 : STD_LOGIC; signal buff1_reg_n_72 : STD_LOGIC; signal buff1_reg_n_73 : STD_LOGIC; signal buff1_reg_n_74 : STD_LOGIC; signal buff1_reg_n_75 : STD_LOGIC; signal buff1_reg_n_76 : STD_LOGIC; signal buff1_reg_n_77 : STD_LOGIC; signal buff1_reg_n_78 : STD_LOGIC; signal buff1_reg_n_79 : STD_LOGIC; signal buff1_reg_n_80 : STD_LOGIC; signal buff1_reg_n_81 : STD_LOGIC; signal buff1_reg_n_82 : STD_LOGIC; signal buff1_reg_n_83 : STD_LOGIC; signal buff1_reg_n_84 : STD_LOGIC; signal buff1_reg_n_85 : STD_LOGIC; signal buff1_reg_n_86 : STD_LOGIC; signal buff1_reg_n_87 : STD_LOGIC; signal buff1_reg_n_88 : STD_LOGIC; signal buff1_reg_n_89 : STD_LOGIC; signal buff1_reg_n_90 : STD_LOGIC; signal buff1_reg_n_91 : STD_LOGIC; signal buff1_reg_n_92 : STD_LOGIC; signal buff1_reg_n_93 : STD_LOGIC; signal buff1_reg_n_94 : STD_LOGIC; signal buff1_reg_n_95 : STD_LOGIC; signal buff1_reg_n_96 : STD_LOGIC; signal buff1_reg_n_97 : STD_LOGIC; signal buff1_reg_n_98 : STD_LOGIC; signal buff1_reg_n_99 : STD_LOGIC; signal \buff2_reg__0_n_106\ : STD_LOGIC; signal \buff2_reg__0_n_107\ : STD_LOGIC; signal \buff2_reg__0_n_108\ : STD_LOGIC; signal \buff2_reg__0_n_109\ : STD_LOGIC; signal \buff2_reg__0_n_110\ : STD_LOGIC; signal \buff2_reg__0_n_111\ : STD_LOGIC; signal \buff2_reg__0_n_112\ : STD_LOGIC; signal \buff2_reg__0_n_113\ : STD_LOGIC; signal \buff2_reg__0_n_114\ : STD_LOGIC; signal \buff2_reg__0_n_115\ : STD_LOGIC; signal \buff2_reg__0_n_116\ : STD_LOGIC; signal \buff2_reg__0_n_117\ : STD_LOGIC; signal \buff2_reg__0_n_118\ : STD_LOGIC; signal \buff2_reg__0_n_119\ : STD_LOGIC; signal \buff2_reg__0_n_120\ : STD_LOGIC; signal \buff2_reg__0_n_121\ : STD_LOGIC; signal \buff2_reg__0_n_122\ : STD_LOGIC; signal \buff2_reg__0_n_123\ : STD_LOGIC; signal \buff2_reg__0_n_124\ : STD_LOGIC; signal \buff2_reg__0_n_125\ : STD_LOGIC; signal \buff2_reg__0_n_126\ : STD_LOGIC; signal \buff2_reg__0_n_127\ : STD_LOGIC; signal \buff2_reg__0_n_128\ : STD_LOGIC; signal \buff2_reg__0_n_129\ : STD_LOGIC; signal \buff2_reg__0_n_130\ : STD_LOGIC; signal \buff2_reg__0_n_131\ : STD_LOGIC; signal \buff2_reg__0_n_132\ : STD_LOGIC; signal \buff2_reg__0_n_133\ : STD_LOGIC; signal \buff2_reg__0_n_134\ : STD_LOGIC; signal \buff2_reg__0_n_135\ : STD_LOGIC; signal \buff2_reg__0_n_136\ : STD_LOGIC; signal \buff2_reg__0_n_137\ : STD_LOGIC; signal \buff2_reg__0_n_138\ : STD_LOGIC; signal \buff2_reg__0_n_139\ : STD_LOGIC; signal \buff2_reg__0_n_140\ : STD_LOGIC; signal \buff2_reg__0_n_141\ : STD_LOGIC; signal \buff2_reg__0_n_142\ : STD_LOGIC; signal \buff2_reg__0_n_143\ : STD_LOGIC; signal \buff2_reg__0_n_144\ : STD_LOGIC; signal \buff2_reg__0_n_145\ : STD_LOGIC; signal \buff2_reg__0_n_146\ : STD_LOGIC; signal \buff2_reg__0_n_147\ : STD_LOGIC; signal \buff2_reg__0_n_148\ : STD_LOGIC; signal \buff2_reg__0_n_149\ : STD_LOGIC; signal \buff2_reg__0_n_150\ : STD_LOGIC; signal \buff2_reg__0_n_151\ : STD_LOGIC; signal \buff2_reg__0_n_152\ : STD_LOGIC; signal \buff2_reg__0_n_153\ : STD_LOGIC; signal \buff3_reg__0_n_100\ : STD_LOGIC; signal \buff3_reg__0_n_101\ : STD_LOGIC; signal \buff3_reg__0_n_102\ : STD_LOGIC; signal \buff3_reg__0_n_103\ : STD_LOGIC; signal \buff3_reg__0_n_104\ : STD_LOGIC; signal \buff3_reg__0_n_105\ : STD_LOGIC; signal \buff3_reg__0_n_58\ : STD_LOGIC; signal \buff3_reg__0_n_59\ : STD_LOGIC; signal \buff3_reg__0_n_60\ : STD_LOGIC; signal \buff3_reg__0_n_61\ : STD_LOGIC; signal \buff3_reg__0_n_62\ : STD_LOGIC; signal \buff3_reg__0_n_63\ : STD_LOGIC; signal \buff3_reg__0_n_64\ : STD_LOGIC; signal \buff3_reg__0_n_65\ : STD_LOGIC; signal \buff3_reg__0_n_66\ : STD_LOGIC; signal \buff3_reg__0_n_67\ : STD_LOGIC; signal \buff3_reg__0_n_68\ : STD_LOGIC; signal \buff3_reg__0_n_69\ : STD_LOGIC; signal \buff3_reg__0_n_70\ : STD_LOGIC; signal \buff3_reg__0_n_71\ : STD_LOGIC; signal \buff3_reg__0_n_72\ : STD_LOGIC; signal \buff3_reg__0_n_73\ : STD_LOGIC; signal \buff3_reg__0_n_74\ : STD_LOGIC; signal \buff3_reg__0_n_75\ : STD_LOGIC; signal \buff3_reg__0_n_76\ : STD_LOGIC; signal \buff3_reg__0_n_77\ : STD_LOGIC; signal \buff3_reg__0_n_78\ : STD_LOGIC; signal \buff3_reg__0_n_79\ : STD_LOGIC; signal \buff3_reg__0_n_80\ : STD_LOGIC; signal \buff3_reg__0_n_81\ : STD_LOGIC; signal \buff3_reg__0_n_82\ : STD_LOGIC; signal \buff3_reg__0_n_83\ : STD_LOGIC; signal \buff3_reg__0_n_84\ : STD_LOGIC; signal \buff3_reg__0_n_85\ : STD_LOGIC; signal \buff3_reg__0_n_86\ : STD_LOGIC; signal \buff3_reg__0_n_87\ : STD_LOGIC; signal \buff3_reg__0_n_88\ : STD_LOGIC; signal \buff3_reg__0_n_89\ : STD_LOGIC; signal \buff3_reg__0_n_90\ : STD_LOGIC; signal \buff3_reg__0_n_91\ : STD_LOGIC; signal \buff3_reg__0_n_92\ : STD_LOGIC; signal \buff3_reg__0_n_93\ : STD_LOGIC; signal \buff3_reg__0_n_94\ : STD_LOGIC; signal \buff3_reg__0_n_95\ : STD_LOGIC; signal \buff3_reg__0_n_96\ : STD_LOGIC; signal \buff3_reg__0_n_97\ : STD_LOGIC; signal \buff3_reg__0_n_98\ : STD_LOGIC; signal \buff3_reg__0_n_99\ : STD_LOGIC; signal NLW_buff1_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); signal NLW_buff1_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); signal NLW_buff1_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_buff2_reg__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 ); signal \NLW_buff2_reg__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 ); signal \NLW_buff2_reg__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_buff2_reg__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 ); signal \NLW_buff3_reg__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 ); signal \NLW_buff3_reg__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 ); signal \NLW_buff3_reg__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_buff3_reg__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 ); attribute srl_bus_name : string; attribute srl_bus_name of \buff4_reg[0]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name : string; attribute srl_name of \buff4_reg[0]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[0]_srl3 "; attribute srl_bus_name of \buff4_reg[10]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[10]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[10]_srl3 "; attribute srl_bus_name of \buff4_reg[11]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[11]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[11]_srl3 "; attribute srl_bus_name of \buff4_reg[12]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[12]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[12]_srl3 "; attribute srl_bus_name of \buff4_reg[13]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[13]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[13]_srl3 "; attribute srl_bus_name of \buff4_reg[14]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[14]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[14]_srl3 "; attribute srl_bus_name of \buff4_reg[15]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[15]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[15]_srl3 "; attribute srl_bus_name of \buff4_reg[16]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[16]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[16]_srl3 "; attribute srl_bus_name of \buff4_reg[1]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[1]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[1]_srl3 "; attribute srl_bus_name of \buff4_reg[2]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[2]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[2]_srl3 "; attribute srl_bus_name of \buff4_reg[3]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[3]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[3]_srl3 "; attribute srl_bus_name of \buff4_reg[4]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[4]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[4]_srl3 "; attribute srl_bus_name of \buff4_reg[5]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[5]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[5]_srl3 "; attribute srl_bus_name of \buff4_reg[6]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[6]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[6]_srl3 "; attribute srl_bus_name of \buff4_reg[7]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[7]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[7]_srl3 "; attribute srl_bus_name of \buff4_reg[8]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[8]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[8]_srl3 "; attribute srl_bus_name of \buff4_reg[9]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[9]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[9]_srl3 "; begin \a_reg0_reg[17]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(17), Q => a_reg0(17), R => '0' ); \a_reg0_reg[18]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(18), Q => a_reg0(18), R => '0' ); \a_reg0_reg[19]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(19), Q => a_reg0(19), R => '0' ); \a_reg0_reg[20]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(20), Q => a_reg0(20), R => '0' ); \a_reg0_reg[21]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(21), Q => a_reg0(21), R => '0' ); \a_reg0_reg[22]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(22), Q => a_reg0(22), R => '0' ); \a_reg0_reg[23]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(23), Q => a_reg0(23), R => '0' ); \a_reg0_reg[24]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(24), Q => a_reg0(24), R => '0' ); \a_reg0_reg[25]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(25), Q => a_reg0(25), R => '0' ); \a_reg0_reg[26]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(26), Q => a_reg0(26), R => '0' ); \a_reg0_reg[27]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(27), Q => a_reg0(27), R => '0' ); \a_reg0_reg[28]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(28), Q => a_reg0(28), R => '0' ); \a_reg0_reg[29]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(29), Q => a_reg0(29), R => '0' ); \a_reg0_reg[30]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(30), Q => a_reg0(30), R => '0' ); \a_reg0_reg[31]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(31), Q => a_reg0(31), R => '0' ); \b_reg0_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(0), Q => b_reg0(0), R => '0' ); \b_reg0_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(10), Q => b_reg0(10), R => '0' ); \b_reg0_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(11), Q => b_reg0(11), R => '0' ); \b_reg0_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(12), Q => b_reg0(12), R => '0' ); \b_reg0_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(13), Q => b_reg0(13), R => '0' ); \b_reg0_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(14), Q => b_reg0(14), R => '0' ); \b_reg0_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(15), Q => b_reg0(15), R => '0' ); \b_reg0_reg[16]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(16), Q => b_reg0(16), R => '0' ); \b_reg0_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(1), Q => b_reg0(1), R => '0' ); \b_reg0_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(2), Q => b_reg0(2), R => '0' ); \b_reg0_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(3), Q => b_reg0(3), R => '0' ); \b_reg0_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(4), Q => b_reg0(4), R => '0' ); \b_reg0_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(5), Q => b_reg0(5), R => '0' ); \b_reg0_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(6), Q => b_reg0(6), R => '0' ); \b_reg0_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(7), Q => b_reg0(7), R => '0' ); \b_reg0_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(8), Q => b_reg0(8), R => '0' ); \b_reg0_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(9), Q => b_reg0(9), R => '0' ); buff1_reg: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 1, ADREG => 1, ALUMODEREG => 0, AREG => 1, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 1, BREG => 1, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 1, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 17) => B"0000000000000", A(16 downto 0) => \int_b_reg[31]\(16 downto 0), ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => NLW_buff1_reg_ACOUT_UNCONNECTED(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17) => '0', B(16 downto 0) => \int_a_reg[31]\(16 downto 0), BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => NLW_buff1_reg_BCOUT_UNCONNECTED(17 downto 0), C(47 downto 0) => B"111111111111111111111111111111111111111111111111", CARRYCASCIN => '0', CARRYCASCOUT => NLW_buff1_reg_CARRYCASCOUT_UNCONNECTED, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => NLW_buff1_reg_CARRYOUT_UNCONNECTED(3 downto 0), CEA1 => '0', CEA2 => '1', CEAD => '0', CEALUMODE => '0', CEB1 => '0', CEB2 => '1', CEC => '0', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '1', CEP => '1', CLK => ap_clk, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => NLW_buff1_reg_MULTSIGNOUT_UNCONNECTED, OPMODE(6 downto 0) => B"0000101", OVERFLOW => NLW_buff1_reg_OVERFLOW_UNCONNECTED, P(47) => buff1_reg_n_58, P(46) => buff1_reg_n_59, P(45) => buff1_reg_n_60, P(44) => buff1_reg_n_61, P(43) => buff1_reg_n_62, P(42) => buff1_reg_n_63, P(41) => buff1_reg_n_64, P(40) => buff1_reg_n_65, P(39) => buff1_reg_n_66, P(38) => buff1_reg_n_67, P(37) => buff1_reg_n_68, P(36) => buff1_reg_n_69, P(35) => buff1_reg_n_70, P(34) => buff1_reg_n_71, P(33) => buff1_reg_n_72, P(32) => buff1_reg_n_73, P(31) => buff1_reg_n_74, P(30) => buff1_reg_n_75, P(29) => buff1_reg_n_76, P(28) => buff1_reg_n_77, P(27) => buff1_reg_n_78, P(26) => buff1_reg_n_79, P(25) => buff1_reg_n_80, P(24) => buff1_reg_n_81, P(23) => buff1_reg_n_82, P(22) => buff1_reg_n_83, P(21) => buff1_reg_n_84, P(20) => buff1_reg_n_85, P(19) => buff1_reg_n_86, P(18) => buff1_reg_n_87, P(17) => buff1_reg_n_88, P(16) => buff1_reg_n_89, P(15) => buff1_reg_n_90, P(14) => buff1_reg_n_91, P(13) => buff1_reg_n_92, P(12) => buff1_reg_n_93, P(11) => buff1_reg_n_94, P(10) => buff1_reg_n_95, P(9) => buff1_reg_n_96, P(8) => buff1_reg_n_97, P(7) => buff1_reg_n_98, P(6) => buff1_reg_n_99, P(5) => buff1_reg_n_100, P(4) => buff1_reg_n_101, P(3) => buff1_reg_n_102, P(2) => buff1_reg_n_103, P(1) => buff1_reg_n_104, P(0) => buff1_reg_n_105, PATTERNBDETECT => NLW_buff1_reg_PATTERNBDETECT_UNCONNECTED, PATTERNDETECT => NLW_buff1_reg_PATTERNDETECT_UNCONNECTED, PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", PCOUT(47) => buff1_reg_n_106, PCOUT(46) => buff1_reg_n_107, PCOUT(45) => buff1_reg_n_108, PCOUT(44) => buff1_reg_n_109, PCOUT(43) => buff1_reg_n_110, PCOUT(42) => buff1_reg_n_111, PCOUT(41) => buff1_reg_n_112, PCOUT(40) => buff1_reg_n_113, PCOUT(39) => buff1_reg_n_114, PCOUT(38) => buff1_reg_n_115, PCOUT(37) => buff1_reg_n_116, PCOUT(36) => buff1_reg_n_117, PCOUT(35) => buff1_reg_n_118, PCOUT(34) => buff1_reg_n_119, PCOUT(33) => buff1_reg_n_120, PCOUT(32) => buff1_reg_n_121, PCOUT(31) => buff1_reg_n_122, PCOUT(30) => buff1_reg_n_123, PCOUT(29) => buff1_reg_n_124, PCOUT(28) => buff1_reg_n_125, PCOUT(27) => buff1_reg_n_126, PCOUT(26) => buff1_reg_n_127, PCOUT(25) => buff1_reg_n_128, PCOUT(24) => buff1_reg_n_129, PCOUT(23) => buff1_reg_n_130, PCOUT(22) => buff1_reg_n_131, PCOUT(21) => buff1_reg_n_132, PCOUT(20) => buff1_reg_n_133, PCOUT(19) => buff1_reg_n_134, PCOUT(18) => buff1_reg_n_135, PCOUT(17) => buff1_reg_n_136, PCOUT(16) => buff1_reg_n_137, PCOUT(15) => buff1_reg_n_138, PCOUT(14) => buff1_reg_n_139, PCOUT(13) => buff1_reg_n_140, PCOUT(12) => buff1_reg_n_141, PCOUT(11) => buff1_reg_n_142, PCOUT(10) => buff1_reg_n_143, PCOUT(9) => buff1_reg_n_144, PCOUT(8) => buff1_reg_n_145, PCOUT(7) => buff1_reg_n_146, PCOUT(6) => buff1_reg_n_147, PCOUT(5) => buff1_reg_n_148, PCOUT(4) => buff1_reg_n_149, PCOUT(3) => buff1_reg_n_150, PCOUT(2) => buff1_reg_n_151, PCOUT(1) => buff1_reg_n_152, PCOUT(0) => buff1_reg_n_153, RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => '0', UNDERFLOW => NLW_buff1_reg_UNDERFLOW_UNCONNECTED ); \buff2_reg__0\: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 2, ADREG => 1, ALUMODEREG => 0, AREG => 2, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 2, BREG => 2, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 1, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 17) => B"0000000000000", A(16 downto 0) => \int_b_reg[31]\(16 downto 0), ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => \NLW_buff2_reg__0_ACOUT_UNCONNECTED\(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17) => \int_a_reg[31]\(31), B(16) => \int_a_reg[31]\(31), B(15) => \int_a_reg[31]\(31), B(14 downto 0) => \int_a_reg[31]\(31 downto 17), BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => \NLW_buff2_reg__0_BCOUT_UNCONNECTED\(17 downto 0), C(47 downto 0) => B"111111111111111111111111111111111111111111111111", CARRYCASCIN => '0', CARRYCASCOUT => \NLW_buff2_reg__0_CARRYCASCOUT_UNCONNECTED\, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => \NLW_buff2_reg__0_CARRYOUT_UNCONNECTED\(3 downto 0), CEA1 => '1', CEA2 => '1', CEAD => '0', CEALUMODE => '0', CEB1 => '1', CEB2 => '1', CEC => '0', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '1', CEP => '1', CLK => ap_clk, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => \NLW_buff2_reg__0_MULTSIGNOUT_UNCONNECTED\, OPMODE(6 downto 0) => B"1010101", OVERFLOW => \NLW_buff2_reg__0_OVERFLOW_UNCONNECTED\, P(47 downto 0) => \NLW_buff2_reg__0_P_UNCONNECTED\(47 downto 0), PATTERNBDETECT => \NLW_buff2_reg__0_PATTERNBDETECT_UNCONNECTED\, PATTERNDETECT => \NLW_buff2_reg__0_PATTERNDETECT_UNCONNECTED\, PCIN(47) => buff1_reg_n_106, PCIN(46) => buff1_reg_n_107, PCIN(45) => buff1_reg_n_108, PCIN(44) => buff1_reg_n_109, PCIN(43) => buff1_reg_n_110, PCIN(42) => buff1_reg_n_111, PCIN(41) => buff1_reg_n_112, PCIN(40) => buff1_reg_n_113, PCIN(39) => buff1_reg_n_114, PCIN(38) => buff1_reg_n_115, PCIN(37) => buff1_reg_n_116, PCIN(36) => buff1_reg_n_117, PCIN(35) => buff1_reg_n_118, PCIN(34) => buff1_reg_n_119, PCIN(33) => buff1_reg_n_120, PCIN(32) => buff1_reg_n_121, PCIN(31) => buff1_reg_n_122, PCIN(30) => buff1_reg_n_123, PCIN(29) => buff1_reg_n_124, PCIN(28) => buff1_reg_n_125, PCIN(27) => buff1_reg_n_126, PCIN(26) => buff1_reg_n_127, PCIN(25) => buff1_reg_n_128, PCIN(24) => buff1_reg_n_129, PCIN(23) => buff1_reg_n_130, PCIN(22) => buff1_reg_n_131, PCIN(21) => buff1_reg_n_132, PCIN(20) => buff1_reg_n_133, PCIN(19) => buff1_reg_n_134, PCIN(18) => buff1_reg_n_135, PCIN(17) => buff1_reg_n_136, PCIN(16) => buff1_reg_n_137, PCIN(15) => buff1_reg_n_138, PCIN(14) => buff1_reg_n_139, PCIN(13) => buff1_reg_n_140, PCIN(12) => buff1_reg_n_141, PCIN(11) => buff1_reg_n_142, PCIN(10) => buff1_reg_n_143, PCIN(9) => buff1_reg_n_144, PCIN(8) => buff1_reg_n_145, PCIN(7) => buff1_reg_n_146, PCIN(6) => buff1_reg_n_147, PCIN(5) => buff1_reg_n_148, PCIN(4) => buff1_reg_n_149, PCIN(3) => buff1_reg_n_150, PCIN(2) => buff1_reg_n_151, PCIN(1) => buff1_reg_n_152, PCIN(0) => buff1_reg_n_153, PCOUT(47) => \buff2_reg__0_n_106\, PCOUT(46) => \buff2_reg__0_n_107\, PCOUT(45) => \buff2_reg__0_n_108\, PCOUT(44) => \buff2_reg__0_n_109\, PCOUT(43) => \buff2_reg__0_n_110\, PCOUT(42) => \buff2_reg__0_n_111\, PCOUT(41) => \buff2_reg__0_n_112\, PCOUT(40) => \buff2_reg__0_n_113\, PCOUT(39) => \buff2_reg__0_n_114\, PCOUT(38) => \buff2_reg__0_n_115\, PCOUT(37) => \buff2_reg__0_n_116\, PCOUT(36) => \buff2_reg__0_n_117\, PCOUT(35) => \buff2_reg__0_n_118\, PCOUT(34) => \buff2_reg__0_n_119\, PCOUT(33) => \buff2_reg__0_n_120\, PCOUT(32) => \buff2_reg__0_n_121\, PCOUT(31) => \buff2_reg__0_n_122\, PCOUT(30) => \buff2_reg__0_n_123\, PCOUT(29) => \buff2_reg__0_n_124\, PCOUT(28) => \buff2_reg__0_n_125\, PCOUT(27) => \buff2_reg__0_n_126\, PCOUT(26) => \buff2_reg__0_n_127\, PCOUT(25) => \buff2_reg__0_n_128\, PCOUT(24) => \buff2_reg__0_n_129\, PCOUT(23) => \buff2_reg__0_n_130\, PCOUT(22) => \buff2_reg__0_n_131\, PCOUT(21) => \buff2_reg__0_n_132\, PCOUT(20) => \buff2_reg__0_n_133\, PCOUT(19) => \buff2_reg__0_n_134\, PCOUT(18) => \buff2_reg__0_n_135\, PCOUT(17) => \buff2_reg__0_n_136\, PCOUT(16) => \buff2_reg__0_n_137\, PCOUT(15) => \buff2_reg__0_n_138\, PCOUT(14) => \buff2_reg__0_n_139\, PCOUT(13) => \buff2_reg__0_n_140\, PCOUT(12) => \buff2_reg__0_n_141\, PCOUT(11) => \buff2_reg__0_n_142\, PCOUT(10) => \buff2_reg__0_n_143\, PCOUT(9) => \buff2_reg__0_n_144\, PCOUT(8) => \buff2_reg__0_n_145\, PCOUT(7) => \buff2_reg__0_n_146\, PCOUT(6) => \buff2_reg__0_n_147\, PCOUT(5) => \buff2_reg__0_n_148\, PCOUT(4) => \buff2_reg__0_n_149\, PCOUT(3) => \buff2_reg__0_n_150\, PCOUT(2) => \buff2_reg__0_n_151\, PCOUT(1) => \buff2_reg__0_n_152\, PCOUT(0) => \buff2_reg__0_n_153\, RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => '0', UNDERFLOW => \NLW_buff2_reg__0_UNDERFLOW_UNCONNECTED\ ); \buff3_reg__0\: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 2, ADREG => 1, ALUMODEREG => 0, AREG => 2, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 2, BREG => 2, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 1, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 17) => B"0000000000000", A(16 downto 0) => b_reg0(16 downto 0), ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => \NLW_buff3_reg__0_ACOUT_UNCONNECTED\(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17) => a_reg0(31), B(16) => a_reg0(31), B(15) => a_reg0(31), B(14 downto 0) => a_reg0(31 downto 17), BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => \NLW_buff3_reg__0_BCOUT_UNCONNECTED\(17 downto 0), C(47 downto 0) => B"111111111111111111111111111111111111111111111111", CARRYCASCIN => '0', CARRYCASCOUT => \NLW_buff3_reg__0_CARRYCASCOUT_UNCONNECTED\, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => \NLW_buff3_reg__0_CARRYOUT_UNCONNECTED\(3 downto 0), CEA1 => '1', CEA2 => '1', CEAD => '0', CEALUMODE => '0', CEB1 => '1', CEB2 => '1', CEC => '0', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '1', CEP => '1', CLK => ap_clk, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => \NLW_buff3_reg__0_MULTSIGNOUT_UNCONNECTED\, OPMODE(6 downto 0) => B"0010101", OVERFLOW => \NLW_buff3_reg__0_OVERFLOW_UNCONNECTED\, P(47) => \buff3_reg__0_n_58\, P(46) => \buff3_reg__0_n_59\, P(45) => \buff3_reg__0_n_60\, P(44) => \buff3_reg__0_n_61\, P(43) => \buff3_reg__0_n_62\, P(42) => \buff3_reg__0_n_63\, P(41) => \buff3_reg__0_n_64\, P(40) => \buff3_reg__0_n_65\, P(39) => \buff3_reg__0_n_66\, P(38) => \buff3_reg__0_n_67\, P(37) => \buff3_reg__0_n_68\, P(36) => \buff3_reg__0_n_69\, P(35) => \buff3_reg__0_n_70\, P(34) => \buff3_reg__0_n_71\, P(33) => \buff3_reg__0_n_72\, P(32) => \buff3_reg__0_n_73\, P(31) => \buff3_reg__0_n_74\, P(30) => \buff3_reg__0_n_75\, P(29) => \buff3_reg__0_n_76\, P(28) => \buff3_reg__0_n_77\, P(27) => \buff3_reg__0_n_78\, P(26) => \buff3_reg__0_n_79\, P(25) => \buff3_reg__0_n_80\, P(24) => \buff3_reg__0_n_81\, P(23) => \buff3_reg__0_n_82\, P(22) => \buff3_reg__0_n_83\, P(21) => \buff3_reg__0_n_84\, P(20) => \buff3_reg__0_n_85\, P(19) => \buff3_reg__0_n_86\, P(18) => \buff3_reg__0_n_87\, P(17) => \buff3_reg__0_n_88\, P(16) => \buff3_reg__0_n_89\, P(15) => \buff3_reg__0_n_90\, P(14) => \buff3_reg__0_n_91\, P(13) => \buff3_reg__0_n_92\, P(12) => \buff3_reg__0_n_93\, P(11) => \buff3_reg__0_n_94\, P(10) => \buff3_reg__0_n_95\, P(9) => \buff3_reg__0_n_96\, P(8) => \buff3_reg__0_n_97\, P(7) => \buff3_reg__0_n_98\, P(6) => \buff3_reg__0_n_99\, P(5) => \buff3_reg__0_n_100\, P(4) => \buff3_reg__0_n_101\, P(3) => \buff3_reg__0_n_102\, P(2) => \buff3_reg__0_n_103\, P(1) => \buff3_reg__0_n_104\, P(0) => \buff3_reg__0_n_105\, PATTERNBDETECT => \NLW_buff3_reg__0_PATTERNBDETECT_UNCONNECTED\, PATTERNDETECT => \NLW_buff3_reg__0_PATTERNDETECT_UNCONNECTED\, PCIN(47) => \buff2_reg__0_n_106\, PCIN(46) => \buff2_reg__0_n_107\, PCIN(45) => \buff2_reg__0_n_108\, PCIN(44) => \buff2_reg__0_n_109\, PCIN(43) => \buff2_reg__0_n_110\, PCIN(42) => \buff2_reg__0_n_111\, PCIN(41) => \buff2_reg__0_n_112\, PCIN(40) => \buff2_reg__0_n_113\, PCIN(39) => \buff2_reg__0_n_114\, PCIN(38) => \buff2_reg__0_n_115\, PCIN(37) => \buff2_reg__0_n_116\, PCIN(36) => \buff2_reg__0_n_117\, PCIN(35) => \buff2_reg__0_n_118\, PCIN(34) => \buff2_reg__0_n_119\, PCIN(33) => \buff2_reg__0_n_120\, PCIN(32) => \buff2_reg__0_n_121\, PCIN(31) => \buff2_reg__0_n_122\, PCIN(30) => \buff2_reg__0_n_123\, PCIN(29) => \buff2_reg__0_n_124\, PCIN(28) => \buff2_reg__0_n_125\, PCIN(27) => \buff2_reg__0_n_126\, PCIN(26) => \buff2_reg__0_n_127\, PCIN(25) => \buff2_reg__0_n_128\, PCIN(24) => \buff2_reg__0_n_129\, PCIN(23) => \buff2_reg__0_n_130\, PCIN(22) => \buff2_reg__0_n_131\, PCIN(21) => \buff2_reg__0_n_132\, PCIN(20) => \buff2_reg__0_n_133\, PCIN(19) => \buff2_reg__0_n_134\, PCIN(18) => \buff2_reg__0_n_135\, PCIN(17) => \buff2_reg__0_n_136\, PCIN(16) => \buff2_reg__0_n_137\, PCIN(15) => \buff2_reg__0_n_138\, PCIN(14) => \buff2_reg__0_n_139\, PCIN(13) => \buff2_reg__0_n_140\, PCIN(12) => \buff2_reg__0_n_141\, PCIN(11) => \buff2_reg__0_n_142\, PCIN(10) => \buff2_reg__0_n_143\, PCIN(9) => \buff2_reg__0_n_144\, PCIN(8) => \buff2_reg__0_n_145\, PCIN(7) => \buff2_reg__0_n_146\, PCIN(6) => \buff2_reg__0_n_147\, PCIN(5) => \buff2_reg__0_n_148\, PCIN(4) => \buff2_reg__0_n_149\, PCIN(3) => \buff2_reg__0_n_150\, PCIN(2) => \buff2_reg__0_n_151\, PCIN(1) => \buff2_reg__0_n_152\, PCIN(0) => \buff2_reg__0_n_153\, PCOUT(47 downto 0) => \NLW_buff3_reg__0_PCOUT_UNCONNECTED\(47 downto 0), RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => '0', UNDERFLOW => \NLW_buff3_reg__0_UNDERFLOW_UNCONNECTED\ ); \buff4_reg[0]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_105\, Q => D(17), R => '0' ); \buff4_reg[0]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_105, Q => D(0) ); \buff4_reg[10]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_95\, Q => D(27), R => '0' ); \buff4_reg[10]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_95, Q => D(10) ); \buff4_reg[11]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_94\, Q => D(28), R => '0' ); \buff4_reg[11]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_94, Q => D(11) ); \buff4_reg[12]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_93\, Q => D(29), R => '0' ); \buff4_reg[12]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_93, Q => D(12) ); \buff4_reg[13]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_92\, Q => D(30), R => '0' ); \buff4_reg[13]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_92, Q => D(13) ); \buff4_reg[14]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_91\, Q => D(31), R => '0' ); \buff4_reg[14]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_91, Q => D(14) ); \buff4_reg[15]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_90, Q => D(15) ); \buff4_reg[16]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_89, Q => D(16) ); \buff4_reg[1]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_104\, Q => D(18), R => '0' ); \buff4_reg[1]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_104, Q => D(1) ); \buff4_reg[2]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_103\, Q => D(19), R => '0' ); \buff4_reg[2]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_103, Q => D(2) ); \buff4_reg[3]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_102\, Q => D(20), R => '0' ); \buff4_reg[3]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_102, Q => D(3) ); \buff4_reg[4]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_101\, Q => D(21), R => '0' ); \buff4_reg[4]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_101, Q => D(4) ); \buff4_reg[5]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_100\, Q => D(22), R => '0' ); \buff4_reg[5]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_100, Q => D(5) ); \buff4_reg[6]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_99\, Q => D(23), R => '0' ); \buff4_reg[6]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_99, Q => D(6) ); \buff4_reg[7]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_98\, Q => D(24), R => '0' ); \buff4_reg[7]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_98, Q => D(7) ); \buff4_reg[8]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_97\, Q => D(25), R => '0' ); \buff4_reg[8]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_97, Q => D(8) ); \buff4_reg[9]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_96\, Q => D(26), R => '0' ); \buff4_reg[9]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_96, Q => D(9) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); ap_clk : in STD_LOGIC; \int_a_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \int_b_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb : entity is "hls_macc_mul_32s_bkb"; end zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb; architecture STRUCTURE of zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb is begin hls_macc_mul_32s_bkb_MulnS_0_U: entity work.zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb_MulnS_0 port map ( D(31 downto 0) => D(31 downto 0), ap_clk => ap_clk, \int_a_reg[31]\(31 downto 0) => \int_a_reg[31]\(31 downto 0), \int_b_reg[31]\(31 downto 0) => \int_b_reg[31]\(31 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zybo_zynq_design_hls_macc_0_0_hls_macc is port ( ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_BVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); interrupt : out STD_LOGIC ); attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is 6; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is 4; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "hls_macc"; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b000000001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b000000010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b000000100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b000001000"; attribute ap_ST_fsm_state5 : string; attribute ap_ST_fsm_state5 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b000010000"; attribute ap_ST_fsm_state6 : string; attribute ap_ST_fsm_state6 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b000100000"; attribute ap_ST_fsm_state7 : string; attribute ap_ST_fsm_state7 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b001000000"; attribute ap_ST_fsm_state8 : string; attribute ap_ST_fsm_state8 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b010000000"; attribute ap_ST_fsm_state9 : string; attribute ap_ST_fsm_state9 of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "9'b100000000"; attribute hls_module : string; attribute hls_module of zybo_zynq_design_hls_macc_0_0_hls_macc : entity is "yes"; end zybo_zynq_design_hls_macc_0_0_hls_macc; architecture STRUCTURE of zybo_zynq_design_hls_macc_0_0_hls_macc is signal \<const0>\ : STD_LOGIC; signal a : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \acc_reg[0]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[0]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[0]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[0]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_5_n_0\ : STD_LOGIC; signal acc_reg_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \acc_reg_reg[0]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_7\ : STD_LOGIC; signal accum_clr_read_reg_85 : STD_LOGIC; signal \ap_CS_fsm[1]_i_3_n_0\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[1]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[2]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[3]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[4]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[5]\ : STD_LOGIC; signal ap_CS_fsm_state7 : STD_LOGIC; signal ap_CS_fsm_state9 : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ap_rst_n_inv : STD_LOGIC; signal b : STD_LOGIC_VECTOR ( 31 downto 0 ); signal hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U_n_73 : STD_LOGIC; signal \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal sel : STD_LOGIC; signal tmp_1_reg_100 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_acc_reg_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute FSM_ENCODING : string; attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[4]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[5]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[6]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[7]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[8]\ : label is "none"; begin s_axi_HLS_MACC_PERIPH_BUS_BRESP(1) <= \<const0>\; s_axi_HLS_MACC_PERIPH_BUS_BRESP(0) <= \<const0>\; s_axi_HLS_MACC_PERIPH_BUS_RRESP(1) <= \<const0>\; s_axi_HLS_MACC_PERIPH_BUS_RRESP(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \acc_reg[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(3), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(3), O => \acc_reg[0]_i_2_n_0\ ); \acc_reg[0]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(2), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(2), O => \acc_reg[0]_i_3_n_0\ ); \acc_reg[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(1), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(1), O => \acc_reg[0]_i_4_n_0\ ); \acc_reg[0]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(0), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(0), O => \acc_reg[0]_i_5_n_0\ ); \acc_reg[12]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(15), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(15), O => \acc_reg[12]_i_2_n_0\ ); \acc_reg[12]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(14), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(14), O => \acc_reg[12]_i_3_n_0\ ); \acc_reg[12]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(13), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(13), O => \acc_reg[12]_i_4_n_0\ ); \acc_reg[12]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(12), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(12), O => \acc_reg[12]_i_5_n_0\ ); \acc_reg[16]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(19), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(19), O => \acc_reg[16]_i_2_n_0\ ); \acc_reg[16]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(18), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(18), O => \acc_reg[16]_i_3_n_0\ ); \acc_reg[16]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(17), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(17), O => \acc_reg[16]_i_4_n_0\ ); \acc_reg[16]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(16), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(16), O => \acc_reg[16]_i_5_n_0\ ); \acc_reg[20]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(23), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(23), O => \acc_reg[20]_i_2_n_0\ ); \acc_reg[20]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(22), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(22), O => \acc_reg[20]_i_3_n_0\ ); \acc_reg[20]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(21), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(21), O => \acc_reg[20]_i_4_n_0\ ); \acc_reg[20]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(20), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(20), O => \acc_reg[20]_i_5_n_0\ ); \acc_reg[24]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(27), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(27), O => \acc_reg[24]_i_2_n_0\ ); \acc_reg[24]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(26), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(26), O => \acc_reg[24]_i_3_n_0\ ); \acc_reg[24]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(25), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(25), O => \acc_reg[24]_i_4_n_0\ ); \acc_reg[24]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(24), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(24), O => \acc_reg[24]_i_5_n_0\ ); \acc_reg[28]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(31), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(31), O => \acc_reg[28]_i_2_n_0\ ); \acc_reg[28]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(30), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(30), O => \acc_reg[28]_i_3_n_0\ ); \acc_reg[28]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(29), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(29), O => \acc_reg[28]_i_4_n_0\ ); \acc_reg[28]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(28), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(28), O => \acc_reg[28]_i_5_n_0\ ); \acc_reg[4]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(7), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(7), O => \acc_reg[4]_i_2_n_0\ ); \acc_reg[4]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(6), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(6), O => \acc_reg[4]_i_3_n_0\ ); \acc_reg[4]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(5), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(5), O => \acc_reg[4]_i_4_n_0\ ); \acc_reg[4]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(4), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(4), O => \acc_reg[4]_i_5_n_0\ ); \acc_reg[8]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(11), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(11), O => \acc_reg[8]_i_2_n_0\ ); \acc_reg[8]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(10), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(10), O => \acc_reg[8]_i_3_n_0\ ); \acc_reg[8]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(9), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(9), O => \acc_reg[8]_i_4_n_0\ ); \acc_reg[8]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(8), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(8), O => \acc_reg[8]_i_5_n_0\ ); \acc_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_7\, Q => acc_reg_reg(0), R => '0' ); \acc_reg_reg[0]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \acc_reg_reg[0]_i_1_n_0\, CO(2) => \acc_reg_reg[0]_i_1_n_1\, CO(1) => \acc_reg_reg[0]_i_1_n_2\, CO(0) => \acc_reg_reg[0]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(3 downto 0), O(3) => \acc_reg_reg[0]_i_1_n_4\, O(2) => \acc_reg_reg[0]_i_1_n_5\, O(1) => \acc_reg_reg[0]_i_1_n_6\, O(0) => \acc_reg_reg[0]_i_1_n_7\, S(3) => \acc_reg[0]_i_2_n_0\, S(2) => \acc_reg[0]_i_3_n_0\, S(1) => \acc_reg[0]_i_4_n_0\, S(0) => \acc_reg[0]_i_5_n_0\ ); \acc_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_5\, Q => acc_reg_reg(10), R => '0' ); \acc_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_4\, Q => acc_reg_reg(11), R => '0' ); \acc_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_7\, Q => acc_reg_reg(12), R => '0' ); \acc_reg_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[8]_i_1_n_0\, CO(3) => \acc_reg_reg[12]_i_1_n_0\, CO(2) => \acc_reg_reg[12]_i_1_n_1\, CO(1) => \acc_reg_reg[12]_i_1_n_2\, CO(0) => \acc_reg_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(15 downto 12), O(3) => \acc_reg_reg[12]_i_1_n_4\, O(2) => \acc_reg_reg[12]_i_1_n_5\, O(1) => \acc_reg_reg[12]_i_1_n_6\, O(0) => \acc_reg_reg[12]_i_1_n_7\, S(3) => \acc_reg[12]_i_2_n_0\, S(2) => \acc_reg[12]_i_3_n_0\, S(1) => \acc_reg[12]_i_4_n_0\, S(0) => \acc_reg[12]_i_5_n_0\ ); \acc_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_6\, Q => acc_reg_reg(13), R => '0' ); \acc_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_5\, Q => acc_reg_reg(14), R => '0' ); \acc_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_4\, Q => acc_reg_reg(15), R => '0' ); \acc_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_7\, Q => acc_reg_reg(16), R => '0' ); \acc_reg_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[12]_i_1_n_0\, CO(3) => \acc_reg_reg[16]_i_1_n_0\, CO(2) => \acc_reg_reg[16]_i_1_n_1\, CO(1) => \acc_reg_reg[16]_i_1_n_2\, CO(0) => \acc_reg_reg[16]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(19 downto 16), O(3) => \acc_reg_reg[16]_i_1_n_4\, O(2) => \acc_reg_reg[16]_i_1_n_5\, O(1) => \acc_reg_reg[16]_i_1_n_6\, O(0) => \acc_reg_reg[16]_i_1_n_7\, S(3) => \acc_reg[16]_i_2_n_0\, S(2) => \acc_reg[16]_i_3_n_0\, S(1) => \acc_reg[16]_i_4_n_0\, S(0) => \acc_reg[16]_i_5_n_0\ ); \acc_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_6\, Q => acc_reg_reg(17), R => '0' ); \acc_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_5\, Q => acc_reg_reg(18), R => '0' ); \acc_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_4\, Q => acc_reg_reg(19), R => '0' ); \acc_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_6\, Q => acc_reg_reg(1), R => '0' ); \acc_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_7\, Q => acc_reg_reg(20), R => '0' ); \acc_reg_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[16]_i_1_n_0\, CO(3) => \acc_reg_reg[20]_i_1_n_0\, CO(2) => \acc_reg_reg[20]_i_1_n_1\, CO(1) => \acc_reg_reg[20]_i_1_n_2\, CO(0) => \acc_reg_reg[20]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(23 downto 20), O(3) => \acc_reg_reg[20]_i_1_n_4\, O(2) => \acc_reg_reg[20]_i_1_n_5\, O(1) => \acc_reg_reg[20]_i_1_n_6\, O(0) => \acc_reg_reg[20]_i_1_n_7\, S(3) => \acc_reg[20]_i_2_n_0\, S(2) => \acc_reg[20]_i_3_n_0\, S(1) => \acc_reg[20]_i_4_n_0\, S(0) => \acc_reg[20]_i_5_n_0\ ); \acc_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_6\, Q => acc_reg_reg(21), R => '0' ); \acc_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_5\, Q => acc_reg_reg(22), R => '0' ); \acc_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_4\, Q => acc_reg_reg(23), R => '0' ); \acc_reg_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_7\, Q => acc_reg_reg(24), R => '0' ); \acc_reg_reg[24]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[20]_i_1_n_0\, CO(3) => \acc_reg_reg[24]_i_1_n_0\, CO(2) => \acc_reg_reg[24]_i_1_n_1\, CO(1) => \acc_reg_reg[24]_i_1_n_2\, CO(0) => \acc_reg_reg[24]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(27 downto 24), O(3) => \acc_reg_reg[24]_i_1_n_4\, O(2) => \acc_reg_reg[24]_i_1_n_5\, O(1) => \acc_reg_reg[24]_i_1_n_6\, O(0) => \acc_reg_reg[24]_i_1_n_7\, S(3) => \acc_reg[24]_i_2_n_0\, S(2) => \acc_reg[24]_i_3_n_0\, S(1) => \acc_reg[24]_i_4_n_0\, S(0) => \acc_reg[24]_i_5_n_0\ ); \acc_reg_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_6\, Q => acc_reg_reg(25), R => '0' ); \acc_reg_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_5\, Q => acc_reg_reg(26), R => '0' ); \acc_reg_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_4\, Q => acc_reg_reg(27), R => '0' ); \acc_reg_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_7\, Q => acc_reg_reg(28), R => '0' ); \acc_reg_reg[28]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[24]_i_1_n_0\, CO(3) => \NLW_acc_reg_reg[28]_i_1_CO_UNCONNECTED\(3), CO(2) => \acc_reg_reg[28]_i_1_n_1\, CO(1) => \acc_reg_reg[28]_i_1_n_2\, CO(0) => \acc_reg_reg[28]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => tmp_1_reg_100(30 downto 28), O(3) => \acc_reg_reg[28]_i_1_n_4\, O(2) => \acc_reg_reg[28]_i_1_n_5\, O(1) => \acc_reg_reg[28]_i_1_n_6\, O(0) => \acc_reg_reg[28]_i_1_n_7\, S(3) => \acc_reg[28]_i_2_n_0\, S(2) => \acc_reg[28]_i_3_n_0\, S(1) => \acc_reg[28]_i_4_n_0\, S(0) => \acc_reg[28]_i_5_n_0\ ); \acc_reg_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_6\, Q => acc_reg_reg(29), R => '0' ); \acc_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_5\, Q => acc_reg_reg(2), R => '0' ); \acc_reg_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_5\, Q => acc_reg_reg(30), R => '0' ); \acc_reg_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_4\, Q => acc_reg_reg(31), R => '0' ); \acc_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_4\, Q => acc_reg_reg(3), R => '0' ); \acc_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_7\, Q => acc_reg_reg(4), R => '0' ); \acc_reg_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[0]_i_1_n_0\, CO(3) => \acc_reg_reg[4]_i_1_n_0\, CO(2) => \acc_reg_reg[4]_i_1_n_1\, CO(1) => \acc_reg_reg[4]_i_1_n_2\, CO(0) => \acc_reg_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(7 downto 4), O(3) => \acc_reg_reg[4]_i_1_n_4\, O(2) => \acc_reg_reg[4]_i_1_n_5\, O(1) => \acc_reg_reg[4]_i_1_n_6\, O(0) => \acc_reg_reg[4]_i_1_n_7\, S(3) => \acc_reg[4]_i_2_n_0\, S(2) => \acc_reg[4]_i_3_n_0\, S(1) => \acc_reg[4]_i_4_n_0\, S(0) => \acc_reg[4]_i_5_n_0\ ); \acc_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_6\, Q => acc_reg_reg(5), R => '0' ); \acc_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_5\, Q => acc_reg_reg(6), R => '0' ); \acc_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_4\, Q => acc_reg_reg(7), R => '0' ); \acc_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_7\, Q => acc_reg_reg(8), R => '0' ); \acc_reg_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[4]_i_1_n_0\, CO(3) => \acc_reg_reg[8]_i_1_n_0\, CO(2) => \acc_reg_reg[8]_i_1_n_1\, CO(1) => \acc_reg_reg[8]_i_1_n_2\, CO(0) => \acc_reg_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(11 downto 8), O(3) => \acc_reg_reg[8]_i_1_n_4\, O(2) => \acc_reg_reg[8]_i_1_n_5\, O(1) => \acc_reg_reg[8]_i_1_n_6\, O(0) => \acc_reg_reg[8]_i_1_n_7\, S(3) => \acc_reg[8]_i_2_n_0\, S(2) => \acc_reg[8]_i_3_n_0\, S(1) => \acc_reg[8]_i_4_n_0\, S(0) => \acc_reg[8]_i_5_n_0\ ); \acc_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_6\, Q => acc_reg_reg(9), R => '0' ); \accum_clr_read_reg_85_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U_n_73, Q => accum_clr_read_reg_85, R => '0' ); \ap_CS_fsm[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \ap_CS_fsm_reg_n_0_[4]\, I1 => \ap_CS_fsm_reg_n_0_[5]\, I2 => \ap_CS_fsm_reg_n_0_[2]\, I3 => \ap_CS_fsm_reg_n_0_[3]\, O => \ap_CS_fsm[1]_i_3_n_0\ ); \ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(0), Q => \ap_CS_fsm_reg_n_0_[0]\, S => ap_rst_n_inv ); \ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(1), Q => \ap_CS_fsm_reg_n_0_[1]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[1]\, Q => \ap_CS_fsm_reg_n_0_[2]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[2]\, Q => \ap_CS_fsm_reg_n_0_[3]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[3]\, Q => \ap_CS_fsm_reg_n_0_[4]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[4]\, Q => \ap_CS_fsm_reg_n_0_[5]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[5]\, Q => ap_CS_fsm_state7, R => ap_rst_n_inv ); \ap_CS_fsm_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_CS_fsm_state7, Q => sel, R => ap_rst_n_inv ); \ap_CS_fsm_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => sel, Q => ap_CS_fsm_state9, R => ap_rst_n_inv ); hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U: entity work.zybo_zynq_design_hls_macc_0_0_hls_macc_HLS_MACC_PERIPH_BUS_s_axi port map ( D(1 downto 0) => ap_NS_fsm(1 downto 0), Q(4) => ap_CS_fsm_state9, Q(3) => sel, Q(2) => ap_CS_fsm_state7, Q(1) => \ap_CS_fsm_reg_n_0_[1]\, Q(0) => \ap_CS_fsm_reg_n_0_[0]\, SR(0) => ap_rst_n_inv, \a_reg0_reg[31]\(31 downto 0) => b(31 downto 0), \acc_reg_reg[31]\(31 downto 0) => acc_reg_reg(31 downto 0), accum_clr_read_reg_85 => accum_clr_read_reg_85, \accum_clr_read_reg_85_reg[0]\ => hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U_n_73, \ap_CS_fsm_reg[4]\ => \ap_CS_fsm[1]_i_3_n_0\, ap_clk => ap_clk, ap_rst_n => ap_rst_n, \buff2_reg__0\(31 downto 0) => a(31 downto 0), interrupt => interrupt, \out\(2) => s_axi_HLS_MACC_PERIPH_BUS_BVALID, \out\(1) => s_axi_HLS_MACC_PERIPH_BUS_WREADY, \out\(0) => s_axi_HLS_MACC_PERIPH_BUS_AWREADY, s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_ARVALID => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_AWVALID => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, s_axi_HLS_MACC_PERIPH_BUS_BREADY => s_axi_HLS_MACC_PERIPH_BUS_BREADY, s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_RREADY => s_axi_HLS_MACC_PERIPH_BUS_RREADY, s_axi_HLS_MACC_PERIPH_BUS_RVALID(1) => s_axi_HLS_MACC_PERIPH_BUS_RVALID, s_axi_HLS_MACC_PERIPH_BUS_RVALID(0) => s_axi_HLS_MACC_PERIPH_BUS_ARREADY, s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WVALID => s_axi_HLS_MACC_PERIPH_BUS_WVALID ); hls_macc_mul_32s_bkb_U1: entity work.zybo_zynq_design_hls_macc_0_0_hls_macc_mul_32s_bkb port map ( D(31 downto 0) => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(31 downto 0), ap_clk => ap_clk, \int_a_reg[31]\(31 downto 0) => a(31 downto 0), \int_b_reg[31]\(31 downto 0) => b(31 downto 0) ); \tmp_1_reg_100_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(0), Q => tmp_1_reg_100(0), R => '0' ); \tmp_1_reg_100_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(10), Q => tmp_1_reg_100(10), R => '0' ); \tmp_1_reg_100_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(11), Q => tmp_1_reg_100(11), R => '0' ); \tmp_1_reg_100_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(12), Q => tmp_1_reg_100(12), R => '0' ); \tmp_1_reg_100_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(13), Q => tmp_1_reg_100(13), R => '0' ); \tmp_1_reg_100_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(14), Q => tmp_1_reg_100(14), R => '0' ); \tmp_1_reg_100_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(15), Q => tmp_1_reg_100(15), R => '0' ); \tmp_1_reg_100_reg[16]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(16), Q => tmp_1_reg_100(16), R => '0' ); \tmp_1_reg_100_reg[17]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(17), Q => tmp_1_reg_100(17), R => '0' ); \tmp_1_reg_100_reg[18]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(18), Q => tmp_1_reg_100(18), R => '0' ); \tmp_1_reg_100_reg[19]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(19), Q => tmp_1_reg_100(19), R => '0' ); \tmp_1_reg_100_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(1), Q => tmp_1_reg_100(1), R => '0' ); \tmp_1_reg_100_reg[20]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(20), Q => tmp_1_reg_100(20), R => '0' ); \tmp_1_reg_100_reg[21]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(21), Q => tmp_1_reg_100(21), R => '0' ); \tmp_1_reg_100_reg[22]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(22), Q => tmp_1_reg_100(22), R => '0' ); \tmp_1_reg_100_reg[23]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(23), Q => tmp_1_reg_100(23), R => '0' ); \tmp_1_reg_100_reg[24]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(24), Q => tmp_1_reg_100(24), R => '0' ); \tmp_1_reg_100_reg[25]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(25), Q => tmp_1_reg_100(25), R => '0' ); \tmp_1_reg_100_reg[26]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(26), Q => tmp_1_reg_100(26), R => '0' ); \tmp_1_reg_100_reg[27]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(27), Q => tmp_1_reg_100(27), R => '0' ); \tmp_1_reg_100_reg[28]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(28), Q => tmp_1_reg_100(28), R => '0' ); \tmp_1_reg_100_reg[29]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(29), Q => tmp_1_reg_100(29), R => '0' ); \tmp_1_reg_100_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(2), Q => tmp_1_reg_100(2), R => '0' ); \tmp_1_reg_100_reg[30]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(30), Q => tmp_1_reg_100(30), R => '0' ); \tmp_1_reg_100_reg[31]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(31), Q => tmp_1_reg_100(31), R => '0' ); \tmp_1_reg_100_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(3), Q => tmp_1_reg_100(3), R => '0' ); \tmp_1_reg_100_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(4), Q => tmp_1_reg_100(4), R => '0' ); \tmp_1_reg_100_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(5), Q => tmp_1_reg_100(5), R => '0' ); \tmp_1_reg_100_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(6), Q => tmp_1_reg_100(6), R => '0' ); \tmp_1_reg_100_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(7), Q => tmp_1_reg_100(7), R => '0' ); \tmp_1_reg_100_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(8), Q => tmp_1_reg_100(8), R => '0' ); \tmp_1_reg_100_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(9), Q => tmp_1_reg_100(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zybo_zynq_design_hls_macc_0_0 is port ( s_axi_HLS_MACC_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_AWVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_BVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of zybo_zynq_design_hls_macc_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of zybo_zynq_design_hls_macc_0_0 : entity is "zybo_zynq_design_hls_macc_0_0,hls_macc,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of zybo_zynq_design_hls_macc_0_0 : entity is "yes"; attribute IP_DEFINITION_SOURCE : string; attribute IP_DEFINITION_SOURCE of zybo_zynq_design_hls_macc_0_0 : entity is "HLS"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of zybo_zynq_design_hls_macc_0_0 : entity is "hls_macc,Vivado 2018.2"; attribute hls_module : string; attribute hls_module of zybo_zynq_design_hls_macc_0_0 : entity is "yes"; end zybo_zynq_design_hls_macc_0_0; architecture STRUCTURE of zybo_zynq_design_hls_macc_0_0 is attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH of inst : label is 6; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH of inst : label is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of inst : label is "9'b000000001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of inst : label is "9'b000000010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of inst : label is "9'b000000100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of inst : label is "9'b000001000"; attribute ap_ST_fsm_state5 : string; attribute ap_ST_fsm_state5 of inst : label is "9'b000010000"; attribute ap_ST_fsm_state6 : string; attribute ap_ST_fsm_state6 of inst : label is "9'b000100000"; attribute ap_ST_fsm_state7 : string; attribute ap_ST_fsm_state7 of inst : label is "9'b001000000"; attribute ap_ST_fsm_state8 : string; attribute ap_ST_fsm_state8 of inst : label is "9'b010000000"; attribute ap_ST_fsm_state9 : string; attribute ap_ST_fsm_state9 of inst : label is "9'b100000000"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_HLS_MACC_PERIPH_BUS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST"; attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}"; attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT"; attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_HLS_MACC_PERIPH_BUS_RREADY : signal is "XIL_INTERFACENAME s_axi_HLS_MACC_PERIPH_BUS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARADDR"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWADDR"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BRESP"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RDATA"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RRESP"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WDATA"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WSTRB"; begin inst: entity work.zybo_zynq_design_hls_macc_0_0_hls_macc port map ( ap_clk => ap_clk, ap_rst_n => ap_rst_n, interrupt => interrupt, s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_ARREADY => s_axi_HLS_MACC_PERIPH_BUS_ARREADY, s_axi_HLS_MACC_PERIPH_BUS_ARVALID => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_AWREADY => s_axi_HLS_MACC_PERIPH_BUS_AWREADY, s_axi_HLS_MACC_PERIPH_BUS_AWVALID => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, s_axi_HLS_MACC_PERIPH_BUS_BREADY => s_axi_HLS_MACC_PERIPH_BUS_BREADY, s_axi_HLS_MACC_PERIPH_BUS_BRESP(1 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_BRESP(1 downto 0), s_axi_HLS_MACC_PERIPH_BUS_BVALID => s_axi_HLS_MACC_PERIPH_BUS_BVALID, s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_RREADY => s_axi_HLS_MACC_PERIPH_BUS_RREADY, s_axi_HLS_MACC_PERIPH_BUS_RRESP(1 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_RRESP(1 downto 0), s_axi_HLS_MACC_PERIPH_BUS_RVALID => s_axi_HLS_MACC_PERIPH_BUS_RVALID, s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WREADY => s_axi_HLS_MACC_PERIPH_BUS_WREADY, s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WVALID => s_axi_HLS_MACC_PERIPH_BUS_WVALID ); end STRUCTURE;
mit
e549657602a4f254733a5fb41788d41a
0.521252
2.551202
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/e50e3d2e678dd930/design_1_auto_pc_0_sim_netlist.vhdl
1
517,925
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:58:12 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_sim_netlist.vhdl -- Design : design_1_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[5]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113"; begin Q(0) <= \^q\(0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0); \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => \axaddr_incr[0]_i_1_n_0\ ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => \axaddr_incr[10]_i_1_n_0\ ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \next\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => \axaddr_incr[11]_i_2_n_0\ ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => \axaddr_incr[1]_i_1_n_0\ ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => \axaddr_incr[2]_i_1_n_0\ ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => \axaddr_incr[3]_i_1_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0102" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"262A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"060A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), I3 => \next\, O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => \axaddr_incr[4]_i_1_n_0\ ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => \axaddr_incr[5]_i_1_n_0\ ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => \axaddr_incr[6]_i_1_n_0\ ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => \axaddr_incr[7]_i_1_n_0\ ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => \axaddr_incr[8]_i_1_n_0\ ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => \axaddr_incr[9]_i_1_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[0]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[10]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[11]_i_2_n_0\, Q => \^axaddr_incr_reg[11]_0\(10), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[1]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[2]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[3]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[4]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[5]_i_1_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[6]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[7]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[8]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[9]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \^q\(0), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[2]_0\, I4 => E(0), I5 => \m_payload_i_reg[46]\(9), O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), I5 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \^q\(0), I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \state_reg[1]\(0), Q => \^q\(0), R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(7), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => \m_payload_i_reg[46]\(7), I3 => \m_payload_i_reg[46]\(4), O => \m_axi_awaddr[5]\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[2]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; \m_axi_araddr[5]\ : out STD_LOGIC; \m_axi_araddr[3]\ : out STD_LOGIC; \m_axi_araddr[2]\ : out STD_LOGIC; \m_axi_araddr[1]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC; signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0201020202020202" ) port map ( I0 => Q(0), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[1]\, I1 => Q(6), I2 => Q(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => Q(3), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A262A2A2A2A2A2A" ) port map ( I0 => Q(2), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A060A0A0A0A0A0A" ) port map ( I0 => Q(1), I1 => Q(5), I2 => Q(6), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[1]\, R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1) => \axaddr_incr_reg_n_0_[1]\, DI(0) => \^axaddr_incr_reg[11]_0\(0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(1) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(8), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(9), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[0]_0\, I4 => E(0), I5 => Q(10), O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => \next_pending_r_i_4__0_n_0\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => Q(7), O => \m_axi_araddr[11]\ ); \m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[1]\, I2 => Q(7), I3 => Q(1), O => \m_axi_araddr[1]\ ); \m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => Q(7), I3 => Q(2), O => \m_axi_araddr[2]\ ); \m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => Q(7), I3 => Q(3), O => \m_axi_araddr[3]\ ); \m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => Q(7), I3 => Q(4), O => \m_axi_araddr[5]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__0_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[47]_0\, O => \^incr_next_pending\ ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \next_pending_r_i_4__0_n_0\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, O => \next_pending_r_i_2__0_n_0\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \next_pending_r_i_4__0_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_i : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[7]_0\ : in STD_LOGIC; s_axburst_eq1_reg : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4"; begin Q(1 downto 0) <= \^q\(1 downto 0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AAEA" ) port map ( I0 => sel_first, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(0), I2 => \^m_payload_i_reg[0]_0\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"00CA" ) port map ( I0 => si_rs_arvalid, I1 => m_axi_arready, I2 => \^q\(0), I3 => \^q\(1), O => E(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00005140" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => m_axi_arready, I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[7]_0\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => si_rs_arvalid, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => m_axi_arready, O => r_push_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8FFF8F8F" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => s_ready_i0 ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFFFFCCCECCCE" ) port map ( I0 => si_rs_arvalid, I1 => areset_d1, I2 => \^m_payload_i_reg[0]\, I3 => \^m_payload_i_reg[0]_0\, I4 => m_axi_arready, I5 => sel_first_reg_2, O => sel_first_i ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"003030303E3E3E3E" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(1), I2 => \^q\(0), I3 => m_axi_arready, I4 => s_axburst_eq1_reg, I5 => \cnt_read_reg[2]_rep__0\, O => \next_state__0\(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00AAB000" ) port map ( I0 => \cnt_read_reg[2]_rep__0\, I1 => s_axburst_eq1_reg, I2 => m_axi_arready, I3 => \^m_payload_i_reg[0]_0\, I4 => \^m_payload_i_reg[0]\, O => \next_state__0\(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \wrap_boundary_axaddr_r_reg[11]\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; si_rs_bready : in STD_LOGIC; bvalid_i_reg_0 : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"EEFEFFFFFFFFEEFE" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \bresp_cnt_reg[7]\(6), I2 => \bresp_cnt_reg[7]\(0), I3 => \memory_reg[3][0]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF6FFFF" ) port map ( I0 => \bresp_cnt_reg[7]\(1), I1 => \memory_reg[3][1]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(4), I3 => \bresp_cnt_reg[7]\(5), I4 => mhandshake_r, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000D00DD00DD00D" ) port map ( I0 => \memory_reg[3][0]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(0), I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \^cnt_read_reg[1]_rep__0_0\, I5 => \^cnt_read_reg[0]_rep__0_0\, O => \bresp_cnt[7]_i_5_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bready, I3 => bvalid_i_reg_0, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => shandshake_r, I3 => Q(1), I4 => Q(0), I5 => bvalid_i_reg_0, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => shandshake_r, I2 => Q(0), O => D(0) ); \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000041004141" ) port map ( I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\, I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, I5 => \memory_reg[3][0]_srl4_i_3_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFFFFFFFFFB" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(5), I3 => \bresp_cnt_reg[7]\(4), I4 => \memory_reg[3][1]_srl4_n_0\, I5 => \bresp_cnt_reg[7]\(1), O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); mhandshake : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A69A" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => shandshake_r, I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(0), I3 => \^q\(1), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal wr_en0 : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19"; begin \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; \cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => s_ready_i_reg, I3 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9AAAA6A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAA6AA9AAAAAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"99AA99AA99AA55A6" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_1\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_2\, I3 => \cnt_read[4]_i_3__0_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_2\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read[4]_i_5_n_0\, I3 => \cnt_read_reg[4]_rep__0_0\, I4 => si_rs_rready, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6000E000FFFFFFFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, I5 => m_axi_rvalid, O => \cnt_read[4]_i_5_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__3_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_1\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"9FFF1FFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA0AAA0AAAAAAA" ) port map ( I0 => m_axi_rvalid, I1 => \cnt_read_reg[0]_rep__3_n_0\, I2 => \^cnt_read_reg[4]_rep__2_0\, I3 => \^cnt_read_reg[4]_rep__2_1\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[2]_rep__2_n_0\, O => wr_en0 ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"40C0C000" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[2]_rep__2_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); s_ready_i_reg : in STD_LOGIC; r_push_r : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"DB24" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7F0080FEFF0100" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9A999AAA" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA2AAA2AAA" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => r_push_r, I4 => \^m_valid_i_reg\, I5 => si_rs_rready, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => r_push_r, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => \cnt_read_reg[0]_rep__1_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"80808080FF808080" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read_reg[3]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2\, I5 => \cnt_read_reg[0]_rep__3\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__1_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"BFEEAAAAAAAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__3_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => \cnt_read_reg[1]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[4]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \axlen_cnt_reg[7]_1\ : out STD_LOGIC; \next\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axburst_eq0_reg : out STD_LOGIC; incr_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[7]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wrap_next_pending : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[7]\ : STD_LOGIC; signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \^next\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \state[0]_i_1_n_0\ : STD_LOGIC; signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\; \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; \next\ <= \^next\; sel_first_i <= \^sel_first_i\; \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(2), I2 => \^axlen_cnt_reg[7]_0\, I3 => si_rs_awvalid, I4 => \^axlen_cnt_reg[7]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0400FFFF04000400" ) port map ( I0 => \^q\(1), I1 => si_rs_awvalid, I2 => \^q\(0), I3 => \m_payload_i_reg[46]\(1), I4 => \axlen_cnt_reg[0]_0\(0), I5 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[0]\(0) ); \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^next\, O => \axaddr_wrap_reg[11]\(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF04" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]\, I3 => \^next\, I4 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[7]_1\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"88008888A800A8A8" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, I2 => m_axi_awready, I3 => \cnt_read_reg[0]_rep__0\, I4 => \cnt_read_reg[1]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF404" ) port map ( I0 => \^e\(0), I1 => next_pending_r_reg, I2 => \^next\, I3 => \axlen_cnt_reg[7]_2\, I4 => \m_payload_i_reg[47]\, O => \^incr_next_pending\ ); next_pending_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F3F3FFFF51000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \^next\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => \^incr_next_pending\, I1 => \^sel_first_i\, I2 => \m_payload_i_reg[46]\(0), I3 => wrap_next_pending, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => \^incr_next_pending\, I1 => \m_payload_i_reg[46]\(0), I2 => \^sel_first_i\, I3 => wrap_next_pending, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first_0, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF04FFFFFF04FF04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, I3 => areset_d1, I4 => \^next\, I5 => sel_first_reg_1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => \state[0]_i_2_n_0\, I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), O => \state[0]_i_1_n_0\ ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00F000F055750000" ) port map ( I0 => m_axi_awready, I1 => s_axburst_eq1_reg_0, I2 => \cnt_read_reg[1]_rep__0\, I3 => \cnt_read_reg[0]_rep__0\, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \state[0]_i_2_n_0\ ); \state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0C0CAE0000000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]\, I5 => \^axlen_cnt_reg[7]_0\, O => \state[1]_i_1__0_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^axlen_cnt_reg[7]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^axlen_cnt_reg[7]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is port ( wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \next\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); sel_first_reg_3 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin sel_first_reg_0 <= \^sel_first_reg_0\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(0), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(0), I3 => \next\, I4 => \m_payload_i_reg[47]\(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(10), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(10), I3 => \next\, I4 => \m_payload_i_reg[47]\(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(11), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(11), I3 => \next\, I4 => \m_payload_i_reg[47]\(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4_n_0\, I1 => wrap_cnt_r(3), I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(1), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(1), I3 => \next\, I4 => \m_payload_i_reg[47]\(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(2), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(2), I3 => \next\, I4 => \m_payload_i_reg[47]\(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(3), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(3), I3 => \next\, I4 => \m_payload_i_reg[47]\(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[47]\(13), I2 => \m_payload_i_reg[47]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(4), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(4), I3 => \next\, I4 => \m_payload_i_reg[47]\(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(5), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(5), I3 => \next\, I4 => \m_payload_i_reg[47]\(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(6), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(6), I3 => \next\, I4 => \m_payload_i_reg[47]\(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(7), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(7), I3 => \next\, I4 => \m_payload_i_reg[47]\(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(8), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(8), I3 => \next\, I4 => \m_payload_i_reg[47]\(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(9), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(9), I3 => \next\, I4 => \m_payload_i_reg[47]\(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => \m_payload_i_reg[47]\(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => \m_payload_i_reg[47]\(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => \m_payload_i_reg[47]\(17), O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => \m_payload_i_reg[47]\(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(2), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(3), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[47]\(5), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(5), I3 => \m_payload_i_reg[47]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(9) ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]_0\, I1 => next_pending_r_reg_n_0, I2 => \next\, I3 => \next_pending_r_i_2__1_n_0\, I4 => E(0), O => \^wrap_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_awvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^wrap_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => wrap_cnt(1) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cnt(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is port ( sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); sel_first_i : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; sel_first_reg_5 : in STD_LOGIC; sel_first_reg_6 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4__0_n_0\, I1 => \wrap_cnt_r_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => Q(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => Q(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => Q(17), O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => Q(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(1), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[1]\, I3 => Q(14), I4 => sel_first_reg_6, O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(2), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[2]\, I3 => Q(14), I4 => sel_first_reg_5, O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(3), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[3]\, I3 => Q(14), I4 => sel_first_reg_4, O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(5), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[5]\, I3 => Q(14), I4 => sel_first_reg_3, O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(9) ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => \next_pending_r_i_2__2_n_0\, I4 => E(0), O => wrap_next_pending ); \next_pending_r_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_arvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__2_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_n_0, R => '0' ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq1_reg ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1__0_n_0\ ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1__0_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[0]\ : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2__0_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2__0_n_0\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2__0_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_0\(0) ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2__0_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_0\(1) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^axaddr_offset_r_reg[3]\, R => \^m_valid_i_reg_0\ ); next_pending_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r_reg[3]\(0) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => \wrap_cnt_r_reg[3]\(1) ); \wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_1\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2__0_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5__0_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5__0_n_0\ ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset_0\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_0\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3__0_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(1), O => \^axaddr_offset\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2_n_0\ ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(2), O => \^axaddr_offset\(1) ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => D(1) ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5_n_0\ ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2_n_0\ ); \wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[4]_rep__0\, O => \cnt_read_reg[2]_rep__0\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \cnt_read_reg[4]_rep__0\, I3 => \^skid_buffer_reg[0]_0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \cnt_read_reg[4]_rep__0\, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_5, bvalid_i_reg_0 => \^si_rs_bvalid\, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(1), I1 => \bresp_cnt_reg__0\(0), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_6_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_6_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_6_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_5, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACEAAAA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[0]\, I1 => m_axi_bresp(0), I2 => m_axi_bresp(1), I3 => \s_bresp_acc_reg_n_0_[1]\, I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EC" ) port map ( I0 => m_axi_bresp(1), I1 => \s_bresp_acc_reg_n_0_[1]\, I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^si_rs_bvalid\, I1 => si_rs_bready, O => shandshake ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \m_payload_i_reg[47]_1\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_16 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd port map ( E(0) => E(0), Q(0) => Q(0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14, \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_15, \m_axi_awaddr[5]\ => incr_cmd_0_n_16, \m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17), \m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12), \m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \next\ => \next\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(0) => \state_reg[1]_0\(0) ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[47]\(15), I2 => s_axburst_eq0, O => \state_reg[1]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), aclk => aclk, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15), \m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_15, sel_first_reg_3 => incr_cmd_0_n_16, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is port ( sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; signal wrap_cmd_0_n_6 : STD_LOGIC; signal wrap_cmd_0_n_7 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17"; begin incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(10 downto 8) => Q(18 downto 16), Q(7 downto 5) => Q(14 downto 12), Q(4) => Q(5), Q(3 downto 0) => Q(3 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_11, \m_axi_araddr[1]\ => incr_cmd_0_n_15, \m_axi_araddr[2]\ => incr_cmd_0_n_14, \m_axi_araddr[3]\ => incr_cmd_0_n_13, \m_axi_araddr[5]\ => incr_cmd_0_n_12, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]_0\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_6, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_7, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(18 downto 14) => Q(19 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), s_axburst_eq0_reg => wrap_cmd_0_n_6, s_axburst_eq1_reg => wrap_cmd_0_n_7, sel_first_i => sel_first_i, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_11, sel_first_reg_3 => incr_cmd_0_n_12, sel_first_reg_4 => incr_cmd_0_n_13, sel_first_reg_5 => incr_cmd_0_n_14, sel_first_reg_6 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_1 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_4 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \state_reg[1]_rep_0\, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1, \cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_4 ); transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2, \cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]_0\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_2\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \wrap_second_len_r_reg[1]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_4\ : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \state_reg[1]_rep_2\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice is signal \ar.ar_pipe_n_2\ : STD_LOGIC; signal \aw.aw_pipe_n_1\ : STD_LOGIC; signal \aw.aw_pipe_n_90\ : STD_LOGIC; begin \ar.ar_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset_0(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\, \axaddr_offset_r_reg[3]\ => si_rs_arvalid, \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \ar.ar_pipe_n_2\, m_valid_i_reg_1(0) => m_valid_i_reg(0), next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_ready_i0 => s_ready_i0, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_2\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\, \wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0) ); \aw.aw_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 port map ( D(1 downto 0) => D(1 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\, \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \aw.aw_pipe_n_1\, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_0\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \b.b_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \r.r_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), \cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\, r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); r_rlast : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_10 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal ar_cmd_fsm_0_n_8 : STD_LOGIC; signal ar_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_10 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_3 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push_r_reg\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm port map ( D(0) => ar_cmd_fsm_0_n_6, E(0) => ar_cmd_fsm_0_n_8, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[46]\(0) => Q(18), \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, m_valid_i0 => m_valid_i0, r_push_r_reg => \^r_push_r_reg\, s_axburst_eq1_reg => cmd_translator_0_n_10, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => s_ready_i0, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_9, sel_first_reg_0 => ar_cmd_fsm_0_n_10, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => cmd_translator_0_n_0, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(19 downto 0) => Q(19 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]\ => cmd_translator_0_n_3, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_8, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_0, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => ar_cmd_fsm_0_n_10, sel_first_reg_3 => ar_cmd_fsm_0_n_9, sel_first_reg_4(0) => ar_cmd_fsm_0_n_16, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_10, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\ => ar_cmd_fsm_0_n_0, \state_reg[1]_rep\ => \^r_push_r_reg\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0), \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); si_rs_awvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel is signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_14 : STD_LOGIC; signal aw_cmd_fsm_0_n_15 : STD_LOGIC; signal aw_cmd_fsm_0_n_16 : STD_LOGIC; signal aw_cmd_fsm_0_n_2 : STD_LOGIC; signal aw_cmd_fsm_0_n_8 : STD_LOGIC; signal aw_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_12 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \next\ : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm port map ( D(0) => wrap_cnt(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14, \axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8, \axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\, \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\, \axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2, \axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[46]\(2) => Q(18), \m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, s_axburst_eq0_reg => aw_cmd_fsm_0_n_9, s_axburst_eq1_reg => aw_cmd_fsm_0_n_12, s_axburst_eq1_reg_0 => cmd_translator_0_n_12, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_15, sel_first_reg_0 => aw_cmd_fsm_0_n_16, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(0) => cmd_translator_0_n_5, S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12, \m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_16, sel_first_reg_2 => aw_cmd_fsm_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_14, \state_reg[0]_rep\ => aw_cmd_fsm_0_n_2, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8, \state_reg[1]_rep\ => cmd_translator_0_n_12, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0), \wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awready : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_10\ : STD_LOGIC; signal \RD.ar_channel_0_n_11\ : STD_LOGIC; signal \RD.ar_channel_0_n_16\ : STD_LOGIC; signal \RD.ar_channel_0_n_3\ : STD_LOGIC; signal \RD.ar_channel_0_n_4\ : STD_LOGIC; signal \RD.ar_channel_0_n_46\ : STD_LOGIC; signal \RD.ar_channel_0_n_47\ : STD_LOGIC; signal \RD.ar_channel_0_n_48\ : STD_LOGIC; signal \RD.ar_channel_0_n_49\ : STD_LOGIC; signal \RD.ar_channel_0_n_5\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_132 : STD_LOGIC; signal SI_REG_n_133 : STD_LOGIC; signal SI_REG_n_134 : STD_LOGIC; signal SI_REG_n_135 : STD_LOGIC; signal SI_REG_n_136 : STD_LOGIC; signal SI_REG_n_137 : STD_LOGIC; signal SI_REG_n_138 : STD_LOGIC; signal SI_REG_n_139 : STD_LOGIC; signal SI_REG_n_140 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_149 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_155 : STD_LOGIC; signal SI_REG_n_156 : STD_LOGIC; signal SI_REG_n_157 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_181 : STD_LOGIC; signal SI_REG_n_182 : STD_LOGIC; signal SI_REG_n_26 : STD_LOGIC; signal SI_REG_n_64 : STD_LOGIC; signal SI_REG_n_8 : STD_LOGIC; signal SI_REG_n_82 : STD_LOGIC; signal \WR.aw_channel_0_n_0\ : STD_LOGIC; signal \WR.aw_channel_0_n_10\ : STD_LOGIC; signal \WR.aw_channel_0_n_15\ : STD_LOGIC; signal \WR.aw_channel_0_n_3\ : STD_LOGIC; signal \WR.aw_channel_0_n_4\ : STD_LOGIC; signal \WR.aw_channel_0_n_47\ : STD_LOGIC; signal \WR.aw_channel_0_n_48\ : STD_LOGIC; signal \WR.aw_channel_0_n_49\ : STD_LOGIC; signal \WR.aw_channel_0_n_50\ : STD_LOGIC; signal \WR.aw_channel_0_n_9\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw.aw_pipe/p_1_in\ : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel port map ( D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), E(0) => \ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(31 downto 20) => s_arid(11 downto 0), Q(19 downto 16) => si_rs_arlen(3 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_82, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_46\, S(2) => \RD.ar_channel_0_n_47\, S(1) => \RD.ar_channel_0_n_48\, S(0) => \RD.ar_channel_0_n_49\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_161, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_165, \cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\, \m_payload_i_reg[3]\(3) => SI_REG_n_132, \m_payload_i_reg[3]\(2) => SI_REG_n_133, \m_payload_i_reg[3]\(1) => SI_REG_n_134, \m_payload_i_reg[3]\(0) => SI_REG_n_135, \m_payload_i_reg[47]\ => SI_REG_n_64, \m_payload_i_reg[47]_0\ => SI_REG_n_167, \m_payload_i_reg[5]\ => SI_REG_n_166, \m_payload_i_reg[6]\(6) => SI_REG_n_176, \m_payload_i_reg[6]\(5) => SI_REG_n_177, \m_payload_i_reg[6]\(4) => SI_REG_n_178, \m_payload_i_reg[6]\(3) => SI_REG_n_179, \m_payload_i_reg[6]\(2) => SI_REG_n_180, \m_payload_i_reg[6]\(1) => SI_REG_n_181, \m_payload_i_reg[6]\(0) => SI_REG_n_182, \m_payload_i_reg[7]\(3) => SI_REG_n_136, \m_payload_i_reg[7]\(2) => SI_REG_n_137, \m_payload_i_reg[7]\(1) => SI_REG_n_138, \m_payload_i_reg[7]\(0) => SI_REG_n_139, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push_r_reg => \RD.ar_channel_0_n_3\, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => \ar.ar_pipe/s_ready_i0\, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\, \wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\, \wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0), \wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157 ); \RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_168, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\ ); SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_26, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_132, \axaddr_incr_reg[3]\(2) => SI_REG_n_133, \axaddr_incr_reg[3]\(1) => SI_REG_n_134, \axaddr_incr_reg[3]\(0) => SI_REG_n_135, \axaddr_incr_reg[7]\(3) => SI_REG_n_136, \axaddr_incr_reg[7]\(2) => SI_REG_n_137, \axaddr_incr_reg[7]\(1) => SI_REG_n_138, \axaddr_incr_reg[7]\(0) => SI_REG_n_139, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\ => SI_REG_n_154, \axaddr_offset_r_reg[2]_0\ => SI_REG_n_166, \axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\, \axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\, \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\, \axlen_cnt_reg[3]\ => SI_REG_n_8, \axlen_cnt_reg[3]_0\ => SI_REG_n_64, b_push => b_push, \cnt_read_reg[2]_rep__0\ => SI_REG_n_168, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\, \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\, next_pending_r_reg => SI_REG_n_155, next_pending_r_reg_0 => SI_REG_n_167, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0), \s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_82, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), s_ready_i0 => \ar.ar_pipe/s_ready_i0\, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \WR.aw_channel_0_n_4\, \state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_0\, \state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182, \wrap_cnt_r_reg[2]\ => SI_REG_n_149, \wrap_cnt_r_reg[2]_0\ => SI_REG_n_161, \wrap_cnt_r_reg[3]\ => SI_REG_n_153, \wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157, \wrap_cnt_r_reg[3]_1\ => SI_REG_n_165, \wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\, \wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\, \wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0) ); \WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, Q(31 downto 20) => s_awid(11 downto 0), Q(19 downto 16) => si_rs_awlen(3 downto 0), Q(15) => si_rs_awburst(1), Q(14) => SI_REG_n_26, Q(13 downto 12) => si_rs_awsize(1 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_149, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_153, \axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\, \axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[47]\ => SI_REG_n_8, \m_payload_i_reg[47]_0\ => SI_REG_n_155, \m_payload_i_reg[5]\ => SI_REG_n_154, \m_payload_i_reg[6]\(6) => SI_REG_n_169, \m_payload_i_reg[6]\(5) => SI_REG_n_170, \m_payload_i_reg[6]\(4) => SI_REG_n_171, \m_payload_i_reg[6]\(3) => SI_REG_n_172, \m_payload_i_reg[6]\(2) => SI_REG_n_173, \m_payload_i_reg[6]\(1) => SI_REG_n_174, \m_payload_i_reg[6]\(0) => SI_REG_n_175, si_rs_awvalid => si_rs_awvalid, \state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\, \wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1) ); \WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0) ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
mit
ded6c64c501f8a0c02f36d51b7318c8c
0.536381
2.550676
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/fir_picoblaze/ssg_display_shared_package.vhdl
1
3,850
-- Author: Varun Nagpal library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use ieee.std_logic_unsigned.all; package ssg_display_shared_package is constant DIGIT_CNT : natural := 4; -- k number of digits constant MIN_DIGITS_C : natural := 1; -- minimum number of digits (board specific) constant MAX_DIGITS_C : natural := 4; -- maximum number of digits (board specific) constant SEG_CNT : natural := 7; -- 7 segments per digit(board specific) constant DP_CNT : natural := DIGIT_CNT; -- 1 decimal point per digit(board specific) constant BCD_CNT : natural := 4; -- Number of bits used in BCD encoding -- This clock on NEXSYS3 running has frequency of 100 MHz -- or period of 10ns. We need to generate clock enable signal -- every 4 ms or @ 250 Hz. This corresponds to ~400000 cc -- log2(400000) = 18.609 = ceil(log2(925283.368)) = 19. -- Thus we can use a 19-bit counter to generate a clock enable signal constant CLK_CYCLE_TIME : time := 10 ns; -- modifiable constant CLK_HIGH_TIME : time := 5 ns; -- modifiable constant CLK_LOW_TIME : time := CLK_CYCLE_TIME - CLK_HIGH_TIME; -- modifiable constant CC_CNT_MAX_I : natural := 400000; -- modifiable constant CC_BIT_CNT_I : natural := natural(ceil(log2(real(CC_CNT_MAX_I)))); subtype CC_CNT_T is unsigned(CC_BIT_CNT_I-1 downto 0); constant CC_CNT_MAX_U : CC_CNT_T:= to_unsigned(CC_CNT_MAX_I, CC_BIT_CNT_I); constant SWITCH_CNT : natural := DIGIT_CNT * BCD_CNT; -- Number of switches = k digits x 4-bits/digit encoded in BCD. constant TOT_SEG_CNTNT : natural := DIGIT_CNT * SEG_CNT; -- k digits x 7 segments/digit constant ENABLE_DIGIT : std_logic := '0'; constant DISABLE_DIGIT : std_logic := '1'; -- active low common anode constant ENABLE_SEG : std_logic := '0'; constant DISABLE_SEG : std_logic := '1'; constant ENABLE_DP : std_logic := '0'; constant DISABLE_DP : std_logic := '1'; subtype SWITCH_T is std_logic_vector(SWITCH_CNT-1 downto 0); subtype SEG_T is std_logic_vector(SEG_CNT-1 downto 0); subtype DP_T is std_logic_vector(DP_CNT-1 downto 0); subtype BCD_T is std_logic_vector(BCD_CNT-1 downto 0); subtype DIGITS_EN_T is std_logic_vector(DIGIT_CNT-1 downto 0); subtype FSM_STATE_T is std_logic_vector(DIGIT_CNT-1 downto 0); -- codes for 7 segments (a,b,c,d,e,f,g) for: -- 1. decimal digits -- 2. hexadecimal digits -- Note: The below constants assumes that 7-segment type is common cathode -- i.e. user can assign only anode terminals (P junction of LED) -- of respective segments of a digit. -- If the 7-segment is of common anode type i.e. all segments of digit share -- common anode and have separate cathode nodes for each segment, then the -- below mentioned constants must be bit-wise complemented before they are -- assigned to individual segments of a digit constant SEG_NUM_D0 : SEG_T := "1111110"; constant SEG_NUM_D1 : SEG_T := "0110000"; constant SEG_NUM_D2 : SEG_T := "1101101"; constant SEG_NUM_D3 : SEG_T := "1111001"; constant SEG_NUM_D4 : SEG_T := "0110011"; constant SEG_NUM_D5 : SEG_T := "1011011"; constant SEG_NUM_D6 : SEG_T := "1011111"; constant SEG_NUM_D7 : SEG_T := "1110000"; constant SEG_NUM_D8 : SEG_T := "1111111"; constant SEG_NUM_D9 : SEG_T := "1110011"; constant SEG_NUM_XA : SEG_T := "1110111"; constant SEG_NUM_XB : SEG_T := "1111111"; constant SEG_NUM_XC : SEG_T := "1001110"; constant SEG_NUM_XD : SEG_T := "1111110"; constant SEG_NUM_XE : SEG_T := "1001111"; constant SEG_NUM_XF : SEG_T := "1000111"; constant SEG_OFF : SEG_T := "0000000"; end ssg_display_shared_package; package body ssg_display_shared_package is -- empty end ssg_display_shared_package;
mit
5846af4ee7d02f5d50bfa4828eff5566
0.661818
3.036278
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.cache/ip/2018.2/4bed305ebc84f97f/zybo_zynq_design_hls_macc_0_0_sim_netlist.vhdl
1
191,433
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Sun Sep 22 02:34:39 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_hls_macc_0_0_sim_netlist.vhdl -- Design : zybo_zynq_design_hls_macc_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_HLS_MACC_PERIPH_BUS_s_axi is port ( \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); interrupt : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \a_reg0_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); \buff2_reg__0\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); \accum_clr_read_reg_85_reg[0]\ : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); ap_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); \ap_CS_fsm_reg[4]\ : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_BREADY : in STD_LOGIC; ap_rst_n : in STD_LOGIC; accum_clr_read_reg_85 : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); \acc_reg_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_HLS_MACC_PERIPH_BUS_s_axi; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_HLS_MACC_PERIPH_BUS_s_axi is signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes"; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^a_reg0_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal accum_clr : STD_LOGIC; signal ap_NS_fsm1 : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_start : STD_LOGIC; signal ar_hs : STD_LOGIC; signal \^buff2_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal int_a0 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \int_a[31]_i_1_n_0\ : STD_LOGIC; signal \int_a[31]_i_3_n_0\ : STD_LOGIC; signal int_accum : STD_LOGIC_VECTOR ( 31 downto 0 ); signal int_accum_ap_vld : STD_LOGIC; signal int_accum_ap_vld1 : STD_LOGIC; signal int_accum_ap_vld_i_1_n_0 : STD_LOGIC; signal \int_accum_clr[0]_i_1_n_0\ : STD_LOGIC; signal \int_accum_clr[0]_i_3_n_0\ : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_done1 : STD_LOGIC; signal int_ap_done_i_1_n_0 : STD_LOGIC; signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_start3_out : STD_LOGIC; signal int_ap_start_i_1_n_0 : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_auto_restart_i_1_n_0 : STD_LOGIC; signal int_b0 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \int_b[31]_i_1_n_0\ : STD_LOGIC; signal int_gie_i_1_n_0 : STD_LOGIC; signal int_gie_reg_n_0 : STD_LOGIC; signal \int_ier[0]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_2_n_0\ : STD_LOGIC; signal \int_ier_reg_n_0_[0]\ : STD_LOGIC; signal int_isr6_out : STD_LOGIC; signal \int_isr[0]_i_1_n_0\ : STD_LOGIC; signal \int_isr[1]_i_1_n_0\ : STD_LOGIC; signal \int_isr_reg_n_0_[0]\ : STD_LOGIC; signal \int_isr_reg_n_0_[1]\ : STD_LOGIC; signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP of \^out\ : signal is "yes"; signal p_0_in : STD_LOGIC; signal p_0_in11_in : STD_LOGIC; signal \rdata[0]_i_1_n_0\ : STD_LOGIC; signal \rdata[0]_i_3_n_0\ : STD_LOGIC; signal \rdata[0]_i_4_n_0\ : STD_LOGIC; signal \rdata[0]_i_5_n_0\ : STD_LOGIC; signal \rdata[10]_i_1_n_0\ : STD_LOGIC; signal \rdata[11]_i_1_n_0\ : STD_LOGIC; signal \rdata[12]_i_1_n_0\ : STD_LOGIC; signal \rdata[13]_i_1_n_0\ : STD_LOGIC; signal \rdata[14]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_1_n_0\ : STD_LOGIC; signal \rdata[16]_i_1_n_0\ : STD_LOGIC; signal \rdata[17]_i_1_n_0\ : STD_LOGIC; signal \rdata[18]_i_1_n_0\ : STD_LOGIC; signal \rdata[19]_i_1_n_0\ : STD_LOGIC; signal \rdata[1]_i_1_n_0\ : STD_LOGIC; signal \rdata[1]_i_2_n_0\ : STD_LOGIC; signal \rdata[1]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_4_n_0\ : STD_LOGIC; signal \rdata[1]_i_5_n_0\ : STD_LOGIC; signal \rdata[20]_i_1_n_0\ : STD_LOGIC; signal \rdata[21]_i_1_n_0\ : STD_LOGIC; signal \rdata[22]_i_1_n_0\ : STD_LOGIC; signal \rdata[23]_i_1_n_0\ : STD_LOGIC; signal \rdata[24]_i_1_n_0\ : STD_LOGIC; signal \rdata[25]_i_1_n_0\ : STD_LOGIC; signal \rdata[26]_i_1_n_0\ : STD_LOGIC; signal \rdata[27]_i_1_n_0\ : STD_LOGIC; signal \rdata[28]_i_1_n_0\ : STD_LOGIC; signal \rdata[29]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_2_n_0\ : STD_LOGIC; signal \rdata[30]_i_1_n_0\ : STD_LOGIC; signal \rdata[31]_i_1_n_0\ : STD_LOGIC; signal \rdata[31]_i_3_n_0\ : STD_LOGIC; signal \rdata[3]_i_1_n_0\ : STD_LOGIC; signal \rdata[3]_i_2_n_0\ : STD_LOGIC; signal \rdata[4]_i_1_n_0\ : STD_LOGIC; signal \rdata[5]_i_1_n_0\ : STD_LOGIC; signal \rdata[6]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_2_n_0\ : STD_LOGIC; signal \rdata[8]_i_1_n_0\ : STD_LOGIC; signal \rdata[9]_i_1_n_0\ : STD_LOGIC; signal \rdata_reg[0]_i_2_n_0\ : STD_LOGIC; signal \^s_axi_hls_macc_periph_bus_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_hls_macc_periph_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \^s_axi_hls_macc_periph_bus_rvalid\ : signal is "yes"; signal waddr : STD_LOGIC; signal \waddr_reg_n_0_[0]\ : STD_LOGIC; signal \waddr_reg_n_0_[1]\ : STD_LOGIC; signal \waddr_reg_n_0_[2]\ : STD_LOGIC; signal \waddr_reg_n_0_[3]\ : STD_LOGIC; signal \waddr_reg_n_0_[4]\ : STD_LOGIC; signal \waddr_reg_n_0_[5]\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \accum_clr_read_reg_85[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \ap_CS_fsm[0]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_2\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \int_a[15]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_a[16]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_a[17]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_a[18]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_a[19]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \int_a[20]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[21]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[22]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_a[23]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_a[24]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \int_a[25]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \int_a[26]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \int_a[27]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \int_a[28]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \int_a[29]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \int_a[30]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \int_a[31]_i_2\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of int_ap_start_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of int_ap_start_i_2 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_b[15]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_b[16]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[17]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[18]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_b[19]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \int_b[20]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_b[21]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_b[22]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[23]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[24]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \int_b[25]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \int_b[26]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \int_b[27]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \int_b[28]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \int_b[29]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \int_b[30]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \int_b[31]_i_2\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0"; begin SR(0) <= \^sr\(0); \a_reg0_reg[31]\(31 downto 0) <= \^a_reg0_reg[31]\(31 downto 0); \buff2_reg__0\(31 downto 0) <= \^buff2_reg__0\(31 downto 0); \out\(2 downto 0) <= \^out\(2 downto 0); s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0) <= \^s_axi_hls_macc_periph_bus_rdata\(31 downto 0); s_axi_HLS_MACC_PERIPH_BUS_RVALID(1 downto 0) <= \^s_axi_hls_macc_periph_bus_rvalid\(1 downto 0); \FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F747" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I1 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I2 => \^s_axi_hls_macc_periph_bus_rvalid\(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_RREADY, O => \FSM_onehot_rstate[1]_i_1_n_0\ ); \FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I1 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I2 => s_axi_HLS_MACC_PERIPH_BUS_RREADY, I3 => \^s_axi_hls_macc_periph_bus_rvalid\(1), O => \FSM_onehot_rstate[2]_i_1_n_0\ ); \FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_rstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[1]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rvalid\(0), R => \^sr\(0) ); \FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[2]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rvalid\(1), R => \^sr\(0) ); \FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"888BFF8B" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_BREADY, I1 => \^out\(2), I2 => \^out\(1), I3 => \^out\(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, O => \FSM_onehot_wstate[1]_i_1_n_0\ ); \FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, I1 => \^out\(0), I2 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I3 => \^out\(1), O => \FSM_onehot_wstate[2]_i_1_n_0\ ); \FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ap_rst_n, O => \^sr\(0) ); \FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I1 => \^out\(1), I2 => s_axi_HLS_MACC_PERIPH_BUS_BREADY, I3 => \^out\(2), O => \FSM_onehot_wstate[3]_i_2_n_0\ ); \FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_wstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[1]_i_1_n_0\, Q => \^out\(0), R => \^sr\(0) ); \FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[2]_i_1_n_0\, Q => \^out\(1), R => \^sr\(0) ); \FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[3]_i_2_n_0\, Q => \^out\(2), R => \^sr\(0) ); \accum_clr_read_reg_85[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => accum_clr, I1 => Q(0), I2 => ap_start, I3 => accum_clr_read_reg_85, O => \accum_clr_read_reg_85_reg[0]\ ); \ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AE" ) port map ( I0 => Q(4), I1 => Q(0), I2 => ap_start, O => D(0) ); \ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => ap_NS_fsm1, I1 => \ap_CS_fsm_reg[4]\, I2 => Q(1), I3 => Q(4), I4 => Q(2), I5 => Q(3), O => D(1) ); \ap_CS_fsm[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => Q(0), I1 => ap_start, O => ap_NS_fsm1 ); \int_a[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(0), O => int_a0(0) ); \int_a[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(10), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(10), O => int_a0(10) ); \int_a[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(11), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(11), O => int_a0(11) ); \int_a[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(12), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(12), O => int_a0(12) ); \int_a[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(13), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(13), O => int_a0(13) ); \int_a[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(14), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(14), O => int_a0(14) ); \int_a[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(15), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(15), O => int_a0(15) ); \int_a[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(16), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(16), O => int_a0(16) ); \int_a[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(17), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(17), O => int_a0(17) ); \int_a[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(18), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(18), O => int_a0(18) ); \int_a[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(19), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(19), O => int_a0(19) ); \int_a[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(1), O => int_a0(1) ); \int_a[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(20), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(20), O => int_a0(20) ); \int_a[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(21), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(21), O => int_a0(21) ); \int_a[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(22), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(22), O => int_a0(22) ); \int_a[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(23), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^buff2_reg__0\(23), O => int_a0(23) ); \int_a[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(24), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(24), O => int_a0(24) ); \int_a[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(25), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(25), O => int_a0(25) ); \int_a[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(26), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(26), O => int_a0(26) ); \int_a[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(27), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(27), O => int_a0(27) ); \int_a[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(28), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(28), O => int_a0(28) ); \int_a[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(29), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(29), O => int_a0(29) ); \int_a[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(2), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(2), O => int_a0(2) ); \int_a[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(30), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(30), O => int_a0(30) ); \int_a[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"10" ) port map ( I0 => \waddr_reg_n_0_[2]\, I1 => \waddr_reg_n_0_[3]\, I2 => \int_a[31]_i_3_n_0\, O => \int_a[31]_i_1_n_0\ ); \int_a[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^buff2_reg__0\(31), O => int_a0(31) ); \int_a[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000002000" ) port map ( I0 => \waddr_reg_n_0_[4]\, I1 => \waddr_reg_n_0_[5]\, I2 => \^out\(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I4 => \waddr_reg_n_0_[0]\, I5 => \waddr_reg_n_0_[1]\, O => \int_a[31]_i_3_n_0\ ); \int_a[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(3), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(3), O => int_a0(3) ); \int_a[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(4), O => int_a0(4) ); \int_a[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(5), O => int_a0(5) ); \int_a[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(6), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(6), O => int_a0(6) ); \int_a[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^buff2_reg__0\(7), O => int_a0(7) ); \int_a[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(8), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(8), O => int_a0(8) ); \int_a[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(9), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^buff2_reg__0\(9), O => int_a0(9) ); \int_a_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(0), Q => \^buff2_reg__0\(0), R => \^sr\(0) ); \int_a_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(10), Q => \^buff2_reg__0\(10), R => \^sr\(0) ); \int_a_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(11), Q => \^buff2_reg__0\(11), R => \^sr\(0) ); \int_a_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(12), Q => \^buff2_reg__0\(12), R => \^sr\(0) ); \int_a_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(13), Q => \^buff2_reg__0\(13), R => \^sr\(0) ); \int_a_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(14), Q => \^buff2_reg__0\(14), R => \^sr\(0) ); \int_a_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(15), Q => \^buff2_reg__0\(15), R => \^sr\(0) ); \int_a_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(16), Q => \^buff2_reg__0\(16), R => \^sr\(0) ); \int_a_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(17), Q => \^buff2_reg__0\(17), R => \^sr\(0) ); \int_a_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(18), Q => \^buff2_reg__0\(18), R => \^sr\(0) ); \int_a_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(19), Q => \^buff2_reg__0\(19), R => \^sr\(0) ); \int_a_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(1), Q => \^buff2_reg__0\(1), R => \^sr\(0) ); \int_a_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(20), Q => \^buff2_reg__0\(20), R => \^sr\(0) ); \int_a_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(21), Q => \^buff2_reg__0\(21), R => \^sr\(0) ); \int_a_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(22), Q => \^buff2_reg__0\(22), R => \^sr\(0) ); \int_a_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(23), Q => \^buff2_reg__0\(23), R => \^sr\(0) ); \int_a_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(24), Q => \^buff2_reg__0\(24), R => \^sr\(0) ); \int_a_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(25), Q => \^buff2_reg__0\(25), R => \^sr\(0) ); \int_a_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(26), Q => \^buff2_reg__0\(26), R => \^sr\(0) ); \int_a_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(27), Q => \^buff2_reg__0\(27), R => \^sr\(0) ); \int_a_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(28), Q => \^buff2_reg__0\(28), R => \^sr\(0) ); \int_a_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(29), Q => \^buff2_reg__0\(29), R => \^sr\(0) ); \int_a_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(2), Q => \^buff2_reg__0\(2), R => \^sr\(0) ); \int_a_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(30), Q => \^buff2_reg__0\(30), R => \^sr\(0) ); \int_a_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(31), Q => \^buff2_reg__0\(31), R => \^sr\(0) ); \int_a_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(3), Q => \^buff2_reg__0\(3), R => \^sr\(0) ); \int_a_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(4), Q => \^buff2_reg__0\(4), R => \^sr\(0) ); \int_a_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(5), Q => \^buff2_reg__0\(5), R => \^sr\(0) ); \int_a_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(6), Q => \^buff2_reg__0\(6), R => \^sr\(0) ); \int_a_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(7), Q => \^buff2_reg__0\(7), R => \^sr\(0) ); \int_a_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(8), Q => \^buff2_reg__0\(8), R => \^sr\(0) ); \int_a_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[31]_i_1_n_0\, D => int_a0(9), Q => \^buff2_reg__0\(9), R => \^sr\(0) ); int_accum_ap_vld_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"BFFFAAAA" ) port map ( I0 => Q(4), I1 => int_accum_ap_vld1, I2 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I3 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I4 => int_accum_ap_vld, O => int_accum_ap_vld_i_1_n_0 ); int_accum_ap_vld_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000001000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), O => int_accum_ap_vld1 ); int_accum_ap_vld_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => int_accum_ap_vld_i_1_n_0, Q => int_accum_ap_vld, R => \^sr\(0) ); \int_accum_clr[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => p_0_in11_in, I3 => accum_clr, O => \int_accum_clr[0]_i_1_n_0\ ); \int_accum_clr[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00400000" ) port map ( I0 => \waddr_reg_n_0_[2]\, I1 => \waddr_reg_n_0_[5]\, I2 => \int_accum_clr[0]_i_3_n_0\, I3 => \waddr_reg_n_0_[4]\, I4 => \waddr_reg_n_0_[3]\, O => p_0_in11_in ); \int_accum_clr[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0008" ) port map ( I0 => \^out\(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I2 => \waddr_reg_n_0_[0]\, I3 => \waddr_reg_n_0_[1]\, O => \int_accum_clr[0]_i_3_n_0\ ); \int_accum_clr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_accum_clr[0]_i_1_n_0\, Q => accum_clr, R => \^sr\(0) ); \int_accum_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(0), Q => int_accum(0), R => \^sr\(0) ); \int_accum_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(10), Q => int_accum(10), R => \^sr\(0) ); \int_accum_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(11), Q => int_accum(11), R => \^sr\(0) ); \int_accum_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(12), Q => int_accum(12), R => \^sr\(0) ); \int_accum_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(13), Q => int_accum(13), R => \^sr\(0) ); \int_accum_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(14), Q => int_accum(14), R => \^sr\(0) ); \int_accum_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(15), Q => int_accum(15), R => \^sr\(0) ); \int_accum_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(16), Q => int_accum(16), R => \^sr\(0) ); \int_accum_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(17), Q => int_accum(17), R => \^sr\(0) ); \int_accum_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(18), Q => int_accum(18), R => \^sr\(0) ); \int_accum_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(19), Q => int_accum(19), R => \^sr\(0) ); \int_accum_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(1), Q => int_accum(1), R => \^sr\(0) ); \int_accum_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(20), Q => int_accum(20), R => \^sr\(0) ); \int_accum_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(21), Q => int_accum(21), R => \^sr\(0) ); \int_accum_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(22), Q => int_accum(22), R => \^sr\(0) ); \int_accum_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(23), Q => int_accum(23), R => \^sr\(0) ); \int_accum_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(24), Q => int_accum(24), R => \^sr\(0) ); \int_accum_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(25), Q => int_accum(25), R => \^sr\(0) ); \int_accum_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(26), Q => int_accum(26), R => \^sr\(0) ); \int_accum_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(27), Q => int_accum(27), R => \^sr\(0) ); \int_accum_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(28), Q => int_accum(28), R => \^sr\(0) ); \int_accum_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(29), Q => int_accum(29), R => \^sr\(0) ); \int_accum_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(2), Q => int_accum(2), R => \^sr\(0) ); \int_accum_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(30), Q => int_accum(30), R => \^sr\(0) ); \int_accum_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(31), Q => int_accum(31), R => \^sr\(0) ); \int_accum_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(3), Q => int_accum(3), R => \^sr\(0) ); \int_accum_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(4), Q => int_accum(4), R => \^sr\(0) ); \int_accum_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(5), Q => int_accum(5), R => \^sr\(0) ); \int_accum_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(6), Q => int_accum(6), R => \^sr\(0) ); \int_accum_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(7), Q => int_accum(7), R => \^sr\(0) ); \int_accum_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(8), Q => int_accum(8), R => \^sr\(0) ); \int_accum_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => Q(4), D => \acc_reg_reg[31]\(9), Q => int_accum(9), R => \^sr\(0) ); int_ap_done_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"BFFFAAAA" ) port map ( I0 => Q(4), I1 => int_ap_done1, I2 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I3 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I4 => int_ap_done, O => int_ap_done_i_1_n_0 ); int_ap_done_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), O => int_ap_done1 ); int_ap_done_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_done_i_1_n_0, Q => int_ap_done, R => \^sr\(0) ); int_ap_idle_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => Q(0), I1 => ap_start, O => ap_idle ); int_ap_idle_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => ap_idle, Q => int_ap_idle, R => \^sr\(0) ); int_ap_ready_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => Q(4), Q => int_ap_ready, R => \^sr\(0) ); int_ap_start_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FBF8" ) port map ( I0 => int_auto_restart, I1 => Q(4), I2 => int_ap_start3_out, I3 => ap_start, O => int_ap_start_i_1_n_0 ); int_ap_start_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"04000000" ) port map ( I0 => \waddr_reg_n_0_[3]\, I1 => \int_ier[1]_i_2_n_0\, I2 => \waddr_reg_n_0_[2]\, I3 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), O => int_ap_start3_out ); int_ap_start_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_start_i_1_n_0, Q => ap_start, R => \^sr\(0) ); int_auto_restart_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFBFF00000800" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \int_ier[1]_i_2_n_0\, I4 => \waddr_reg_n_0_[3]\, I5 => int_auto_restart, O => int_auto_restart_i_1_n_0 ); int_auto_restart_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_auto_restart_i_1_n_0, Q => int_auto_restart, R => \^sr\(0) ); \int_b[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(0), O => int_b0(0) ); \int_b[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(10), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(10), O => int_b0(10) ); \int_b[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(11), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(11), O => int_b0(11) ); \int_b[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(12), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(12), O => int_b0(12) ); \int_b[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(13), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(13), O => int_b0(13) ); \int_b[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(14), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(14), O => int_b0(14) ); \int_b[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(15), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(15), O => int_b0(15) ); \int_b[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(16), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(16), O => int_b0(16) ); \int_b[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(17), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(17), O => int_b0(17) ); \int_b[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(18), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(18), O => int_b0(18) ); \int_b[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(19), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(19), O => int_b0(19) ); \int_b[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(1), O => int_b0(1) ); \int_b[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(20), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(20), O => int_b0(20) ); \int_b[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(21), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(21), O => int_b0(21) ); \int_b[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(22), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(22), O => int_b0(22) ); \int_b[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(23), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(2), I2 => \^a_reg0_reg[31]\(23), O => int_b0(23) ); \int_b[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(24), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(24), O => int_b0(24) ); \int_b[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(25), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(25), O => int_b0(25) ); \int_b[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(26), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(26), O => int_b0(26) ); \int_b[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(27), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(27), O => int_b0(27) ); \int_b[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(28), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(28), O => int_b0(28) ); \int_b[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(29), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(29), O => int_b0(29) ); \int_b[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(2), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(2), O => int_b0(2) ); \int_b[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(30), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(30), O => int_b0(30) ); \int_b[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \waddr_reg_n_0_[2]\, I1 => \waddr_reg_n_0_[3]\, I2 => \int_a[31]_i_3_n_0\, O => \int_b[31]_i_1_n_0\ ); \int_b[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3), I2 => \^a_reg0_reg[31]\(31), O => int_b0(31) ); \int_b[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(3), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(3), O => int_b0(3) ); \int_b[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(4), O => int_b0(4) ); \int_b[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(5), O => int_b0(5) ); \int_b[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(6), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(6), O => int_b0(6) ); \int_b[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \^a_reg0_reg[31]\(7), O => int_b0(7) ); \int_b[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(8), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(8), O => int_b0(8) ); \int_b[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(9), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(1), I2 => \^a_reg0_reg[31]\(9), O => int_b0(9) ); \int_b_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(0), Q => \^a_reg0_reg[31]\(0), R => \^sr\(0) ); \int_b_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(10), Q => \^a_reg0_reg[31]\(10), R => \^sr\(0) ); \int_b_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(11), Q => \^a_reg0_reg[31]\(11), R => \^sr\(0) ); \int_b_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(12), Q => \^a_reg0_reg[31]\(12), R => \^sr\(0) ); \int_b_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(13), Q => \^a_reg0_reg[31]\(13), R => \^sr\(0) ); \int_b_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(14), Q => \^a_reg0_reg[31]\(14), R => \^sr\(0) ); \int_b_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(15), Q => \^a_reg0_reg[31]\(15), R => \^sr\(0) ); \int_b_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(16), Q => \^a_reg0_reg[31]\(16), R => \^sr\(0) ); \int_b_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(17), Q => \^a_reg0_reg[31]\(17), R => \^sr\(0) ); \int_b_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(18), Q => \^a_reg0_reg[31]\(18), R => \^sr\(0) ); \int_b_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(19), Q => \^a_reg0_reg[31]\(19), R => \^sr\(0) ); \int_b_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(1), Q => \^a_reg0_reg[31]\(1), R => \^sr\(0) ); \int_b_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(20), Q => \^a_reg0_reg[31]\(20), R => \^sr\(0) ); \int_b_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(21), Q => \^a_reg0_reg[31]\(21), R => \^sr\(0) ); \int_b_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(22), Q => \^a_reg0_reg[31]\(22), R => \^sr\(0) ); \int_b_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(23), Q => \^a_reg0_reg[31]\(23), R => \^sr\(0) ); \int_b_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(24), Q => \^a_reg0_reg[31]\(24), R => \^sr\(0) ); \int_b_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(25), Q => \^a_reg0_reg[31]\(25), R => \^sr\(0) ); \int_b_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(26), Q => \^a_reg0_reg[31]\(26), R => \^sr\(0) ); \int_b_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(27), Q => \^a_reg0_reg[31]\(27), R => \^sr\(0) ); \int_b_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(28), Q => \^a_reg0_reg[31]\(28), R => \^sr\(0) ); \int_b_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(29), Q => \^a_reg0_reg[31]\(29), R => \^sr\(0) ); \int_b_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(2), Q => \^a_reg0_reg[31]\(2), R => \^sr\(0) ); \int_b_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(30), Q => \^a_reg0_reg[31]\(30), R => \^sr\(0) ); \int_b_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(31), Q => \^a_reg0_reg[31]\(31), R => \^sr\(0) ); \int_b_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(3), Q => \^a_reg0_reg[31]\(3), R => \^sr\(0) ); \int_b_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(4), Q => \^a_reg0_reg[31]\(4), R => \^sr\(0) ); \int_b_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(5), Q => \^a_reg0_reg[31]\(5), R => \^sr\(0) ); \int_b_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(6), Q => \^a_reg0_reg[31]\(6), R => \^sr\(0) ); \int_b_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(7), Q => \^a_reg0_reg[31]\(7), R => \^sr\(0) ); \int_b_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(8), Q => \^a_reg0_reg[31]\(8), R => \^sr\(0) ); \int_b_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[31]_i_1_n_0\, D => int_b0(9), Q => \^a_reg0_reg[31]\(9), R => \^sr\(0) ); int_gie_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFBFFFFF00800000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[3]\, I4 => \waddr_reg_n_0_[2]\, I5 => int_gie_reg_n_0, O => int_gie_i_1_n_0 ); int_gie_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_gie_i_1_n_0, Q => int_gie_reg_n_0, R => \^sr\(0) ); \int_ier[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \waddr_reg_n_0_[3]\, I4 => \int_ier[1]_i_2_n_0\, I5 => \int_ier_reg_n_0_[0]\, O => \int_ier[0]_i_1_n_0\ ); \int_ier[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \waddr_reg_n_0_[3]\, I4 => \int_ier[1]_i_2_n_0\, I5 => p_0_in, O => \int_ier[1]_i_1_n_0\ ); \int_ier[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => \waddr_reg_n_0_[5]\, I1 => \^out\(1), I2 => s_axi_HLS_MACC_PERIPH_BUS_WVALID, I3 => \waddr_reg_n_0_[0]\, I4 => \waddr_reg_n_0_[1]\, I5 => \waddr_reg_n_0_[4]\, O => \int_ier[1]_i_2_n_0\ ); \int_ier_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[0]_i_1_n_0\, Q => \int_ier_reg_n_0_[0]\, R => \^sr\(0) ); \int_ier_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[1]_i_1_n_0\, Q => p_0_in, R => \^sr\(0) ); \int_isr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F777F888" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(0), I1 => int_isr6_out, I2 => Q(4), I3 => \int_ier_reg_n_0_[0]\, I4 => \int_isr_reg_n_0_[0]\, O => \int_isr[0]_i_1_n_0\ ); \int_isr[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(0), I1 => \waddr_reg_n_0_[3]\, I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, O => int_isr6_out ); \int_isr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F777F888" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_WDATA(1), I1 => int_isr6_out, I2 => p_0_in, I3 => Q(4), I4 => \int_isr_reg_n_0_[1]\, O => \int_isr[1]_i_1_n_0\ ); \int_isr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[0]_i_1_n_0\, Q => \int_isr_reg_n_0_[0]\, R => \^sr\(0) ); \int_isr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[1]_i_1_n_0\, Q => \int_isr_reg_n_0_[1]\, R => \^sr\(0) ); interrupt_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \int_isr_reg_n_0_[1]\, I1 => \int_isr_reg_n_0_[0]\, I2 => int_gie_reg_n_0, O => interrupt ); \rdata[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata_reg[0]_i_2_n_0\, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), I2 => \rdata[0]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_hls_macc_periph_bus_rdata\(0), O => \rdata[0]_i_1_n_0\ ); \rdata[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033223000002230" ) port map ( I0 => int_accum_ap_vld, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_gie_reg_n_0, I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => \int_isr_reg_n_0_[0]\, O => \rdata[0]_i_3_n_0\ ); \rdata[0]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(0), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => ap_start, O => \rdata[0]_i_4_n_0\ ); \rdata[0]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_reg0_reg[31]\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => accum_clr, I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => \int_ier_reg_n_0_[0]\, O => \rdata[0]_i_5_n_0\ ); \rdata[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(10), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(10), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(10), O => \rdata[10]_i_1_n_0\ ); \rdata[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(11), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(11), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(11), O => \rdata[11]_i_1_n_0\ ); \rdata[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(12), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(12), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(12), O => \rdata[12]_i_1_n_0\ ); \rdata[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(13), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(13), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(13), O => \rdata[13]_i_1_n_0\ ); \rdata[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(14), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(14), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(14), O => \rdata[14]_i_1_n_0\ ); \rdata[15]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(15), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(15), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(15), O => \rdata[15]_i_1_n_0\ ); \rdata[16]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(16), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(16), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(16), O => \rdata[16]_i_1_n_0\ ); \rdata[17]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(17), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(17), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(17), O => \rdata[17]_i_1_n_0\ ); \rdata[18]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(18), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(18), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(18), O => \rdata[18]_i_1_n_0\ ); \rdata[19]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(19), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(19), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(19), O => \rdata[19]_i_1_n_0\ ); \rdata[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata[1]_i_2_n_0\, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), I2 => \rdata[1]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_hls_macc_periph_bus_rdata\(1), O => \rdata[1]_i_1_n_0\ ); \rdata[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => p_0_in, I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I5 => \rdata[1]_i_5_n_0\, O => \rdata[1]_i_2_n_0\ ); \rdata[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I3 => \int_isr_reg_n_0_[1]\, O => \rdata[1]_i_3_n_0\ ); \rdata[1]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), O => \rdata[1]_i_4_n_0\ ); \rdata[1]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(1), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_ap_done, O => \rdata[1]_i_5_n_0\ ); \rdata[20]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(20), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(20), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(20), O => \rdata[20]_i_1_n_0\ ); \rdata[21]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(21), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(21), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(21), O => \rdata[21]_i_1_n_0\ ); \rdata[22]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(22), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(22), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(22), O => \rdata[22]_i_1_n_0\ ); \rdata[23]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(23), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(23), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(23), O => \rdata[23]_i_1_n_0\ ); \rdata[24]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(24), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(24), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(24), O => \rdata[24]_i_1_n_0\ ); \rdata[25]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(25), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(25), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(25), O => \rdata[25]_i_1_n_0\ ); \rdata[26]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(26), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(26), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(26), O => \rdata[26]_i_1_n_0\ ); \rdata[27]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(27), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(27), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(27), O => \rdata[27]_i_1_n_0\ ); \rdata[28]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(28), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(28), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(28), O => \rdata[28]_i_1_n_0\ ); \rdata[29]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(29), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(29), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(29), O => \rdata[29]_i_1_n_0\ ); \rdata[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(2), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I4 => \rdata[2]_i_2_n_0\, O => \rdata[2]_i_1_n_0\ ); \rdata[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(2), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(2), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_ap_idle, O => \rdata[2]_i_2_n_0\ ); \rdata[30]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(30), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(30), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(30), O => \rdata[30]_i_1_n_0\ ); \rdata[31]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88888880" ) port map ( I0 => \^s_axi_hls_macc_periph_bus_rvalid\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I2 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(1), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(0), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(2), O => \rdata[31]_i_1_n_0\ ); \rdata[31]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, I1 => \^s_axi_hls_macc_periph_bus_rvalid\(0), O => ar_hs ); \rdata[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(31), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(31), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(31), O => \rdata[31]_i_3_n_0\ ); \rdata[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(3), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I4 => \rdata[3]_i_2_n_0\, O => \rdata[3]_i_1_n_0\ ); \rdata[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(3), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(3), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_ap_ready, O => \rdata[3]_i_2_n_0\ ); \rdata[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(4), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(4), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(4), O => \rdata[4]_i_1_n_0\ ); \rdata[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(5), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(5), O => \rdata[5]_i_1_n_0\ ); \rdata[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(6), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(6), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(6), O => \rdata[6]_i_1_n_0\ ); \rdata[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => \^a_reg0_reg[31]\(7), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I4 => \rdata[7]_i_2_n_0\, O => \rdata[7]_i_1_n_0\ ); \rdata[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^buff2_reg__0\(7), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I2 => int_accum(7), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I4 => int_auto_restart, O => \rdata[7]_i_2_n_0\ ); \rdata[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(8), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(8), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(8), O => \rdata[8]_i_1_n_0\ ); \rdata[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^a_reg0_reg[31]\(9), I1 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3), I2 => \^buff2_reg__0\(9), I3 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(4), I4 => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5), I5 => int_accum(9), O => \rdata[9]_i_1_n_0\ ); \rdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[0]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(0), R => '0' ); \rdata_reg[0]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \rdata[0]_i_4_n_0\, I1 => \rdata[0]_i_5_n_0\, O => \rdata_reg[0]_i_2_n_0\, S => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(3) ); \rdata_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[10]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(10), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[11]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(11), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[12]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(12), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[13]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(13), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[14]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(14), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[15]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(15), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[16]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[16]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(16), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[17]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[17]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(17), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[18]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[18]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(18), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[19]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[19]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(19), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[1]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(1), R => '0' ); \rdata_reg[20]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[20]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(20), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[21]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[21]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(21), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[22]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[22]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(22), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[23]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[23]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(23), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[24]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[24]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(24), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[25]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[25]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(25), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[26]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[26]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(26), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[27]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[27]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(27), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[28]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[28]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(28), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[29]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[29]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(29), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[2]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(2), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[30]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[30]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(30), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[31]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[31]_i_3_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(31), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[3]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(3), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[4]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(4), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[5]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(5), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[6]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(6), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[7]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(7), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[8]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(8), R => \rdata[31]_i_1_n_0\ ); \rdata_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[9]_i_1_n_0\, Q => \^s_axi_hls_macc_periph_bus_rdata\(9), R => \rdata[31]_i_1_n_0\ ); \waddr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^out\(0), I1 => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, O => waddr ); \waddr_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(0), Q => \waddr_reg_n_0_[0]\, R => '0' ); \waddr_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(1), Q => \waddr_reg_n_0_[1]\, R => '0' ); \waddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(2), Q => \waddr_reg_n_0_[2]\, R => '0' ); \waddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(3), Q => \waddr_reg_n_0_[3]\, R => '0' ); \waddr_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(4), Q => \waddr_reg_n_0_[4]\, R => '0' ); \waddr_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5), Q => \waddr_reg_n_0_[5]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb_MulnS_0 is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); ap_clk : in STD_LOGIC; \int_a_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \int_b_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb_MulnS_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb_MulnS_0 is signal a_reg0 : STD_LOGIC_VECTOR ( 31 downto 17 ); signal b_reg0 : STD_LOGIC_VECTOR ( 16 downto 0 ); signal buff1_reg_n_100 : STD_LOGIC; signal buff1_reg_n_101 : STD_LOGIC; signal buff1_reg_n_102 : STD_LOGIC; signal buff1_reg_n_103 : STD_LOGIC; signal buff1_reg_n_104 : STD_LOGIC; signal buff1_reg_n_105 : STD_LOGIC; signal buff1_reg_n_106 : STD_LOGIC; signal buff1_reg_n_107 : STD_LOGIC; signal buff1_reg_n_108 : STD_LOGIC; signal buff1_reg_n_109 : STD_LOGIC; signal buff1_reg_n_110 : STD_LOGIC; signal buff1_reg_n_111 : STD_LOGIC; signal buff1_reg_n_112 : STD_LOGIC; signal buff1_reg_n_113 : STD_LOGIC; signal buff1_reg_n_114 : STD_LOGIC; signal buff1_reg_n_115 : STD_LOGIC; signal buff1_reg_n_116 : STD_LOGIC; signal buff1_reg_n_117 : STD_LOGIC; signal buff1_reg_n_118 : STD_LOGIC; signal buff1_reg_n_119 : STD_LOGIC; signal buff1_reg_n_120 : STD_LOGIC; signal buff1_reg_n_121 : STD_LOGIC; signal buff1_reg_n_122 : STD_LOGIC; signal buff1_reg_n_123 : STD_LOGIC; signal buff1_reg_n_124 : STD_LOGIC; signal buff1_reg_n_125 : STD_LOGIC; signal buff1_reg_n_126 : STD_LOGIC; signal buff1_reg_n_127 : STD_LOGIC; signal buff1_reg_n_128 : STD_LOGIC; signal buff1_reg_n_129 : STD_LOGIC; signal buff1_reg_n_130 : STD_LOGIC; signal buff1_reg_n_131 : STD_LOGIC; signal buff1_reg_n_132 : STD_LOGIC; signal buff1_reg_n_133 : STD_LOGIC; signal buff1_reg_n_134 : STD_LOGIC; signal buff1_reg_n_135 : STD_LOGIC; signal buff1_reg_n_136 : STD_LOGIC; signal buff1_reg_n_137 : STD_LOGIC; signal buff1_reg_n_138 : STD_LOGIC; signal buff1_reg_n_139 : STD_LOGIC; signal buff1_reg_n_140 : STD_LOGIC; signal buff1_reg_n_141 : STD_LOGIC; signal buff1_reg_n_142 : STD_LOGIC; signal buff1_reg_n_143 : STD_LOGIC; signal buff1_reg_n_144 : STD_LOGIC; signal buff1_reg_n_145 : STD_LOGIC; signal buff1_reg_n_146 : STD_LOGIC; signal buff1_reg_n_147 : STD_LOGIC; signal buff1_reg_n_148 : STD_LOGIC; signal buff1_reg_n_149 : STD_LOGIC; signal buff1_reg_n_150 : STD_LOGIC; signal buff1_reg_n_151 : STD_LOGIC; signal buff1_reg_n_152 : STD_LOGIC; signal buff1_reg_n_153 : STD_LOGIC; signal buff1_reg_n_58 : STD_LOGIC; signal buff1_reg_n_59 : STD_LOGIC; signal buff1_reg_n_60 : STD_LOGIC; signal buff1_reg_n_61 : STD_LOGIC; signal buff1_reg_n_62 : STD_LOGIC; signal buff1_reg_n_63 : STD_LOGIC; signal buff1_reg_n_64 : STD_LOGIC; signal buff1_reg_n_65 : STD_LOGIC; signal buff1_reg_n_66 : STD_LOGIC; signal buff1_reg_n_67 : STD_LOGIC; signal buff1_reg_n_68 : STD_LOGIC; signal buff1_reg_n_69 : STD_LOGIC; signal buff1_reg_n_70 : STD_LOGIC; signal buff1_reg_n_71 : STD_LOGIC; signal buff1_reg_n_72 : STD_LOGIC; signal buff1_reg_n_73 : STD_LOGIC; signal buff1_reg_n_74 : STD_LOGIC; signal buff1_reg_n_75 : STD_LOGIC; signal buff1_reg_n_76 : STD_LOGIC; signal buff1_reg_n_77 : STD_LOGIC; signal buff1_reg_n_78 : STD_LOGIC; signal buff1_reg_n_79 : STD_LOGIC; signal buff1_reg_n_80 : STD_LOGIC; signal buff1_reg_n_81 : STD_LOGIC; signal buff1_reg_n_82 : STD_LOGIC; signal buff1_reg_n_83 : STD_LOGIC; signal buff1_reg_n_84 : STD_LOGIC; signal buff1_reg_n_85 : STD_LOGIC; signal buff1_reg_n_86 : STD_LOGIC; signal buff1_reg_n_87 : STD_LOGIC; signal buff1_reg_n_88 : STD_LOGIC; signal buff1_reg_n_89 : STD_LOGIC; signal buff1_reg_n_90 : STD_LOGIC; signal buff1_reg_n_91 : STD_LOGIC; signal buff1_reg_n_92 : STD_LOGIC; signal buff1_reg_n_93 : STD_LOGIC; signal buff1_reg_n_94 : STD_LOGIC; signal buff1_reg_n_95 : STD_LOGIC; signal buff1_reg_n_96 : STD_LOGIC; signal buff1_reg_n_97 : STD_LOGIC; signal buff1_reg_n_98 : STD_LOGIC; signal buff1_reg_n_99 : STD_LOGIC; signal \buff2_reg__0_n_106\ : STD_LOGIC; signal \buff2_reg__0_n_107\ : STD_LOGIC; signal \buff2_reg__0_n_108\ : STD_LOGIC; signal \buff2_reg__0_n_109\ : STD_LOGIC; signal \buff2_reg__0_n_110\ : STD_LOGIC; signal \buff2_reg__0_n_111\ : STD_LOGIC; signal \buff2_reg__0_n_112\ : STD_LOGIC; signal \buff2_reg__0_n_113\ : STD_LOGIC; signal \buff2_reg__0_n_114\ : STD_LOGIC; signal \buff2_reg__0_n_115\ : STD_LOGIC; signal \buff2_reg__0_n_116\ : STD_LOGIC; signal \buff2_reg__0_n_117\ : STD_LOGIC; signal \buff2_reg__0_n_118\ : STD_LOGIC; signal \buff2_reg__0_n_119\ : STD_LOGIC; signal \buff2_reg__0_n_120\ : STD_LOGIC; signal \buff2_reg__0_n_121\ : STD_LOGIC; signal \buff2_reg__0_n_122\ : STD_LOGIC; signal \buff2_reg__0_n_123\ : STD_LOGIC; signal \buff2_reg__0_n_124\ : STD_LOGIC; signal \buff2_reg__0_n_125\ : STD_LOGIC; signal \buff2_reg__0_n_126\ : STD_LOGIC; signal \buff2_reg__0_n_127\ : STD_LOGIC; signal \buff2_reg__0_n_128\ : STD_LOGIC; signal \buff2_reg__0_n_129\ : STD_LOGIC; signal \buff2_reg__0_n_130\ : STD_LOGIC; signal \buff2_reg__0_n_131\ : STD_LOGIC; signal \buff2_reg__0_n_132\ : STD_LOGIC; signal \buff2_reg__0_n_133\ : STD_LOGIC; signal \buff2_reg__0_n_134\ : STD_LOGIC; signal \buff2_reg__0_n_135\ : STD_LOGIC; signal \buff2_reg__0_n_136\ : STD_LOGIC; signal \buff2_reg__0_n_137\ : STD_LOGIC; signal \buff2_reg__0_n_138\ : STD_LOGIC; signal \buff2_reg__0_n_139\ : STD_LOGIC; signal \buff2_reg__0_n_140\ : STD_LOGIC; signal \buff2_reg__0_n_141\ : STD_LOGIC; signal \buff2_reg__0_n_142\ : STD_LOGIC; signal \buff2_reg__0_n_143\ : STD_LOGIC; signal \buff2_reg__0_n_144\ : STD_LOGIC; signal \buff2_reg__0_n_145\ : STD_LOGIC; signal \buff2_reg__0_n_146\ : STD_LOGIC; signal \buff2_reg__0_n_147\ : STD_LOGIC; signal \buff2_reg__0_n_148\ : STD_LOGIC; signal \buff2_reg__0_n_149\ : STD_LOGIC; signal \buff2_reg__0_n_150\ : STD_LOGIC; signal \buff2_reg__0_n_151\ : STD_LOGIC; signal \buff2_reg__0_n_152\ : STD_LOGIC; signal \buff2_reg__0_n_153\ : STD_LOGIC; signal \buff3_reg__0_n_100\ : STD_LOGIC; signal \buff3_reg__0_n_101\ : STD_LOGIC; signal \buff3_reg__0_n_102\ : STD_LOGIC; signal \buff3_reg__0_n_103\ : STD_LOGIC; signal \buff3_reg__0_n_104\ : STD_LOGIC; signal \buff3_reg__0_n_105\ : STD_LOGIC; signal \buff3_reg__0_n_58\ : STD_LOGIC; signal \buff3_reg__0_n_59\ : STD_LOGIC; signal \buff3_reg__0_n_60\ : STD_LOGIC; signal \buff3_reg__0_n_61\ : STD_LOGIC; signal \buff3_reg__0_n_62\ : STD_LOGIC; signal \buff3_reg__0_n_63\ : STD_LOGIC; signal \buff3_reg__0_n_64\ : STD_LOGIC; signal \buff3_reg__0_n_65\ : STD_LOGIC; signal \buff3_reg__0_n_66\ : STD_LOGIC; signal \buff3_reg__0_n_67\ : STD_LOGIC; signal \buff3_reg__0_n_68\ : STD_LOGIC; signal \buff3_reg__0_n_69\ : STD_LOGIC; signal \buff3_reg__0_n_70\ : STD_LOGIC; signal \buff3_reg__0_n_71\ : STD_LOGIC; signal \buff3_reg__0_n_72\ : STD_LOGIC; signal \buff3_reg__0_n_73\ : STD_LOGIC; signal \buff3_reg__0_n_74\ : STD_LOGIC; signal \buff3_reg__0_n_75\ : STD_LOGIC; signal \buff3_reg__0_n_76\ : STD_LOGIC; signal \buff3_reg__0_n_77\ : STD_LOGIC; signal \buff3_reg__0_n_78\ : STD_LOGIC; signal \buff3_reg__0_n_79\ : STD_LOGIC; signal \buff3_reg__0_n_80\ : STD_LOGIC; signal \buff3_reg__0_n_81\ : STD_LOGIC; signal \buff3_reg__0_n_82\ : STD_LOGIC; signal \buff3_reg__0_n_83\ : STD_LOGIC; signal \buff3_reg__0_n_84\ : STD_LOGIC; signal \buff3_reg__0_n_85\ : STD_LOGIC; signal \buff3_reg__0_n_86\ : STD_LOGIC; signal \buff3_reg__0_n_87\ : STD_LOGIC; signal \buff3_reg__0_n_88\ : STD_LOGIC; signal \buff3_reg__0_n_89\ : STD_LOGIC; signal \buff3_reg__0_n_90\ : STD_LOGIC; signal \buff3_reg__0_n_91\ : STD_LOGIC; signal \buff3_reg__0_n_92\ : STD_LOGIC; signal \buff3_reg__0_n_93\ : STD_LOGIC; signal \buff3_reg__0_n_94\ : STD_LOGIC; signal \buff3_reg__0_n_95\ : STD_LOGIC; signal \buff3_reg__0_n_96\ : STD_LOGIC; signal \buff3_reg__0_n_97\ : STD_LOGIC; signal \buff3_reg__0_n_98\ : STD_LOGIC; signal \buff3_reg__0_n_99\ : STD_LOGIC; signal NLW_buff1_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_buff1_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); signal NLW_buff1_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); signal NLW_buff1_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_buff2_reg__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff2_reg__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 ); signal \NLW_buff2_reg__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 ); signal \NLW_buff2_reg__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_buff2_reg__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 ); signal \NLW_buff3_reg__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC; signal \NLW_buff3_reg__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 ); signal \NLW_buff3_reg__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 ); signal \NLW_buff3_reg__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_buff3_reg__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 ); attribute srl_bus_name : string; attribute srl_bus_name of \buff4_reg[0]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name : string; attribute srl_name of \buff4_reg[0]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[0]_srl3 "; attribute srl_bus_name of \buff4_reg[10]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[10]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[10]_srl3 "; attribute srl_bus_name of \buff4_reg[11]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[11]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[11]_srl3 "; attribute srl_bus_name of \buff4_reg[12]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[12]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[12]_srl3 "; attribute srl_bus_name of \buff4_reg[13]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[13]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[13]_srl3 "; attribute srl_bus_name of \buff4_reg[14]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[14]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[14]_srl3 "; attribute srl_bus_name of \buff4_reg[15]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[15]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[15]_srl3 "; attribute srl_bus_name of \buff4_reg[16]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[16]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[16]_srl3 "; attribute srl_bus_name of \buff4_reg[1]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[1]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[1]_srl3 "; attribute srl_bus_name of \buff4_reg[2]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[2]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[2]_srl3 "; attribute srl_bus_name of \buff4_reg[3]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[3]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[3]_srl3 "; attribute srl_bus_name of \buff4_reg[4]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[4]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[4]_srl3 "; attribute srl_bus_name of \buff4_reg[5]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[5]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[5]_srl3 "; attribute srl_bus_name of \buff4_reg[6]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[6]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[6]_srl3 "; attribute srl_bus_name of \buff4_reg[7]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[7]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[7]_srl3 "; attribute srl_bus_name of \buff4_reg[8]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[8]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[8]_srl3 "; attribute srl_bus_name of \buff4_reg[9]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg "; attribute srl_name of \buff4_reg[9]_srl3\ : label is "inst/\hls_macc_mul_32s_bkb_U1/hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg[9]_srl3 "; begin \a_reg0_reg[17]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(17), Q => a_reg0(17), R => '0' ); \a_reg0_reg[18]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(18), Q => a_reg0(18), R => '0' ); \a_reg0_reg[19]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(19), Q => a_reg0(19), R => '0' ); \a_reg0_reg[20]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(20), Q => a_reg0(20), R => '0' ); \a_reg0_reg[21]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(21), Q => a_reg0(21), R => '0' ); \a_reg0_reg[22]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(22), Q => a_reg0(22), R => '0' ); \a_reg0_reg[23]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(23), Q => a_reg0(23), R => '0' ); \a_reg0_reg[24]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(24), Q => a_reg0(24), R => '0' ); \a_reg0_reg[25]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(25), Q => a_reg0(25), R => '0' ); \a_reg0_reg[26]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(26), Q => a_reg0(26), R => '0' ); \a_reg0_reg[27]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(27), Q => a_reg0(27), R => '0' ); \a_reg0_reg[28]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(28), Q => a_reg0(28), R => '0' ); \a_reg0_reg[29]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(29), Q => a_reg0(29), R => '0' ); \a_reg0_reg[30]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(30), Q => a_reg0(30), R => '0' ); \a_reg0_reg[31]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_b_reg[31]\(31), Q => a_reg0(31), R => '0' ); \b_reg0_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(0), Q => b_reg0(0), R => '0' ); \b_reg0_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(10), Q => b_reg0(10), R => '0' ); \b_reg0_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(11), Q => b_reg0(11), R => '0' ); \b_reg0_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(12), Q => b_reg0(12), R => '0' ); \b_reg0_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(13), Q => b_reg0(13), R => '0' ); \b_reg0_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(14), Q => b_reg0(14), R => '0' ); \b_reg0_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(15), Q => b_reg0(15), R => '0' ); \b_reg0_reg[16]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(16), Q => b_reg0(16), R => '0' ); \b_reg0_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(1), Q => b_reg0(1), R => '0' ); \b_reg0_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(2), Q => b_reg0(2), R => '0' ); \b_reg0_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(3), Q => b_reg0(3), R => '0' ); \b_reg0_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(4), Q => b_reg0(4), R => '0' ); \b_reg0_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(5), Q => b_reg0(5), R => '0' ); \b_reg0_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(6), Q => b_reg0(6), R => '0' ); \b_reg0_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(7), Q => b_reg0(7), R => '0' ); \b_reg0_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(8), Q => b_reg0(8), R => '0' ); \b_reg0_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \int_a_reg[31]\(9), Q => b_reg0(9), R => '0' ); buff1_reg: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 1, ADREG => 1, ALUMODEREG => 0, AREG => 1, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 1, BREG => 1, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 1, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 17) => B"0000000000000", A(16 downto 0) => \int_b_reg[31]\(16 downto 0), ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => NLW_buff1_reg_ACOUT_UNCONNECTED(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17) => '0', B(16 downto 0) => \int_a_reg[31]\(16 downto 0), BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => NLW_buff1_reg_BCOUT_UNCONNECTED(17 downto 0), C(47 downto 0) => B"111111111111111111111111111111111111111111111111", CARRYCASCIN => '0', CARRYCASCOUT => NLW_buff1_reg_CARRYCASCOUT_UNCONNECTED, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => NLW_buff1_reg_CARRYOUT_UNCONNECTED(3 downto 0), CEA1 => '0', CEA2 => '1', CEAD => '0', CEALUMODE => '0', CEB1 => '0', CEB2 => '1', CEC => '0', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '1', CEP => '1', CLK => ap_clk, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => NLW_buff1_reg_MULTSIGNOUT_UNCONNECTED, OPMODE(6 downto 0) => B"0000101", OVERFLOW => NLW_buff1_reg_OVERFLOW_UNCONNECTED, P(47) => buff1_reg_n_58, P(46) => buff1_reg_n_59, P(45) => buff1_reg_n_60, P(44) => buff1_reg_n_61, P(43) => buff1_reg_n_62, P(42) => buff1_reg_n_63, P(41) => buff1_reg_n_64, P(40) => buff1_reg_n_65, P(39) => buff1_reg_n_66, P(38) => buff1_reg_n_67, P(37) => buff1_reg_n_68, P(36) => buff1_reg_n_69, P(35) => buff1_reg_n_70, P(34) => buff1_reg_n_71, P(33) => buff1_reg_n_72, P(32) => buff1_reg_n_73, P(31) => buff1_reg_n_74, P(30) => buff1_reg_n_75, P(29) => buff1_reg_n_76, P(28) => buff1_reg_n_77, P(27) => buff1_reg_n_78, P(26) => buff1_reg_n_79, P(25) => buff1_reg_n_80, P(24) => buff1_reg_n_81, P(23) => buff1_reg_n_82, P(22) => buff1_reg_n_83, P(21) => buff1_reg_n_84, P(20) => buff1_reg_n_85, P(19) => buff1_reg_n_86, P(18) => buff1_reg_n_87, P(17) => buff1_reg_n_88, P(16) => buff1_reg_n_89, P(15) => buff1_reg_n_90, P(14) => buff1_reg_n_91, P(13) => buff1_reg_n_92, P(12) => buff1_reg_n_93, P(11) => buff1_reg_n_94, P(10) => buff1_reg_n_95, P(9) => buff1_reg_n_96, P(8) => buff1_reg_n_97, P(7) => buff1_reg_n_98, P(6) => buff1_reg_n_99, P(5) => buff1_reg_n_100, P(4) => buff1_reg_n_101, P(3) => buff1_reg_n_102, P(2) => buff1_reg_n_103, P(1) => buff1_reg_n_104, P(0) => buff1_reg_n_105, PATTERNBDETECT => NLW_buff1_reg_PATTERNBDETECT_UNCONNECTED, PATTERNDETECT => NLW_buff1_reg_PATTERNDETECT_UNCONNECTED, PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", PCOUT(47) => buff1_reg_n_106, PCOUT(46) => buff1_reg_n_107, PCOUT(45) => buff1_reg_n_108, PCOUT(44) => buff1_reg_n_109, PCOUT(43) => buff1_reg_n_110, PCOUT(42) => buff1_reg_n_111, PCOUT(41) => buff1_reg_n_112, PCOUT(40) => buff1_reg_n_113, PCOUT(39) => buff1_reg_n_114, PCOUT(38) => buff1_reg_n_115, PCOUT(37) => buff1_reg_n_116, PCOUT(36) => buff1_reg_n_117, PCOUT(35) => buff1_reg_n_118, PCOUT(34) => buff1_reg_n_119, PCOUT(33) => buff1_reg_n_120, PCOUT(32) => buff1_reg_n_121, PCOUT(31) => buff1_reg_n_122, PCOUT(30) => buff1_reg_n_123, PCOUT(29) => buff1_reg_n_124, PCOUT(28) => buff1_reg_n_125, PCOUT(27) => buff1_reg_n_126, PCOUT(26) => buff1_reg_n_127, PCOUT(25) => buff1_reg_n_128, PCOUT(24) => buff1_reg_n_129, PCOUT(23) => buff1_reg_n_130, PCOUT(22) => buff1_reg_n_131, PCOUT(21) => buff1_reg_n_132, PCOUT(20) => buff1_reg_n_133, PCOUT(19) => buff1_reg_n_134, PCOUT(18) => buff1_reg_n_135, PCOUT(17) => buff1_reg_n_136, PCOUT(16) => buff1_reg_n_137, PCOUT(15) => buff1_reg_n_138, PCOUT(14) => buff1_reg_n_139, PCOUT(13) => buff1_reg_n_140, PCOUT(12) => buff1_reg_n_141, PCOUT(11) => buff1_reg_n_142, PCOUT(10) => buff1_reg_n_143, PCOUT(9) => buff1_reg_n_144, PCOUT(8) => buff1_reg_n_145, PCOUT(7) => buff1_reg_n_146, PCOUT(6) => buff1_reg_n_147, PCOUT(5) => buff1_reg_n_148, PCOUT(4) => buff1_reg_n_149, PCOUT(3) => buff1_reg_n_150, PCOUT(2) => buff1_reg_n_151, PCOUT(1) => buff1_reg_n_152, PCOUT(0) => buff1_reg_n_153, RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => '0', UNDERFLOW => NLW_buff1_reg_UNDERFLOW_UNCONNECTED ); \buff2_reg__0\: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 2, ADREG => 1, ALUMODEREG => 0, AREG => 2, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 2, BREG => 2, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 1, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 17) => B"0000000000000", A(16 downto 0) => \int_b_reg[31]\(16 downto 0), ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => \NLW_buff2_reg__0_ACOUT_UNCONNECTED\(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17) => \int_a_reg[31]\(31), B(16) => \int_a_reg[31]\(31), B(15) => \int_a_reg[31]\(31), B(14 downto 0) => \int_a_reg[31]\(31 downto 17), BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => \NLW_buff2_reg__0_BCOUT_UNCONNECTED\(17 downto 0), C(47 downto 0) => B"111111111111111111111111111111111111111111111111", CARRYCASCIN => '0', CARRYCASCOUT => \NLW_buff2_reg__0_CARRYCASCOUT_UNCONNECTED\, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => \NLW_buff2_reg__0_CARRYOUT_UNCONNECTED\(3 downto 0), CEA1 => '1', CEA2 => '1', CEAD => '0', CEALUMODE => '0', CEB1 => '1', CEB2 => '1', CEC => '0', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '1', CEP => '1', CLK => ap_clk, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => \NLW_buff2_reg__0_MULTSIGNOUT_UNCONNECTED\, OPMODE(6 downto 0) => B"1010101", OVERFLOW => \NLW_buff2_reg__0_OVERFLOW_UNCONNECTED\, P(47 downto 0) => \NLW_buff2_reg__0_P_UNCONNECTED\(47 downto 0), PATTERNBDETECT => \NLW_buff2_reg__0_PATTERNBDETECT_UNCONNECTED\, PATTERNDETECT => \NLW_buff2_reg__0_PATTERNDETECT_UNCONNECTED\, PCIN(47) => buff1_reg_n_106, PCIN(46) => buff1_reg_n_107, PCIN(45) => buff1_reg_n_108, PCIN(44) => buff1_reg_n_109, PCIN(43) => buff1_reg_n_110, PCIN(42) => buff1_reg_n_111, PCIN(41) => buff1_reg_n_112, PCIN(40) => buff1_reg_n_113, PCIN(39) => buff1_reg_n_114, PCIN(38) => buff1_reg_n_115, PCIN(37) => buff1_reg_n_116, PCIN(36) => buff1_reg_n_117, PCIN(35) => buff1_reg_n_118, PCIN(34) => buff1_reg_n_119, PCIN(33) => buff1_reg_n_120, PCIN(32) => buff1_reg_n_121, PCIN(31) => buff1_reg_n_122, PCIN(30) => buff1_reg_n_123, PCIN(29) => buff1_reg_n_124, PCIN(28) => buff1_reg_n_125, PCIN(27) => buff1_reg_n_126, PCIN(26) => buff1_reg_n_127, PCIN(25) => buff1_reg_n_128, PCIN(24) => buff1_reg_n_129, PCIN(23) => buff1_reg_n_130, PCIN(22) => buff1_reg_n_131, PCIN(21) => buff1_reg_n_132, PCIN(20) => buff1_reg_n_133, PCIN(19) => buff1_reg_n_134, PCIN(18) => buff1_reg_n_135, PCIN(17) => buff1_reg_n_136, PCIN(16) => buff1_reg_n_137, PCIN(15) => buff1_reg_n_138, PCIN(14) => buff1_reg_n_139, PCIN(13) => buff1_reg_n_140, PCIN(12) => buff1_reg_n_141, PCIN(11) => buff1_reg_n_142, PCIN(10) => buff1_reg_n_143, PCIN(9) => buff1_reg_n_144, PCIN(8) => buff1_reg_n_145, PCIN(7) => buff1_reg_n_146, PCIN(6) => buff1_reg_n_147, PCIN(5) => buff1_reg_n_148, PCIN(4) => buff1_reg_n_149, PCIN(3) => buff1_reg_n_150, PCIN(2) => buff1_reg_n_151, PCIN(1) => buff1_reg_n_152, PCIN(0) => buff1_reg_n_153, PCOUT(47) => \buff2_reg__0_n_106\, PCOUT(46) => \buff2_reg__0_n_107\, PCOUT(45) => \buff2_reg__0_n_108\, PCOUT(44) => \buff2_reg__0_n_109\, PCOUT(43) => \buff2_reg__0_n_110\, PCOUT(42) => \buff2_reg__0_n_111\, PCOUT(41) => \buff2_reg__0_n_112\, PCOUT(40) => \buff2_reg__0_n_113\, PCOUT(39) => \buff2_reg__0_n_114\, PCOUT(38) => \buff2_reg__0_n_115\, PCOUT(37) => \buff2_reg__0_n_116\, PCOUT(36) => \buff2_reg__0_n_117\, PCOUT(35) => \buff2_reg__0_n_118\, PCOUT(34) => \buff2_reg__0_n_119\, PCOUT(33) => \buff2_reg__0_n_120\, PCOUT(32) => \buff2_reg__0_n_121\, PCOUT(31) => \buff2_reg__0_n_122\, PCOUT(30) => \buff2_reg__0_n_123\, PCOUT(29) => \buff2_reg__0_n_124\, PCOUT(28) => \buff2_reg__0_n_125\, PCOUT(27) => \buff2_reg__0_n_126\, PCOUT(26) => \buff2_reg__0_n_127\, PCOUT(25) => \buff2_reg__0_n_128\, PCOUT(24) => \buff2_reg__0_n_129\, PCOUT(23) => \buff2_reg__0_n_130\, PCOUT(22) => \buff2_reg__0_n_131\, PCOUT(21) => \buff2_reg__0_n_132\, PCOUT(20) => \buff2_reg__0_n_133\, PCOUT(19) => \buff2_reg__0_n_134\, PCOUT(18) => \buff2_reg__0_n_135\, PCOUT(17) => \buff2_reg__0_n_136\, PCOUT(16) => \buff2_reg__0_n_137\, PCOUT(15) => \buff2_reg__0_n_138\, PCOUT(14) => \buff2_reg__0_n_139\, PCOUT(13) => \buff2_reg__0_n_140\, PCOUT(12) => \buff2_reg__0_n_141\, PCOUT(11) => \buff2_reg__0_n_142\, PCOUT(10) => \buff2_reg__0_n_143\, PCOUT(9) => \buff2_reg__0_n_144\, PCOUT(8) => \buff2_reg__0_n_145\, PCOUT(7) => \buff2_reg__0_n_146\, PCOUT(6) => \buff2_reg__0_n_147\, PCOUT(5) => \buff2_reg__0_n_148\, PCOUT(4) => \buff2_reg__0_n_149\, PCOUT(3) => \buff2_reg__0_n_150\, PCOUT(2) => \buff2_reg__0_n_151\, PCOUT(1) => \buff2_reg__0_n_152\, PCOUT(0) => \buff2_reg__0_n_153\, RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => '0', UNDERFLOW => \NLW_buff2_reg__0_UNDERFLOW_UNCONNECTED\ ); \buff3_reg__0\: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 2, ADREG => 1, ALUMODEREG => 0, AREG => 2, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 2, BREG => 2, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 1, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 17) => B"0000000000000", A(16 downto 0) => b_reg0(16 downto 0), ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => \NLW_buff3_reg__0_ACOUT_UNCONNECTED\(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17) => a_reg0(31), B(16) => a_reg0(31), B(15) => a_reg0(31), B(14 downto 0) => a_reg0(31 downto 17), BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => \NLW_buff3_reg__0_BCOUT_UNCONNECTED\(17 downto 0), C(47 downto 0) => B"111111111111111111111111111111111111111111111111", CARRYCASCIN => '0', CARRYCASCOUT => \NLW_buff3_reg__0_CARRYCASCOUT_UNCONNECTED\, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => \NLW_buff3_reg__0_CARRYOUT_UNCONNECTED\(3 downto 0), CEA1 => '1', CEA2 => '1', CEAD => '0', CEALUMODE => '0', CEB1 => '1', CEB2 => '1', CEC => '0', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '1', CEP => '1', CLK => ap_clk, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => \NLW_buff3_reg__0_MULTSIGNOUT_UNCONNECTED\, OPMODE(6 downto 0) => B"0010101", OVERFLOW => \NLW_buff3_reg__0_OVERFLOW_UNCONNECTED\, P(47) => \buff3_reg__0_n_58\, P(46) => \buff3_reg__0_n_59\, P(45) => \buff3_reg__0_n_60\, P(44) => \buff3_reg__0_n_61\, P(43) => \buff3_reg__0_n_62\, P(42) => \buff3_reg__0_n_63\, P(41) => \buff3_reg__0_n_64\, P(40) => \buff3_reg__0_n_65\, P(39) => \buff3_reg__0_n_66\, P(38) => \buff3_reg__0_n_67\, P(37) => \buff3_reg__0_n_68\, P(36) => \buff3_reg__0_n_69\, P(35) => \buff3_reg__0_n_70\, P(34) => \buff3_reg__0_n_71\, P(33) => \buff3_reg__0_n_72\, P(32) => \buff3_reg__0_n_73\, P(31) => \buff3_reg__0_n_74\, P(30) => \buff3_reg__0_n_75\, P(29) => \buff3_reg__0_n_76\, P(28) => \buff3_reg__0_n_77\, P(27) => \buff3_reg__0_n_78\, P(26) => \buff3_reg__0_n_79\, P(25) => \buff3_reg__0_n_80\, P(24) => \buff3_reg__0_n_81\, P(23) => \buff3_reg__0_n_82\, P(22) => \buff3_reg__0_n_83\, P(21) => \buff3_reg__0_n_84\, P(20) => \buff3_reg__0_n_85\, P(19) => \buff3_reg__0_n_86\, P(18) => \buff3_reg__0_n_87\, P(17) => \buff3_reg__0_n_88\, P(16) => \buff3_reg__0_n_89\, P(15) => \buff3_reg__0_n_90\, P(14) => \buff3_reg__0_n_91\, P(13) => \buff3_reg__0_n_92\, P(12) => \buff3_reg__0_n_93\, P(11) => \buff3_reg__0_n_94\, P(10) => \buff3_reg__0_n_95\, P(9) => \buff3_reg__0_n_96\, P(8) => \buff3_reg__0_n_97\, P(7) => \buff3_reg__0_n_98\, P(6) => \buff3_reg__0_n_99\, P(5) => \buff3_reg__0_n_100\, P(4) => \buff3_reg__0_n_101\, P(3) => \buff3_reg__0_n_102\, P(2) => \buff3_reg__0_n_103\, P(1) => \buff3_reg__0_n_104\, P(0) => \buff3_reg__0_n_105\, PATTERNBDETECT => \NLW_buff3_reg__0_PATTERNBDETECT_UNCONNECTED\, PATTERNDETECT => \NLW_buff3_reg__0_PATTERNDETECT_UNCONNECTED\, PCIN(47) => \buff2_reg__0_n_106\, PCIN(46) => \buff2_reg__0_n_107\, PCIN(45) => \buff2_reg__0_n_108\, PCIN(44) => \buff2_reg__0_n_109\, PCIN(43) => \buff2_reg__0_n_110\, PCIN(42) => \buff2_reg__0_n_111\, PCIN(41) => \buff2_reg__0_n_112\, PCIN(40) => \buff2_reg__0_n_113\, PCIN(39) => \buff2_reg__0_n_114\, PCIN(38) => \buff2_reg__0_n_115\, PCIN(37) => \buff2_reg__0_n_116\, PCIN(36) => \buff2_reg__0_n_117\, PCIN(35) => \buff2_reg__0_n_118\, PCIN(34) => \buff2_reg__0_n_119\, PCIN(33) => \buff2_reg__0_n_120\, PCIN(32) => \buff2_reg__0_n_121\, PCIN(31) => \buff2_reg__0_n_122\, PCIN(30) => \buff2_reg__0_n_123\, PCIN(29) => \buff2_reg__0_n_124\, PCIN(28) => \buff2_reg__0_n_125\, PCIN(27) => \buff2_reg__0_n_126\, PCIN(26) => \buff2_reg__0_n_127\, PCIN(25) => \buff2_reg__0_n_128\, PCIN(24) => \buff2_reg__0_n_129\, PCIN(23) => \buff2_reg__0_n_130\, PCIN(22) => \buff2_reg__0_n_131\, PCIN(21) => \buff2_reg__0_n_132\, PCIN(20) => \buff2_reg__0_n_133\, PCIN(19) => \buff2_reg__0_n_134\, PCIN(18) => \buff2_reg__0_n_135\, PCIN(17) => \buff2_reg__0_n_136\, PCIN(16) => \buff2_reg__0_n_137\, PCIN(15) => \buff2_reg__0_n_138\, PCIN(14) => \buff2_reg__0_n_139\, PCIN(13) => \buff2_reg__0_n_140\, PCIN(12) => \buff2_reg__0_n_141\, PCIN(11) => \buff2_reg__0_n_142\, PCIN(10) => \buff2_reg__0_n_143\, PCIN(9) => \buff2_reg__0_n_144\, PCIN(8) => \buff2_reg__0_n_145\, PCIN(7) => \buff2_reg__0_n_146\, PCIN(6) => \buff2_reg__0_n_147\, PCIN(5) => \buff2_reg__0_n_148\, PCIN(4) => \buff2_reg__0_n_149\, PCIN(3) => \buff2_reg__0_n_150\, PCIN(2) => \buff2_reg__0_n_151\, PCIN(1) => \buff2_reg__0_n_152\, PCIN(0) => \buff2_reg__0_n_153\, PCOUT(47 downto 0) => \NLW_buff3_reg__0_PCOUT_UNCONNECTED\(47 downto 0), RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => '0', UNDERFLOW => \NLW_buff3_reg__0_UNDERFLOW_UNCONNECTED\ ); \buff4_reg[0]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_105\, Q => D(17), R => '0' ); \buff4_reg[0]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_105, Q => D(0) ); \buff4_reg[10]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_95\, Q => D(27), R => '0' ); \buff4_reg[10]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_95, Q => D(10) ); \buff4_reg[11]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_94\, Q => D(28), R => '0' ); \buff4_reg[11]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_94, Q => D(11) ); \buff4_reg[12]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_93\, Q => D(29), R => '0' ); \buff4_reg[12]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_93, Q => D(12) ); \buff4_reg[13]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_92\, Q => D(30), R => '0' ); \buff4_reg[13]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_92, Q => D(13) ); \buff4_reg[14]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_91\, Q => D(31), R => '0' ); \buff4_reg[14]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_91, Q => D(14) ); \buff4_reg[15]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_90, Q => D(15) ); \buff4_reg[16]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_89, Q => D(16) ); \buff4_reg[1]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_104\, Q => D(18), R => '0' ); \buff4_reg[1]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_104, Q => D(1) ); \buff4_reg[2]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_103\, Q => D(19), R => '0' ); \buff4_reg[2]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_103, Q => D(2) ); \buff4_reg[3]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_102\, Q => D(20), R => '0' ); \buff4_reg[3]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_102, Q => D(3) ); \buff4_reg[4]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_101\, Q => D(21), R => '0' ); \buff4_reg[4]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_101, Q => D(4) ); \buff4_reg[5]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_100\, Q => D(22), R => '0' ); \buff4_reg[5]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_100, Q => D(5) ); \buff4_reg[6]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_99\, Q => D(23), R => '0' ); \buff4_reg[6]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_99, Q => D(6) ); \buff4_reg[7]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_98\, Q => D(24), R => '0' ); \buff4_reg[7]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_98, Q => D(7) ); \buff4_reg[8]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_97\, Q => D(25), R => '0' ); \buff4_reg[8]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_97, Q => D(8) ); \buff4_reg[9]__0\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \buff3_reg__0_n_96\, Q => D(26), R => '0' ); \buff4_reg[9]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => ap_clk, D => buff1_reg_n_96, Q => D(9) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); ap_clk : in STD_LOGIC; \int_a_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \int_b_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb is begin hls_macc_mul_32s_bkb_MulnS_0_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb_MulnS_0 port map ( D(31 downto 0) => D(31 downto 0), ap_clk => ap_clk, \int_a_reg[31]\(31 downto 0) => \int_a_reg[31]\(31 downto 0), \int_b_reg[31]\(31 downto 0) => \int_b_reg[31]\(31 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc is port ( ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_BVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); interrupt : out STD_LOGIC ); attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is 6; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is 4; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b000000001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b000000010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b000000100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b000001000"; attribute ap_ST_fsm_state5 : string; attribute ap_ST_fsm_state5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b000010000"; attribute ap_ST_fsm_state6 : string; attribute ap_ST_fsm_state6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b000100000"; attribute ap_ST_fsm_state7 : string; attribute ap_ST_fsm_state7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b001000000"; attribute ap_ST_fsm_state8 : string; attribute ap_ST_fsm_state8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b010000000"; attribute ap_ST_fsm_state9 : string; attribute ap_ST_fsm_state9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "9'b100000000"; attribute hls_module : string; attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc is signal \<const0>\ : STD_LOGIC; signal a : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \acc_reg[0]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[0]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[0]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[0]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[12]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[16]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[20]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[24]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[28]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[4]_i_5_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_2_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_3_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_4_n_0\ : STD_LOGIC; signal \acc_reg[8]_i_5_n_0\ : STD_LOGIC; signal acc_reg_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \acc_reg_reg[0]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[0]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[12]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[16]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[20]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[24]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[28]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[4]_i_1_n_7\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_0\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_1\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_2\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_3\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_4\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_5\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_6\ : STD_LOGIC; signal \acc_reg_reg[8]_i_1_n_7\ : STD_LOGIC; signal accum_clr_read_reg_85 : STD_LOGIC; signal \ap_CS_fsm[1]_i_3_n_0\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[1]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[2]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[3]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[4]\ : STD_LOGIC; signal \ap_CS_fsm_reg_n_0_[5]\ : STD_LOGIC; signal ap_CS_fsm_state7 : STD_LOGIC; signal ap_CS_fsm_state9 : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ap_rst_n_inv : STD_LOGIC; signal b : STD_LOGIC_VECTOR ( 31 downto 0 ); signal hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U_n_73 : STD_LOGIC; signal \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal sel : STD_LOGIC; signal tmp_1_reg_100 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_acc_reg_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute FSM_ENCODING : string; attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[4]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[5]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[6]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[7]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[8]\ : label is "none"; begin s_axi_HLS_MACC_PERIPH_BUS_BRESP(1) <= \<const0>\; s_axi_HLS_MACC_PERIPH_BUS_BRESP(0) <= \<const0>\; s_axi_HLS_MACC_PERIPH_BUS_RRESP(1) <= \<const0>\; s_axi_HLS_MACC_PERIPH_BUS_RRESP(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \acc_reg[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(3), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(3), O => \acc_reg[0]_i_2_n_0\ ); \acc_reg[0]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(2), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(2), O => \acc_reg[0]_i_3_n_0\ ); \acc_reg[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(1), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(1), O => \acc_reg[0]_i_4_n_0\ ); \acc_reg[0]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(0), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(0), O => \acc_reg[0]_i_5_n_0\ ); \acc_reg[12]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(15), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(15), O => \acc_reg[12]_i_2_n_0\ ); \acc_reg[12]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(14), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(14), O => \acc_reg[12]_i_3_n_0\ ); \acc_reg[12]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(13), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(13), O => \acc_reg[12]_i_4_n_0\ ); \acc_reg[12]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(12), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(12), O => \acc_reg[12]_i_5_n_0\ ); \acc_reg[16]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(19), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(19), O => \acc_reg[16]_i_2_n_0\ ); \acc_reg[16]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(18), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(18), O => \acc_reg[16]_i_3_n_0\ ); \acc_reg[16]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(17), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(17), O => \acc_reg[16]_i_4_n_0\ ); \acc_reg[16]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(16), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(16), O => \acc_reg[16]_i_5_n_0\ ); \acc_reg[20]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(23), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(23), O => \acc_reg[20]_i_2_n_0\ ); \acc_reg[20]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(22), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(22), O => \acc_reg[20]_i_3_n_0\ ); \acc_reg[20]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(21), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(21), O => \acc_reg[20]_i_4_n_0\ ); \acc_reg[20]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(20), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(20), O => \acc_reg[20]_i_5_n_0\ ); \acc_reg[24]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(27), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(27), O => \acc_reg[24]_i_2_n_0\ ); \acc_reg[24]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(26), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(26), O => \acc_reg[24]_i_3_n_0\ ); \acc_reg[24]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(25), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(25), O => \acc_reg[24]_i_4_n_0\ ); \acc_reg[24]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(24), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(24), O => \acc_reg[24]_i_5_n_0\ ); \acc_reg[28]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(31), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(31), O => \acc_reg[28]_i_2_n_0\ ); \acc_reg[28]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(30), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(30), O => \acc_reg[28]_i_3_n_0\ ); \acc_reg[28]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(29), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(29), O => \acc_reg[28]_i_4_n_0\ ); \acc_reg[28]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(28), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(28), O => \acc_reg[28]_i_5_n_0\ ); \acc_reg[4]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(7), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(7), O => \acc_reg[4]_i_2_n_0\ ); \acc_reg[4]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(6), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(6), O => \acc_reg[4]_i_3_n_0\ ); \acc_reg[4]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(5), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(5), O => \acc_reg[4]_i_4_n_0\ ); \acc_reg[4]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(4), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(4), O => \acc_reg[4]_i_5_n_0\ ); \acc_reg[8]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(11), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(11), O => \acc_reg[8]_i_2_n_0\ ); \acc_reg[8]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(10), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(10), O => \acc_reg[8]_i_3_n_0\ ); \acc_reg[8]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(9), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(9), O => \acc_reg[8]_i_4_n_0\ ); \acc_reg[8]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => tmp_1_reg_100(8), I1 => accum_clr_read_reg_85, I2 => acc_reg_reg(8), O => \acc_reg[8]_i_5_n_0\ ); \acc_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_7\, Q => acc_reg_reg(0), R => '0' ); \acc_reg_reg[0]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \acc_reg_reg[0]_i_1_n_0\, CO(2) => \acc_reg_reg[0]_i_1_n_1\, CO(1) => \acc_reg_reg[0]_i_1_n_2\, CO(0) => \acc_reg_reg[0]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(3 downto 0), O(3) => \acc_reg_reg[0]_i_1_n_4\, O(2) => \acc_reg_reg[0]_i_1_n_5\, O(1) => \acc_reg_reg[0]_i_1_n_6\, O(0) => \acc_reg_reg[0]_i_1_n_7\, S(3) => \acc_reg[0]_i_2_n_0\, S(2) => \acc_reg[0]_i_3_n_0\, S(1) => \acc_reg[0]_i_4_n_0\, S(0) => \acc_reg[0]_i_5_n_0\ ); \acc_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_5\, Q => acc_reg_reg(10), R => '0' ); \acc_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_4\, Q => acc_reg_reg(11), R => '0' ); \acc_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_7\, Q => acc_reg_reg(12), R => '0' ); \acc_reg_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[8]_i_1_n_0\, CO(3) => \acc_reg_reg[12]_i_1_n_0\, CO(2) => \acc_reg_reg[12]_i_1_n_1\, CO(1) => \acc_reg_reg[12]_i_1_n_2\, CO(0) => \acc_reg_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(15 downto 12), O(3) => \acc_reg_reg[12]_i_1_n_4\, O(2) => \acc_reg_reg[12]_i_1_n_5\, O(1) => \acc_reg_reg[12]_i_1_n_6\, O(0) => \acc_reg_reg[12]_i_1_n_7\, S(3) => \acc_reg[12]_i_2_n_0\, S(2) => \acc_reg[12]_i_3_n_0\, S(1) => \acc_reg[12]_i_4_n_0\, S(0) => \acc_reg[12]_i_5_n_0\ ); \acc_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_6\, Q => acc_reg_reg(13), R => '0' ); \acc_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_5\, Q => acc_reg_reg(14), R => '0' ); \acc_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[12]_i_1_n_4\, Q => acc_reg_reg(15), R => '0' ); \acc_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_7\, Q => acc_reg_reg(16), R => '0' ); \acc_reg_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[12]_i_1_n_0\, CO(3) => \acc_reg_reg[16]_i_1_n_0\, CO(2) => \acc_reg_reg[16]_i_1_n_1\, CO(1) => \acc_reg_reg[16]_i_1_n_2\, CO(0) => \acc_reg_reg[16]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(19 downto 16), O(3) => \acc_reg_reg[16]_i_1_n_4\, O(2) => \acc_reg_reg[16]_i_1_n_5\, O(1) => \acc_reg_reg[16]_i_1_n_6\, O(0) => \acc_reg_reg[16]_i_1_n_7\, S(3) => \acc_reg[16]_i_2_n_0\, S(2) => \acc_reg[16]_i_3_n_0\, S(1) => \acc_reg[16]_i_4_n_0\, S(0) => \acc_reg[16]_i_5_n_0\ ); \acc_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_6\, Q => acc_reg_reg(17), R => '0' ); \acc_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_5\, Q => acc_reg_reg(18), R => '0' ); \acc_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[16]_i_1_n_4\, Q => acc_reg_reg(19), R => '0' ); \acc_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_6\, Q => acc_reg_reg(1), R => '0' ); \acc_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_7\, Q => acc_reg_reg(20), R => '0' ); \acc_reg_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[16]_i_1_n_0\, CO(3) => \acc_reg_reg[20]_i_1_n_0\, CO(2) => \acc_reg_reg[20]_i_1_n_1\, CO(1) => \acc_reg_reg[20]_i_1_n_2\, CO(0) => \acc_reg_reg[20]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(23 downto 20), O(3) => \acc_reg_reg[20]_i_1_n_4\, O(2) => \acc_reg_reg[20]_i_1_n_5\, O(1) => \acc_reg_reg[20]_i_1_n_6\, O(0) => \acc_reg_reg[20]_i_1_n_7\, S(3) => \acc_reg[20]_i_2_n_0\, S(2) => \acc_reg[20]_i_3_n_0\, S(1) => \acc_reg[20]_i_4_n_0\, S(0) => \acc_reg[20]_i_5_n_0\ ); \acc_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_6\, Q => acc_reg_reg(21), R => '0' ); \acc_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_5\, Q => acc_reg_reg(22), R => '0' ); \acc_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[20]_i_1_n_4\, Q => acc_reg_reg(23), R => '0' ); \acc_reg_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_7\, Q => acc_reg_reg(24), R => '0' ); \acc_reg_reg[24]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[20]_i_1_n_0\, CO(3) => \acc_reg_reg[24]_i_1_n_0\, CO(2) => \acc_reg_reg[24]_i_1_n_1\, CO(1) => \acc_reg_reg[24]_i_1_n_2\, CO(0) => \acc_reg_reg[24]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(27 downto 24), O(3) => \acc_reg_reg[24]_i_1_n_4\, O(2) => \acc_reg_reg[24]_i_1_n_5\, O(1) => \acc_reg_reg[24]_i_1_n_6\, O(0) => \acc_reg_reg[24]_i_1_n_7\, S(3) => \acc_reg[24]_i_2_n_0\, S(2) => \acc_reg[24]_i_3_n_0\, S(1) => \acc_reg[24]_i_4_n_0\, S(0) => \acc_reg[24]_i_5_n_0\ ); \acc_reg_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_6\, Q => acc_reg_reg(25), R => '0' ); \acc_reg_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_5\, Q => acc_reg_reg(26), R => '0' ); \acc_reg_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[24]_i_1_n_4\, Q => acc_reg_reg(27), R => '0' ); \acc_reg_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_7\, Q => acc_reg_reg(28), R => '0' ); \acc_reg_reg[28]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[24]_i_1_n_0\, CO(3) => \NLW_acc_reg_reg[28]_i_1_CO_UNCONNECTED\(3), CO(2) => \acc_reg_reg[28]_i_1_n_1\, CO(1) => \acc_reg_reg[28]_i_1_n_2\, CO(0) => \acc_reg_reg[28]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => tmp_1_reg_100(30 downto 28), O(3) => \acc_reg_reg[28]_i_1_n_4\, O(2) => \acc_reg_reg[28]_i_1_n_5\, O(1) => \acc_reg_reg[28]_i_1_n_6\, O(0) => \acc_reg_reg[28]_i_1_n_7\, S(3) => \acc_reg[28]_i_2_n_0\, S(2) => \acc_reg[28]_i_3_n_0\, S(1) => \acc_reg[28]_i_4_n_0\, S(0) => \acc_reg[28]_i_5_n_0\ ); \acc_reg_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_6\, Q => acc_reg_reg(29), R => '0' ); \acc_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_5\, Q => acc_reg_reg(2), R => '0' ); \acc_reg_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_5\, Q => acc_reg_reg(30), R => '0' ); \acc_reg_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[28]_i_1_n_4\, Q => acc_reg_reg(31), R => '0' ); \acc_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[0]_i_1_n_4\, Q => acc_reg_reg(3), R => '0' ); \acc_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_7\, Q => acc_reg_reg(4), R => '0' ); \acc_reg_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[0]_i_1_n_0\, CO(3) => \acc_reg_reg[4]_i_1_n_0\, CO(2) => \acc_reg_reg[4]_i_1_n_1\, CO(1) => \acc_reg_reg[4]_i_1_n_2\, CO(0) => \acc_reg_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(7 downto 4), O(3) => \acc_reg_reg[4]_i_1_n_4\, O(2) => \acc_reg_reg[4]_i_1_n_5\, O(1) => \acc_reg_reg[4]_i_1_n_6\, O(0) => \acc_reg_reg[4]_i_1_n_7\, S(3) => \acc_reg[4]_i_2_n_0\, S(2) => \acc_reg[4]_i_3_n_0\, S(1) => \acc_reg[4]_i_4_n_0\, S(0) => \acc_reg[4]_i_5_n_0\ ); \acc_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_6\, Q => acc_reg_reg(5), R => '0' ); \acc_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_5\, Q => acc_reg_reg(6), R => '0' ); \acc_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[4]_i_1_n_4\, Q => acc_reg_reg(7), R => '0' ); \acc_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_7\, Q => acc_reg_reg(8), R => '0' ); \acc_reg_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \acc_reg_reg[4]_i_1_n_0\, CO(3) => \acc_reg_reg[8]_i_1_n_0\, CO(2) => \acc_reg_reg[8]_i_1_n_1\, CO(1) => \acc_reg_reg[8]_i_1_n_2\, CO(0) => \acc_reg_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => tmp_1_reg_100(11 downto 8), O(3) => \acc_reg_reg[8]_i_1_n_4\, O(2) => \acc_reg_reg[8]_i_1_n_5\, O(1) => \acc_reg_reg[8]_i_1_n_6\, O(0) => \acc_reg_reg[8]_i_1_n_7\, S(3) => \acc_reg[8]_i_2_n_0\, S(2) => \acc_reg[8]_i_3_n_0\, S(1) => \acc_reg[8]_i_4_n_0\, S(0) => \acc_reg[8]_i_5_n_0\ ); \acc_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => sel, D => \acc_reg_reg[8]_i_1_n_6\, Q => acc_reg_reg(9), R => '0' ); \accum_clr_read_reg_85_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U_n_73, Q => accum_clr_read_reg_85, R => '0' ); \ap_CS_fsm[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \ap_CS_fsm_reg_n_0_[4]\, I1 => \ap_CS_fsm_reg_n_0_[5]\, I2 => \ap_CS_fsm_reg_n_0_[2]\, I3 => \ap_CS_fsm_reg_n_0_[3]\, O => \ap_CS_fsm[1]_i_3_n_0\ ); \ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(0), Q => \ap_CS_fsm_reg_n_0_[0]\, S => ap_rst_n_inv ); \ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(1), Q => \ap_CS_fsm_reg_n_0_[1]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[1]\, Q => \ap_CS_fsm_reg_n_0_[2]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[2]\, Q => \ap_CS_fsm_reg_n_0_[3]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[3]\, Q => \ap_CS_fsm_reg_n_0_[4]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[4]\, Q => \ap_CS_fsm_reg_n_0_[5]\, R => ap_rst_n_inv ); \ap_CS_fsm_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \ap_CS_fsm_reg_n_0_[5]\, Q => ap_CS_fsm_state7, R => ap_rst_n_inv ); \ap_CS_fsm_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_CS_fsm_state7, Q => sel, R => ap_rst_n_inv ); \ap_CS_fsm_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => sel, Q => ap_CS_fsm_state9, R => ap_rst_n_inv ); hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_HLS_MACC_PERIPH_BUS_s_axi port map ( D(1 downto 0) => ap_NS_fsm(1 downto 0), Q(4) => ap_CS_fsm_state9, Q(3) => sel, Q(2) => ap_CS_fsm_state7, Q(1) => \ap_CS_fsm_reg_n_0_[1]\, Q(0) => \ap_CS_fsm_reg_n_0_[0]\, SR(0) => ap_rst_n_inv, \a_reg0_reg[31]\(31 downto 0) => b(31 downto 0), \acc_reg_reg[31]\(31 downto 0) => acc_reg_reg(31 downto 0), accum_clr_read_reg_85 => accum_clr_read_reg_85, \accum_clr_read_reg_85_reg[0]\ => hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U_n_73, \ap_CS_fsm_reg[4]\ => \ap_CS_fsm[1]_i_3_n_0\, ap_clk => ap_clk, ap_rst_n => ap_rst_n, \buff2_reg__0\(31 downto 0) => a(31 downto 0), interrupt => interrupt, \out\(2) => s_axi_HLS_MACC_PERIPH_BUS_BVALID, \out\(1) => s_axi_HLS_MACC_PERIPH_BUS_WREADY, \out\(0) => s_axi_HLS_MACC_PERIPH_BUS_AWREADY, s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_ARVALID => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_AWVALID => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, s_axi_HLS_MACC_PERIPH_BUS_BREADY => s_axi_HLS_MACC_PERIPH_BUS_BREADY, s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_RREADY => s_axi_HLS_MACC_PERIPH_BUS_RREADY, s_axi_HLS_MACC_PERIPH_BUS_RVALID(1) => s_axi_HLS_MACC_PERIPH_BUS_RVALID, s_axi_HLS_MACC_PERIPH_BUS_RVALID(0) => s_axi_HLS_MACC_PERIPH_BUS_ARREADY, s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WVALID => s_axi_HLS_MACC_PERIPH_BUS_WVALID ); hls_macc_mul_32s_bkb_U1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc_mul_32s_bkb port map ( D(31 downto 0) => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(31 downto 0), ap_clk => ap_clk, \int_a_reg[31]\(31 downto 0) => a(31 downto 0), \int_b_reg[31]\(31 downto 0) => b(31 downto 0) ); \tmp_1_reg_100_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(0), Q => tmp_1_reg_100(0), R => '0' ); \tmp_1_reg_100_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(10), Q => tmp_1_reg_100(10), R => '0' ); \tmp_1_reg_100_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(11), Q => tmp_1_reg_100(11), R => '0' ); \tmp_1_reg_100_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(12), Q => tmp_1_reg_100(12), R => '0' ); \tmp_1_reg_100_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(13), Q => tmp_1_reg_100(13), R => '0' ); \tmp_1_reg_100_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(14), Q => tmp_1_reg_100(14), R => '0' ); \tmp_1_reg_100_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(15), Q => tmp_1_reg_100(15), R => '0' ); \tmp_1_reg_100_reg[16]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(16), Q => tmp_1_reg_100(16), R => '0' ); \tmp_1_reg_100_reg[17]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(17), Q => tmp_1_reg_100(17), R => '0' ); \tmp_1_reg_100_reg[18]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(18), Q => tmp_1_reg_100(18), R => '0' ); \tmp_1_reg_100_reg[19]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(19), Q => tmp_1_reg_100(19), R => '0' ); \tmp_1_reg_100_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(1), Q => tmp_1_reg_100(1), R => '0' ); \tmp_1_reg_100_reg[20]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(20), Q => tmp_1_reg_100(20), R => '0' ); \tmp_1_reg_100_reg[21]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(21), Q => tmp_1_reg_100(21), R => '0' ); \tmp_1_reg_100_reg[22]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(22), Q => tmp_1_reg_100(22), R => '0' ); \tmp_1_reg_100_reg[23]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(23), Q => tmp_1_reg_100(23), R => '0' ); \tmp_1_reg_100_reg[24]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(24), Q => tmp_1_reg_100(24), R => '0' ); \tmp_1_reg_100_reg[25]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(25), Q => tmp_1_reg_100(25), R => '0' ); \tmp_1_reg_100_reg[26]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(26), Q => tmp_1_reg_100(26), R => '0' ); \tmp_1_reg_100_reg[27]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(27), Q => tmp_1_reg_100(27), R => '0' ); \tmp_1_reg_100_reg[28]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(28), Q => tmp_1_reg_100(28), R => '0' ); \tmp_1_reg_100_reg[29]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(29), Q => tmp_1_reg_100(29), R => '0' ); \tmp_1_reg_100_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(2), Q => tmp_1_reg_100(2), R => '0' ); \tmp_1_reg_100_reg[30]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(30), Q => tmp_1_reg_100(30), R => '0' ); \tmp_1_reg_100_reg[31]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(31), Q => tmp_1_reg_100(31), R => '0' ); \tmp_1_reg_100_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(3), Q => tmp_1_reg_100(3), R => '0' ); \tmp_1_reg_100_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(4), Q => tmp_1_reg_100(4), R => '0' ); \tmp_1_reg_100_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(5), Q => tmp_1_reg_100(5), R => '0' ); \tmp_1_reg_100_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(6), Q => tmp_1_reg_100(6), R => '0' ); \tmp_1_reg_100_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(7), Q => tmp_1_reg_100(7), R => '0' ); \tmp_1_reg_100_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(8), Q => tmp_1_reg_100(8), R => '0' ); \tmp_1_reg_100_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_CS_fsm_state7, D => \hls_macc_mul_32s_bkb_MulnS_0_U/buff4_reg\(9), Q => tmp_1_reg_100(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( s_axi_HLS_MACC_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_AWVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_AWREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_WVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_WREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_BVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_BREADY : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_ARVALID : in STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_ARREADY : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_HLS_MACC_PERIPH_BUS_RVALID : out STD_LOGIC; s_axi_HLS_MACC_PERIPH_BUS_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zybo_zynq_design_hls_macc_0_0,hls_macc,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute IP_DEFINITION_SOURCE : string; attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HLS"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "hls_macc,Vivado 2018.2"; attribute hls_module : string; attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH of inst : label is 6; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_HLS_MACC_PERIPH_BUS_WSTRB_WIDTH of inst : label is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of inst : label is "9'b000000001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of inst : label is "9'b000000010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of inst : label is "9'b000000100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of inst : label is "9'b000001000"; attribute ap_ST_fsm_state5 : string; attribute ap_ST_fsm_state5 of inst : label is "9'b000010000"; attribute ap_ST_fsm_state6 : string; attribute ap_ST_fsm_state6 of inst : label is "9'b000100000"; attribute ap_ST_fsm_state7 : string; attribute ap_ST_fsm_state7 of inst : label is "9'b001000000"; attribute ap_ST_fsm_state8 : string; attribute ap_ST_fsm_state8 of inst : label is "9'b010000000"; attribute ap_ST_fsm_state9 : string; attribute ap_ST_fsm_state9 of inst : label is "9'b100000000"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_HLS_MACC_PERIPH_BUS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST"; attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}"; attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT"; attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_HLS_MACC_PERIPH_BUS_RREADY : signal is "XIL_INTERFACENAME s_axi_HLS_MACC_PERIPH_BUS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WREADY"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WVALID"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARADDR"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWADDR"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BRESP"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RDATA"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RRESP"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WDATA"; attribute X_INTERFACE_INFO of s_axi_HLS_MACC_PERIPH_BUS_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_hls_macc port map ( ap_clk => ap_clk, ap_rst_n => ap_rst_n, interrupt => interrupt, s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_ARADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_ARREADY => s_axi_HLS_MACC_PERIPH_BUS_ARREADY, s_axi_HLS_MACC_PERIPH_BUS_ARVALID => s_axi_HLS_MACC_PERIPH_BUS_ARVALID, s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_AWADDR(5 downto 0), s_axi_HLS_MACC_PERIPH_BUS_AWREADY => s_axi_HLS_MACC_PERIPH_BUS_AWREADY, s_axi_HLS_MACC_PERIPH_BUS_AWVALID => s_axi_HLS_MACC_PERIPH_BUS_AWVALID, s_axi_HLS_MACC_PERIPH_BUS_BREADY => s_axi_HLS_MACC_PERIPH_BUS_BREADY, s_axi_HLS_MACC_PERIPH_BUS_BRESP(1 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_BRESP(1 downto 0), s_axi_HLS_MACC_PERIPH_BUS_BVALID => s_axi_HLS_MACC_PERIPH_BUS_BVALID, s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_RDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_RREADY => s_axi_HLS_MACC_PERIPH_BUS_RREADY, s_axi_HLS_MACC_PERIPH_BUS_RRESP(1 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_RRESP(1 downto 0), s_axi_HLS_MACC_PERIPH_BUS_RVALID => s_axi_HLS_MACC_PERIPH_BUS_RVALID, s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WDATA(31 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WREADY => s_axi_HLS_MACC_PERIPH_BUS_WREADY, s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0) => s_axi_HLS_MACC_PERIPH_BUS_WSTRB(3 downto 0), s_axi_HLS_MACC_PERIPH_BUS_WVALID => s_axi_HLS_MACC_PERIPH_BUS_WVALID ); end STRUCTURE;
mit
f228dc0de06101bcb52ba227d53c1dba
0.521462
2.55479
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_rst_ps7_0_49M_0/synth/gcd_zynq_snick_rst_ps7_0_49M_0.vhd
1
8,154
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_12; USE proc_sys_reset_v5_0_12.proc_sys_reset; ENTITY gcd_zynq_snick_rst_ps7_0_49M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END gcd_zynq_snick_rst_ps7_0_49M_0; ARCHITECTURE gcd_zynq_snick_rst_ps7_0_49M_0_arch OF gcd_zynq_snick_rst_ps7_0_49M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF gcd_zynq_snick_rst_ps7_0_49M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF gcd_zynq_snick_rst_ps7_0_49M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2018.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF gcd_zynq_snick_rst_ps7_0_49M_0_arch : ARCHITECTURE IS "gcd_zynq_snick_rst_ps7_0_49M_0,proc_sys_reset,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF gcd_zynq_snick_rst_ps7_0_49M_0_arch: ARCHITECTURE IS "gcd_zynq_snick_rst_ps7_0_49M_0,proc_sys_reset,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END gcd_zynq_snick_rst_ps7_0_49M_0_arch;
mit
a1563366dbd680758c41e1142c007e16
0.72909
3.460951
false
false
false
false
MartinCura/SistDig-TP4
src/uart/receive.vhd
1
3,515
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity receive is generic ( NDBits : natural := 8 ); port ( clk : in std_logic; rst : in std_logic; Rx : in std_logic; Dout : out std_logic_vector(NDBits-1 downto 0); RxErr : out std_logic; RxRdy : out std_logic; Top16 : in std_logic; ClrDiv : out std_logic; TopRx : in std_logic ); end; architecture arch of receive is signal Rx_Reg : std_logic_vector (NDBits-1 downto 0); type t_state is (Idle, Start_Rx, Edge_Rx, Shift_Rx, Stop_Rx, Rx_Ovf); signal RxFsm : t_state; signal RxBitCnt : integer; signal Sig_RxRdy : std_logic; begin RxRdy <= Sig_RxRdy; Rx_FSM: process (rst, clk) begin if rst='1' then Rx_Reg <= (others => '0'); Dout <= (others => '0'); RxBitCnt <= 0; RxFSM <= Idle; Sig_RxRdy <= '0'; ClrDiv <= '0'; RxErr <= '0'; elsif rising_edge(clk) then ClrDiv <= '0'; -- default value -- reset error when a word has been received Ok: if Sig_RxRdy='1' then RxErr <= '0'; Sig_RxRdy <= '0'; end if; case RxFSM is when Idle => -- wait on start bit RxBitCnt <= 0; if Top16='1' then if Rx='0' then RxFSM <= Start_Rx; ClrDiv <='1'; -- Synchronize the divisor end if; -- else false start, stay in Idle end if; when Start_Rx => -- wait on first data bit if TopRx = '1' then if Rx='1' then -- framing error RxFSM <= Rx_OVF; report "Start bit error." severity note; else RxFSM <= Edge_Rx; end if; end if; when Edge_Rx => -- should be near Rx edge if TopRx = '1' then RxFSM <= Shift_Rx; if RxBitCnt = NDbits then RxFSM <= Stop_Rx; else RxFSM <= Shift_Rx; end if; end if; when Shift_Rx => -- Sample data ! if TopRx = '1' then RxBitCnt <= RxBitCnt + 1; -- shift right : Rx_Reg <= Rx & Rx_Reg (Rx_Reg'high downto 1); RxFSM <= Edge_Rx; end if; when Stop_Rx => -- during Stop bit if TopRx = '1' then Dout <= Rx_reg; Sig_RxRdy <='1'; RxFSM <= Idle; -- assert (debug < 1) report "Character received in decimal is : " & integer'image(to_integer(unsigned(Rx_Reg))) severity note; end if; when Rx_OVF => -- Overflow / Error RxErr <= '1'; if Rx='1' then RxFSM <= Idle; end if; end case; end if; end process; end;
gpl-3.0
f2c23a6ad1c5c3771b32b3f5cc3ba6dc
0.386913
4.848276
false
false
false
false
astoria-d/super-duper-nes
duper_cartridge/prg_rom.vhd
1
3,400
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.conv_integer; use ieee.std_logic_arith.conv_std_logic_vector; entity prg_rom is port ( pi_base_clk : in std_logic; pi_ce_n : in std_logic; pi_oe_n : in std_logic; pi_addr : in std_logic_vector (14 downto 0); po_data : out std_logic_vector (7 downto 0) ); end prg_rom; architecture rtl of prg_rom is --PROG ROM is 32k --constant PROM_SIZE : integer := 15; --prom size is reduced to 8kb. constant PROM_SIZE : integer := 13; subtype rom_data is std_logic_vector (7 downto 0); type rom_array is array (0 to 2**PROM_SIZE - 1) of rom_data; ----for ModelSim environment from here --impure function rom_fill return rom_array is --type binary_file is file of character; --FILE nes_file : binary_file OPEN read_mode IS "../duper-rom.nes" ; --variable read_data : character; --variable i : integer; --variable ret : rom_array; --begin -- --skip first 16 bit data(NES cardridge header part.) -- for i in 0 to 15 loop -- read(nes_file, read_data); -- end loop; -- for i in ret'range loop -- read(nes_file, read_data); -- ret(i) := -- conv_std_logic_vector(character'pos(read_data), 8); -- end loop; -- return ret; --end rom_fill; -- ----itinialize with the rom_fill function. --signal p_rom : rom_array := rom_fill; ----ModelSim environment ends here --for Quartus II environment signal p_rom : rom_array; attribute ram_init_file : string; attribute ram_init_file of p_rom : signal is "sample1-prg-8k.hex"; signal reg_out_n : std_logic; begin p : process (pi_base_clk) begin if (rising_edge(pi_base_clk)) then if (pi_ce_n = '0' and pi_oe_n = '0') then po_data <= p_rom(conv_integer(pi_addr(PROM_SIZE - 1 downto 0))); else po_data <= (others => 'Z'); end if; end if; end process; end rtl; --------------------------------------------------- --------------------------------------------------- --------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.conv_integer; entity chr_rom is port ( pi_base_clk : in std_logic; pi_ce_n : in std_logic; pi_oe_n : in std_logic; pi_addr : in std_logic_vector (12 downto 0); po_data : out std_logic_vector (7 downto 0) ); end chr_rom; architecture rtl of chr_rom is --constant CROM_SIZE : integer := 13; constant CROM_SIZE : integer := 12; subtype rom_data is std_logic_vector (7 downto 0); type rom_array is array (0 to 2**CROM_SIZE - 1) of rom_data; --for Quartus II environment signal p_rom : rom_array; attribute ram_init_file : string; attribute ram_init_file of p_rom : signal is "sample1-chr-4k.hex"; begin p : process (pi_base_clk) begin if (rising_edge(pi_base_clk)) then if (pi_ce_n = '0' and pi_oe_n = '0') then po_data <= p_rom(conv_integer(pi_addr(CROM_SIZE - 1 downto 0))); else po_data <= (others => 'Z'); end if; end if; end process; end rtl;
apache-2.0
dc70990914042060773397f435e70e5b
0.541471
3.235014
false
false
false
false
kuba-moo/VHDL-lib
freq_generator.vhd
1
1,800
-- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- -- Copyright (C) 2014 Jakub Kicinski <[email protected]> library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.globals.all; -- Generate '1' on @Output with given @FREQUENCY entity freq_generator is generic (FREQUENCY : integer; -- target freq CLK_FREQUENCY : integer := FPGA_CLK_FREQ); port (Clk : in std_logic; Rst : in std_logic; Output : out std_logic); end freq_generator; -- Operation: -- Calculate how many clocks must pass and count to that value architecture Behavioral of freq_generator is constant CLK_MAX : integer := CLK_FREQUENCY/FREQUENCY; -- 100 MHz signal counter : integer range 0 to CLK_MAX - 1; begin logi : process (Clk, Rst) is begin if rising_edge(Clk) then Output <= '0'; counter <= counter + 1; if counter + 1 = CLK_MAX then Output <= '1'; counter <= 0; end if; if Rst = '1' then counter <= 0; end if; end if; end process logi; end Behavioral;
gpl-3.0
d628f5330cffdb977d1f30a068a4065e
0.639444
3.991131
false
false
false
false
MartinCura/SistDig-TP4
old/rotador/cordic_lib.vhd
1
5,126
library ieee; use ieee.std_logic_1164.all; ---library work; ---use work.float_pkg.all; --library ieee_proposed; --use ieee_proposed.float_pkg.all; library floatfixlib; use floatfixlib.float_pkg.all; -- -- Para usar: -- library work; -- use work.cordic_lib.all; package cordic_lib is constant N_PF : natural := 32; constant N_BITS_DIR : natural := 10; subtype t_float is float32; subtype t_coordenada is t_float; --- := CERO; -- tipo coordenada type t_pos is array (1 to 3) of t_coordenada; -- tipo posición 3D (x,y,z) type t_vec is array (1 to 2) of t_coordenada; -- tipo posición 2D (x,y) type t_dir is array (1 to 2) of std_logic_vector(N_BITS_DIR-1 downto 0); -- tipo dirección en memoria ---float32 es 23 a -8, que no cause problemas... type t_pos_mem is array (1 to 3) of std_logic_vector(15 downto 0); -- tipo de posición 3D (x,y,z) tal como son recibidas y guardadas en memoria interna constant PI_PF : t_float := "01000000010010010000111111011011"; constant HALF_PI_PF : t_float := "00111111110010010000111111011011"; constant CERO : t_float := "00000000000000000000000000000000"; -- Firma de función cordic, para que pueda ser llamada function cordic (vector : t_vec; beta : t_float) return t_vec; function cordic (pos : t_pos; beta : t_float) return t_pos; end package cordic_lib; package body cordic_lib is -- Función ayuda: si recibe t_pos, rota en (x) [o sea, rota (y,z)] y devuelve los valores girados en (x,y) function cordic (pos : t_pos; beta : t_float) return t_pos is variable vec : t_vec; variable ret : t_pos := (others => CERO); begin vec(1) := pos(2); vec(2) := pos(3); vec := cordic(vec, beta); ret(1) := vec(1); ret(2) := vec(2); return ret; end function; -- Funciôn CORDIC: rotar vector 2D en el plano con ángulo beta (en radianes) function cordic (vector : t_vec; beta : t_float) return t_vec is constant P : natural := 24; -- Cantidad de iteraciones, que determina la precisión type T_ANGLES is array (0 to 27) of real; constant ANGLES : T_ANGLES := ( -- 28 primeros valores de atan(2^-i) 0.785398163397448279, 0.463647609000806094, 0.244978663126864143, 0.124354994546761438, 0.062418809995957350, 0.031239833430268277, 0.015623728620476831, 0.007812341060101111, 0.003906230131966972, 0.001953122516478819, 0.000976562189559319, 0.000488281211194898, 0.000244140620149362, 0.000122070311893670, 0.000061035156174209, 0.000030517578115526, 0.000015258789061316, 0.000007629394531102, 0.000003814697265606, 0.000001907348632810, 0.000000953674316406, 0.000000476837158203, 0.000000238418579102, 0.000000119209289551, 0.000000059604644775, 0.000000029802322388, 0.000000014901161194, 0.000000007450580597 ); type T_KVALUES is array (0 to 25) of real; constant K_VALUES: T_KVALUES := ( -- 26 primeros cumprod(1 ./ abs(1 + 1j*2.^(-(0:25)))) 0.707106781186547462, 0.632455532033675771, 0.613571991077896284, 0.608833912517752429, 0.607648256256168140, 0.607351770141295932, 0.607277644093526026, 0.607259112298892734, 0.607254479332562269, 0.607253321089875175, 0.607253031529134346, 0.607252959138944837, 0.607252941041397154, 0.607252936517010178, 0.607252935385913406, 0.607252935103139269, 0.607252935032445706, 0.607252935014772288, 0.607252935010353934, 0.607252935009249373, 0.607252935008973260, 0.607252935008904204, 0.607252935008886885, 0.607252935008882666, 0.607252935008881555, 0.607252935008881223 ); variable v, v_aux : t_vec := vector; variable sigma : integer := 1; variable angle_i : t_float := to_float(ANGLES(0)); variable Kn : t_float; variable beta_i : t_float := beta; begin if (beta_i < -PI_PF/2 or beta_i > PI_PF/2) then if (beta_i < 0) then v := cordic(vector, beta_i + PI_PF); else v := cordic(vector, beta_i - PI_PF); end if; v(1) := -1 * v(1); v(2) := -1 * v(2); return v; end if; for i in 0 to P-1 loop if (i > (ANGLES'length - 1)) then angle_i := angle_i / 2; -- Si superé la tabla, aproximo else angle_i := to_float(ANGLES(i)); -- Si no, tabla end if; if (beta_i < 0) then sigma := -1; else sigma := 1; end if; v_aux(1) := v(1) - sigma * (v(2) / 2**(i)); --- Cambié desde * 2**(-i) v_aux(2) := sigma * (v(1) / 2**(i)) + v(2); --- Same v := v_aux; -- Actualizo ángulo beta_i faltante beta_i := beta_i - sigma * angle_i; end loop; if (P > K_VALUES'length) then Kn := to_float(K_VALUES(K_VALUES'length - 1)); else Kn := to_float(K_VALUES(P - 1)); end if; -- Ajusto magnitud del vector for i in 1 to 2 loop v(i) := Kn * v(i); end loop; return v; end function; end package body cordic_lib;
gpl-3.0
365d31fc6d4b87965bc09533d2fb9f5c
0.622605
2.894171
false
false
false
false
ls1intum/ArTEMiS
src/main/resources/templates/vhdl/solution/verzoegerung_tb.vhd
2
1,374
library ieee; use ieee.std_logic_1164.all; entity verzoegerung_tb is end verzoegerung_tb; architecture behavior of verzoegerung_tb is component verzoegerung port( CLK, START : in std_logic; STOP : in std_logic; -- Aufgabe 2 ALARM : out std_logic ); end component; signal START : std_logic := '0'; signal STOP : std_logic := '0'; signal CLK : std_logic := '0'; signal ALARM : std_logic; constant clk_period : time := 1 sec; begin uut: verzoegerung port map (START => START, STOP => STOP, CLK => CLK, ALARM => ALARM ); p0 :process begin CLK <= '0'; wait for clk_period/2; CLK <= '1'; wait for clk_period/2; end process; p1: process begin wait for 2 * clk_period; START <= '1'; wait for clk_period; wait for clk_period; wait for clk_period; wait for clk_period; wait for clk_period; wait for clk_period; START <= '0'; wait for clk_period; START <= '1'; wait for clk_period; wait for clk_period; STOP <= '1'; wait for clk_period; wait for clk_period; wait for clk_period; wait for clk_period; end process; end;
mit
aeb1da8d3f61c559043436b9146d771b
0.513828
3.764384
false
false
false
false
MartinCura/SistDig-TP4
src/ctrl_global.vhd
1
5,024
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity global_ctrl is generic ( Nangle : natural := 16 ); port ( clock : in std_logic; write_rst_i: in std_logic; read_rst_i : in std_logic; sw_x_pos, sw_x_neg: in std_logic; sw_y_pos, sw_y_neg: in std_logic; sw_z_pos, sw_z_neg: in std_logic; delta_angle: in std_logic_vector(Nangle-1 downto 0); alfa, beta, gama: out std_logic_vector(Nangle-1 downto 0); clear_reset, clear_enable: out std_logic; clear_stop: in std_logic; read_start: out std_logic; read_stop: in std_logic; read_reset_out, write_reset_out: out std_logic; vga_start, vga_stop: in std_logic ); end; architecture global_ctrl_arq of global_ctrl is type t_estado is (IDLE, CLEARING, READING, REFRESHING); signal estado : t_estado := IDLE; type t_subestado is (WAITING, REFRESHING); signal refresh_subestado : t_subestado := WAITING; signal ctrl_alfa, ctrl_beta, ctrl_gama : std_logic_vector(1 downto 0) := (others => '0'); signal alfa_aux, beta_aux, gama_aux: std_logic_vector(Nangle-1 downto 0) := (others => '0'); signal delta_alfa, delta_beta, delta_gama: std_logic_vector(Nangle-1 downto 0) := (others => '0'); signal minus_delta_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0'); signal button_down : std_logic := '0'; begin button_down <= (sw_x_pos or sw_x_neg or sw_y_pos or sw_y_neg or sw_z_pos or sw_z_neg or write_rst_i or read_rst_i); --button_down <= ( (sw_x_pos XOR sw_x_neg) OR (sw_y_pos XOR sw_y_neg) OR (sw_z_pos XOR sw_z_neg) -- OR write_rst_i OR read_rst_i ); clear_enable <= '1' when (estado = CLEARING) else '0'; read_reset_out <= '1' when (estado = CLEARING) else '0'; read_start <= '1' when (estado = READING) else '0'; write_reset_out <= write_rst_i; process(clock, button_down) begin if rising_edge(clock) then case estado is when IDLE => refresh_subestado <= WAITING; if button_down = '1' then estado <= CLEARING; clear_reset <= '0'; end if; -- Borro la memoria de video when CLEARING => if clear_stop = '1' then clear_reset <= '1'; estado <= READING; end if; -- Leo los nuevos datos when READING => clear_reset <= '0'; if read_stop = '1' then estado <= REFRESHING; end if; -- Espero a que refresque la pantalla con los nuevos datos leídos when REFRESHING => clear_reset <= '0'; case refresh_subestado is when WAITING => if vga_start = '1' then refresh_subestado <= REFRESHING; -- else refresh_subestado <= WAITING; end if; when REFRESHING => if vga_stop = '1' then estado <= IDLE; refresh_subestado <= WAITING; -- else -- refresh_subestado <= REFRESHING; end if; end case; end case; end if; end process; -- Ángulos -- Ctrl +/- (selector del mux) ctrl_alfa <= sw_x_pos & sw_x_neg; ctrl_beta <= sw_y_pos & sw_y_neg; ctrl_gama <= sw_z_pos & sw_z_neg; -- Menos delta (-delta) minus_delta_angle <= std_logic_vector(unsigned(not delta_angle) + 1); -- Mux delta_alfa <= delta_angle when ctrl_alfa = "10" else minus_delta_angle when ctrl_alfa = "01" else (others => '0'); delta_beta <= delta_angle when ctrl_beta = "10" else minus_delta_angle when ctrl_beta = "01" else (others => '0'); delta_gama <= delta_angle when ctrl_gama = "10" else minus_delta_angle when ctrl_gama = "01" else (others => '0'); alfa <= alfa_aux; beta <= beta_aux; gama <= gama_aux; -- Acumulador de ángulos process(clock, estado) begin if rising_edge(clock) then if estado = IDLE then alfa_aux <= std_logic_vector( unsigned(alfa_aux) + unsigned(delta_alfa) ); beta_aux <= std_logic_vector( unsigned(beta_aux) + unsigned(delta_beta) ); gama_aux <= std_logic_vector( unsigned(gama_aux) + unsigned(delta_gama) ); end if; end if; end process; end;
gpl-3.0
62b801ca3a6d09507fec0da193809dd1
0.490341
3.755423
false
false
false
false
jakubcabal/uart-for-fpga
examples/loopback/uart_loopback_cyc1000.vhd
2
2,402
-------------------------------------------------------------------------------- -- PROJECT: SIMPLE UART FOR FPGA -------------------------------------------------------------------------------- -- AUTHORS: Jakub Cabal <[email protected]> -- LICENSE: The MIT License, please read LICENSE file -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- UART LOOPBACK EXAMPLE TOP MODULE FOR CYC1000 BOARD -- ================================================== -- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!! -- OTHER PARAMETERS CAN BE SET USING GENERICS. entity UART_LOOPBACK_CYC1000 is Generic ( CLK_FREQ : integer := 12e6; -- set system clock frequency in Hz BAUD_RATE : integer := 115200; -- baud rate value PARITY_BIT : string := "none"; -- legal values: "none", "even", "odd", "mark", "space" USE_DEBOUNCER : boolean := True -- enable/disable debouncer ); Port ( CLK_12M : in std_logic; -- system clock 12 MHz RST_BTN_N : in std_logic; -- low active reset button -- UART INTERFACE UART_TXD : out std_logic; UART_RXD : in std_logic ); end entity; architecture RTL of UART_LOOPBACK_CYC1000 is signal rst_btn : std_logic; signal reset : std_logic; signal data : std_logic_vector(7 downto 0); signal valid : std_logic; begin rst_btn <= not RST_BTN_N; rst_sync_i : entity work.RST_SYNC port map ( CLK => CLK_12M, ASYNC_RST => rst_btn, SYNCED_RST => reset ); uart_i: entity work.UART generic map ( CLK_FREQ => CLK_FREQ, BAUD_RATE => BAUD_RATE, PARITY_BIT => PARITY_BIT, USE_DEBOUNCER => USE_DEBOUNCER ) port map ( CLK => CLK_12M, RST => reset, -- UART INTERFACE UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- USER DATA INPUT INTERFACE DIN => data, DIN_VLD => valid, DIN_RDY => open, -- USER DATA OUTPUT INTERFACE DOUT => data, DOUT_VLD => valid, FRAME_ERROR => open, PARITY_ERROR => open ); end architecture;
mit
0a2fc136cb7f2ccfa3900fafdff77173
0.490425
4.148532
false
false
false
false
MartinCura/SistDig-TP4
src/video_ram/clear_video_ram.vhd
1
1,328
library ieee; use ieee.std_logic_1164.all; entity clear_video_ram is generic( N_bits_row: natural := 2; N_bits_col: natural := 2; N_ROWS: natural := 2; N_COLS: natural := 2 ); port( clock: in std_logic; reset: in std_logic; enable: in std_logic; row_counter: out std_logic_vector(N_bits_row-1 downto 0); col_counter: out std_logic_vector(N_bits_col-1 downto 0); carry_out: out std_logic ); end; architecture clear_video_ram_arch of clear_video_ram is signal row_enable_aux : std_logic := '0'; signal row_enable : std_logic := '0'; begin col_counter_inst: entity work.counter generic map( N_bits => N_bits_col, MAX_COUNT => N_COLS-1 ) port map( clock => clock, reset => reset, enable => enable, counter_output => col_counter, carry_out => row_enable_aux ); -- Contador de filas row_enable <= enable AND row_enable_aux; row_counter_inst: entity work.counter generic map( N_bits => N_bits_row, MAX_COUNT => N_ROWS-1 ) port map( clock => clock, reset => reset, enable => row_enable, counter_output => row_counter, carry_out => carry_out ); end clear_video_ram_arch;
gpl-3.0
cc231dda8918195cf92fee1dd7a15dc9
0.559488
3.449351
false
false
false
false
Feuerwerk/fpgaNES
master_reconfig.vhd
1
6,755
-- megafunction wizard: %PLL Reconfig Intel FPGA IP v18.0% -- GENERATION: XML -- master_reconfig.vhd -- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity master_reconfig is generic ( ENABLE_BYTEENABLE : boolean := false; BYTEENABLE_WIDTH : integer := 4; RECONFIG_ADDR_WIDTH : integer := 6; RECONFIG_DATA_WIDTH : integer := 32; reconf_width : integer := 64; WAIT_FOR_LOCK : boolean := true ); port ( mgmt_clk : in std_logic := '0'; -- mgmt_clk.clk mgmt_reset : in std_logic := '0'; -- mgmt_reset.reset mgmt_waitrequest : out std_logic; -- mgmt_avalon_slave.waitrequest mgmt_read : in std_logic := '0'; -- .read mgmt_write : in std_logic := '0'; -- .write mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata mgmt_address : in std_logic_vector(5 downto 0) := (others => '0'); -- .address mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll.reconfig_to_pll reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => '0') -- reconfig_from_pll.reconfig_from_pll ); end entity master_reconfig; architecture rtl of master_reconfig is component altera_pll_reconfig_top is generic ( device_family : string := ""; ENABLE_MIF : boolean := false; MIF_FILE_NAME : string := ""; ENABLE_BYTEENABLE : boolean := false; BYTEENABLE_WIDTH : integer := 4; RECONFIG_ADDR_WIDTH : integer := 6; RECONFIG_DATA_WIDTH : integer := 32; reconf_width : integer := 64; WAIT_FOR_LOCK : boolean := true ); port ( mgmt_clk : in std_logic := 'X'; -- clk mgmt_reset : in std_logic := 'X'; -- reset mgmt_waitrequest : out std_logic; -- waitrequest mgmt_read : in std_logic := 'X'; -- read mgmt_write : in std_logic := 'X'; -- write mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata mgmt_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_from_pll mgmt_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable ); end component altera_pll_reconfig_top; begin master_reconfig_inst : component altera_pll_reconfig_top generic map ( device_family => "Cyclone V", ENABLE_MIF => false, MIF_FILE_NAME => "", ENABLE_BYTEENABLE => ENABLE_BYTEENABLE, BYTEENABLE_WIDTH => BYTEENABLE_WIDTH, RECONFIG_ADDR_WIDTH => RECONFIG_ADDR_WIDTH, RECONFIG_DATA_WIDTH => RECONFIG_DATA_WIDTH, reconf_width => reconf_width, WAIT_FOR_LOCK => WAIT_FOR_LOCK ) port map ( mgmt_clk => mgmt_clk, -- mgmt_clk.clk mgmt_reset => mgmt_reset, -- mgmt_reset.reset mgmt_waitrequest => mgmt_waitrequest, -- mgmt_avalon_slave.waitrequest mgmt_read => mgmt_read, -- .read mgmt_write => mgmt_write, -- .write mgmt_readdata => mgmt_readdata, -- .readdata mgmt_address => mgmt_address, -- .address mgmt_writedata => mgmt_writedata, -- .writedata reconfig_to_pll => reconfig_to_pll, -- reconfig_to_pll.reconfig_to_pll reconfig_from_pll => reconfig_from_pll, -- reconfig_from_pll.reconfig_from_pll mgmt_byteenable => "0000" -- (terminated) ); end architecture rtl; -- of master_reconfig -- Retrieval info: <?xml version="1.0"?> --<!-- -- Generated by Altera MegaWizard Launcher Utility version 1.0 -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ -- Copyright (C) 1991-2018 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> -- Retrieval info: <instance entity-name="altera_pll_reconfig" version="18.0" > -- Retrieval info: <generic name="device_family" value="Cyclone V" /> -- Retrieval info: <generic name="ENABLE_MIF" value="false" /> -- Retrieval info: <generic name="MIF_FILE_NAME" value="" /> -- Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" /> -- Retrieval info: </instance> -- IPFS_FILES : master_reconfig.vho -- RELATED_FILES: master_reconfig.vhd, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
gpl-3.0
5d04948f6c774a31c5ba0717d1d69552
0.574093
3.849003
false
true
false
false
MartinCura/SistDig-TP4
old/VGActrl.vhd
1
6,285
-------------------------------------------------------------------------- -- Modulo: Controlador VGA -- Descripción: -- Autor: Sistemas Digitales (66.17) -- Universidad de Buenos Aires - Facultad de Ingeniería -- www.campus.fi.uba.ar -- Fecha: 16/04/13 -------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity vga_ctrl is port ( mclk: in std_logic; red_i: in std_logic; grn_i: in std_logic; blu_i: in std_logic; hs: out std_logic; vs: out std_logic; red_o: out std_logic_vector(2 downto 0); grn_o: out std_logic_vector(2 downto 0); blu_o: out std_logic_vector(1 downto 0); pixel_row: out std_logic_vector(9 downto 0); pixel_col: out std_logic_vector(9 downto 0) ); attribute loc: string; -- Mapeo de pines para el kit Nexys 2 (spartan 3E) -- attribute loc of mclk: signal is "B8"; -- attribute loc of red_i: signal is "K18"; -- attribute loc of grn_i: signal is "H18"; -- attribute loc of blu_i: signal is "G18"; -- attribute loc of hs: signal is "T4"; -- attribute loc of vs: signal is "U3"; -- attribute loc of red_o: signal is "R8 T8 R9"; -- attribute loc of grn_o: signal is "P6 P8 N8"; -- attribute loc of blu_o: signal is "U4 U5"; -- Mapeo de pines para el kit spartan 3E -- attribute loc of mclk: signal is "C9"; -- attribute loc of red_i: signal is "H18"; -- attribute loc of grn_i: signal is "L14"; -- attribute loc of blu_i: signal is "L13"; -- attribute loc of hs: signal is "F15"; -- attribute loc of vs: signal is "F14"; -- attribute loc of red_o: signal is "H14"; -- attribute loc of grn_o: signal is "H15"; -- attribute loc of blu_o: signal is "G15"; -- Mapeo de pines para el kit spartan 3 -- attribute loc of mclk: signal is "T9"; -- attribute loc of red_i: signal is "K13"; -- attribute loc of grn_i: signal is "K14"; -- attribute loc of blu_i: signal is "J13"; -- attribute loc of hs: signal is "R9"; -- attribute loc of vs: signal is "T10"; -- attribute loc of red_o: signal is "R12"; -- attribute loc of grn_o: signal is "T12"; -- attribute loc of blu_o: signal is "R11"; end vga_ctrl; architecture vga_ctrl_arq of vga_ctrl is -- Numero de pixeles en una linea horizontal (800) constant hpixels: unsigned(9 downto 0) := "1100100000"; -- Numero de lineas horizontales en el display (521) constant vlines: unsigned(9 downto 0) := "1000001001"; constant hbp: unsigned(9 downto 0) := "0010010000"; -- Back porch horizontal (144) constant hfp: unsigned(9 downto 0) := "1100010000"; -- Front porch horizontal (784) constant vbp: unsigned(9 downto 0) := "0000011111"; -- Back porch vertical (31) constant vfp: unsigned(9 downto 0) := "0111111111"; -- Front porch vertical (511) -- Contadores (horizontal y vertical) signal hc, vc: unsigned(9 downto 0) := (others => '0'); -- Flag para obtener una habilitación cada dos ciclos de clock signal clkdiv_flag: std_logic := '0'; -- Señal para habilitar la visualización de datos signal vidon: std_logic := '0'; -- Señal para habilitar el contador vertical signal vsenable: std_logic := '0'; begin -- División de la frecuencia del reloj process(mclk) begin if rising_edge(mclk) then clkdiv_flag <= not clkdiv_flag; end if; end process; -- Contador horizontal process(mclk) begin if rising_edge(mclk) then if clkdiv_flag = '1' then if hc = hpixels then hc <= (others => '0'); -- El cont horiz se resetea cuando alcanza la cuenta máxima de pixeles vsenable <= '1'; -- Habilitación del cont vert else hc <= hc + 1; -- Incremento del cont horiz vsenable <= '0'; -- El cont vert se mantiene deshabilitado end if; end if; end if; end process; -- Contador vertical process(mclk) begin if rising_edge(mclk) then if clkdiv_flag = '1' then -- Flag que habilita la operaci�n una vez cada dos ciclos (25 MHz) if vsenable = '1' then -- Cuando el cont horiz llega al m�ximo de su cuenta habilita al cont vert if vc = vlines then vc <= (others => '0'); -- El cont vert se resetea cuando alcanza la cantidad máxima de lineas else vc <= vc + 1; -- Incremento del cont vert end if; end if; end if; end if; end process; -- hs <= '1' when (hc(9 downto 7) = "000") else '0'; -- vs <= '1' when (vc(9 downto 1) = "000000000") else '0'; hs <= '1' when (hc < "0001100001") else '0'; -- Generación de la señal de sincronismo horizontal vs <= '1' when (vc < "0000000011") else '0'; -- Generación de la señal de sincronismo vertical pixel_col <= std_logic_vector(hc - 144) when (vidon = '1') else std_logic_vector(hc); pixel_row <= std_logic_vector(vc - 31) when (vidon = '1') else std_logic_vector(vc); ---Modificación para probar: ---TESTEAR -- Resto 1 para que cuente desde fila 0 y columna 0 (si no empieza en 1); y que cuando no escribe se quede en 0. --pixel_col <= std_logic_vector(hc - 144 - 1) when (vidon = '1') else (others => '0'); --pixel_row <= std_logic_vector(vc - 31 - 1) when (vidon = '1') else (others => '0'); -- Habilitación de la salida de datos por el display cuando se encuentra entre los porches vidon <= '1' when (((hc < hfp) and (hc > hbp)) and ((vc < vfp) and (vc > vbp))) else '0'; -- Pinta la pantalla del color formado por la combinación de las entradas red_i, grn_i y blu_i (switches) red_o <= (others => '1') when (red_i = '1' and vidon = '1') else (others => '0'); grn_o <= (others => '1') when (grn_i = '1' and vidon = '1') else (others => '0'); blu_o <= (others => '1') when (blu_i = '1' and vidon = '1') else (others => '0'); end vga_ctrl_arq; --- Opcional: Agregar un modo arcoiris, donde va cambiando el color de la salida
gpl-3.0
a1bb6872f710cb7915741504944fd078
0.579183
3.408052
false
false
false
false
Feuerwerk/fpgaNES
i2c_master.vhd
1
6,094
/* This file is part of fpgaNES. fpgaNES is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. fpgaNES is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with fpgaNES. If not, see <http://www.gnu.org/licenses/>. */ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.common.all; entity i2c_master is generic ( CLK_SPEED : integer := 50_000_000; WAIT_TIMEOUT : integer := 100 ); port ( i_clk : in std_logic; i_reset_n : in std_logic := '1'; i_enable : in std_logic := '0'; i_active : in std_logic := '0'; i_addr : in std_logic_vector(7 downto 0) := x"00"; i_cmd : in std_logic_vector(7 downto 0) := x"00"; i_data : in std_logic_vector(7 downto 0) := x"00"; i_read_not_write : std_logic := '1'; io_sda : inout std_logic; io_scl : inout std_logic; o_q : out std_logic_vector(7 downto 0); o_busy : out std_logic; o_ack_error : out std_logic ); end i2c_master; architecture behavioral of i2c_master is component i2c is generic ( input_clk : integer := 50_000_000; bus_clk : integer := 400_000 ); port ( i_clk : in std_logic; i_reset_n : in std_logic; i_enable : in std_logic; i_flag : in std_logic; i_start_condition : in std_logic; i_stop_condition : in std_logic; i_enable_ack : in std_logic; i_data : in std_logic_vector(7 downto 0); io_sda : inout std_logic; io_scl : inout std_logic; o_q : out std_logic_vector(7 downto 0); o_status : out std_logic_vector(4 downto 0); o_busy : out std_logic; o_ack_error : out std_logic ); end component; type state_t is (idle, start_read, addr_for_read1, cmd_for_read, restart, addr_for_read2, read_data, start_write, addr_for_write, cmd_for_write, write_data, wait_after_write, ready, stopping); signal s_state : state_t := idle; signal s_start : std_logic := '0'; signal s_stop : std_logic := '0'; signal s_busy : std_logic; signal s_addr : std_logic_vector(6 downto 0) := 7x"00"; signal s_cmd : std_logic_vector(7 downto 0) := x"00"; signal s_data : std_logic_vector(7 downto 0) := x"00"; signal s_buffer : std_logic_vector(7 downto 0) := x"00"; signal s_transition : boolean; signal s_wait_counter : integer range 0 to WAIT_TIMEOUT := 0; signal s_cmd_enable : std_logic; signal s_enable : std_logic := '0'; begin i2c_cmp : i2c generic map ( input_clk => CLK_SPEED ) port map ( i_clk => i_clk, i_reset_n => i_reset_n, i_enable => '1', i_flag => s_cmd_enable, i_start_condition => s_start, i_stop_condition => s_stop, i_enable_ack => '0', i_data => s_buffer, io_sda => io_sda, io_scl => io_scl, o_q => o_q, o_busy => s_busy, o_ack_error => o_ack_error ); process (i_clk) begin if rising_edge(i_clk) then s_enable <= '0'; if i_reset_n = '0' then s_state <= idle; s_wait_counter <= 0; s_addr <= 7x"00"; s_cmd <= x"00"; s_data <= x"00"; s_buffer <= x"00"; s_start <= '0'; else if (s_wait_counter /= 0) then s_wait_counter <= s_wait_counter - 1; end if; if s_transition then case s_state is when idle => if i_enable = '1' then if i_active = '1' then if i_read_not_write = '1' then s_state <= start_read; else s_state <= start_write; end if; s_addr <= i_addr(7 downto 1); s_cmd <= i_cmd; s_data <= i_data; s_start <= '1'; s_enable <= '1'; end if; end if; when ready => if i_enable = '1' then if i_active = '1' then if i_read_not_write = '1' then s_state <= start_read; else s_state <= start_write; end if; s_addr <= i_addr(7 downto 1); s_cmd <= i_cmd; s_data <= i_data; s_start <= '1'; s_enable <= '1'; else s_stop <= '1'; s_enable <= '1'; s_state <= stopping; end if; end if; when stopping => s_stop <= '0'; s_state <= idle; when start_read => s_start <= '0'; s_buffer <= s_addr & '0'; s_state <= addr_for_read1; s_enable <= '1'; when addr_for_read1 => s_buffer <= s_cmd; s_state <= cmd_for_read; s_enable <= '1'; when cmd_for_read => s_start <= '1'; s_state <= restart; s_enable <= '1'; when restart => s_start <= '0'; s_buffer <= s_addr & '1'; s_state <= addr_for_read2; s_enable <= '1'; when addr_for_read2 => s_state <= read_data; s_enable <= '1'; when read_data => s_state <= ready; when start_write => s_start <= '0'; s_buffer <= s_addr & '0'; s_state <= addr_for_write; s_enable <= '1'; when addr_for_write => s_buffer <= s_cmd; s_state <= cmd_for_write; s_enable <= '1'; when cmd_for_write => s_buffer <= s_data; s_state <= write_data; s_enable <= '1'; when write_data => s_wait_counter <= WAIT_TIMEOUT; -- Nach einem Schreibkommando je 7 ms auf EE2 warten s_state <= wait_after_write; when wait_after_write => if s_wait_counter = 0 then s_state <= ready; end if; end case; end if; end if; end if; end process; s_cmd_enable <= '0' when s_state = wait_after_write else s_enable; s_transition <= (s_wait_counter = 0) when s_state = wait_after_write else (s_busy = '0') and (s_enable = '0'); o_busy <= '0' when (s_state = idle) or (s_state = ready) else '1'; end behavioral;
gpl-3.0
b697224d438f146b199209f2cd27b17b
0.56088
2.792851
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/0141074d64e361c1/design_1_processing_system7_0_2_sim_netlist.vhdl
1
206,286
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 05:33:33 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_2_sim_netlist.vhdl -- Design : design_1_processing_system7_0_2 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "design_1_processing_system7_0_2.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_2.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0"; attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW"; attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"; attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => IRQ_F2P(0), IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;
mit
ae3d8ecd35620f9a942fbfff8640889f
0.639704
2.766711
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/synth/zybo_zynq_design_rst_ps7_0_100M_0.vhd
1
8,190
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_12; USE proc_sys_reset_v5_0_12.proc_sys_reset; ENTITY zybo_zynq_design_rst_ps7_0_100M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END zybo_zynq_design_rst_ps7_0_100M_0; ARCHITECTURE zybo_zynq_design_rst_ps7_0_100M_0_arch OF zybo_zynq_design_rst_ps7_0_100M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zybo_zynq_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF zybo_zynq_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2018.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF zybo_zynq_design_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "zybo_zynq_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF zybo_zynq_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "zybo_zynq_design_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END zybo_zynq_design_rst_ps7_0_100M_0_arch;
mit
c341d75dc9be115c5efd0e3dfa1198ae
0.730281
3.494027
false
false
false
false
MartinCura/SistDig-TP4
old/UART/data_adq/data_capture_module.vhd
1
2,508
--top level para la UART y transfer_unit de 16 bits LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity data_acq_unit is port ( clk : in std_logic; rst : in std_logic; rx : in std_logic; data_out_16bits:out std_logic_vector(15 downto 0); data_ready:out std_logic ); end data_acq_unit; architecture arch of data_acq_unit is component uart generic ( F: natural; baud_rate: natural; num_data_bits: natural ); port ( Rx : in std_logic; Tx : out std_logic; Din : in std_logic_vector(num_data_bits-1 downto 0); StartTx : in std_logic; TxBusy : out std_logic; Dout : out std_logic_vector(num_data_bits-1 downto 0); RxRdy : out std_logic; RxErr : out std_logic; clk : in std_logic; rst : in std_logic ); end component; component data_loader generic ( in_data_bits : natural := 8; --cantidad de bits del dato que entra out_data_bits: natural:=16; -- cant de bits del dato que sale data_midpoint: natural:=8 -- bits/2 del dato que sale ); port( -- clock: in std_logic; reset: in std_logic; data_in: in std_logic_vector(in_data_bits-1 downto 0); data_out: out std_logic_vector(out_data_bits-1 downto 0); RxRdy_in: in std_logic; RxRdy_out: out std_logic ); end component; signal sig_Dout_16: std_logic_vector(15 downto 0); signal sig_Din : std_logic_vector(7 downto 0); signal sig_Dout_UART : std_logic_vector(7 downto 0); signal sig_RxErr : std_logic; signal sig_RxRdy : std_logic; signal sig_RxRdy_loader: std_logic; signal sig_TxBusy : std_logic; signal sig_StartTx: std_logic; signal tx_aux:std_logic; begin -- UART Instanciation : UUT : uart generic map ( F => 50000, baud_rate => 9600, num_data_bits => 8 ) port map ( Rx => rx, Tx => tx_aux, Din => sig_Din, StartTx => sig_StartTx, TxBusy => sig_TxBusy, Dout => sig_Dout_UART, RxRdy => sig_RxRdy, RxErr => open, clk => clk, rst => rst ); UUT3:data_loader generic map ( in_data_bits => 8, --cantidad de bits del dato que entra out_data_bits =>16, -- cant de bits del dato que sale data_midpoint => 8 -- bits/2 del dato que sale ) port map( --clock => clk, reset => rst, data_in => sig_Dout_UART, data_out => data_out_16bits, RxRdy_in =>sig_RxRdy, RxRdy_out => data_ready ); end arch;
gpl-3.0
1ba6cd5bec9f214168faaaa0182c52e5
0.593301
2.950588
false
false
false
false
MartinCura/SistDig-TP4
src/comps/counter.vhd
1
1,178
-- Contador de N bits library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is generic( N_bits : natural := 2; MAX_COUNT : natural := 2 ); port( clock: in std_logic; reset: in std_logic; enable: in std_logic; counter_output: out std_logic_vector(N_bits-1 downto 0); carry_out: out std_logic ); end entity counter; architecture counter_arch of counter is signal counter_aux : unsigned(N_bits-1 downto 0) := (others => '0'); begin counter_output <= std_logic_vector(counter_aux); process(clock, enable, reset) begin -- Reset if reset = '1' then counter_aux <= (others => '0'); carry_out <= '0'; elsif rising_edge(clock) then if enable = '1' then if counter_aux = MAX_COUNT then counter_aux <= (others => '0'); carry_out <= '1'; else counter_aux <= counter_aux + 1; carry_out <= '0'; end if; end if; end if; end process; end counter_arch;
gpl-3.0
29b56333e3239616ee283ac149717764
0.50764
3.875
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0/design_1_rst_ps7_0_50M_0_sim_netlist.vhdl
2
34,722
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 06:23:47 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top design_1_rst_ps7_0_50M_0 -prefix -- design_1_rst_ps7_0_50M_0_ design_1_rst_ps7_0_50M_0_sim_netlist.vhdl -- Design : design_1_rst_ps7_0_50M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0_cdc_sync is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); ext_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end design_1_rst_ps7_0_50M_0_cdc_sync; architecture STRUCTURE of design_1_rst_ps7_0_50M_0_cdc_sync is signal exr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => exr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => ext_reset_in, I1 => mb_debug_sys_rst, O => exr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(1), I2 => p_3_out(2), I3 => \^scndry_out\, I4 => p_3_out(0), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0_cdc_sync_0 is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_rst_ps7_0_50M_0_cdc_sync_0 : entity is "cdc_sync"; end design_1_rst_ps7_0_50M_0_cdc_sync_0; architecture STRUCTURE of design_1_rst_ps7_0_50M_0_cdc_sync_0 is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => p_1_in, I2 => p_2_in, I3 => \^scndry_out\, I4 => asr_lpf(0), O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end design_1_rst_ps7_0_50M_0_upcnt_n; architecture STRUCTURE of design_1_rst_ps7_0_50M_0_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; ext_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); end design_1_rst_ps7_0_50M_0_lpf; architecture STRUCTURE of design_1_rst_ps7_0_50M_0_lpf is signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.design_1_rst_ps7_0_50M_0_cdc_sync port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.design_1_rst_ps7_0_50M_0_cdc_sync_0 port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => dcm_locked, I1 => lpf_exr, I2 => lpf_asr, I3 => Q, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end design_1_rst_ps7_0_50M_0_sequence_psr; architecture STRUCTURE of design_1_rst_ps7_0_50M_0_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.design_1_rst_ps7_0_50M_0_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0090" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9000" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0018" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(0), I2 => seq_cnt(2), I3 => seq_cnt(1), O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0480" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is "1'b1"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of design_1_rst_ps7_0_50M_0_proc_sys_reset : entity is 1; end design_1_rst_ps7_0_50M_0_proc_sys_reset; architecture STRUCTURE of design_1_rst_ps7_0_50M_0_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.design_1_rst_ps7_0_50M_0_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.design_1_rst_ps7_0_50M_0_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_rst_ps7_0_50M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of design_1_rst_ps7_0_50M_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of design_1_rst_ps7_0_50M_0 : entity is "design_1_rst_ps7_0_50M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of design_1_rst_ps7_0_50M_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of design_1_rst_ps7_0_50M_0 : entity is "proc_sys_reset,Vivado 2018.2"; end design_1_rst_ps7_0_50M_0; architecture STRUCTURE of design_1_rst_ps7_0_50M_0 is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b1"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.design_1_rst_ps7_0_50M_0_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;
mit
681d755ec2f0251279070b5a492c43f4
0.581274
2.858719
false
false
false
false
besm6/micro-besm
tests/2901/vhdl/funct_blocks_alg_beh/funct_block_alg_beh2901.vhdl
1
5,799
-------------------------------------------------------------------------------- -- -- AM2901 Benchmark -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Jan 1, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD -- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD -------------------------------------------------------------------------------- use work.types.all; -- some MVL7 functions use work.MVL7_functions.all; -- some MVL7 functions use work.synthesis_types.all; -- some data types ( hints for synthesis) entity a2901 is port ( I : in MVL7_vector(8 downto 0); Aadd, Badd : in integer range 15 downto 0; D : in MVL7_vector(3 downto 0); Y : out MVL7_vector(3 downto 0); RAM0, RAM3, Q0, Q3 : in MVL7; RAM0out, RAM3out, Q0out, Q3out : out MVL7; CLK : in clock; C0 : in MVL7; OEbar : in MVL7; C4, Gbar, Pbar, OVR, F3, F30 : out MVL7); end a2901; architecture a2901 of a2901 is signal RAM : Memory(15 downto 0); signal RE,S : MVL7_vector(3 downto 0); signal A, B : MVL7_vector(3 downto 0); signal Q : MVL7_vector(3 downto 0); signal F : MVL7_vector(3 downto 0); begin ------------------------------------------------------------------------- alu_inputs : block begin A <= RAM(Aadd); B <= RAM(Badd); -- SELECT THE SOURCE OPERANDS FOR ALU. SELECTED OPERANDS ARE "RE" AND "S". with I(2 downto 0) select RE <= A when "000" | "001", "0000" when "010" | "011" | "100", D when others; with I(2 downto 0) select S <= A when "100" | "101", B when "001" | "011", "0000" when "111", Q when others; end block alu_inputs; ------------------------------------------------------------------------- alu : block signal R_ext,S_ext,result,temp_p,temp_g : MVL7_vector(4 downto 0); begin -- TO FACILITATE COMPUTATION OF CARRY-OUT "C4", WE EXTEND THE CHOSEN -- ALU OPERANDS "RE" AND "S" (4 BIT OPERANDS) BY 1 BIT IN THE MSB POSITION. -- THUS THE EXTENDED OPERANDS "R_EXT" AND "S_EXT" (5 BIT OPERANDS) ARE -- FORMED AND ARE USED IN THE ALU OPERATION. THE EXTRA BIT IS SET TO '0' -- INITIALLY. THE ALU'S EXTENDED OUTPUT ( 5 BITS LONG) IS "result". R_ext <= '0' & not(RE) when I(5 downto 3) = "001" else '0' & RE; S_ext <= '0' & not(S) when I(5 downto 3) = "010" else '0' & S; -- SELECT THE FUNCTION FOR ALU. -- IN THE ADD/SUBTRACT OPERATIONS, THE CARRY-INPUT "C0" (1 BIT) IS EXTENDED -- BY 4 BITS ( ALL '0') IN THE MORE SIGNIFICANT BITS TO MATCH ITS LENGTH TO -- THAT OF "R_ext" AND "S_ext". THEN, THESE THREE OPERANDS ARE ADDED. -- ADD/SUBTRACT OPERATIONS ARE DONE ON 2'S COMPLEMENT OPERANDS. with I(5 downto 3) select result <= R_ext + S_ext + ("0000" & C0) when "000" | "001" | "010", R_ext or S_ext when "011", R_ext and S_ext when "100", not(R_ext) and S_ext when "101", R_ext xor S_ext when "110", not( R_ext xor S_ext) when others; -- EVALUATE OTHER ALU OUTPUTS. -- FROM EXTENDED OUTPUT "result" ( 5 BITS), WE OBTAIN THE NORMAL ALU OUTPUT, -- "F" (4 BITS) BY LEAVING OUT THE MSB ( WHICH CORRESPONDS TO CARRY-OUT -- "C4"). -- TO FACILITATE COMPUTATION OF CARRY LOOKAHEAD TERMS "Pbar" AND "Gbar", WE -- COMPUTE INTERMEDIATE TERMS "temp_p" AND "temp_g". F <= result(3 downto 0); OVR <= not (R_ext(3) xor S_ext(3)) and ( R_ext(3) xor result(3) ); C4 <= result(4); temp_p <= R_ext or S_ext; -- R or S may get temp_g <= R_ext and S_ext; -- inverted (sub) Pbar <= not(temp_p(0) and temp_p(1) and temp_p(2) and temp_p(3)); Gbar <= not( temp_g(3) or (temp_p(3) and temp_g(2)) or (temp_p(3) and temp_p(2) and temp_g(1)) or (temp_p(3) and temp_p(2) and temp_p(1) and temp_g(0)) ); F3 <= result(3); F30 <= not(result(3) or result(2) or result(1) or result(0)); end block alu; ------------------------------------------------------------------------- mem : block ( (not clk'stable) and (clk = '1') ) begin -- WRITE TO RAM WITH/WITHOUT SHIFTING. RAM DESTINATIONS ARE -- ADDRESSED BY "Badd". RAM(Badd) <= guarded F when ((not(I(8)) and I(7)) = '1') else RAM3 & F(3 downto 1) when ((I(8) and not(I(7))) = '1') else F(2 downto 0) & RAM0 when ((I(8) and I(7)) = '1') else RAM(Badd); end block mem; ------------------------------------------------------------------------- Q_reg : block ( (not clk'stable) and (clk = '1') ) begin -- WRITE TO Q REGISTER WITH/WITHOUT SHIFTING. Q <= guarded F when (I(8 downto 6) = "000") else Q3 & Q(3 downto 1) when (I(8 downto 6) = "100") else Q(2 downto 0) & Q0 when (I(8 downto 6) = "110") else Q; end block Q_reg; ------------------------------------------------------------------------- output_and_shifter : block begin -- GENERATE DATA OUTPUT "Y" Y <= A when (( I(8 downto 6) = "010") and ( OEbar = '0')) else F when (not(( I(8 downto 6) = "010")) and ( OEbar = '0')) else "ZZZZ"; -- GENERATE BIDIRECTIONAL SHIFTER SIGNALS. RAM0out <= F(0) when ( I(8) = '1') and ( I(7) = '0' ) else 'Z'; RAM3out <= F(3) when ( I(8) = '1') and ( I(7) = '1' ) else 'Z'; Q3out <= Q(3) when ( I(8) = '1') and ( I(7) = '1') else 'Z'; Q0out <= Q(0) when ( I(8) = '1') and ( I(7) = '0') else 'Z'; end block output_and_shifter; ------------------------------------------------------------------------- end a2901;
mit
8616c4bdaaf60b9713d5119e9f1a3c05
0.507329
3.089505
false
false
false
false
Feuerwerk/fpgaNES
soamem.vhd
1
6,688
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: soamem.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ --Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Intel Program License --Subscription Agreement, the Intel Quartus Prime License Agreement, --the Intel FPGA IP License Agreement, or other applicable license --agreement, including, without limitation, that your use is for --the sole purpose of programming logic devices manufactured by --Intel and sold by Intel or its authorized distributors. Please --refer to the applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY soamem IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clken : IN STD_LOGIC := '1'; clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END soamem; ARCHITECTURE SYN OF soamem IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "NORMAL", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone V", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 32, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 5, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, clocken0 => clken, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "1" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" -- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
gpl-3.0
b28810d0acbefc87b3bb9eada06cfff9
0.65924
3.518148
false
false
false
false
gardintrapp/cpu_4004
src/cpu_4004.vhd
1
12,414
--cpu_4004.vhd --- -- --Filename: cpu_4004.vhd --Description: --Author: Oddbjørn Norstrand <[email protected] --Maintainer: Oddbjørn Norstrand <[email protected]> --Created: Sat Dec 15 21:38:10 2012 (+0100) --Version: 0.1 --Last-Updated: Mon Dec 31 16:24:20 2012 (+0100) -- By: oddbjorn -- Update #: 132 --URL: --Keywords: --Compatibility: -- -- --Commentary: -- -- -- -- --Change Log: -- -- -- --This program is free software; you can redistribute it and/or --modify it under the terms of the GNU General Public License as --published by the Free Software Foundation; either version 3, or --(at your option) any later version. -- --This program is distributed in the hope that it will be useful, --but WITHOUT ANY WARRANTY; without even the implied warranty of --MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --General Public License for more details. -- --You should have received a copy of the GNU General Public License --along with this program; see the file COPYING. If not, write to --the Free Software Foundation, Inc., 51 Franklin Street, Fifth --Floor, Boston, MA 02110-1301, USA. -- -- --Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sim_pkg.all; use work.cpu_4004_pkg.all; entity cpu_4004 is generic ( READ_LATENCY : natural := 2); port ( clk : in std_logic; reset_n : in std_logic; cpu_input : in cpu_4004_input_type; cpu_output : out cpu_4004_output_type); end entity cpu_4004; architecture twoproc of cpu_4004 is type state_type is (halted, fetch_addr, fetch_read, decode, decode_two, ex_halt, ex_inc_r0, ex_dec_r0, ex_inc_r1, ex_dec_r1, ex_add_r0_r1, ex_sub_r0_r1, ex_print_r0, ex_jp_if_r0_nz, ex_jp_if_r0_z, ex_load_r0, ex_load_r1, ex_store_r0, ex_store_r1, ex_swap_r0_addr_0, ex_swap_r0_addr_1, ex_swap_r1_addr_0, ex_swap_r1_addr_1, paused); type reg_type is record cpu_input : cpu_4004_input_type; cpu_output : cpu_4004_output_type; state : state_type; cnt : byte; second_ins_byte : boolean; data_not_ins : boolean; data : byte; addr : byte; end record reg_type; signal r, rin : reg_type; begin -- architecture twoproc -- purpose: Main logic -- type : combinational p_comb : process (cpu_input, r) is variable v : reg_type; begin -- process p_comb v := r; --Read inputs v.cpu_input := cpu_input; --Default values v.cpu_output.beep := '0'; v.cpu_output.digit_latch := '0'; v.cpu_output.led_fetch := '0'; v.cpu_output.led_dec := '0'; v.cpu_output.led_exec := '0'; v.cpu_output.mem_wr := '0'; v.cpu_output.mem_rd := '0'; v.cpu_output.halted := '0'; v.cpu_output.running := '1'; v.cpu_output.paused := '0'; --The CPU state machine case r.state is when halted => --Wait for the CPU to be started v.cpu_output.halted := '1'; v.cpu_output.running := '0'; v.cpu_output.paused := '0'; v.second_ins_byte := false; v.data_not_ins := false; v.addr := 0; v.data := 0; v.cpu_output.digit_value := 0; v.cpu_output.mem_wdata := 0; v.cpu_output.mem_addr := 0; if r.cpu_input.run = '1' then v.state := fetch_addr; v.cpu_output.reg_ip := 0; v.cpu_output.reg_is := 0; v.cpu_output.reg_r0 := 0; v.cpu_output.reg_r1 := 0; end if; when fetch_addr => --Address the instruction pointed to by the instruction pointer v.cpu_output.led_fetch := '1'; v.cpu_output.mem_rd := '1'; if r.data_not_ins then v.cpu_output.mem_addr := r.addr; else v.cpu_output.mem_addr := r.cpu_output.reg_ip; v.cpu_output.reg_ip := (r.cpu_output.reg_ip + 1) mod byte_values; end if; v.state := fetch_read; v.cnt := READ_LATENCY; when fetch_read => --Wait for data and read the instruction addressed in fetch_addr v.cpu_output.led_fetch := '1'; if r.cnt = 0 then if r.data_not_ins then v.data_not_ins := false; v.data := r.cpu_input.mem_rdata; if r.cpu_output.reg_is = SWAP_R0_ADDR then v.state := ex_swap_r0_addr_1; elsif r.cpu_output.reg_is = SWAP_R1_ADDR then v.state := ex_swap_r1_addr_1; else v.state := halted; end if; elsif r.second_ins_byte then v.second_ins_byte := false; v.data := r.cpu_input.mem_rdata; v.state := decode_two; else v.cpu_output.reg_is := r.cpu_input.mem_rdata; v.state := decode; end if; else v.cnt := r.cnt - 1; end if; when decode => --Decode the fetched instruction v.cpu_output.led_dec := '1'; case r.cpu_output.reg_is is when HALT => v.state := ex_halt; when INC_R0 => v.state := ex_inc_r0; when DEC_R0 => v.state := ex_dec_r0; when INC_R1 => v.state := ex_inc_r1; when DEC_R1 => v.state := ex_dec_r1; when ADD_R0_R1 => v.state := ex_add_r0_r1; when SUB_R0_R1 => v.state := ex_sub_r0_r1; when PRINT_R0 => v.state := ex_print_r0; when JP_IF_R0_NZ | JP_IF_R0_Z | LOAD_R0 | LOAD_R1 | STORE_R0 | STORE_R1 | SWAP_R0_ADDR | SWAP_R1_ADDR => --Fetch second byte for all two byte instructions v.second_ins_byte := true; v.state := fetch_addr; when others => v.state := ex_halt; end case; when decode_two => --Second decode stage for two byte instructions v.cpu_output.led_dec := '1'; case r.cpu_output.reg_is is when JP_IF_R0_NZ => v.state := ex_jp_if_r0_nz; when JP_IF_R0_Z => v.state := ex_jp_if_r0_z; when LOAD_R0 => v.state := ex_load_r0; when LOAD_R1 => v.state := ex_load_r1; when STORE_R0 => v.state := ex_store_r0; when STORE_R1 => v.state := ex_store_r1; when SWAP_R0_ADDR => v.state := ex_swap_r0_addr_0; when SWAP_R1_ADDR => v.state := ex_swap_r1_addr_0; when others => v.state := ex_halt; end case; when ex_halt => --Execute the halt instruction v.cpu_output.led_exec := '1'; v.state := halted; when ex_inc_r0 => --Increment the R0 register v.cpu_output.led_exec := '1'; v.cpu_output.reg_r0 := (r.cpu_output.reg_r0 + 1) mod byte_values; v.state := fetch_addr; when ex_dec_r0 => --Decrement the R0 register v.cpu_output.led_exec := '1'; v.cpu_output.reg_r0 := (r.cpu_output.reg_r0 - 1) mod byte_values; v.state := fetch_addr; when ex_inc_r1 => --Increment the R1 register v.cpu_output.led_exec := '1'; v.cpu_output.reg_r1 := (r.cpu_output.reg_r1 + 1) mod byte_values; v.state := fetch_addr; when ex_dec_r1 => --Decrement the R1 register v.cpu_output.led_exec := '1'; v.cpu_output.reg_r1 := (r.cpu_output.reg_r1 - 1) mod byte_values; v.state := fetch_addr; when ex_add_r0_r1 => --Add R0 and R1 and store the result in R0 v.cpu_output.led_exec := '1'; v.cpu_output.reg_r0 := (r.cpu_output.reg_r0 + r.cpu_output.reg_r1) mod byte_values; v.state := fetch_addr; when ex_sub_r0_r1 => --Subtract R1 from R0 and store the result in R0 v.cpu_output.led_exec := '1'; v.cpu_output.reg_r0 := (r.cpu_output.reg_r0 - r.cpu_output.reg_r1) mod byte_values; v.state := fetch_addr; when ex_print_r0 => --Printout the value of R0 v.cpu_output.led_exec := '1'; v.cpu_output.digit_value := r.cpu_output.reg_r0; v.cpu_output.digit_latch := '1'; v.state := fetch_addr; when ex_jp_if_r0_nz => --JUmp to address pointed to by data is R0 != 0 v.cpu_output.led_exec := '1'; if not (r.cpu_output.reg_r0 = 0) then v.cpu_output.reg_ip := r.data; end if; v.state := fetch_addr; when ex_jp_if_r0_z => --JUmp to address pointed to by data is R0 == 0 v.cpu_output.led_exec := '1'; if r.cpu_output.reg_r0 = 0 then v.cpu_output.reg_ip := r.data; end if; v.state := fetch_addr; when ex_load_r0 => --Load the fetched data into R0 v.cpu_output.led_exec := '1'; v.cpu_output.reg_r0 := r.data; v.state := fetch_addr; when ex_load_r1 => --Load the fetched data into R1 v.cpu_output.led_exec := '1'; v.cpu_output.reg_r1 := r.data; v.state := fetch_addr; when ex_store_r0 => --Store the content of R0 in memory v.cpu_output.led_exec := '1'; v.cpu_output.mem_wdata := r.cpu_output.reg_r0; v.cpu_output.mem_addr := r.data; v.cpu_output.mem_wr := '1'; v.state := fetch_addr; when ex_store_r1 => --Store the content of R0 in memory v.cpu_output.led_exec := '1'; v.cpu_output.mem_wdata := r.cpu_output.reg_r1; v.cpu_output.mem_addr := r.data; v.cpu_output.mem_wr := '1'; v.state := fetch_addr; when ex_swap_r0_addr_0 => --Swap the content of R0 with the contnet of a memory location --Part 0 read v.cpu_output.led_exec := '1'; v.data_not_ins := true; v.addr := r.data; v.state := fetch_addr; when ex_swap_r0_addr_1 => --Swap the content of R0 with the contnet of a memory location --Part 1 write v.cpu_output.reg_r0 := r.data; v.cpu_output.led_exec := '1'; v.cpu_output.mem_wdata := r.cpu_output.reg_r0; v.cpu_output.mem_addr := r.addr; v.cpu_output.mem_wr := '1'; v.state := fetch_addr; when ex_swap_r1_addr_0 => --Swap the content of R1 with the contnet of a memory location --Part 0 read v.cpu_output.led_exec := '1'; v.data_not_ins := true; v.addr := r.data; v.state := fetch_addr; when ex_swap_r1_addr_1 => --Swap the content of R1 with the contnet of a memory location --Part 1 write v.cpu_output.reg_r1 := r.data; v.cpu_output.led_exec := '1'; v.cpu_output.mem_wdata := r.cpu_output.reg_r1; v.cpu_output.mem_addr := r.addr; v.cpu_output.mem_wr := '1'; v.state := fetch_addr; when others => null; end case; --Drive outputs cpu_output <= r.cpu_output; --Drive register rin <= v; end process p_comb; -- purpose: Register -- type : sequential p_reg : process (clk, reset_n) is begin -- process p_reg if reset_n = '0' then r.cpu_output.halted <= '1'; r.cpu_output.running <= '0'; r.cpu_output.paused <= '0'; r.cpu_output.beep <= '0'; r.cpu_output.digit_latch <= '0'; r.cpu_output.led_fetch <= '0'; r.cpu_output.led_dec <= '0'; r.cpu_output.led_exec <= '0'; r.cpu_output.mem_wr <= '0'; r.cpu_output.mem_rd <= '0'; r.state <= halted; elsif rising_edge(clk) then r <= rin; end if; end process p_reg; end architecture twoproc; --cpu_4004.vhd ends here
gpl-3.0
25aed44b53dd601b4edb9b147354ff65
0.507815
3.164712
false
false
false
false
natsutan/NPU
fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/synth/mult_17x16.vhd
1
5,692
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:mult_gen:12.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY mult_gen_v12_0_12; USE mult_gen_v12_0_12.mult_gen_v12_0_12; ENTITY mult_17x16 IS PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(16 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); P : OUT STD_LOGIC_VECTOR(24 DOWNTO 0) ); END mult_17x16; ARCHITECTURE mult_17x16_arch OF mult_17x16 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_17x16_arch: ARCHITECTURE IS "yes"; COMPONENT mult_gen_v12_0_12 IS GENERIC ( C_VERBOSITY : INTEGER; C_MODEL_TYPE : INTEGER; C_OPTIMIZE_GOAL : INTEGER; C_XDEVICEFAMILY : STRING; C_HAS_CE : INTEGER; C_HAS_SCLR : INTEGER; C_LATENCY : INTEGER; C_A_WIDTH : INTEGER; C_A_TYPE : INTEGER; C_B_WIDTH : INTEGER; C_B_TYPE : INTEGER; C_OUT_HIGH : INTEGER; C_OUT_LOW : INTEGER; C_MULT_TYPE : INTEGER; C_CE_OVERRIDES_SCLR : INTEGER; C_CCM_IMP : INTEGER; C_B_VALUE : STRING; C_HAS_ZERO_DETECT : INTEGER; C_ROUND_OUTPUT : INTEGER; C_ROUND_PT : INTEGER ); PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(16 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); CE : IN STD_LOGIC; SCLR : IN STD_LOGIC; P : OUT STD_LOGIC_VECTOR(24 DOWNTO 0) ); END COMPONENT mult_gen_v12_0_12; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF mult_17x16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF mult_17x16_arch : ARCHITECTURE IS "mult_17x16,mult_gen_v12_0_12,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF mult_17x16_arch: ARCHITECTURE IS "mult_17x16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=4,C_A_WIDTH=17,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=1,C_OUT_HIGH=32,C_OUT_LOW=8,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA"; BEGIN U0 : mult_gen_v12_0_12 GENERIC MAP ( C_VERBOSITY => 0, C_MODEL_TYPE => 0, C_OPTIMIZE_GOAL => 1, C_XDEVICEFAMILY => "kintexu", C_HAS_CE => 0, C_HAS_SCLR => 0, C_LATENCY => 4, C_A_WIDTH => 17, C_A_TYPE => 1, C_B_WIDTH => 16, C_B_TYPE => 1, C_OUT_HIGH => 32, C_OUT_LOW => 8, C_MULT_TYPE => 0, C_CE_OVERRIDES_SCLR => 0, C_CCM_IMP => 0, C_B_VALUE => "10000001", C_HAS_ZERO_DETECT => 0, C_ROUND_OUTPUT => 0, C_ROUND_PT => 0 ) PORT MAP ( CLK => CLK, A => A, B => B, CE => '1', SCLR => '0', P => P ); END mult_17x16_arch;
bsd-3-clause
d42e6b7732d90bbb7df617a2422fd7b8
0.680429
3.348235
false
false
false
false
besm6/micro-besm
tests/2910/vhdl/funct_block_alg_beh/funct_block_alg_beh2910.vhdl
1
5,955
-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Feb 19, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD -- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD -------------------------------------------------------------------------------- use work.types.all; use work.MVL7_functions.all; use work.synthesis_types.all; entity AM2910 is port ( I : in MVL7_VECTOR(3 downto 0); CCEN_BAR : in MVL7; CC_BAR : in MVL7; RLD_BAR : in MVL7; CI : in MVL7; OEbar : in MVL7; clk : in clock; D : in MVL7_VECTOR(11 downto 0); Y : out MVL7_VECTOR(11 downto 0); PL_BAR : out MVL7; VECT_BAR : out MVL7; MAP_BAR : out MVL7; FULL_BAR : out MVL7 ); end AM2910; architecture AM2910 of AM2910 is signal sp : INTEGER range 0 to 5; signal R_sel,D_sel,uPC_sel,stack_sel,decr,load,Rzero_bar,clear,push,pop : MVL7; signal Y_temp,RE,uPC : MVL7_VECTOR(11 downto 0); signal reg_file : MEMORY_12_BIT(5 downto 0); begin ------------------------------------------------------------------------------- muxr : block begin Y_temp <= RE WHEN R_sel = '1' ELSE D WHEN D_sel = '1' ELSE uPC WHEN uPC_sel = '1' ELSE reg_file(sp) WHEN stack_sel = '1' ELSE "000000000000"; Y <= Y_temp when OEbar = '0' else "ZZZZZZZZZZZZ"; end block muxr; ------------------------------------------------------------------------------- reg_ctr : block ( (clk = '1') and (not clk'stable) ) begin RE <= guarded D WHEN (( load = '1') or (RLD_BAR = '0')) ELSE -- load RE - "000000000001" WHEN (decr = '1') and (RLD_BAR = '1') ELSE -- decr RE ; -- hold Rzero_bar <= RE(0) or RE(1) or RE(2) or RE(4) or RE(5) or RE(6) or RE(7) or RE(8) or RE(9) or RE(10) or RE (11); end block reg_ctr; ------------------------------------------------------------------------------- PC : block ( (clk = '1') and (not clk'stable) ) begin uPC <= guarded Y_temp + ("00000000000" & CI) WHEN (clear = '0') ELSE "000000000000" WHEN clear = '1' ELSE uPC; end block PC; ------------------------------------------------------------------------------ stack_and_sp : block ( (clk = '1') and (not clk'stable) ) signal write_address : INTEGER range 0 to 5; begin sp <= guarded (sp - 1) WHEN (pop = '1') and (sp /= 0) ELSE (sp + 1) WHEN (push = '1') and (sp /= 5) ELSE 0 when clear = '1'ELSE sp; write_address <= sp + 1 WHEN (sp /= 5) ELSE -- sp; reg_file(write_address) <= guarded uPC WHEN (push = '1') ELSE reg_file(write_address); FULL_BAR <= '0' WHEN sp = 5 ELSE '1'; end block stack_and_sp; ------------------------------------------------------------------------------ ctrl:block signal fail : MVL7; begin fail <= cc_bar and not(ccen_bar); D_sel <= '1' WHEN ( I = "0010") or ( Rzero_bar = '1' and I = "1001") or ( Rzero_bar = '0' and fail = '1' and I = "1111") or ( ( fail = '0') and ( ( I = "0001" ) or ( I = "0011" ) or ( I = "0101" ) or ( I = "0110" ) or ( I = "0111" ) or ( I = "1011" ) ) ) ELSE '0'; uPC_sel <= '1' WHEN ( I = "0100" ) or ( I = "1100" ) or ( I = "1110") or ( ( fail = '1') and ( ( I = "0001" ) or ( I = "0011" ) or ( I = "0110" ) or ( I = "1010" ) or ( I = "1011" ) or ( I = "1110" ) ) ) or ( ( Rzero_bar = '0') and ( ( I = "1000" ) or ( I = "1001") ) ) or ( (fail = '0') and ( ( I = "1111" ) or ( I = "1101") ) ) ELSE '0'; stack_sel <= '1' WHEN ( Rzero_bar = '1' and I = "1000") or ( fail = '0' and I = "1010") or ( fail = '1' and I = "1101") or ( Rzero_bar = '1' and fail = '1' and I = "1111") ELSE '0'; R_sel <= '1' WHEN (( fail = '1') and (( I = "0101" ) or ( I = "0111"))) ELSE '0'; push <= '1' WHEN ( (fail = '0') and ( I = "0001") ) or ( I = "0100" ) or ( I = "0101") ELSE '0'; pop <= '1' WHEN ( (fail = '0') and ( ( I = "1010" ) or ( I = "1011" ) or ( I = "1101" ) or ( I = "1111" ) ) ) or ( (Rzero_bar = '0') and ( (I = "1000" ) or ( I = "1111") ) ) ELSE '0'; load <= '1' WHEN ( (I = "1100") or ( I = "0100" and fail = '0')) ELSE '0'; decr <= '1' WHEN ( (Rzero_bar = '1') and ( (I = "1000" ) or ( I = "1001" ) or ( I = "1111") ) ) ELSE '0'; MAP_BAR <= '0' WHEN I = "0010" ELSE '1'; VECT_BAR <= '0' WHEN I = "0110" ELSE '1'; PL_BAR <= '1' WHEN ( I = "0010" ) or ( I = "0110") ELSE '0'; clear <= '1' WHEN I = "0000" ELSE '0'; end block ctrl; ------------------------------------------------------------------------------ end AM2910;
mit
922c6fd4a4d8504dc7dc8aef45426e3d
0.372796
3.557348
false
false
false
false
gardintrapp/cpu_4004
src/cpu_4004_pkg.vhd
1
2,950
--cpu_4004_pkg.vhd --- -- --Filename: cpu_4004_pkg.vhd --Description: --Author: Oddbjørn Norstrand <[email protected]> --Maintainer: Oddbjørn Norstrand <[email protected]> --Created: Sat Dec 15 21:45:52 2012 (+0100) --Version: 0.1 --Last-Updated: Mon Dec 31 16:24:01 2012 (+0100) -- By: oddbjorn -- Update #: 24 --URL: --Keywords: --Compatibility: -- -- --Commentary: -- -- -- -- --Change Log: -- -- -- --This program is free software; you can redistribute it and/or --modify it under the terms of the GNU General Public License as --published by the Free Software Foundation; either version 3, or --(at your option) any later version. -- --This program is distributed in the hope that it will be useful, --but WITHOUT ANY WARRANTY; without even the implied warranty of --MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --General Public License for more details. -- --You should have received a copy of the GNU General Public License --along with this program; see the file COPYING. If not, write to --the Free Software Foundation, Inc., 51 Franklin Street, Fifth --Floor, Boston, MA 02110-1301, USA. -- -- --Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package cpu_4004_pkg is subtype byte is integer range 0 to 15; constant byte_values : integer := byte'high + 1; subtype addr_range is integer range 0 to 15; type memory_type is array (addr_range) of byte; --Instructions --One byte instructions constant HALT : byte := 0; constant INC_R0 : byte := 1; constant DEC_R0 : byte := 2; constant INC_R1 : byte := 3; constant DEC_R1 : byte := 4; constant ADD_R0_R1 : byte := 5; constant SUB_R0_R1 : byte := 6; constant PRINT_R0 : byte := 7; --Two byute instructions constant JP_IF_R0_NZ : byte := 8; constant JP_IF_R0_Z : byte := 9; constant LOAD_R0 : byte := 16#a#; constant LOAD_R1 : byte := 16#b#; constant STORE_R0 : byte := 16#c#; constant STORE_R1 : byte := 16#d#; constant SWAP_R0_ADDR : byte := 16#e#; constant SWAP_R1_ADDR : byte := 16#f#; --Input signals to the 4004 type cpu_4004_input_type is record run : std_logic; stop : std_logic; step : std_logic; mem_rdata : byte; end record cpu_4004_input_type; --Output signals from the 4004 type cpu_4004_output_type is record running : std_logic; paused : std_logic; halted : std_logic; beep : std_logic; digit_value : byte; digit_latch : std_logic; led_fetch : std_logic; led_dec : std_logic; led_exec : std_logic; mem_wdata : byte; mem_addr : addr_range; mem_wr : std_logic; mem_rd : std_logic; reg_r0 : byte; reg_r1 : byte; reg_ip : byte; reg_is : byte; end record cpu_4004_output_type; end package cpu_4004_pkg; --cpu_4004_pkg.vhd ends here
gpl-3.0
36c4394175dc43b77cd3af9917fe2407
0.632293
3.13951
false
false
false
false
MartinCura/SistDig-TP4
old/UART/data_adq/uart.vhd
1
1,890
----------------------------------------------- -- UART core -- ----------------------------------------------- -- RxRdy es generado por la uart cuando recibe un dato correctamente (luego de leer cada uno de los 8 bits, genera un pulso en dicha señal en el STOP BIT, y luego vuelve a 0 en IDLE o en el siguiente START BIT) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --library work; --use work.uart_comps.all; use work.uart_comps.all; entity uart is generic ( F : natural := 50000; -- Device clock frequency [KHz]. baud_rate : natural := 1200; num_data_bits : natural := 8 ); port ( Rx : in std_logic; Tx : out std_logic; Din : in std_logic_vector(num_data_bits-1 downto 0); StartTx : in std_logic; TxBusy : out std_logic; Dout : out std_logic_vector(num_data_bits-1 downto 0); RxRdy : out std_logic; RxErr : out std_logic; clk : in std_logic; rst : in std_logic ); end; architecture arch of uart is signal top16 : std_logic; signal toprx : std_logic; signal toptx : std_logic; signal Sig_ClrDiv : std_logic; begin reception_unit: receive generic map ( NDBits => num_data_bits ) port map ( CLK => clk, RST => rst, Rx => Rx, Dout => Dout, RxErr => RxErr, RxRdy => RxRdy, ClrDiv => Sig_ClrDiv, Top16 => top16, TopRx => toprx ); transmission_unit: transmit generic map ( NDBits => num_data_bits ) port map ( CLK => clk, RST => rst, Tx => Tx, Din => Din, TxBusy => TxBusy, TopTx => toptx, StartTx => StartTx ); timings_unit: timing generic map ( F => F, baud_rate => baud_rate ) port map ( CLK => clk, RST => rst, ClrDiv => Sig_ClrDiv, Top16 => top16, TopTx => toptx, TopRx => toprx ); end;
gpl-3.0
5a20fc9409b10aa1bc532d15b2bc321c
0.548438
2.888379
false
false
false
false
MartinCura/SistDig-TP4
src/comps/delay.vhd
1
1,180
-- Retarda en N ciclos el vector recibido library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity delay_reg is generic( N: natural := 8; DELAY: natural := 0 ); port( clock: in std_logic; reset: in std_logic; enable: in std_logic; A: in std_logic_vector(N-1 downto 0); B: out std_logic_vector(N-1 downto 0) ); end entity delay_reg; architecture delay_arch of delay_reg is type t_aux is array(0 to DELAY+1) of std_logic_vector(N-1 downto 0); signal aux: t_aux; begin -- Entrada aux(0) <= A; gen_retardo: for i in 0 to DELAY generate sin_retardo: if i = 0 generate aux(1) <= aux(0); end generate sin_retardo; con_retardo: if i > 0 generate reg: entity work.registroNb generic map(N) port map( clk => clock, rst => reset, ena => enable, d => aux(i), q => aux(i+1) ); end generate con_retardo; end generate gen_retardo; -- Salida B <= aux(DELAY+1); end architecture delay_arch;
gpl-3.0
8938ec4bc743e209526e9509a5aacb17
0.530508
3.554217
false
false
false
false
mrozo/programmable-digital-circuits
rs232monitor/counterTb.vhd
1
2,231
LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; ENTITY counterTb IS Generic ( counter1Width : integer :=2; counter2Width : integer :=5; counter3Width : integer :=8; counter4Width : integer :=16 ); END counterTb; ARCHITECTURE behavior OF counterTb IS COMPONENT counter Generic ( width : integer ); PORT( rst : IN std_logic; clk : IN std_logic; clear : IN std_logic; state : OUT std_logic_vector((width-1) downto 0) ); END COMPONENT; --Inputs signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal clear1 : std_logic := '0'; signal clear2 : std_logic := '0'; signal clear3 : std_logic := '0'; signal clear4 : std_logic := '0'; --Outputs signal state1 : std_logic_vector((counter1Width-1) downto 0); signal state2 : std_logic_vector((counter2Width-1) downto 0); signal state3 : std_logic_vector((counter3Width-1) downto 0); signal state4 : std_logic_vector((counter4Width-1) downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN clk <= not clk after clk_period; c1: counter GENERIC MAP ( width => counter1Width ) PORT MAP ( rst => rst, clk => clk, clear => clear1, state => state1 ); c2: counter GENERIC MAP ( width => counter2Width ) PORT MAP ( rst => rst, clk => clk, clear => clear2, state => state2 ); c3: counter GENERIC MAP ( width => counter3Width ) PORT MAP ( rst => rst, clk => clk, clear => clear3, state => state3 ); clear4 <= '1' when unsigned(state4)=101 else '0'; c4: counter GENERIC MAP ( width => counter4Width ) PORT MAP ( rst => rst, clk => clk, clear => clear4, state => state4 ); stim_proc: process begin wait for 100 ns; wait for clk_period*10; wait; end process; END;
bsd-3-clause
170ec47fc8f9132486d631044ea0104e
0.511878
3.586817
false
false
false
false
besm6/micro-besm
tests/2901/vhdl/funct_blocks_alg_beh/components/alu_inputs/MVL7_functions.vhd
4
12,872
--*************************************************************************** -- VHDL BIT_VECTOR Operations for MVL7 type -- -- Copyright (c) 1990 UCI CADLAB, Dept. of ICS -- Author : Sanjiv Narayan ([email protected]) -- -- Updated 7/8/91 by Sanjiv and Frank -- -- updated by Champaka Ramachandran 16/10/92 -- --*************************************************************************** use work.TYPES.all; package MVL7_functions is function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR; function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR; function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR; function I2B( Number : integer ; len : integer ) return MVL7_VECTOR; function B2I( v2 : MVL7_VECTOR ) return integer; function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR; function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR; function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7; function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7; function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR; function SUM( v2 : MVL7_VECTOR ) return integer; function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR; function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR; function INC( x : MVL7_VECTOR ) return MVL7_VECTOR; function CARRY_ADD( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; function "-"( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR; -- truth table for "WiredOr" function constant tbl_WIREDOR: MVL7_TABLE := -- ----------------------------------------------- -- | X 0 1 Z W L H | | -- ----------------------------------------------- (('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X | ('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 | ('1', '1', '1', '1', '1', '1', '1'), -- | 1 | ('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z | ('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W | ('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L | ('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H | function WiredOr (V: MVL7_VECTOR) return MVL7; end; package body MVL7_functions is --*************************************************************************** function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable shift_val: MVL7_VECTOR (v1'high downto v1'low); variable I: integer; begin v1 := v2; for I in v1'high downto (v1'low + 1) loop shift_val(I) := v1(I - 1); end loop ; shift_val(v1'low) := fill; return shift_val; end; --*************************************************************************** function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHL(v1,'0'); end loop ; return v1; end; --*************************************************************************** function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHL(v1,'1'); end loop ; return v1; end; --*************************************************************************** function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable shift_val: MVL7_VECTOR (v1'high downto v1'low); begin v1 := v2; for I in v1'low to (v1'high - 1) loop shift_val(I) := v1(I + 1); end loop ; shift_val(v1'high) := fill; return shift_val; end; --*************************************************************************** function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHR(v1,'0'); end loop ; return v1; end; --*************************************************************************** function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for I in 1 to dist loop v1 := SHR(v1,'1'); end loop ; return v1; end; --*************************************************************************** function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for i in 1 to dist loop v1 := SHR(v1,v1(v1'low)); end loop ; return v1; end; --*************************************************************************** function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable I: INTEGER; begin v1 := v2; for i in 1 to dist loop v1 := SHL(v1,v1(v1'high)); end loop ; return v1; end; --*************************************************************************** function I2B( Number : integer ; len : integer ) return MVL7_VECTOR is variable temp: MVL7_VECTOR (len - 1 downto 0); variable NUM: integer:=0; variable QUOTIENT: integer:=0; begin QUOTIENT := Number; for I in 0 to len - 1 loop NUM := 0; while QUOTIENT > 1 loop QUOTIENT := QUOTIENT - 2; NUM := NUM + 1; end loop ; case QUOTIENT is when 1 => temp(I) := '1'; when 0 => temp(I) := '0'; when others => null; end case; QUOTIENT := NUM; end loop ; return temp; end; --*************************************************************************** function B2I( v2 : MVL7_VECTOR ) return integer is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable SUM: integer:=0; begin v1 := v2; for N in v1'low to v1'high loop if v1(N) = '1' then SUM := SUM + (2 ** (N - v1'low)); end if; end loop ; return SUM; end; --*************************************************************************** function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable temp: MVL7_VECTOR (v1'high downto v1'low); variable I: INTEGER; begin v1 := v2; for I in v1'low to v1'high loop if v1(I) = '0' then temp(i) := '1'; else temp(i) := '0'; end if; end loop ; return temp; end; --*************************************************************************** function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable temp: MVL7_VECTOR (v1'high downto v1'low); begin v1 := v2; temp := comp(v1); temp := INC(temp); return temp; end; --*************************************************************************** function "-" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable SUM: MVL7_VECTOR (v1'high downto v1'low); begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7 vector -: operands of unequal lengths" severity FAILURE; SUM := I2B(B2I(v1) - B2I(v2),SUM'length); return (SUM); end; --*************************************************************************** function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR is variable v: MVL7_VECTOR (x'high downto x'low); begin v := x; return I2B(B2I(v) - 1,v'length); end; --*************************************************************************** function CARRY_ADD( x1: MVL7_VECTOR ; x2: MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable SUM: MVL7_VECTOR (x1'high - x1'low + 1 downto 0); -- + 1 is for carry begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7vector carry add:operands of unequal lengths" severity FAILURE; SUM := I2B(B2I(v1) + B2I(v2),SUM'length); return (SUM); end; --*************************************************************************** function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable SUM: MVL7_VECTOR (v1'high downto v1'low); begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7 vector +: operands of unequal lengths" severity FAILURE; SUM := I2B(B2I(v1) + B2I(v2),SUM'length); return (SUM); end; --*************************************************************************** function INC( x : MVL7_VECTOR ) return MVL7_VECTOR is variable v: MVL7_VECTOR (x'high downto x'low); begin v := x; return I2B(B2I(v) + 1,v'length); end; --*************************************************************************** function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7 is begin if ((SUM(v1) mod 2) = 1) then return '0'; else return '1'; end if; end; --*************************************************************************** function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7 is begin if ((SUM(v1) mod 2) = 1) then return '1'; else return '0'; end if; end; --*************************************************************************** function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable temp: MVL7_VECTOR (v1'high downto v1'low); begin v1 := v2; for I in v1'high downto v1'low loop temp(I) := v1(v1'high - I + v1'low); end loop ; return temp; end; --*************************************************************************** function SUM( v2 : MVL7_VECTOR ) return integer is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable count: integer:=0; begin v1 := v2; for I in v1'high downto v1'low loop if (v1(I) = '1') then count := count + 1; end if; end loop ; return count; end; --*************************************************************************** function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR is begin return I2B(B2I(v),width); end; --*************************************************************************** function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (x1'high - x1'low downto 0); variable v2: MVL7_VECTOR (x2'high - x2'low downto 0); variable PROD: MVL7_VECTOR (v1'high downto v1'low); begin v1 := x1; v2 := x2; assert v1'length = v2'length report "MVL7 vector MUL: operands of unequal lengths" severity FAILURE; PROD := I2B(B2I(v1) * B2I(v2),PROD'length); return (PROD); end; --*************************************************************************** function WiredOr (V: MVL7_VECTOR) return MVL7 is variable result: MVL7; begin result := 'Z'; for i in V'range loop result := tbl_WIREDOr(result, V(i)); exit when result = '1'; end loop; return result; end WiredOr; --*************************************************************************** end;
mit
1c333e9fc538487890e365b466d8f38e
0.458825
3.566639
false
false
false
false
kuba-moo/VHDL-lib
__tmpl.vhd
1
1,471
-- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- -- Copyright (C) 2014 Jakub Kicinski <[email protected]> library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.globals.all; -- short description entity __TMPL__ is port (Clk : in std_logic; Rst : in std_logic); end __TMPL__; -- Operation: -- architecture Behavioral of __TMPL__ is type state_t is (IDLE); signal state, NEXT_state : state_t; begin NEXT_fsm : process (state) begin NEXT_state <= state; case state is when IDLE => end case; end process; fsm : process (Clk) begin if rising_edge(Clk) then state <= NEXT_state; if Rst = '1' then state <= IDLE; end if; end if; end process; end Behavioral;
gpl-3.0
990e6f4c63c189aad7edc9e3ed3c8ef4
0.647179
3.830729
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/snickerdoodle_try/snickerdoodle_try.cache/ip/2017.4.1/3096c1ea67ba29c5/design_1_processing_system7_0_1_sim_netlist.vhdl
1
205,819
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018 -- Date : Wed Apr 4 23:01:45 2018 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_1_sim_netlist.vhdl -- Design : design_1_processing_system7_0_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg400-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "design_1_processing_system7_0_1.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={26} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={166.666489} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p0} clockFreq={99.999893} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={49} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_processing_system7_0_1,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.4.1"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_1.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={26} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={166.666489} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p0} clockFreq={99.999893} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={49} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0"; attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW"; attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of GPIO_I : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I"; attribute X_INTERFACE_INFO of GPIO_O : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O"; attribute X_INTERFACE_INFO of GPIO_T : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 49999947, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => GPIO_I(63 downto 0), GPIO_O(63 downto 0) => GPIO_O(63 downto 0), GPIO_T(63 downto 0) => GPIO_T(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => '0', IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => NLW_inst_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => '0', USB0_VBUS_PWRSELECT => NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;
mit
af74659578f94ecce5160fa1535476fb
0.639232
2.764452
false
false
false
false
natsutan/NPU
fpga_implement/npu8/npu8.cache/ip/492adc01b6634d6a/mul8_8_sim_netlist.vhdl
1
179,563
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 -- Date : Sat Jan 21 17:57:15 2017 -- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_8_sim_netlist.vhdl -- Design : mul8_8 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xcku035-fbva676-3-e -- -------------------------------------------------------------------------------- `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA I7rHN/CieA== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5 Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo OP1PSFj5jpodG+LwXm4= `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF /kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3 251QPjQoZCw3A7W9PDc= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4 udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw== `protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7 rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61 /ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2 hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg== `protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50 ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" `protect encoding = (enctype="base64", line_length=76, bytes=256) `protect key_block IlkcB2vj+S59NGmvAhLuhfhOpb0w7qsABrGeBgEJWBzJuSHxqh8uFhxsIq8d4PUKJf/xeJ6AD2F6 OmX8D49bWdBC16iosHBzHcOqEOB+hroKr3c6L3dxnQ++dxRn752GPcuD5djPfSQEmprWHIr48lAH 9c6Sy6VCQwcFwGOcyUf3/cc2Z1UWsE2xr2x+KMDRlXRPnP+PSIyhLlbGjf3jEgVfYHiqdxVef1n2 pH15tXCWtf0PCRd0kKKzUnu8LvEYgFodl4kqXn7AHoSiU64exSn+k4fGo5Uutiutibr3VtU/x5Nn khQsZA743xbBtpXeaJ3XPhb+16XoxLpIAUKaXA== `protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa" `protect encoding = (enctype="base64", line_length=76, bytes=256) `protect key_block s66zKv0cTtr8J8zuaIRK0uyLu6EWxGbkEIlj2GfS/DIrKdc5OTdtaPxIt6GjMz0hJ3EPzfua7JRH ex+r4C2frce0fgoGDkc9yJ91w5zEoJboDMNA4DydgDJ58zwcczV5mslurd8frRJMtCYyMDg7Gkp4 HqtCUZoQCzwUx2fHN8AZNNVuD0eDuFr4YWsW3/bzXh5ofEXqh44nP5mlP8PmGbYnX8X9pHtpiUIB tg0YmKFe5QH8qkuX+Lw1jSDppr5gdnntTV50MsIWuPrXWXkYhteDkFpyHt3qrDdsy03u2aIxHsnr lsz1A2+82zSusWQF5yPS46sW/1aiasPJmgB1Mw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 122032) `protect data_block 0SZ68j5AgJ4s8OUOcn8VBcfMtDsdZKm4cVVV2Vk5BDe0P+CUil64i0c81xA1aXHt1knJ43mw+P9r GDdI84sX8Nejml4wL7NwZz1hqrXg3+TD02z8KjkPIrGXa4Yas3AB2QNAAWpoX8Of1NzhHSunlF15 Ve8ASumR106jfOd0Z9Rleimedt8kiiV/d+N/Hl8oz6ng1NpmYJFe/mJZPNkD7COHHxYX+U5OWOwf ZMa832kjONInnG19/ZrnaBmpwkM0upxy2f45ewM6Zt7nQXlhtefJ3XY288qQxPvlvhAWeIdArZS0 DrMSIkudZmOIIZYktC3U9nXXbI7ygiR2ODowqCO3PqpkKshTMIzeHOMQ6n24HMRYjE39o6P9UcVD gc/YdQO9zGp/EQpiSGsZf5LTGxI8Lb+kZ1glBVjtwVozQmZh6nzdsmVRfSLbKlsj5VI5t5BNNznk 2tFNGP5ulchabKNgqeT4KXNtcxNd0PIQMP8b186oKz8Oo0PtcVLVTIEdcvhQZqKCG3Fi2WP5waq5 DJl532VANWgZ1ITopM9pjc5jl8glio7msgfB/BjpeKnoKdAAQiS4yVnqIPXS7Uqo/Bv8qzVqNFgZ Ob5Y1eqIbuMqXD8ywxIFxWiSc161q37hlzRd+rjtj+e/+E9vaVJILB/sIxLM3vkIg6W5fRQetHqk M8oIEvkdQSYY0qBlmSLEv9ogSPKr6NklljSadOUe9Cag3uXNPaNj9+HtFr/udjFIaWjvnBtEGi/+ icBaR0Dvd+ZzvZ6+IkBTQ3LgnmiwE1iFQX18Lxlsqt+QgbUEJfmyWzICVowjBu0xT4Ha8eJWnfQY CJhyc406jLOYUieuI0Os8yy9oLF5JfIYjGOvp9OFQksM4640ExUeS9HSeud4kg9KQrqxb+jORa4w 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xktC5laS1dzD1PYFczna3TKxeT+CpNAbgbWXaTqUuHthNIP8hnnAzA5UZKmRG2O1EGfbMy3yueqJ mMJ2wJTr/0pazDX7aENprXWWOnI2qD7FHZoagX+/zxMKYHrLQ4wZ6dYlvgTggAeDZ5sULxD0hxoz GySwzkTiNMnwuzYocLA3mcEobL4O6m9RCCzQWQXWzDNOV7+9qSgy8MlqJNWCsp59k43vSRO2jrl9 X5PrIBSMU+S9kbNBhi+w8wLE1ebloIXzzGVeIreZmDJKDHHH5R15qGSISE1iRNxceGxHKXioGoWg 1rIJG/kt5z/STUusJobPuM8Xd7HHuJRXX4HpBaIK8PFgOSb0BK6ooX31wgMQUZdDV5O3UmKn3+T1 1sHop3+6fBBH5ILwE6rbrFVzZxJsxWI5MfLhQt/9JPRDSTL5soTpUcXTDs3foodKXNlBMR1xY5Br rmwEVmM8fYJhHzUAWzAiflE2/LLBiQ1GilmU1lOq3AeNEYolE19DpNWONVek0Rq87/X5vroc0PVB WAMHuG1l3zYJfLRF5YqD6qyOD+XElBLd4/eHVhG/c4v0U9PcXokSEvCn9qm/MKCgfUnu6knVW64n X/vMgiANJfuFYQ02Gg2doecmsJaN34j0tILXsXk6Y5KWdeTirAl8OLCWm2tiiU/yD3SKtDicsOPm KAITpjy6M8SDYtt4k/z8lYg/6Bfril+WL4lZ81awphyt+LWNYnFCVJaWFqUADfiRs9Diu/5T/5xa K3JRUhpD2h27DqxW0nRPzVxcm7VPfevleh9JZOFBNiTlvnFmG2wQkvLaaU+8ccoav3jIT0FBA6SP X5dy2IRTA6y/GParo5LXPu/TzB5nRuRBZ2NghizJygculXbBhpTA3CHDqEriaGykUD9RP32X1Vhm xPbo3K2KufNxj9MMBHR5VxKgh78N5kV7sK0KtjXxYRkRTjLJie13Cd0P9YgclancUTffJZBN4ooq VlbcHJFFMzkJRWYr+bqYY1dmjYUcAFAgN+akfrsS1ZaY5ciR5metLDmY8Xd+tG237X375TUpR+AQ j5LyzBrmwoToTGIDGcJ2LYX77ZS+DkjFJl+OiY6rUw1rQ4vOQrymlKqkWmAihiP2YFtHJGsAzOEY pwrG4Nu9IwTopoYD0EZnPaveV2UtWQFDie1zjCbeZouSrnDcrVengME7hlKePhe6fKH4RjJ8zbVL AVx0OSMHm1irh449oN3WWluencsEy+voYoHRlmkbBzJIZz3+DbE1uMUlJf39xZFlytdTIwNCOWcv IPU4TvAhTOOTSM3duzzmJDh1Ae0fAwOgYiCgT9Jeufsp101zneuTNrkYhXcMvNrcurc0LWm/IzHA woZ7aN8XLaBjnGfWLSAVTmLVaoYZg8X8RU5j0MEWoC0nK1bGU0tRT3S7aDotSMGydAGukSl+0qq2 DQQhb1U+jhtFuSS5g5ued41YXuMM/H7Pvs9qVgUNnLSuzrK3v7SXc9A+jhE9QXDP8XDoJXMVKCTs ooGb5fhRvZ4zVHhmYKML4oVMsol5/0C3NJMmC+Adqb+vRR1hgdkRL4bQzKmQqdcuXGpq0Krh6zsN x7+/E/C8ZubwRE3CJgrxqNzK6e2yXE0tccCCYCy7d8xbZOodrsiF4LQ0jcagWGOur+SOBp1wFQw9 RK9PFK24mC+xFo1hLzXmtpnEnKytrJz2LI3LlxEjin4fvniXr/Agy1D9YMP0ypeuzU+K2g== `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 7 downto 0 ); B : in STD_LOGIC_VECTOR ( 7 downto 0 ); CE : in STD_LOGIC; SCLR : in STD_LOGIC; ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 ); P : out STD_LOGIC_VECTOR ( 15 downto 0 ); PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 ) ); attribute C_A_TYPE : integer; attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8; attribute C_B_TYPE : integer; attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 3; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_OPTIMIZE_GOAL : integer; attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 15; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is signal \<const0>\ : STD_LOGIC; signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE of i_mult : label is 1; attribute C_A_WIDTH of i_mult : label is 8; attribute C_B_TYPE of i_mult : label is 1; attribute C_B_VALUE of i_mult : label is "10000001"; attribute C_B_WIDTH of i_mult : label is 8; attribute C_CCM_IMP of i_mult : label is 0; attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0; attribute C_HAS_CE of i_mult : label is 0; attribute C_HAS_SCLR of i_mult : label is 0; attribute C_HAS_ZERO_DETECT of i_mult : label is 0; attribute C_LATENCY of i_mult : label is 3; attribute C_MODEL_TYPE of i_mult : label is 0; attribute C_MULT_TYPE of i_mult : label is 0; attribute C_OUT_HIGH of i_mult : label is 15; attribute C_OUT_LOW of i_mult : label is 0; attribute C_ROUND_OUTPUT of i_mult : label is 0; attribute C_ROUND_PT of i_mult : label is 0; attribute C_VERBOSITY of i_mult : label is 0; attribute C_XDEVICEFAMILY of i_mult : label is "kintexu"; attribute c_optimize_goal of i_mult : label is 1; attribute downgradeipidentifiedwarnings of i_mult : label is "yes"; begin PCASC(47) <= \<const0>\; PCASC(46) <= \<const0>\; PCASC(45) <= \<const0>\; PCASC(44) <= \<const0>\; PCASC(43) <= \<const0>\; PCASC(42) <= \<const0>\; PCASC(41) <= \<const0>\; PCASC(40) <= \<const0>\; PCASC(39) <= \<const0>\; PCASC(38) <= \<const0>\; PCASC(37) <= \<const0>\; PCASC(36) <= \<const0>\; PCASC(35) <= \<const0>\; PCASC(34) <= \<const0>\; PCASC(33) <= \<const0>\; PCASC(32) <= \<const0>\; PCASC(31) <= \<const0>\; PCASC(30) <= \<const0>\; PCASC(29) <= \<const0>\; PCASC(28) <= \<const0>\; PCASC(27) <= \<const0>\; PCASC(26) <= \<const0>\; PCASC(25) <= \<const0>\; PCASC(24) <= \<const0>\; PCASC(23) <= \<const0>\; PCASC(22) <= \<const0>\; PCASC(21) <= \<const0>\; PCASC(20) <= \<const0>\; PCASC(19) <= \<const0>\; PCASC(18) <= \<const0>\; PCASC(17) <= \<const0>\; PCASC(16) <= \<const0>\; PCASC(15) <= \<const0>\; PCASC(14) <= \<const0>\; PCASC(13) <= \<const0>\; PCASC(12) <= \<const0>\; PCASC(11) <= \<const0>\; PCASC(10) <= \<const0>\; PCASC(9) <= \<const0>\; PCASC(8) <= \<const0>\; PCASC(7) <= \<const0>\; PCASC(6) <= \<const0>\; PCASC(5) <= \<const0>\; PCASC(4) <= \<const0>\; PCASC(3) <= \<const0>\; PCASC(2) <= \<const0>\; PCASC(1) <= \<const0>\; PCASC(0) <= \<const0>\; ZERO_DETECT(1) <= \<const0>\; ZERO_DETECT(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv port map ( A(7 downto 0) => A(7 downto 0), B(7 downto 0) => B(7 downto 0), CE => '0', CLK => CLK, P(15 downto 0) => P(15 downto 0), PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 7 downto 0 ); B : in STD_LOGIC_VECTOR ( 7 downto 0 ); P : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mul8_8,mult_gen_v12_0_12,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE : integer; attribute C_A_TYPE of U0 : label is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of U0 : label is 8; attribute C_B_TYPE : integer; attribute C_B_TYPE of U0 : label is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of U0 : label is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of U0 : label is 8; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of U0 : label is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of U0 : label is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of U0 : label is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of U0 : label is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of U0 : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 3; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of U0 : label is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of U0 : label is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of U0 : label is 15; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of U0 : label is 0; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of U0 : label is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of U0 : label is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of U0 : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "kintexu"; attribute c_optimize_goal : integer; attribute c_optimize_goal of U0 : label is 1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 port map ( A(7 downto 0) => A(7 downto 0), B(7 downto 0) => B(7 downto 0), CE => '1', CLK => CLK, P(15 downto 0) => P(15 downto 0), PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE;
bsd-3-clause
90be4405bc79f3817e73b6396a513205
0.936496
1.855641
false
false
false
false
MartinCura/SistDig-TP4
sin_usar/Contador/bcd.vhd
1
680
library IEEE; use IEEE.std_logic_1164.all; -- Contador BCD 0-9 con flag entity bcd is port ( clk: in std_logic; rst: in std_logic; ena: in std_logic; q: out std_logic_vector(3 downto 0); c: out std_logic -- Flag de carry ); end; architecture bcd_arq of bcd is signal rst_aux: std_logic := '0'; signal q_aux: std_logic_vector(3 downto 0) := "0000"; begin -- Salida q <= q_aux; -- Flag de carry c <= q_aux(0) and q_aux(3); -- Si pasa el 9, reset rst_aux <= rst or (q_aux(1) and q_aux(3)); Contador: entity work.contador4b port map( clk => clk, rst => rst_aux, ena => ena, q => q_aux ); end;
gpl-3.0
5703bd05ade4c897f4ea292ffaee5f62
0.564706
2.615385
false
false
false
false
MartinCura/SistDig-TP4
sin_usar/control_unit (idea).vhd
1
625
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity control_unit is Generic ( clock_frec : integer := 50 -- MHz ); Port ( clock :in STD_LOGIC; -- 100MHz/50MHz reset :in STD_LOGIC; en :in STD_LOGIC; ); end entity control_unit; architecture behavioral of control_unit is type state_t is (INIT, ); signal state: state_t := INIT; begin SYNC_PROC : process (clock, reset) begin if reset = '1' then state <= INIT; elsif (clk’event and clk=’l’) then case state is when INIT => when => end process;
gpl-3.0
1e957964a6c20b2998fe58c7e80c425a
0.555735
3.438889
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado-hls/gcd/solution1/syn/vhdl/gcd_gcd_bus_s_axi.vhd
3
16,375
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2018.2 -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity gcd_gcd_bus_s_axi is generic ( C_S_AXI_ADDR_WIDTH : INTEGER := 6; C_S_AXI_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; a :out STD_LOGIC_VECTOR(15 downto 0); b :out STD_LOGIC_VECTOR(15 downto 0); pResult :in STD_LOGIC_VECTOR(15 downto 0); pResult_ap_vld :in STD_LOGIC ); end entity gcd_gcd_bus_s_axi; -- ------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/COH) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x10 : Data signal of a -- bit 15~0 - a[15:0] (Read/Write) -- others - reserved -- 0x14 : reserved -- 0x18 : Data signal of b -- bit 15~0 - b[15:0] (Read/Write) -- others - reserved -- 0x1c : reserved -- 0x20 : Data signal of pResult -- bit 15~0 - pResult[15:0] (Read) -- others - reserved -- 0x24 : Control signal of pResult -- bit 0 - pResult_ap_vld (Read/COR) -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of gcd_gcd_bus_s_axi is type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states signal wstate : states := wrreset; signal rstate : states := rdreset; signal wnext, rnext: states; constant ADDR_AP_CTRL : INTEGER := 16#00#; constant ADDR_GIE : INTEGER := 16#04#; constant ADDR_IER : INTEGER := 16#08#; constant ADDR_ISR : INTEGER := 16#0c#; constant ADDR_A_DATA_0 : INTEGER := 16#10#; constant ADDR_A_CTRL : INTEGER := 16#14#; constant ADDR_B_DATA_0 : INTEGER := 16#18#; constant ADDR_B_CTRL : INTEGER := 16#1c#; constant ADDR_PRESULT_DATA_0 : INTEGER := 16#20#; constant ADDR_PRESULT_CTRL : INTEGER := 16#24#; constant ADDR_BITS : INTEGER := 6; signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC := '0'; signal int_ap_start : STD_LOGIC := '0'; signal int_auto_restart : STD_LOGIC := '0'; signal int_gie : STD_LOGIC := '0'; signal int_ier : UNSIGNED(1 downto 0) := (others => '0'); signal int_isr : UNSIGNED(1 downto 0) := (others => '0'); signal int_a : UNSIGNED(15 downto 0) := (others => '0'); signal int_b : UNSIGNED(15 downto 0) := (others => '0'); signal int_pResult : UNSIGNED(15 downto 0) := (others => '0'); signal int_pResult_ap_vld : STD_LOGIC; begin -- ----------------------- Instantiation------------------ -- ----------------------- AXI WRITE --------------------- AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then wstate <= wrreset; elsif (ACLK_EN = '1') then wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end if; end process; -- ----------------------- AXI READ ---------------------- ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then rstate <= rdreset; elsif (ACLK_EN = '1') then rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (0 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0'); when ADDR_A_DATA_0 => rdata_data <= RESIZE(int_a(15 downto 0), 32); when ADDR_B_DATA_0 => rdata_data <= RESIZE(int_b(15 downto 0), 32); when ADDR_PRESULT_DATA_0 => rdata_data <= RESIZE(int_pResult(15 downto 0), 32); when ADDR_PRESULT_CTRL => rdata_data <= (0 => int_pResult_ap_vld, others => '0'); when others => rdata_data <= (others => '0'); end case; end if; end if; end if; end process; -- ----------------------- Register logic ---------------- interrupt <= int_gie and (int_isr(0) or int_isr(1)); ap_start <= int_ap_start; a <= STD_LOGIC_VECTOR(int_a); b <= STD_LOGIC_VECTOR(int_b); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (ap_ready = '1') then int_ap_start <= int_auto_restart; -- clear on handshake/auto restart end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_idle <= '0'; elsif (ACLK_EN = '1') then if (true) then int_ap_idle <= ap_idle; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_ready <= '0'; elsif (ACLK_EN = '1') then if (true) then int_ap_ready <= ap_ready; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= "00"; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= UNSIGNED(WDATA(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(0) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(0) = '1' and ap_done = '1') then int_isr(0) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(1) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(1) = '1' and ap_ready = '1') then int_isr(1) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_A_DATA_0) then int_a(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_a(15 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_B_DATA_0) then int_b(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_b(15 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_pResult <= (others => '0'); elsif (ACLK_EN = '1') then if (pResult_ap_vld = '1') then int_pResult <= UNSIGNED(pResult); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_pResult_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (pResult_ap_vld = '1') then int_pResult_ap_vld <= '1'; elsif (ar_hs = '1' and raddr = ADDR_PRESULT_CTRL) then int_pResult_ap_vld <= '0'; -- clear on read end if; end if; end if; end process; -- ----------------------- Memory logic ------------------ end architecture behave;
mit
1e70333b164cacbfda46c5fd08241cc9
0.433771
3.868415
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0_1/design_1_auto_pc_0_sim_netlist.vhdl
3
514,797
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:58:12 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top design_1_auto_pc_0 -prefix -- design_1_auto_pc_0_ design_1_auto_pc_0_sim_netlist.vhdl -- Design : design_1_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[5]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113"; begin Q(0) <= \^q\(0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0); \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => \axaddr_incr[0]_i_1_n_0\ ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => \axaddr_incr[10]_i_1_n_0\ ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \next\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => \axaddr_incr[11]_i_2_n_0\ ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => \axaddr_incr[1]_i_1_n_0\ ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => \axaddr_incr[2]_i_1_n_0\ ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => \axaddr_incr[3]_i_1_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0102" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"262A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"060A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), I3 => \next\, O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => \axaddr_incr[4]_i_1_n_0\ ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => \axaddr_incr[5]_i_1_n_0\ ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => \axaddr_incr[6]_i_1_n_0\ ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => \axaddr_incr[7]_i_1_n_0\ ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => \axaddr_incr[8]_i_1_n_0\ ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => \axaddr_incr[9]_i_1_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[0]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[10]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[11]_i_2_n_0\, Q => \^axaddr_incr_reg[11]_0\(10), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[1]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[2]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[3]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[4]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[5]_i_1_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[6]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[7]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[8]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[9]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \^q\(0), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[2]_0\, I4 => E(0), I5 => \m_payload_i_reg[46]\(9), O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), I5 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \^q\(0), I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \state_reg[1]\(0), Q => \^q\(0), R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(7), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => \m_payload_i_reg[46]\(7), I3 => \m_payload_i_reg[46]\(4), O => \m_axi_awaddr[5]\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[2]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; \m_axi_araddr[5]\ : out STD_LOGIC; \m_axi_araddr[3]\ : out STD_LOGIC; \m_axi_araddr[2]\ : out STD_LOGIC; \m_axi_araddr[1]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC; signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0201020202020202" ) port map ( I0 => Q(0), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[1]\, I1 => Q(6), I2 => Q(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => Q(3), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A262A2A2A2A2A2A" ) port map ( I0 => Q(2), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A060A0A0A0A0A0A" ) port map ( I0 => Q(1), I1 => Q(5), I2 => Q(6), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[1]\, R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1) => \axaddr_incr_reg_n_0_[1]\, DI(0) => \^axaddr_incr_reg[11]_0\(0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(1) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(8), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(9), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[0]_0\, I4 => E(0), I5 => Q(10), O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => \next_pending_r_i_4__0_n_0\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => Q(7), O => \m_axi_araddr[11]\ ); \m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[1]\, I2 => Q(7), I3 => Q(1), O => \m_axi_araddr[1]\ ); \m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => Q(7), I3 => Q(2), O => \m_axi_araddr[2]\ ); \m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => Q(7), I3 => Q(3), O => \m_axi_araddr[3]\ ); \m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => Q(7), I3 => Q(4), O => \m_axi_araddr[5]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__0_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[47]_0\, O => \^incr_next_pending\ ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \next_pending_r_i_4__0_n_0\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, O => \next_pending_r_i_2__0_n_0\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \next_pending_r_i_4__0_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_i : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[7]_0\ : in STD_LOGIC; s_axburst_eq1_reg : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4"; begin Q(1 downto 0) <= \^q\(1 downto 0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AAEA" ) port map ( I0 => sel_first, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(0), I2 => \^m_payload_i_reg[0]_0\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"00CA" ) port map ( I0 => si_rs_arvalid, I1 => m_axi_arready, I2 => \^q\(0), I3 => \^q\(1), O => E(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00005140" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => m_axi_arready, I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[7]_0\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => si_rs_arvalid, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => m_axi_arready, O => r_push_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8FFF8F8F" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => s_ready_i0 ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFFFFCCCECCCE" ) port map ( I0 => si_rs_arvalid, I1 => areset_d1, I2 => \^m_payload_i_reg[0]\, I3 => \^m_payload_i_reg[0]_0\, I4 => m_axi_arready, I5 => sel_first_reg_2, O => sel_first_i ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"003030303E3E3E3E" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(1), I2 => \^q\(0), I3 => m_axi_arready, I4 => s_axburst_eq1_reg, I5 => \cnt_read_reg[2]_rep__0\, O => \next_state__0\(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00AAB000" ) port map ( I0 => \cnt_read_reg[2]_rep__0\, I1 => s_axburst_eq1_reg, I2 => m_axi_arready, I3 => \^m_payload_i_reg[0]_0\, I4 => \^m_payload_i_reg[0]\, O => \next_state__0\(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \wrap_boundary_axaddr_r_reg[11]\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; si_rs_bready : in STD_LOGIC; bvalid_i_reg_0 : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"EEFEFFFFFFFFEEFE" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \bresp_cnt_reg[7]\(6), I2 => \bresp_cnt_reg[7]\(0), I3 => \memory_reg[3][0]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF6FFFF" ) port map ( I0 => \bresp_cnt_reg[7]\(1), I1 => \memory_reg[3][1]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(4), I3 => \bresp_cnt_reg[7]\(5), I4 => mhandshake_r, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000D00DD00DD00D" ) port map ( I0 => \memory_reg[3][0]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(0), I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \^cnt_read_reg[1]_rep__0_0\, I5 => \^cnt_read_reg[0]_rep__0_0\, O => \bresp_cnt[7]_i_5_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bready, I3 => bvalid_i_reg_0, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => shandshake_r, I3 => Q(1), I4 => Q(0), I5 => bvalid_i_reg_0, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => shandshake_r, I2 => Q(0), O => D(0) ); \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000041004141" ) port map ( I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\, I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, I5 => \memory_reg[3][0]_srl4_i_3_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFFFFFFFFFB" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(5), I3 => \bresp_cnt_reg[7]\(4), I4 => \memory_reg[3][1]_srl4_n_0\, I5 => \bresp_cnt_reg[7]\(1), O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); mhandshake : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A69A" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => shandshake_r, I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(0), I3 => \^q\(1), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal wr_en0 : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19"; begin \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; \cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => s_ready_i_reg, I3 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9AAAA6A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAA6AA9AAAAAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"99AA99AA99AA55A6" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_1\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_2\, I3 => \cnt_read[4]_i_3__0_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_2\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read[4]_i_5_n_0\, I3 => \cnt_read_reg[4]_rep__0_0\, I4 => si_rs_rready, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6000E000FFFFFFFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, I5 => m_axi_rvalid, O => \cnt_read[4]_i_5_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__3_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_1\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"9FFF1FFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA0AAA0AAAAAAA" ) port map ( I0 => m_axi_rvalid, I1 => \cnt_read_reg[0]_rep__3_n_0\, I2 => \^cnt_read_reg[4]_rep__2_0\, I3 => \^cnt_read_reg[4]_rep__2_1\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[2]_rep__2_n_0\, O => wr_en0 ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"40C0C000" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[2]_rep__2_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); s_ready_i_reg : in STD_LOGIC; r_push_r : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"DB24" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7F0080FEFF0100" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9A999AAA" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA2AAA2AAA" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => r_push_r, I4 => \^m_valid_i_reg\, I5 => si_rs_rready, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => r_push_r, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => \cnt_read_reg[0]_rep__1_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"80808080FF808080" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read_reg[3]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2\, I5 => \cnt_read_reg[0]_rep__3\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__1_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"BFEEAAAAAAAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__3_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => \cnt_read_reg[1]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[4]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \axlen_cnt_reg[7]_1\ : out STD_LOGIC; \next\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axburst_eq0_reg : out STD_LOGIC; incr_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[7]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wrap_next_pending : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[7]\ : STD_LOGIC; signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \^next\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \state[0]_i_1_n_0\ : STD_LOGIC; signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\; \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; \next\ <= \^next\; sel_first_i <= \^sel_first_i\; \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(2), I2 => \^axlen_cnt_reg[7]_0\, I3 => si_rs_awvalid, I4 => \^axlen_cnt_reg[7]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0400FFFF04000400" ) port map ( I0 => \^q\(1), I1 => si_rs_awvalid, I2 => \^q\(0), I3 => \m_payload_i_reg[46]\(1), I4 => \axlen_cnt_reg[0]_0\(0), I5 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[0]\(0) ); \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^next\, O => \axaddr_wrap_reg[11]\(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF04" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]\, I3 => \^next\, I4 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[7]_1\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"88008888A800A8A8" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, I2 => m_axi_awready, I3 => \cnt_read_reg[0]_rep__0\, I4 => \cnt_read_reg[1]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF404" ) port map ( I0 => \^e\(0), I1 => next_pending_r_reg, I2 => \^next\, I3 => \axlen_cnt_reg[7]_2\, I4 => \m_payload_i_reg[47]\, O => \^incr_next_pending\ ); next_pending_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F3F3FFFF51000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \^next\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => \^incr_next_pending\, I1 => \^sel_first_i\, I2 => \m_payload_i_reg[46]\(0), I3 => wrap_next_pending, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => \^incr_next_pending\, I1 => \m_payload_i_reg[46]\(0), I2 => \^sel_first_i\, I3 => wrap_next_pending, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first_0, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF04FFFFFF04FF04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, I3 => areset_d1, I4 => \^next\, I5 => sel_first_reg_1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => \state[0]_i_2_n_0\, I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), O => \state[0]_i_1_n_0\ ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00F000F055750000" ) port map ( I0 => m_axi_awready, I1 => s_axburst_eq1_reg_0, I2 => \cnt_read_reg[1]_rep__0\, I3 => \cnt_read_reg[0]_rep__0\, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \state[0]_i_2_n_0\ ); \state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0C0CAE0000000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]\, I5 => \^axlen_cnt_reg[7]_0\, O => \state[1]_i_1__0_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^axlen_cnt_reg[7]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^axlen_cnt_reg[7]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is port ( wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \next\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); sel_first_reg_3 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin sel_first_reg_0 <= \^sel_first_reg_0\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(0), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(0), I3 => \next\, I4 => \m_payload_i_reg[47]\(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(10), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(10), I3 => \next\, I4 => \m_payload_i_reg[47]\(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(11), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(11), I3 => \next\, I4 => \m_payload_i_reg[47]\(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4_n_0\, I1 => wrap_cnt_r(3), I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(1), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(1), I3 => \next\, I4 => \m_payload_i_reg[47]\(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(2), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(2), I3 => \next\, I4 => \m_payload_i_reg[47]\(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(3), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(3), I3 => \next\, I4 => \m_payload_i_reg[47]\(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[47]\(13), I2 => \m_payload_i_reg[47]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(4), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(4), I3 => \next\, I4 => \m_payload_i_reg[47]\(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(5), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(5), I3 => \next\, I4 => \m_payload_i_reg[47]\(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(6), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(6), I3 => \next\, I4 => \m_payload_i_reg[47]\(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(7), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(7), I3 => \next\, I4 => \m_payload_i_reg[47]\(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(8), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(8), I3 => \next\, I4 => \m_payload_i_reg[47]\(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(9), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(9), I3 => \next\, I4 => \m_payload_i_reg[47]\(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => \m_payload_i_reg[47]\(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => \m_payload_i_reg[47]\(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => \m_payload_i_reg[47]\(17), O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => \m_payload_i_reg[47]\(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(2), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(3), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[47]\(5), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(5), I3 => \m_payload_i_reg[47]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(9) ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]_0\, I1 => next_pending_r_reg_n_0, I2 => \next\, I3 => \next_pending_r_i_2__1_n_0\, I4 => E(0), O => \^wrap_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_awvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^wrap_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => wrap_cnt(1) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cnt(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is port ( sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); sel_first_i : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; sel_first_reg_5 : in STD_LOGIC; sel_first_reg_6 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4__0_n_0\, I1 => \wrap_cnt_r_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => Q(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => Q(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => Q(17), O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => Q(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(1), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[1]\, I3 => Q(14), I4 => sel_first_reg_6, O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(2), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[2]\, I3 => Q(14), I4 => sel_first_reg_5, O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(3), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[3]\, I3 => Q(14), I4 => sel_first_reg_4, O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(5), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[5]\, I3 => Q(14), I4 => sel_first_reg_3, O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(9) ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => \next_pending_r_i_2__2_n_0\, I4 => E(0), O => wrap_next_pending ); \next_pending_r_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_arvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__2_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_n_0, R => '0' ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq1_reg ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1__0_n_0\ ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1__0_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[0]\ : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2__0_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2__0_n_0\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2__0_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_0\(0) ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2__0_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_0\(1) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^axaddr_offset_r_reg[3]\, R => \^m_valid_i_reg_0\ ); next_pending_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r_reg[3]\(0) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => \wrap_cnt_r_reg[3]\(1) ); \wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_1\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2__0_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5__0_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5__0_n_0\ ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset_0\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_0\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3__0_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(1), O => \^axaddr_offset\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2_n_0\ ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(2), O => \^axaddr_offset\(1) ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => D(1) ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5_n_0\ ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2_n_0\ ); \wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[4]_rep__0\, O => \cnt_read_reg[2]_rep__0\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \cnt_read_reg[4]_rep__0\, I3 => \^skid_buffer_reg[0]_0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \cnt_read_reg[4]_rep__0\, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_5, bvalid_i_reg_0 => \^si_rs_bvalid\, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(1), I1 => \bresp_cnt_reg__0\(0), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_6_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_6_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_6_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_5, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACEAAAA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[0]\, I1 => m_axi_bresp(0), I2 => m_axi_bresp(1), I3 => \s_bresp_acc_reg_n_0_[1]\, I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EC" ) port map ( I0 => m_axi_bresp(1), I1 => \s_bresp_acc_reg_n_0_[1]\, I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^si_rs_bvalid\, I1 => si_rs_bready, O => shandshake ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \m_payload_i_reg[47]_1\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_16 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd port map ( E(0) => E(0), Q(0) => Q(0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14, \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_15, \m_axi_awaddr[5]\ => incr_cmd_0_n_16, \m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17), \m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12), \m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \next\ => \next\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(0) => \state_reg[1]_0\(0) ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[47]\(15), I2 => s_axburst_eq0, O => \state_reg[1]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), aclk => aclk, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15), \m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_15, sel_first_reg_3 => incr_cmd_0_n_16, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is port ( sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; signal wrap_cmd_0_n_6 : STD_LOGIC; signal wrap_cmd_0_n_7 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17"; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(10 downto 8) => Q(18 downto 16), Q(7 downto 5) => Q(14 downto 12), Q(4) => Q(5), Q(3 downto 0) => Q(3 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_11, \m_axi_araddr[1]\ => incr_cmd_0_n_15, \m_axi_araddr[2]\ => incr_cmd_0_n_14, \m_axi_araddr[3]\ => incr_cmd_0_n_13, \m_axi_araddr[5]\ => incr_cmd_0_n_12, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]_0\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_6, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_7, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(18 downto 14) => Q(19 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), s_axburst_eq0_reg => wrap_cmd_0_n_6, s_axburst_eq1_reg => wrap_cmd_0_n_7, sel_first_i => sel_first_i, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_11, sel_first_reg_3 => incr_cmd_0_n_12, sel_first_reg_4 => incr_cmd_0_n_13, sel_first_reg_5 => incr_cmd_0_n_14, sel_first_reg_6 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_1 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_4 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \state_reg[1]_rep_0\, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1, \cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_4 ); transaction_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2, \cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]_0\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_2\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \wrap_second_len_r_reg[1]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_4\ : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \state_reg[1]_rep_2\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is signal \ar.ar_pipe_n_2\ : STD_LOGIC; signal \aw.aw_pipe_n_1\ : STD_LOGIC; signal \aw.aw_pipe_n_90\ : STD_LOGIC; begin \ar.ar_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset_0(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\, \axaddr_offset_r_reg[3]\ => si_rs_arvalid, \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \ar.ar_pipe_n_2\, m_valid_i_reg_1(0) => m_valid_i_reg(0), next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_ready_i0 => s_ready_i0, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_2\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\, \wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0) ); \aw.aw_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 port map ( D(1 downto 0) => D(1 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\, \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \aw.aw_pipe_n_1\, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_0\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \b.b_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \r.r_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), \cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\, r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); r_rlast : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_10 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal ar_cmd_fsm_0_n_8 : STD_LOGIC; signal ar_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_10 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_3 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push_r_reg\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); ar_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm port map ( D(0) => ar_cmd_fsm_0_n_6, E(0) => ar_cmd_fsm_0_n_8, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[46]\(0) => Q(18), \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, m_valid_i0 => m_valid_i0, r_push_r_reg => \^r_push_r_reg\, s_axburst_eq1_reg => cmd_translator_0_n_10, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => s_ready_i0, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_9, sel_first_reg_0 => ar_cmd_fsm_0_n_10, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => cmd_translator_0_n_0, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(19 downto 0) => Q(19 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]\ => cmd_translator_0_n_3, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_8, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_0, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => ar_cmd_fsm_0_n_10, sel_first_reg_3 => ar_cmd_fsm_0_n_9, sel_first_reg_4(0) => ar_cmd_fsm_0_n_16, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_10, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\ => ar_cmd_fsm_0_n_0, \state_reg[1]_rep\ => \^r_push_r_reg\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0), \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); si_rs_awvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_14 : STD_LOGIC; signal aw_cmd_fsm_0_n_15 : STD_LOGIC; signal aw_cmd_fsm_0_n_16 : STD_LOGIC; signal aw_cmd_fsm_0_n_2 : STD_LOGIC; signal aw_cmd_fsm_0_n_8 : STD_LOGIC; signal aw_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_12 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \next\ : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); aw_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm port map ( D(0) => wrap_cnt(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14, \axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8, \axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\, \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\, \axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2, \axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[46]\(2) => Q(18), \m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, s_axburst_eq0_reg => aw_cmd_fsm_0_n_9, s_axburst_eq1_reg => aw_cmd_fsm_0_n_12, s_axburst_eq1_reg_0 => cmd_translator_0_n_12, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_15, sel_first_reg_0 => aw_cmd_fsm_0_n_16, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(0) => cmd_translator_0_n_5, S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12, \m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_16, sel_first_reg_2 => aw_cmd_fsm_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_14, \state_reg[0]_rep\ => aw_cmd_fsm_0_n_2, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8, \state_reg[1]_rep\ => cmd_translator_0_n_12, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0), \wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awready : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_10\ : STD_LOGIC; signal \RD.ar_channel_0_n_11\ : STD_LOGIC; signal \RD.ar_channel_0_n_16\ : STD_LOGIC; signal \RD.ar_channel_0_n_3\ : STD_LOGIC; signal \RD.ar_channel_0_n_4\ : STD_LOGIC; signal \RD.ar_channel_0_n_46\ : STD_LOGIC; signal \RD.ar_channel_0_n_47\ : STD_LOGIC; signal \RD.ar_channel_0_n_48\ : STD_LOGIC; signal \RD.ar_channel_0_n_49\ : STD_LOGIC; signal \RD.ar_channel_0_n_5\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_132 : STD_LOGIC; signal SI_REG_n_133 : STD_LOGIC; signal SI_REG_n_134 : STD_LOGIC; signal SI_REG_n_135 : STD_LOGIC; signal SI_REG_n_136 : STD_LOGIC; signal SI_REG_n_137 : STD_LOGIC; signal SI_REG_n_138 : STD_LOGIC; signal SI_REG_n_139 : STD_LOGIC; signal SI_REG_n_140 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_149 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_155 : STD_LOGIC; signal SI_REG_n_156 : STD_LOGIC; signal SI_REG_n_157 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_181 : STD_LOGIC; signal SI_REG_n_182 : STD_LOGIC; signal SI_REG_n_26 : STD_LOGIC; signal SI_REG_n_64 : STD_LOGIC; signal SI_REG_n_8 : STD_LOGIC; signal SI_REG_n_82 : STD_LOGIC; signal \WR.aw_channel_0_n_0\ : STD_LOGIC; signal \WR.aw_channel_0_n_10\ : STD_LOGIC; signal \WR.aw_channel_0_n_15\ : STD_LOGIC; signal \WR.aw_channel_0_n_3\ : STD_LOGIC; signal \WR.aw_channel_0_n_4\ : STD_LOGIC; signal \WR.aw_channel_0_n_47\ : STD_LOGIC; signal \WR.aw_channel_0_n_48\ : STD_LOGIC; signal \WR.aw_channel_0_n_49\ : STD_LOGIC; signal \WR.aw_channel_0_n_50\ : STD_LOGIC; signal \WR.aw_channel_0_n_9\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw.aw_pipe/p_1_in\ : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel port map ( D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), E(0) => \ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(31 downto 20) => s_arid(11 downto 0), Q(19 downto 16) => si_rs_arlen(3 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_82, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_46\, S(2) => \RD.ar_channel_0_n_47\, S(1) => \RD.ar_channel_0_n_48\, S(0) => \RD.ar_channel_0_n_49\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_161, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_165, \cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\, \m_payload_i_reg[3]\(3) => SI_REG_n_132, \m_payload_i_reg[3]\(2) => SI_REG_n_133, \m_payload_i_reg[3]\(1) => SI_REG_n_134, \m_payload_i_reg[3]\(0) => SI_REG_n_135, \m_payload_i_reg[47]\ => SI_REG_n_64, \m_payload_i_reg[47]_0\ => SI_REG_n_167, \m_payload_i_reg[5]\ => SI_REG_n_166, \m_payload_i_reg[6]\(6) => SI_REG_n_176, \m_payload_i_reg[6]\(5) => SI_REG_n_177, \m_payload_i_reg[6]\(4) => SI_REG_n_178, \m_payload_i_reg[6]\(3) => SI_REG_n_179, \m_payload_i_reg[6]\(2) => SI_REG_n_180, \m_payload_i_reg[6]\(1) => SI_REG_n_181, \m_payload_i_reg[6]\(0) => SI_REG_n_182, \m_payload_i_reg[7]\(3) => SI_REG_n_136, \m_payload_i_reg[7]\(2) => SI_REG_n_137, \m_payload_i_reg[7]\(1) => SI_REG_n_138, \m_payload_i_reg[7]\(0) => SI_REG_n_139, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push_r_reg => \RD.ar_channel_0_n_3\, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => \ar.ar_pipe/s_ready_i0\, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\, \wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\, \wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0), \wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157 ); \RD.r_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_168, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\ ); SI_REG: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_26, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_132, \axaddr_incr_reg[3]\(2) => SI_REG_n_133, \axaddr_incr_reg[3]\(1) => SI_REG_n_134, \axaddr_incr_reg[3]\(0) => SI_REG_n_135, \axaddr_incr_reg[7]\(3) => SI_REG_n_136, \axaddr_incr_reg[7]\(2) => SI_REG_n_137, \axaddr_incr_reg[7]\(1) => SI_REG_n_138, \axaddr_incr_reg[7]\(0) => SI_REG_n_139, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\ => SI_REG_n_154, \axaddr_offset_r_reg[2]_0\ => SI_REG_n_166, \axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\, \axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\, \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\, \axlen_cnt_reg[3]\ => SI_REG_n_8, \axlen_cnt_reg[3]_0\ => SI_REG_n_64, b_push => b_push, \cnt_read_reg[2]_rep__0\ => SI_REG_n_168, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\, \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\, next_pending_r_reg => SI_REG_n_155, next_pending_r_reg_0 => SI_REG_n_167, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0), \s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_82, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), s_ready_i0 => \ar.ar_pipe/s_ready_i0\, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \WR.aw_channel_0_n_4\, \state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_0\, \state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182, \wrap_cnt_r_reg[2]\ => SI_REG_n_149, \wrap_cnt_r_reg[2]_0\ => SI_REG_n_161, \wrap_cnt_r_reg[3]\ => SI_REG_n_153, \wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157, \wrap_cnt_r_reg[3]_1\ => SI_REG_n_165, \wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\, \wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\, \wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0) ); \WR.aw_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, Q(31 downto 20) => s_awid(11 downto 0), Q(19 downto 16) => si_rs_awlen(3 downto 0), Q(15) => si_rs_awburst(1), Q(14) => SI_REG_n_26, Q(13 downto 12) => si_rs_awsize(1 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_149, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_153, \axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\, \axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[47]\ => SI_REG_n_8, \m_payload_i_reg[47]_0\ => SI_REG_n_155, \m_payload_i_reg[5]\ => SI_REG_n_154, \m_payload_i_reg[6]\(6) => SI_REG_n_169, \m_payload_i_reg[6]\(5) => SI_REG_n_170, \m_payload_i_reg[6]\(4) => SI_REG_n_171, \m_payload_i_reg[6]\(3) => SI_REG_n_172, \m_payload_i_reg[6]\(2) => SI_REG_n_173, \m_payload_i_reg[6]\(1) => SI_REG_n_174, \m_payload_i_reg[6]\(0) => SI_REG_n_175, si_rs_awvalid => si_rs_awvalid, \state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\, \wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1) ); \WR.b_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0) ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of design_1_auto_pc_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of design_1_auto_pc_0 : entity is "design_1_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0 : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of design_1_auto_pc_0 : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; end design_1_auto_pc_0; architecture STRUCTURE of design_1_auto_pc_0 is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
mit
a402808f45f9bd187b3bf8652441197a
0.534356
2.545501
false
false
false
false
natsutan/NPU
fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_gen_0/synth/mult_gen_0.vhd
1
5,688
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:mult_gen:12.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY mult_gen_v12_0_12; USE mult_gen_v12_0_12.mult_gen_v12_0_12; ENTITY mult_gen_0 IS PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(7 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END mult_gen_0; ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes"; COMPONENT mult_gen_v12_0_12 IS GENERIC ( C_VERBOSITY : INTEGER; C_MODEL_TYPE : INTEGER; C_OPTIMIZE_GOAL : INTEGER; C_XDEVICEFAMILY : STRING; C_HAS_CE : INTEGER; C_HAS_SCLR : INTEGER; C_LATENCY : INTEGER; C_A_WIDTH : INTEGER; C_A_TYPE : INTEGER; C_B_WIDTH : INTEGER; C_B_TYPE : INTEGER; C_OUT_HIGH : INTEGER; C_OUT_LOW : INTEGER; C_MULT_TYPE : INTEGER; C_CE_OVERRIDES_SCLR : INTEGER; C_CCM_IMP : INTEGER; C_B_VALUE : STRING; C_HAS_ZERO_DETECT : INTEGER; C_ROUND_OUTPUT : INTEGER; C_ROUND_PT : INTEGER ); PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(7 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); CE : IN STD_LOGIC; SCLR : IN STD_LOGIC; P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT mult_gen_v12_0_12; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF mult_gen_0_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF mult_gen_0_arch : ARCHITECTURE IS "mult_gen_0,mult_gen_v12_0_12,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF mult_gen_0_arch: ARCHITECTURE IS "mult_gen_0,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=3,C_A_WIDTH=8,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=0,C_OUT_HIGH=23,C_OUT_LOW=8,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA"; BEGIN U0 : mult_gen_v12_0_12 GENERIC MAP ( C_VERBOSITY => 0, C_MODEL_TYPE => 0, C_OPTIMIZE_GOAL => 1, C_XDEVICEFAMILY => "kintexu", C_HAS_CE => 0, C_HAS_SCLR => 0, C_LATENCY => 3, C_A_WIDTH => 8, C_A_TYPE => 1, C_B_WIDTH => 16, C_B_TYPE => 0, C_OUT_HIGH => 23, C_OUT_LOW => 8, C_MULT_TYPE => 0, C_CE_OVERRIDES_SCLR => 0, C_CCM_IMP => 0, C_B_VALUE => "10000001", C_HAS_ZERO_DETECT => 0, C_ROUND_OUTPUT => 0, C_ROUND_PT => 0 ) PORT MAP ( CLK => CLK, A => A, B => B, CE => '1', SCLR => '0', P => P ); END mult_gen_0_arch;
bsd-3-clause
bbdaf917d15cca409a5783ee0bed3a82
0.67827
3.345882
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/iir/bq/filter_out_data_controller.vhd
1
7,015
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.filter_shared_package.all; entity filter_out_data_controller is generic ( BIQUADS : natural := B; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( clk : in std_logic; rstn : in std_logic; cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); cnt_delay_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_delay_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); y_input : in std_logic; input_ok : in std_logic; valid_delay : in std_logic; y_rdaddr : out Y_ADD_T; y_rden : out std_logic; y_wraddr : out Y_ADD_T; y_wren : out std_logic ); end filter_out_data_controller; architecture behaviour_dataflow of filter_out_data_controller is constant MAC_BIQUAD : natural := MAC_FILTER_CH/BIQUADS; -- Number of y pages required for given number of biquads:2*BIQUADS+1 constant MIN_COUNT : natural := 0; constant MAX_COUNT : natural := 2*BIQUADS+1; type my_unsigned_array_t is array(0 to MAC_BIQUAD-1) of unsigned(natural(ceil(log2(real(MAX_COUNT+1))))-1 downto 0); signal pagecntr_arr_s : my_unsigned_array_t; signal mac_cnt_s : integer range 0 to MAC_BIQUAD; signal cntr_s, newcntr_s, finalcntr_s : unsigned(natural(ceil(log2(real(MAX_COUNT+1))))-1 downto 0); signal mod_s : std_logic; signal page_s : unsigned(natural(ceil(log2(real(MAX_COUNT))))-1 downto 0); signal y_mod_page_s : std_logic_vector(natural(ceil(log2(real(MAX_COUNT))))-1 downto 0); -- log2(2*b+1) downto 0 signal y_mod_page_delay_s : std_logic_vector(natural(ceil(log2(real(MAX_COUNT))))-1 downto 0); -- log2(2*b+1) downto 0 signal enable_s, getnext_y_page_s : std_logic; begin process (clk, rstn) is begin if (rstn = '0') then enable_s <= '0'; getnext_y_page_s <= '0'; elsif (clk = '1' and clk'event) then enable_s <= '0'; if (cnt_ch = std_logic_vector(to_unsigned(CHANNELS-2, cnt_ch'length))) then -- Donot get new y page for rms and mean value iteration if (cnt_mac = std_logic_vector(to_unsigned(MAC_FILTER_CH-1, cnt_mac'length))) then getnext_y_page_s <= '0'; end if; if getnext_y_page_s = '1' then -- enable the y page counter enable_s <= '1'; end if; end if; if (cnt_ch = std_logic_vector(to_unsigned(CHANNELS-1, cnt_ch'length))) then -- MAC_FILTER_CH + RMS_CH_EN+MEAN_CH_EN(1x RMS, 1x MEAN) mac operations if (cnt_mac = std_logic_vector(to_unsigned(MAC_FILTER_CH + RMS_CH_EN+MEAN_CH_EN - 1, cnt_mac'length))) then if (input_ok = '1') then -- get new y page getnext_y_page_s <= '1'; end if; end if; end if; end if; end process; -- Modulous-MAC_BIQUAD counter used for selecting mac operation MAC_Counter_Memzing : process (clk, rstn) begin if rstn = '0' then mac_cnt_s <= 0; elsif (rising_edge(clk)) then if(enable_s = '1') then mac_cnt_s <= mac_cnt_s + 1; if(mac_cnt_s = MAC_BIQUAD-1) then mac_cnt_s <= 0; end if; end if; end if; end process MAC_Counter_Memzing; -- Actual page counting(modulous) operation Next_Page_Counter : block begin -- Select a page counter cntr_s <= pagecntr_arr_s(mac_cnt_s); -- Increment the selected counter newcntr_s <= cntr_s + 1; -- Modulous operation mod_s <= '1' when (newcntr_s = MAX_COUNT) else '0'; with mod_s select finalcntr_s <= newcntr_s when '0', to_unsigned(0,finalcntr_s'length) when others; end block Next_Page_Counter; -- Page counter registers Page_Counter_Regs_Memzing : process (clk, rstn) begin if rstn = '0' then -- rstn the five page counters to default values pagecntr_arr_s(0) <= to_unsigned(2*BIQUADS,pagecntr_arr_s(0)'length); pagecntr_arr_s(1) <= to_unsigned(BIQUADS-1,pagecntr_arr_s(1)'length); pagecntr_arr_s(2) <= to_unsigned(2*BIQUADS-1,pagecntr_arr_s(2)'length); pagecntr_arr_s(3) <= to_unsigned(MIN_COUNT,pagecntr_arr_s(3)'length); pagecntr_arr_s(4) <= to_unsigned(BIQUADS,pagecntr_arr_s(4)'length); elsif (rising_edge(clk)) then if(enable_s = '1') then -- Update selected page counter register pagecntr_arr_s(mac_cnt_s) <= finalcntr_s; end if; end if; end process Page_Counter_Regs_Memzing; -- Next page based on current mac operation page_s <= pagecntr_arr_s(mac_cnt_s); Read_Y_Memory : block begin y_mod_page_s <= std_logic_vector(page_s); y_rdaddr <= std_logic_vector(resize(unsigned(y_mod_page_s) * to_unsigned(CHANNELS,cnt_ch'length), y_rdaddr'length)+ unsigned(cnt_ch)); -- p*C + c y_rden <= not y_input; end block Read_Y_Memory; Write_Y_Memory : block begin y_mod_page_delay_s <= std_logic_vector(pagecntr_arr_s(2)); y_wraddr <= std_logic_vector(resize(unsigned(y_mod_page_delay_s) * to_unsigned(CHANNELS,cnt_delay_ch'length), y_wraddr'length) + unsigned(cnt_delay_ch)); -- p*C + c Y_Wren_Memless : process(cnt_delay_mac,valid_delay) variable tmp_cnt_delay_mac : unsigned(cnt_delay_mac'range); begin tmp_cnt_delay_mac := unsigned(cnt_delay_mac)+1; y_wren <= '0'; -- end of biquad 0,1,2,3,4... if(((tmp_cnt_delay_mac) mod (MAC_BIQUAD) = 0) and tmp_cnt_delay_mac <= MAC_FILTER_CH) then y_wren <= valid_delay; end if; end process Y_Wren_Memless; end block Write_Y_Memory; end behaviour_dataflow;
mit
a41394857b9bc3def7fa309b91eeeeb6
0.542837
3.366123
false
false
false
false
besm6/micro-besm
tests/2901/vhdl/test_vectors_2901.vhdl
1
135,685
-------------------------------------------------------------------------------- -- -- AM2901 Benchmark -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Jan 1, 1992 -- -- Modified by : Champaka Ramachandran -- -- Modified on : Sept 16, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran 16 Sept,92 ZYCAD -- Functionality yes Champaka Ramachandran 16 Sept,92 ZYCAD -------------------------------------------------------------------------------- use work.types.all; use work.MVL7_functions.all; --some binary functions use work.synthesis_types.all; --hints for synthesis entity testbench is end; architecture A of testbench is component AM2901 port ( I : in MVL7_vector(8 downto 0); Aadd, Badd : in integer range 0 to 15; D : in MVL7_vector(3 downto 0); Y : out MVL7_vector(3 downto 0); RAM0, RAM3, Q0, Q3 : in MVL7; RAM0out, RAM3out, Q0out, Q3out : out MVL7; CLK : in clock; C0 : in MVL7; OEbar : in MVL7; C4, Gbar, Pbar, OVR, F3, F30 : out MVL7 ); end component; signal I : MVL7_vector(8 downto 0); signal Aadd, Badd : integer range 0 to 15; signal D : MVL7_vector(3 downto 0); signal Y : MVL7_vector(3 downto 0); signal RAM0, RAM3, Q0, Q3 : MVL7; signal RAM0out, RAM3out, Q0out, Q3out : MVL7; signal CLK : clock; signal C0 : MVL7; signal OEbar : MVL7; signal C4, Gbar, Pbar, OVR, F3, F30 : MVL7; for all : AM2901 use entity work.a2901(a2901); begin AM1 : AM2901 port map( I, Aadd, Badd, D, Y, RAM0, RAM3, Q0, Q3, RAM0out, RAM3out, Q0out, Q3out, CLK, C0, OEbar, C4, Gbar, Pbar, OVR, F3, F30 ); process begin -- ************************ -- * * -- * TEST VECTORS FOR ALU * -- * * -- ************************ -- ******** ADDITION R + S ******** -------------------------- clk <= '1'; -- Cycle No: 0 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 1 wait for 1 ns; I <= "001000110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 0 : < Y /= 0000 >" -- Vector No: 0 severity warning; assert (C4 = '0') report "Assert 1 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 2 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 3 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 4 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 5 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 6 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 2 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 3 wait for 1 ns; I <= "001000110"; D <= "0000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 7 : < Y /= 0001 >" -- Vector No: 1 severity warning; assert (C4 = '0') report "Assert 8 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 9 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 10 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 11 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 12 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 13 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 4 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 5 wait for 1 ns; I <= "001000110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 14 : < Y /= 1111 >" -- Vector No: 2 severity warning; assert (C4 = '0') report "Assert 15 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 16 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 17 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 18 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 19 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 20 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 6 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 7 wait for 1 ns; I <= "001000110"; D <= "0000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 21 : < Y /= 0000 >" -- Vector No: 3 severity warning; assert (C4 = '1') report "Assert 22 : < C4 /= 1 >" severity warning; assert (Gbar = '1') report "Assert 23 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 24 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 25 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 26 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 27 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 8 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 9 wait for 1 ns; I <= "001000110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1110") report "Assert 28 : < Y /= 1110 >" -- Vector No: 4 severity warning; assert (C4 = '1') report "Assert 29 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 30 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 31 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 32 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 33 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 34 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 10 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 11 wait for 1 ns; I <= "001000110"; D <= "1111"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 35 : < Y /= 1111 >" -- Vector No: 5 severity warning; assert (C4 = '1') report "Assert 36 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 37 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 38 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 39 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 40 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 41 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 12 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 13 wait for 1 ns; I <= "001000110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 42 : < Y /= 1111 >" -- Vector No: 6 severity warning; assert (C4 = '0') report "Assert 43 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 44 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 45 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 46 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 47 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 48 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 14 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 15 wait for 1 ns; I <= "001000110"; D <= "1111"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 49 : < Y /= 0000 >" -- Vector No: 7 severity warning; assert (C4 = '1') report "Assert 50 : < C4 /= 1 >" severity warning; assert (Gbar = '1') report "Assert 51 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 52 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 53 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 54 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 55 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 16 wait for 1 ns; I <= "000000111"; D <= "0001"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 17 wait for 1 ns; I <= "000000110"; D <= "0001"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0010") report "Assert 56 : < Y /= 0010 >" -- Vector No: 8 severity warning; assert (C4 = '0') report "Assert 57 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 58 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 59 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 60 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 61 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 62 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 18 wait for 1 ns; I <= "000000111"; D <= "0010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 19 wait for 1 ns; I <= "001000110"; D <= "0010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0100") report "Assert 63 : < Y /= 0100 >" -- Vector No: 9 severity warning; assert (C4 = '0') report "Assert 64 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 65 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 66 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 67 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 68 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 69 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 20 wait for 1 ns; I <= "000000111"; D <= "0100"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 21 wait for 1 ns; I <= "001000110"; D <= "0100"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1000") report "Assert 70 : < Y /= 1000 >" -- Vector No: 10 severity warning; assert (C4 = '0') report "Assert 71 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 72 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 73 : < Pbar /= 1 >" severity warning; assert (OVR = '1') report "Assert 74 : < OVR /= 1 >" severity warning; assert (F3 = '1') report "Assert 75 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 76 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 22 wait for 1 ns; I <= "000000111"; D <= "1000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 23 wait for 1 ns; I <= "001000110"; D <= "1000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 77 : < Y /= 0000 >" -- Vector No: 11 severity warning; assert (C4 = '1') report "Assert 78 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 79 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 80 : < Pbar /= 1 >" severity warning; assert (OVR = '1') report "Assert 81 : < OVR /= 1 >" severity warning; assert (F3 = '0') report "Assert 82 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 83 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -- ******** SUBTRACTION S - R ******** -------------------------- clk <= '1'; -- Cycle No: 24 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 25 wait for 1 ns; I <= "001001110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 84 : < Y /= 1111 >" -- Vector No: 12 severity warning; assert (C4 = '0') report "Assert 85 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 86 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 87 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 88 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 89 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 90 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 26 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 27 wait for 1 ns; I <= "001001110"; D <= "0000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 91 : < Y /= 0000 >" -- Vector No: 13 severity warning; assert (C4 = '1') report "Assert 92 : < C4 /= 1 >" severity warning; assert (Gbar = '1') report "Assert 93 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 94 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 95 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 96 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 97 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 28 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 29 wait for 1 ns; I <= "001001110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 98 : < Y /= 0000 >" -- Vector No: 14 severity warning; assert (C4 = '0') report "Assert 99 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 100 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 101 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 102 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 103 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 104 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 30 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 31 wait for 1 ns; I <= "001001110"; D <= "1111"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 105 : < Y /= 0001 >" -- Vector No: 15 severity warning; assert (C4 = '0') report "Assert 106 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 107 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 108 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 109 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 110 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 111 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 32 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 33 wait for 1 ns; I <= "001001110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 112 : < Y /= 1111 >" -- Vector No: 16 severity warning; assert (C4 = '0') report "Assert 113 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 114 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 115 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 116 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 117 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 118 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 34 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 35 wait for 1 ns; I <= "001001110"; D <= "1111"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 119 : < Y /= 0000 >" -- Vector No: 17 severity warning; assert (C4 = '1') report "Assert 120 : < C4 /= 1 >" severity warning; assert (Gbar = '1') report "Assert 121 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 122 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 123 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 124 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 125 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 36 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 37 wait for 1 ns; I <= "001001110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1110") report "Assert 126 : < Y /= 1110 >" -- Vector No: 18 severity warning; assert (C4 = '1') report "Assert 127 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 128 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 129 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 130 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 131 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 132 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 38 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 39 wait for 1 ns; I <= "001001110"; D <= "0000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 133 : < Y /= 1111 >" -- Vector No: 19 severity warning; assert (C4 = '1') report "Assert 134 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 135 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 136 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 137 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 138 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 139 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 40 wait for 1 ns; I <= "000000111"; D <= "0001"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 41 wait for 1 ns; I <= "001001110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 140 : < Y /= 0000 >" -- Vector No: 20 severity warning; assert (C4 = '1') report "Assert 141 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 142 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 143 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 144 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 145 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 146 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 42 wait for 1 ns; I <= "000000111"; D <= "0010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 43 wait for 1 ns; I <= "001001110"; D <= "0001"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 147 : < Y /= 0001 >" -- Vector No: 21 severity warning; assert (C4 = '1') report "Assert 148 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 149 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 150 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 151 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 152 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 153 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 44 wait for 1 ns; I <= "000000111"; D <= "0100"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 45 wait for 1 ns; I <= "001001110"; D <= "0010"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0010") report "Assert 154 : < Y /= 0010 >" -- Vector No: 22 severity warning; assert (C4 = '1') report "Assert 155 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 156 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 157 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 158 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 159 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 160 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 46 wait for 1 ns; I <= "000000111"; D <= "1000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 47 wait for 1 ns; I <= "001001110"; D <= "0100"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0100") report "Assert 161 : < Y /= 0100 >" -- Vector No: 23 severity warning; assert (C4 = '1') report "Assert 162 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 163 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 164 : < Pbar /= 1 >" severity warning; assert (OVR = '1') report "Assert 165 : < OVR /= 1 >" severity warning; assert (F3 = '0') report "Assert 166 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 167 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** SUBTRACTION R - S ******** -------------------------- clk <= '1'; -- Cycle No: 48 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 49 wait for 1 ns; I <= "001010110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 168 : < Y /= 1111 >" -- Vector No: 24 severity warning; assert (C4 = '0') report "Assert 169 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 170 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 171 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 172 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 173 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 174 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 50 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 51 wait for 1 ns; I <= "001010110"; D <= "0000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 175 : < Y /= 0000 >" -- Vector No: 25 severity warning; assert (C4 = '1') report "Assert 176 : < C4 /= 1 >" severity warning; assert (Gbar = '1') report "Assert 177 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 178 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 179 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 180 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 181 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 52 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 53 wait for 1 ns; I <= "001010110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 182 : < Y /= 0000 >" -- Vector No: 26 severity warning; assert (C4 = '0') report "Assert 183 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 184 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 185 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 186 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 187 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 188 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 54 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 55 wait for 1 ns; I <= "001010110"; D <= "0000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 189 : < Y /= 0001 >" -- Vector No: 27 severity warning; assert (C4 = '0') report "Assert 190 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 191 : < Gbar /= 1 >" severity warning; assert (Pbar = '1') report "Assert 192 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 193 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 194 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 195 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 56 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 57 wait for 1 ns; I <= "001010110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 196 : < Y /= 1111 >" -- Vector No: 28 severity warning; assert (C4 = '0') report "Assert 197 : < C4 /= 0 >" severity warning; assert (Gbar = '1') report "Assert 198 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 199 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 200 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 201 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 202 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 58 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 59 wait for 1 ns; I <= "001010110"; D <= "1111"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 203 : < Y /= 0000 >" -- Vector No: 29 severity warning; assert (C4 = '1') report "Assert 204 : < C4 /= 1 >" severity warning; assert (Gbar = '1') report "Assert 205 : < Gbar /= 1 >" severity warning; assert (Pbar = '0') report "Assert 206 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 207 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 208 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 209 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 60 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 61 wait for 1 ns; I <= "001010110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1110") report "Assert 210 : < Y /= 1110 >" -- Vector No: 30 severity warning; assert (C4 = '1') report "Assert 211 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 212 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 213 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 214 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 215 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 216 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 62 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 63 wait for 1 ns; I <= "001010110"; D <= "1111"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 217 : < Y /= 1111 >" -- Vector No: 31 severity warning; assert (C4 = '1') report "Assert 218 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 219 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 220 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 221 : < OVR /= 0 >" severity warning; assert (F3 = '1') report "Assert 222 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 223 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 64 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 65 wait for 1 ns; I <= "001010110"; D <= "0001"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 224 : < Y /= 0000 >" -- Vector No: 32 severity warning; assert (C4 = '1') report "Assert 225 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 226 : < Gbar /= 0 >" severity warning; assert (Pbar = '0') report "Assert 227 : < Pbar /= 0 >" severity warning; assert (OVR = '0') report "Assert 228 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 229 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 230 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 66 wait for 1 ns; I <= "000000111"; D <= "0001"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 67 wait for 1 ns; I <= "001010110"; D <= "0010"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 231 : < Y /= 0001 >" -- Vector No: 33 severity warning; assert (C4 = '1') report "Assert 232 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 233 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 234 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 235 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 236 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 237 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 68 wait for 1 ns; I <= "000000111"; D <= "0010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 69 wait for 1 ns; I <= "001010110"; D <= "0100"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0010") report "Assert 238 : < Y /= 0010 >" -- Vector No: 34 severity warning; assert (C4 = '1') report "Assert 239 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 240 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 241 : < Pbar /= 1 >" severity warning; assert (OVR = '0') report "Assert 242 : < OVR /= 0 >" severity warning; assert (F3 = '0') report "Assert 243 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 244 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 70 wait for 1 ns; I <= "000000111"; D <= "0100"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 71 wait for 1 ns; I <= "001010110"; D <= "1000"; C0 <= '1'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0100") report "Assert 245 : < Y /= 0100 >" -- Vector No: 35 severity warning; assert (C4 = '1') report "Assert 246 : < C4 /= 1 >" severity warning; assert (Gbar = '0') report "Assert 247 : < Gbar /= 0 >" severity warning; assert (Pbar = '1') report "Assert 248 : < Pbar /= 1 >" severity warning; assert (OVR = '1') report "Assert 249 : < OVR /= 1 >" severity warning; assert (F3 = '0') report "Assert 250 : < F3 /= 0 >" severity warning; assert (F30 = '0') report "Assert 251 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** OR (R or S) ******** -------------------------- clk <= '1'; -- Cycle No: 72 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 73 wait for 1 ns; I <= "001011110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 252 : < Y /= 0000 >" -- Vector No: 36 severity warning; assert (F3 = '0') report "Assert 253 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 254 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 74 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 75 wait for 1 ns; I <= "001011110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 255 : < Y /= 1111 >" -- Vector No: 37 severity warning; assert (F3 = '1') report "Assert 256 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 257 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 76 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 77 wait for 1 ns; I <= "001011110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 258 : < Y /= 1111 >" -- Vector No: 38 severity warning; assert (F3 = '1') report "Assert 259 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 260 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 78 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 79 wait for 1 ns; I <= "001011110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 261 : < Y /= 1111 >" -- Vector No: 39 severity warning; assert (F3 = '1') report "Assert 262 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 263 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** AND (R and S) ******** -------------------------- clk <= '1'; -- Cycle No: 80 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 81 wait for 1 ns; I <= "001100110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 264 : < Y /= 0000 >" -- Vector No: 40 severity warning; assert (F3 = '0') report "Assert 265 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 266 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 82 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 83 wait for 1 ns; I <= "001100110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 267 : < Y /= 0000 >" -- Vector No: 41 severity warning; assert (F3 = '0') report "Assert 268 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 269 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 84 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 85 wait for 1 ns; I <= "001100110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 270 : < Y /= 1111 >" -- Vector No: 42 severity warning; assert (F3 = '1') report "Assert 271 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 272 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 86 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 87 wait for 1 ns; I <= "001100110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 273 : < Y /= 0000 >" -- Vector No: 43 severity warning; assert (F3 = '0') report "Assert 274 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 275 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -- ******** AND (not(R) and S) ******** -------------------------- clk <= '1'; -- Cycle No: 88 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 89 wait for 1 ns; I <= "001101110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 276 : < Y /= 0000 >" -- Vector No: 44 severity warning; assert (F3 = '0') report "Assert 277 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 278 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 90 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 91 wait for 1 ns; I <= "001101110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 279 : < Y /= 1111 >" -- Vector No: 45 severity warning; assert (F3 = '1') report "Assert 280 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 281 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 92 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 93 wait for 1 ns; I <= "001101110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 282 : < Y /= 0000 >" -- Vector No: 46 severity warning; assert (F3 = '0') report "Assert 283 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 284 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 94 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 95 wait for 1 ns; I <= "001101110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 285 : < Y /= 0000 >" -- Vector No: 47 severity warning; assert (F3 = '0') report "Assert 286 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 287 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -- ******** XOR (R xor S) ******** -------------------------- clk <= '1'; -- Cycle No: 96 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 97 wait for 1 ns; I <= "001110110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 288 : < Y /= 0000 >" -- Vector No: 48 severity warning; assert (F3 = '0') report "Assert 289 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 290 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 98 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 99 wait for 1 ns; I <= "001110110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 291 : < Y /= 1111 >" -- Vector No: 49 severity warning; assert (F3 = '1') report "Assert 292 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 293 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 100 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 101 wait for 1 ns; I <= "001110110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 294 : < Y /= 0000 >" -- Vector No: 50 severity warning; assert (F3 = '0') report "Assert 295 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 296 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 102 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 103 wait for 1 ns; I <= "001110110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 297 : < Y /= 1111 >" -- Vector No: 51 severity warning; assert (F3 = '1') report "Assert 298 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 299 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** XNOR (R xnor S) ******** -------------------------- clk <= '1'; -- Cycle No: 104 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 105 wait for 1 ns; I <= "001111110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 300 : < Y /= 1111 >" -- Vector No: 52 severity warning; assert (F3 = '1') report "Assert 301 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 302 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 106 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 107 wait for 1 ns; I <= "001111110"; D <= "0000"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 303 : < Y /= 0000 >" -- Vector No: 53 severity warning; assert (F3 = '0') report "Assert 304 : < F3 /= 0 >" severity warning; assert (F30 = '1') report "Assert 305 : < F30 /= 1 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 108 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 109 wait for 1 ns; I <= "001111110"; D <= "1111"; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 306 : < Y /= 1111 >" -- Vector No: 54 severity warning; assert (F3 = '1') report "Assert 307 : < F3 /= 1 >" severity warning; assert (F30 = '0') report "Assert 308 : < F30 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ************************ -- * * -- * TEST VECTORS FOR RAM * -- * * -- ************************ -- ******** WRITING 0's AND 1's IN RAM LOCATIONS ******** -------------------------- clk <= '1'; -- Cycle No: 110 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 111 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 309 : < Y /= 0000 >" -- Vector No: 55 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 112 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 113 wait for 1 ns; I <= "001000100"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 310 : < Y /= 0000 >" -- Vector No: 56 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 114 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 115 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 311 : < Y /= 1111 >" -- Vector No: 57 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 116 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 117 wait for 1 ns; I <= "001000100"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 312 : < Y /= 1111 >" -- Vector No: 58 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 118 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 119 wait for 1 ns; I <= "001000100"; Aadd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 313 : < Y /= 0000 >" -- Vector No: 59 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 120 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 121 wait for 1 ns; I <= "001000100"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 314 : < Y /= 0000 >" -- Vector No: 60 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 122 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 123 wait for 1 ns; I <= "001000100"; Aadd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 315 : < Y /= 1111 >" -- Vector No: 61 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 124 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 125 wait for 1 ns; I <= "001000100"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 316 : < Y /= 1111 >" -- Vector No: 62 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 126 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 127 wait for 1 ns; I <= "001000100"; Aadd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 317 : < Y /= 0000 >" -- Vector No: 63 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 128 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 129 wait for 1 ns; I <= "001000100"; Badd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 318 : < Y /= 0000 >" -- Vector No: 64 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 130 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 131 wait for 1 ns; I <= "001000100"; Aadd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 319 : < Y /= 1111 >" -- Vector No: 65 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 132 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 133 wait for 1 ns; I <= "001000100"; Badd <= 2 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 320 : < Y /= 1111 >" -- Vector No: 66 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 134 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 135 wait for 1 ns; I <= "001000100"; Aadd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 321 : < Y /= 0000 >" -- Vector No: 67 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 136 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 137 wait for 1 ns; I <= "001000100"; Badd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 322 : < Y /= 0000 >" -- Vector No: 68 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 138 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 139 wait for 1 ns; I <= "001000100"; Aadd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 323 : < Y /= 1111 >" -- Vector No: 69 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 140 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 141 wait for 1 ns; I <= "001000100"; Badd <= 3 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 324 : < Y /= 1111 >" -- Vector No: 70 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 142 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 143 wait for 1 ns; I <= "001000100"; Aadd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 325 : < Y /= 0000 >" -- Vector No: 71 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 144 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 145 wait for 1 ns; I <= "001000100"; Badd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 326 : < Y /= 0000 >" -- Vector No: 72 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 146 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 147 wait for 1 ns; I <= "001000100"; Aadd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 327 : < Y /= 1111 >" -- Vector No: 73 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 148 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 149 wait for 1 ns; I <= "001000100"; Badd <= 4 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 328 : < Y /= 1111 >" -- Vector No: 74 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 150 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 151 wait for 1 ns; I <= "001000100"; Aadd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 329 : < Y /= 0000 >" -- Vector No: 75 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 152 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 153 wait for 1 ns; I <= "001000100"; Badd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 330 : < Y /= 0000 >" -- Vector No: 76 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 154 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 155 wait for 1 ns; I <= "001000100"; Aadd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 331 : < Y /= 1111 >" -- Vector No: 77 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 156 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 157 wait for 1 ns; I <= "001000100"; Badd <= 5 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 332 : < Y /= 1111 >" -- Vector No: 78 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 158 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 159 wait for 1 ns; I <= "001000100"; Aadd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 333 : < Y /= 0000 >" -- Vector No: 79 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 160 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 161 wait for 1 ns; I <= "001000100"; Badd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 334 : < Y /= 0000 >" -- Vector No: 80 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 162 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 163 wait for 1 ns; I <= "001000100"; Aadd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 335 : < Y /= 1111 >" -- Vector No: 81 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 164 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 165 wait for 1 ns; I <= "001000100"; Badd <= 6 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 336 : < Y /= 1111 >" -- Vector No: 82 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 166 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 167 wait for 1 ns; I <= "001000100"; Aadd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 337 : < Y /= 0000 >" -- Vector No: 83 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 168 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 169 wait for 1 ns; I <= "001000100"; Badd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 338 : < Y /= 0000 >" -- Vector No: 84 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 170 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 171 wait for 1 ns; I <= "001000100"; Aadd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 339 : < Y /= 1111 >" -- Vector No: 85 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 172 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 173 wait for 1 ns; I <= "001000100"; Badd <= 7 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 340 : < Y /= 1111 >" -- Vector No: 86 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 174 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 175 wait for 1 ns; I <= "001000100"; Aadd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 341 : < Y /= 0000 >" -- Vector No: 87 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 176 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 177 wait for 1 ns; I <= "001000100"; Badd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 342 : < Y /= 0000 >" -- Vector No: 88 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 178 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 179 wait for 1 ns; I <= "001000100"; Aadd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 343 : < Y /= 1111 >" -- Vector No: 89 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 180 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 181 wait for 1 ns; I <= "001000100"; Badd <= 8 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 344 : < Y /= 1111 >" -- Vector No: 90 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 182 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 183 wait for 1 ns; I <= "001000100"; Aadd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 345 : < Y /= 0000 >" -- Vector No: 91 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 184 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 185 wait for 1 ns; I <= "001000100"; Badd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 346 : < Y /= 0000 >" -- Vector No: 92 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 186 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 187 wait for 1 ns; I <= "001000100"; Aadd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 347 : < Y /= 1111 >" -- Vector No: 93 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 188 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 189 wait for 1 ns; I <= "001000100"; Badd <= 9 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 348 : < Y /= 1111 >" -- Vector No: 94 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 190 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 191 wait for 1 ns; I <= "001000100"; Aadd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 349 : < Y /= 0000 >" -- Vector No: 95 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 192 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 193 wait for 1 ns; I <= "001000100"; Badd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 350 : < Y /= 0000 >" -- Vector No: 96 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 194 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 195 wait for 1 ns; I <= "001000100"; Aadd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 351 : < Y /= 1111 >" -- Vector No: 97 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 196 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 197 wait for 1 ns; I <= "001000100"; Badd <= 10 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 352 : < Y /= 1111 >" -- Vector No: 98 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 198 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 199 wait for 1 ns; I <= "001000100"; Aadd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 353 : < Y /= 0000 >" -- Vector No: 99 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 200 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 201 wait for 1 ns; I <= "001000100"; Badd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 354 : < Y /= 0000 >" -- Vector No: 100 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 202 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 203 wait for 1 ns; I <= "001000100"; Aadd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 355 : < Y /= 1111 >" -- Vector No: 101 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 204 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 205 wait for 1 ns; I <= "001000100"; Badd <= 11 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 356 : < Y /= 1111 >" -- Vector No: 102 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 206 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 207 wait for 1 ns; I <= "001000100"; Aadd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 357 : < Y /= 0000 >" -- Vector No: 103 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 208 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 209 wait for 1 ns; I <= "001000100"; Badd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 358 : < Y /= 0000 >" -- Vector No: 104 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 210 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 211 wait for 1 ns; I <= "001000100"; Aadd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 359 : < Y /= 1111 >" -- Vector No: 105 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 212 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 213 wait for 1 ns; I <= "001000100"; Badd <= 12 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 360 : < Y /= 1111 >" -- Vector No: 106 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 214 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 215 wait for 1 ns; I <= "001000100"; Aadd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 361 : < Y /= 0000 >" -- Vector No: 107 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 216 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 217 wait for 1 ns; I <= "001000100"; Badd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 362 : < Y /= 0000 >" -- Vector No: 108 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 218 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 219 wait for 1 ns; I <= "001000100"; Aadd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 363 : < Y /= 1111 >" -- Vector No: 109 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 220 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 221 wait for 1 ns; I <= "001000100"; Badd <= 13 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 364 : < Y /= 1111 >" -- Vector No: 110 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 222 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 223 wait for 1 ns; I <= "001000100"; Aadd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 365 : < Y /= 0000 >" -- Vector No: 111 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 224 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 225 wait for 1 ns; I <= "001000100"; Badd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 366 : < Y /= 0000 >" -- Vector No: 112 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 226 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 227 wait for 1 ns; I <= "001000100"; Aadd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 367 : < Y /= 1111 >" -- Vector No: 113 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 228 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 229 wait for 1 ns; I <= "001000100"; Badd <= 14 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 368 : < Y /= 1111 >" -- Vector No: 114 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 230 wait for 1 ns; I <= "010000111"; D <= "0000"; Badd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 231 wait for 1 ns; I <= "001000100"; Aadd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 369 : < Y /= 0000 >" -- Vector No: 115 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 232 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 233 wait for 1 ns; I <= "001000100"; Badd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 370 : < Y /= 0000 >" -- Vector No: 116 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 234 wait for 1 ns; I <= "010000111"; D <= "1111"; Badd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 235 wait for 1 ns; I <= "001000100"; Aadd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 371 : < Y /= 1111 >" -- Vector No: 117 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 236 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 237 wait for 1 ns; I <= "001000100"; Badd <= 15 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 372 : < Y /= 1111 >" -- Vector No: 118 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING RAM SHIFTERS ******** -------------------------- clk <= '1'; -- Cycle No: 238 wait for 1 ns; I <= "100000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= 'Z'; RAM3 <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM0out = '0') report "Assert 373 : < RAM0 /= 0 >" -- Vector No: 119 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 239 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1000") report "Assert 374 : < Y /= 1000 >" -- Vector No: 120 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 240 wait for 1 ns; I <= "100000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= 'Z'; RAM3 <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM0out = '1') report "Assert 375 : < RAM0 /= 1 >" -- Vector No: 121 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 241 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0111") report "Assert 376 : < Y /= 0111 >" -- Vector No: 122 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 242 wait for 1 ns; I <= "101000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= 'Z'; RAM3 <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM0out = '0') report "Assert 377 : < RAM0 /= 0 >" -- Vector No: 123 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 243 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1000") report "Assert 378 : < Y /= 1000 >" -- Vector No: 124 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 244 wait for 1 ns; I <= "101000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= 'Z'; RAM3 <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM0out = '1') report "Assert 379 : < RAM0 /= 1 >" -- Vector No: 125 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 245 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0111") report "Assert 380 : < Y /= 0111 >" -- Vector No: 126 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 246 wait for 1 ns; I <= "110000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= '1'; RAM3 <= 'Z'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM3out = '0') report "Assert 381 : < RAM3 /= 0 >" -- Vector No: 127 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 247 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 382 : < Y /= 0001 >" -- Vector No: 128 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 248 wait for 1 ns; I <= "110000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= '0'; RAM3 <= 'Z'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM3out = '1') report "Assert 383 : < RAM3 /= 1 >" -- Vector No: 129 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 249 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1110") report "Assert 384 : < Y /= 1110 >" -- Vector No: 130 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 250 wait for 1 ns; I <= "111000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= '1'; RAM3 <= 'Z'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM3out = '0') report "Assert 385 : < RAM3 /= 0 >" -- Vector No: 131 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 251 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 386 : < Y /= 0001 >" -- Vector No: 132 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 252 wait for 1 ns; I <= "111000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; RAM0 <= '0'; RAM3 <= 'Z'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (RAM3out = '1') report "Assert 387 : < RAM3 /= 1 >" -- Vector No: 133 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 253 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1110") report "Assert 388 : < Y /= 1110 >" -- Vector No: 134 severity warning; wait for 1 ns; -- ************************ -- ******************************* -- * * -- * TEST VECTORS FOR Q-REGISTER * -- * * -- ******************************* -- ******** WRITING 0's AND 1's ******** -------------------------- clk <= '1'; -- Cycle No: 254 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 255 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 389 : < Y /= 1111 >" -- Vector No: 135 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 256 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 257 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 390 : < Y /= 0000 >" -- Vector No: 136 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING Q-REGISTER SHIFTERS ******** -------------------------- clk <= '1'; -- Cycle No: 258 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 259 wait for 1 ns; I <= "100000111"; C0 <= '0'; OEbar <= '0'; Q0 <= 'Z'; Q3 <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Q0out = '0') report "Assert 391 : < Q0 /= 0 >" -- Vector No: 137 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 260 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1000") report "Assert 392 : < Y /= 1000 >" -- Vector No: 138 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 261 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 262 wait for 1 ns; I <= "100000111"; C0 <= '0'; OEbar <= '0'; Q0 <= 'Z'; Q3 <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Q0out = '1') report "Assert 393 : < Q0 /= 1 >" -- Vector No: 139 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 263 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0111") report "Assert 394 : < Y /= 0111 >" -- Vector No: 140 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 264 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 265 wait for 1 ns; I <= "110000111"; C0 <= '0'; OEbar <= '0'; Q0 <= '1'; Q3 <= 'Z'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Q3out = '0') report "Assert 395 : < Q3 /= 0 >" -- Vector No: 141 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 266 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0001") report "Assert 396 : < Y /= 0001 >" -- Vector No: 142 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 267 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 268 wait for 1 ns; I <= "110000111"; C0 <= '0'; OEbar <= '0'; Q0 <= '0'; Q3 <= 'Z'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Q3out = '1') report "Assert 397 : < Q3 /= 1 >" -- Vector No: 143 severity warning; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 269 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1110") report "Assert 398 : < Y /= 1110 >" -- Vector No: 144 severity warning; wait for 1 ns; -- ************************ -- **************************************** -- * * -- * TEST VECTORS FOR ALU SOURCE-SELECTOR * -- * * -- **************************************** -- ******** TESTING FOR ALU SOURCE-SELECT ( R = A, S = Q) ******** -------------------------- clk <= '1'; -- Cycle No: 270 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 271 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 272 wait for 1 ns; I <= "001000000"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 399 : < Y /= 1111 >" -- Vector No: 145 severity warning; assert (C4 = '0') report "Assert 400 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 273 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 274 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 275 wait for 1 ns; I <= "001000000"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 401 : < Y /= 1111 >" -- Vector No: 146 severity warning; assert (C4 = '0') report "Assert 402 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = A, S = B) ******** -------------------------- clk <= '1'; -- Cycle No: 276 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 277 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 278 wait for 1 ns; I <= "001000001"; Aadd <= 0 ; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 403 : < Y /= 1111 >" -- Vector No: 147 severity warning; assert (C4 = '0') report "Assert 404 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 279 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 280 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 281 wait for 1 ns; I <= "001000001"; Aadd <= 0 ; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 405 : < Y /= 1111 >" -- Vector No: 148 severity warning; assert (C4 = '0') report "Assert 406 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = 0, S = Q) ******** -------------------------- clk <= '1'; -- Cycle No: 282 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 283 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 407 : < Y /= 0000 >" -- Vector No: 149 severity warning; assert (C4 = '0') report "Assert 408 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 284 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 285 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 409 : < Y /= 1111 >" -- Vector No: 150 severity warning; assert (C4 = '0') report "Assert 410 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = 0, S = B) ******** -------------------------- clk <= '1'; -- Cycle No: 286 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 287 wait for 1 ns; I <= "001000011"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 411 : < Y /= 0000 >" -- Vector No: 151 severity warning; assert (C4 = '0') report "Assert 412 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 288 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 289 wait for 1 ns; I <= "001000011"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 413 : < Y /= 1111 >" -- Vector No: 152 severity warning; assert (C4 = '0') report "Assert 414 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = 0, S = A) ******** -------------------------- clk <= '1'; -- Cycle No: 290 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 291 wait for 1 ns; I <= "001000100"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 415 : < Y /= 0000 >" -- Vector No: 153 severity warning; assert (C4 = '0') report "Assert 416 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 292 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 293 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 417 : < Y /= 1111 >" -- Vector No: 154 severity warning; assert (C4 = '0') report "Assert 418 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = D, S = A) ******** -------------------------- clk <= '1'; -- Cycle No: 294 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 295 wait for 1 ns; I <= "001000101"; D <= "1111"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 419 : < Y /= 1111 >" -- Vector No: 155 severity warning; assert (C4 = '0') report "Assert 420 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 296 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 297 wait for 1 ns; I <= "001000101"; D <= "0000"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 421 : < Y /= 1111 >" -- Vector No: 156 severity warning; assert (C4 = '0') report "Assert 422 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = D, S = Q) ******** -------------------------- clk <= '1'; -- Cycle No: 298 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 299 wait for 1 ns; I <= "001000110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 423 : < Y /= 1111 >" -- Vector No: 157 severity warning; assert (C4 = '0') report "Assert 424 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 300 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 301 wait for 1 ns; I <= "001000110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 425 : < Y /= 1111 >" -- Vector No: 158 severity warning; assert (C4 = '0') report "Assert 426 : < C4 /= 0 >" severity warning; wait for 1 ns; -- ************************ -- ******** TESTING FOR ALU SOURCE-SELECT ( R = D, S = 0) ******** -------------------------- clk <= '1'; -- Cycle No: 302 wait for 1 ns; I <= "001000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 427 : < Y /= 0000 >" -- Vector No: 159 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 303 wait for 1 ns; I <= "001000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 428 : < Y /= 1111 >" -- Vector No: 160 severity warning; wait for 1 ns; -- ************************ -- ************************************ -- * * -- * TEST VECTORS FOR OUTPUT-SELECTOR * -- * * -- ************************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 000) ******** -------------------------- clk <= '1'; -- Cycle No: 304 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 429 : < Y /= 0000 >" -- Vector No: 161 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 305 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 430 : < Y /= 1111 >" -- Vector No: 162 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 306 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 431 : < Y /= ZZZZ >" -- Vector No: 163 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 001) ******** -------------------------- clk <= '1'; -- Cycle No: 307 wait for 1 ns; I <= "001000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 432 : < Y /= 0000 >" -- Vector No: 164 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 308 wait for 1 ns; I <= "001000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 433 : < Y /= 1111 >" -- Vector No: 165 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 309 wait for 1 ns; I <= "001000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 434 : < Y /= ZZZZ >" -- Vector No: 166 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 010) ******** -------------------------- clk <= '1'; -- Cycle No: 310 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 311 wait for 1 ns; I <= "010000111"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 435 : < Y /= 0000 >" -- Vector No: 167 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 312 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 313 wait for 1 ns; I <= "010000111"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 436 : < Y /= 1111 >" -- Vector No: 168 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 314 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 315 wait for 1 ns; I <= "010000111"; Aadd <= 0 ; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 437 : < Y /= ZZZZ >" -- Vector No: 169 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 011) ******** -------------------------- clk <= '1'; -- Cycle No: 316 wait for 1 ns; I <= "011000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 438 : < Y /= 0000 >" -- Vector No: 170 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 317 wait for 1 ns; I <= "011000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 439 : < Y /= 1111 >" -- Vector No: 171 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 318 wait for 1 ns; I <= "011000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 440 : < Y /= ZZZZ >" -- Vector No: 172 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 100) ******** -------------------------- clk <= '1'; -- Cycle No: 319 wait for 1 ns; I <= "100000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 441 : < Y /= 0000 >" -- Vector No: 173 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 320 wait for 1 ns; I <= "100000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 442 : < Y /= 1111 >" -- Vector No: 174 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 321 wait for 1 ns; I <= "100000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 443 : < Y /= ZZZZ >" -- Vector No: 175 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 101) ******** -------------------------- clk <= '1'; -- Cycle No: 322 wait for 1 ns; I <= "101000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 444 : < Y /= 0000 >" -- Vector No: 176 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 323 wait for 1 ns; I <= "101000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 445 : < Y /= 1111 >" -- Vector No: 177 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 324 wait for 1 ns; I <= "101000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 446 : < Y /= ZZZZ >" -- Vector No: 178 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 110) ******** -------------------------- clk <= '1'; -- Cycle No: 325 wait for 1 ns; I <= "110000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 447 : < Y /= 0000 >" -- Vector No: 179 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 326 wait for 1 ns; I <= "110000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 448 : < Y /= 1111 >" -- Vector No: 180 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 327 wait for 1 ns; I <= "110000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 449 : < Y /= ZZZZ >" -- Vector No: 181 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING OUTPUT FOR (I8 I7 I6 = 111) ******** -------------------------- clk <= '1'; -- Cycle No: 328 wait for 1 ns; I <= "111000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 450 : < Y /= 0000 >" -- Vector No: 182 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 329 wait for 1 ns; I <= "111000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 451 : < Y /= 1111 >" -- Vector No: 183 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 330 wait for 1 ns; I <= "111000111"; D <= "1111"; C0 <= '0'; OEbar <= '1'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "ZZZZ") report "Assert 452 : < Y /= ZZZZ >" -- Vector No: 184 severity warning; wait for 1 ns; -- ************************ -- ************************** -- * * -- * TEST VECTORS FOR PATHS * -- * * -- ************************** -- ******** TESTING PATHS ( "ALU-SOURCES" --> F --> Q ) ******** -- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = Q ) * * * * -------------------------- clk <= '1'; -- Cycle No: 331 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 332 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 333 wait for 1 ns; I <= "000011000"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 334 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 453 : < Y /= 0000 >" -- Vector No: 185 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 335 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 336 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 337 wait for 1 ns; I <= "000100000"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 338 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 454 : < Y /= 1111 >" -- Vector No: 186 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = B ) * * * * -------------------------- clk <= '1'; -- Cycle No: 339 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 340 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 341 wait for 1 ns; I <= "000011001"; Aadd <= 0 ; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 342 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 455 : < Y /= 0000 >" -- Vector No: 187 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 343 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 344 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 345 wait for 1 ns; I <= "000100001"; Aadd <= 0 ; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 346 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 456 : < Y /= 1111 >" -- Vector No: 188 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = Q ) * * * * -------------------------- clk <= '1'; -- Cycle No: 347 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 348 wait for 1 ns; I <= "000011010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 349 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 457 : < Y /= 0000 >" -- Vector No: 189 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 350 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 351 wait for 1 ns; I <= "000011010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 352 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 458 : < Y /= 1111 >" -- Vector No: 190 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = B ) * * * * -------------------------- clk <= '1'; -- Cycle No: 353 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 354 wait for 1 ns; I <= "000011011"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 355 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 459 : < Y /= 0000 >" -- Vector No: 191 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 356 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 357 wait for 1 ns; I <= "000011011"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 358 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 460 : < Y /= 1111 >" -- Vector No: 192 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = A ) * * * * -------------------------- clk <= '1'; -- Cycle No: 359 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 360 wait for 1 ns; I <= "000011100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 361 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 461 : < Y /= 0000 >" -- Vector No: 193 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 362 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 363 wait for 1 ns; I <= "000011100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 364 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 462 : < Y /= 1111 >" -- Vector No: 194 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = A ) * * * * -------------------------- clk <= '1'; -- Cycle No: 365 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 366 wait for 1 ns; I <= "000011101"; D <= "0000"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 367 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 463 : < Y /= 0000 >" -- Vector No: 195 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 368 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 369 wait for 1 ns; I <= "000100101"; D <= "1111"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 370 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 464 : < Y /= 1111 >" -- Vector No: 196 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = Q ) * * * * -------------------------- clk <= '1'; -- Cycle No: 371 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 372 wait for 1 ns; I <= "000011110"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 373 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 465 : < Y /= 0000 >" -- Vector No: 197 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 374 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 375 wait for 1 ns; I <= "000100110"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 376 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 466 : < Y /= 1111 >" -- Vector No: 198 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = 0 ) * * * * -------------------------- clk <= '1'; -- Cycle No: 377 wait for 1 ns; I <= "000011111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 378 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 467 : < Y /= 0000 >" -- Vector No: 199 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = 0 ) * * * * -------------------------- clk <= '1'; -- Cycle No: 379 wait for 1 ns; I <= "000011111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 380 wait for 1 ns; I <= "001000010"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 468 : < Y /= 1111 >" -- Vector No: 200 severity warning; wait for 1 ns; -- ************************ -- ******** TESTING PATHS ( "ALU-SOURCES" --> F --> B ) ******** -- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = Q ) * * * * -------------------------- clk <= '1'; -- Cycle No: 381 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 382 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 383 wait for 1 ns; I <= "011011000"; Aadd <= 0 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 384 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 469 : < Y /= 0000 >" -- Vector No: 201 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 385 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 386 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 387 wait for 1 ns; I <= "011100000"; Aadd <= 0 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 388 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 470 : < Y /= 1111 >" -- Vector No: 202 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = B ) * * * * -------------------------- clk <= '1'; -- Cycle No: 389 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 390 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 391 wait for 1 ns; I <= "011011001"; Aadd <= 1 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 392 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 471 : < Y /= 0000 >" -- Vector No: 203 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 393 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 394 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 1 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 395 wait for 1 ns; I <= "011100001"; Aadd <= 1 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 396 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 472 : < Y /= 1111 >" -- Vector No: 204 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = Q ) * * * * -------------------------- clk <= '1'; -- Cycle No: 397 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 398 wait for 1 ns; I <= "011011010"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 399 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 473 : < Y /= 0000 >" -- Vector No: 205 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 400 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 401 wait for 1 ns; I <= "011011010"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 402 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 474 : < Y /= 1111 >" -- Vector No: 206 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = B ) * * * * -------------------------- clk <= '1'; -- Cycle No: 403 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 404 wait for 1 ns; I <= "011011011"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 405 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 475 : < Y /= 0000 >" -- Vector No: 207 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 406 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 407 wait for 1 ns; I <= "011011011"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 408 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 476 : < Y /= 1111 >" -- Vector No: 208 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = A ) * * * * -------------------------- clk <= '1'; -- Cycle No: 409 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 410 wait for 1 ns; I <= "011011100"; Aadd <= 0 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 411 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 477 : < Y /= 0000 >" -- Vector No: 209 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 412 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 413 wait for 1 ns; I <= "011011100"; Aadd <= 0 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 414 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 478 : < Y /= 1111 >" -- Vector No: 210 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = A ) * * * * -------------------------- clk <= '1'; -- Cycle No: 415 wait for 1 ns; I <= "011000111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 416 wait for 1 ns; I <= "011011101"; D <= "0000"; Aadd <= 0 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 417 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 479 : < Y /= 0000 >" -- Vector No: 211 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 418 wait for 1 ns; I <= "011000111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 419 wait for 1 ns; I <= "011100101"; D <= "1111"; Aadd <= 0 ; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 420 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 480 : < Y /= 1111 >" -- Vector No: 212 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = Q ) * * * * -------------------------- clk <= '1'; -- Cycle No: 421 wait for 1 ns; I <= "000000111"; D <= "0000"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 422 wait for 1 ns; I <= "011011110"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 423 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 481 : < Y /= 0000 >" -- Vector No: 213 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 424 wait for 1 ns; I <= "000000111"; D <= "1111"; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 425 wait for 1 ns; I <= "011100110"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 426 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 482 : < Y /= 1111 >" -- Vector No: 214 severity warning; wait for 1 ns; -- ************************ -- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = 0 ) * * * * -------------------------- clk <= '1'; -- Cycle No: 427 wait for 1 ns; I <= "011011111"; D <= "0000"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 428 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "0000") report "Assert 483 : < Y /= 0000 >" -- Vector No: 215 severity warning; wait for 1 ns; -- ************************ -------------------------- clk <= '1'; -- Cycle No: 429 wait for 1 ns; I <= "011011111"; D <= "1111"; Badd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; wait for 1 ns; -------------------------- clk <= '1'; -- Cycle No: 430 wait for 1 ns; I <= "001000100"; Aadd <= 0 ; C0 <= '0'; OEbar <= '0'; wait for 4 ns; clk <= '0'; wait for 4 ns; assert (Y = "1111") report "Assert 484 : < Y /= 1111 >" -- Vector No: 216 severity warning; wait for 1 ns; -- ************************ -------------------------- report "Test PASS"; wait; end process; end A;
mit
2de826a08ce55463a2d52a2a4aca399d
0.457125
2.633944
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_rst_ps7_0_100M_0/gcd_block_design_rst_ps7_0_100M_0_sim_netlist.vhdl
2
35,850
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Sun Sep 22 03:32:35 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_rst_ps7_0_100M_0/gcd_block_design_rst_ps7_0_100M_0_sim_netlist.vhdl -- Design : gcd_block_design_rst_ps7_0_100M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_block_design_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync"; end gcd_block_design_rst_ps7_0_100M_0_cdc_sync; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => p_1_in, I2 => p_2_in, I3 => \^scndry_out\, I4 => asr_lpf(0), O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_block_design_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync"; end gcd_block_design_rst_ps7_0_100M_0_cdc_sync_0; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0_cdc_sync_0 is signal exr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => exr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => exr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(1), I2 => p_3_out(2), I3 => \^scndry_out\, I4 => p_3_out(0), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_block_design_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n"; end gcd_block_design_rst_ps7_0_100M_0_upcnt_n; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_block_design_rst_ps7_0_100M_0_lpf : entity is "lpf"; end gcd_block_design_rst_ps7_0_100M_0_lpf; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.gcd_block_design_rst_ps7_0_100M_0_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.gcd_block_design_rst_ps7_0_100M_0_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => dcm_locked, I1 => lpf_exr, I2 => lpf_asr, I3 => Q, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_block_design_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr"; end gcd_block_design_rst_ps7_0_100M_0_sequence_psr; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.gcd_block_design_rst_ps7_0_100M_0_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0090" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9000" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0018" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(0), I2 => seq_cnt(2), I3 => seq_cnt(1), O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0480" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset"; end gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.gcd_block_design_rst_ps7_0_100M_0_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.gcd_block_design_rst_ps7_0_100M_0_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_block_design_rst_ps7_0_100M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of gcd_block_design_rst_ps7_0_100M_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of gcd_block_design_rst_ps7_0_100M_0 : entity is "gcd_block_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of gcd_block_design_rst_ps7_0_100M_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of gcd_block_design_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2018.2"; end gcd_block_design_rst_ps7_0_100M_0; architecture STRUCTURE of gcd_block_design_rst_ps7_0_100M_0 is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.gcd_block_design_rst_ps7_0_100M_0_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;
mit
a4314cd5ed11b0063bf924f99362dcda
0.588006
2.870986
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/iir/bq/filter_converter_dp2sp.vhd
1
990
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity filter_converter_dp2sp is port ( double : in std_logic_vector(65 downto 0); float : out std_logic_vector(33 downto 0) ); end filter_converter_dp2sp; architecture behaviour of filter_converter_dp2sp is signal inf_s : std_logic; begin -- infinity if double is too big for float inf_s <= '1' when ((double(62 downto 59) /= "1000") and (double(62 downto 59) /= "0111")) else '0'; -- FloPoCo Control bits -- mark as infinity when double is too big for float float(33 downto 32) <= "10" when ((double(65 downto 64) = "01") and (inf_s = '1')) else double(65 downto 64); -- sign float(31) <= double(63); -- exponent float(30) <= double(62); float(29 downto 23) <= double(58 downto 52); -- mantissa (IEEE rounding mode "truncation") float(22 downto 0) <= double(51 downto 29); end behaviour;
mit
344bf83bf3938a0ae3935b9276e896d5
0.607071
3.523132
false
false
false
false
MartinCura/SistDig-TP4
old/tp4.vhd
1
6,990
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.cordic_lib.all; --library ieee_proposed; --use ieee_proposed.float_pkg.all; library floatfixlib; use floatfixlib.float_pkg.all; entity tp4 is generic( N_BITS_COORD : integer := 32 --- REVISAR ); port( clk_i: in std_logic; -- Clock general data_i: in std_logic; -- Entrada de datos rst_i: in std_logic; -- Botón de reset --rot_on, rot_vel: in std_logic; -- Switches y botones para controlar la rotación --rot_x_on, rot_y_on, rot_z_on: in std_logic; rot_x_ng, rot_y_ng, rot_z_ng: in std_logic; inc_alfa, inc_beta, inc_gama: in std_logic; rst_angs_i: in std_logic; data_volt_out: out std_logic; hs, vs: out std_logic; -- Output para el display VGA red_o: out std_logic_vector(2 downto 0); grn_o: out std_logic_vector(2 downto 0); blu_o: out std_logic_vector(1 downto 0); a,b,c,d,e,f,g,dp: out std_logic -- Segmentos del display de 7 segmentos ); attribute loc: string; attribute slew: string; attribute drive: string; attribute iostandard: string; attribute CLOCK_DEDICATED_ROUTE: string; attribute CLOCK_DEDICATED_ROUTE of rst_i: signal is "false"; -- Mapeo de pines para el kit Nexys 2 (spartan 3E) -- https://reference.digilentinc.com/_media/nexys:nexys2:nexys2_rm.pdf attribute loc of clk_i: signal is "B8"; attribute loc of data_i: signal is "L15"; -- Pin físico de entrada de datos -- VGA attribute loc of hs: signal is "T4"; attribute loc of vs: signal is "U3"; attribute loc of red_o: signal is "R8 T8 R9"; attribute loc of grn_o: signal is "P6 P8 N8"; attribute loc of blu_o: signal is "U4 U5"; -- Switches -- attribute loc of rot_on: signal is "R17"; -- Prender rotación constante -- attribute loc of rot_vel: signal is "N17"; -- Velocidad lenta o rápida -- attribute loc of rot_x_on: signal is "L13"; -- Rotación en x -- attribute loc of rot_y_on: signal is "K17"; -- Rotación en y -- attribute loc of rot_z_on: signal is "H18"; -- Rotación en z attribute loc of rot_x_ng: signal is "L14"; -- Rotación negativa en x attribute loc of rot_y_ng: signal is "K18"; -- Rotación negativa en y attribute loc of rot_z_ng: signal is "G18"; -- Rotación negativa en z -- Botones attribute loc of rst_i: signal is "B18"; -- Botón para resetear todo attribute loc of inc_alfa: signal is "H13"; attribute loc of inc_beta: signal is "E18"; attribute loc of inc_gama: signal is "D18"; -- attribute loc of rst_angs_i: signal is "B18"; -- Reseteo a posición inicial -- Apagar los segmentos del display attribute loc of a: signal is "L18"; attribute loc of b: signal is "F18"; attribute loc of c: signal is "D17"; attribute loc of d: signal is "D16"; attribute loc of e: signal is "G14"; attribute loc of f: signal is "J17"; attribute loc of g: signal is "H14"; attribute loc of dp: signal is "C17"; end; architecture tp4_arq of tp4 is -- signal rot_ena: std_logic := '0'; -- Enable de rotar signal ena_o: std_logic := '0'; signal ram_int_refresh, rst_pdram: std_logic := '0'; signal alfa, beta, gama: t_float; signal pos_leida, pos_rotada: t_pos; signal vec_pos_pixel: t_vec; signal dir_pixel: t_dir; signal pix_x, pix_y: std_logic_vector(9 downto 0) := (others => '0'); signal pix_on: std_logic := '0'; signal RxRdy: std_logic := '0'; -- Si el próximo dato está listo para leerse ---Falta un bit para saber si se terminó de leer [todos los] datos? signal Dout_uart: std_logic_vector(15 downto 0) := (others => '0'); signal pos_mem_leida: t_pos_mem := (others => (others => '0')); signal rst_angs: std_logic := '0'; begin -- *** RECIBIR Y GUARDAR *** -- UART para recibir los datos de la PC y mandarlos a la RAM externa uart: entity work.data_acq_unit port map( clk => clk_i, rst => rst_i, rx => data_i, data_out_16bits => Dout_uart, data_ready => RxRdy ); --- Se guarda un dato de lectura listo en memoria [interna]. Paralelamente, continuamente se escriben en vector pos_leida los datos ya guardados ram_int: entity work.ram_interna generic map( N_BITS => N_BITS_COORD, CANT_P => 100 ) port map( clk => clk_i, rst => rst_i, Rx => RxRdy, Din => Dout_uart, Dout => pos_mem_leida, Rdy => ena_o, barrido => ram_int_refresh ); -- Paso a formato punto flotante process(pos_mem_leida) begin --- pos_leida(i) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_mem_leida(i))),N_BITS_COORD))); pos_leida(1) <= to_float(pos_mem_leida(1)); pos_leida(2) <= to_float(pos_mem_leida(2)); pos_leida(3) <= to_float(pos_mem_leida(3)); end process; -- *** LEER Y ROTAR *** --- Si hiciéramos rotación constante: --- 3 contadores de pasos angulares en cada eje, --- se multiplican a la velocidad de rotación (lenta o rápida según rot_vel), --- y eso son los 3 ángulos: alfa, beta, gama. rst_angs <= rst_angs_i or rst_i; -- Obtengo los ángulos de rotación para cada eje angles: entity work.det_angulos port map( clk_i, '0',---APAGO PARA TESTEAR---ena_o, -- and rot_ena, rst_angs, inc_alfa, inc_beta, inc_gama, rot_x_ng, rot_y_ng, rot_z_ng, alfa, beta, gama ); -- Roto la posición leída según los ángulos de rotación ---rotador: entity work.rotador3d COMENTADA para probar sintetizar --- port map( --- ena => ena_o, ---ena => rot_ena, --- pos_in => pos_leida, --- alfa => alfa, --- beta => beta, --- gama => gama, --- --- pos_rotada => pos_rotada --- ); pos_rotada <= pos_leida;--- -- Aplano a ejes (y,z) vec_pos_pixel(1) <= pos_rotada(2); vec_pos_pixel(2) <= pos_rotada(3); -- Para la posición rotada genero la dirección en memoria correspondiente gen_dir: entity work.gen_dirs port map( pos_2d => vec_pos_pixel, dir => dir_pixel ); ---rst_pdram <= ram_int_refresh or rst_i; ----APAGO BARRIDO para tests rst_pdram <= '0'; -- Prendo el bit para la posición apropiada en la dual port ram ram_video: entity work.video_ram port map ( clock => clk_i, write_enable => ena_o, ---Chequear barrido => rst_pdram, A_row => dir_pixel(2), B_row => pix_y, A_col => dir_pixel(1), B_col => pix_x, data_A => '1', data_B => pix_on ); --pix_on <= pix_on and ena_o;---Quilombo? -- *** IMPRIMIR *** [De acá en más, se tratan los ejes como (x,y)] -- VGA vga: entity work.VGA_ctrl port map( mclk => clk_i, red_i => pix_on, --- 1 si hay algo, 0 si no grn_i => pix_on, --- 1 si hay algo, 0 si no blu_i => pix_on,---'1', hs => hs, vs => vs, red_o => red_o, grn_o => grn_o, blu_o => blu_o, pixel_row => pix_y, -- y del píxel que se está imprimiendo pixel_col => pix_x -- x del píxel que se está imprimiendo ); -- Apago todos los segmentos del display de 7 segmentos a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '1'; dp <= '1'; end;
gpl-3.0
146e66580fd7d700e73a3a78de2e583f
0.631473
2.591129
false
false
false
false
besm6/micro-besm
tests/2901/vhdl/funct_blocks_alg_beh/components/alu_inputs/q_reg.vhdl
3
1,494
-------------------------------------------------------------------------------- -- -- AM2901 Benchmark -- -- Source: AMD data book -- -- VHDL Benchmark author Indraneel Ghosh -- University Of California, Irvine, CA 92717 -- -- Developed on Jan 1, 1992 -- -- Verification Information: -- -- Verified By whom? Date Simulator -- -------- ------------ -------- ------------ -- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD -- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD -------------------------------------------------------------------------------- --library ZYCAD; use work.TYPES.all; use work.MVL7_functions.all; use work.synthesis_types.all; entity Q_reg is port ( F : in MVL7_vector(3 downto 0); clk : in clock; I : in MVL7_vector(8 downto 0); Q0, Q3 : in MVL7; Q : inout MVL7_vector(3 downto 0) ); end Q_reg; architecture Q_reg of Q_reg is begin Q_reg1 : block ( (clk = '1') and (not clk'stable ) ) begin -- WRITE TO Q REGISTER WITH/WITHOUT SHIFTING. Q <= guarded F when (I(8 downto 6) = "000") else Q3 & Q(3 downto 1) when (I(8 downto 6) = "100") else Q(2 downto 0) & Q0 when (I(8 downto 6) = "110") else Q; end block Q_reg1; end Q_reg; ---------------------------------------------
mit
e1f4257b17c11377e5482a7b3f896053
0.437082
3.811224
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/iir/bq/filter_in_data_controller.vhd
1
5,940
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.filter_shared_package.all; entity filter_in_data_controller is generic ( MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( clk : in std_logic; rstn : in std_logic; cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); x_input : in std_logic; valid : in std_logic; sink_valid : in std_logic; sink_endofpacket : in std_logic; sink_startofpacket : in std_logic; input_ack : in std_logic; sink_ready : out std_logic; input_ok : out std_logic; x_rdaddr : out X_ADD_T; x_rden : out std_logic; x_wraddr : out X_ADD_T; x_wren : out std_logic ); end filter_in_data_controller; architecture behaviour of filter_in_data_controller is type STATE_TYPE is ( IDLE_STATE, START_STATE, WRITE_STATE, DONE_STATE); signal cs_s : STATE_TYPE; signal ns_s : STATE_TYPE; signal x_cur_page_s : std_logic_vector(1 downto 0); signal x_nxt_page_s : std_logic_vector(1 downto 0); signal x_mod_page_s : std_logic_vector(1 downto 0); signal int_cnt_ch_s : unsigned(cnt_ch'range); signal wren_s : std_logic; signal select_s : std_logic_vector(3 downto 0); signal input_ok_s : std_logic; begin process (clk, rstn) is begin if (rstn = '0') then x_cur_page_s <= (others => '0'); elsif (clk = '1' and clk'event) then if (input_ok_s = '1') then -- flip pages (shift register emulation) x_cur_page_s <= x_nxt_page_s; end if; end if; end process; -- read interface select_s <= x_cur_page_s(1 downto 0) & cnt_mac(1 downto 0); with (select_s) select x_mod_page_s <= "00" when "0000", "01" when "0100", "10" when "1000", "01" when "0001", "10" when "0101", "00" when "1001", "10" when "0010", "00" when "0110", "01" when "1010", -- TODO: was "XX" "00" when others; x_rdaddr <= std_logic_vector(resize(unsigned(x_mod_page_s) * to_unsigned(CHANNELS,cnt_ch'length), x_rdaddr'length) + unsigned(cnt_ch)); -- p*C + c x_rden <= x_input; -- write interface x_nxt_page_s(1) <= x_cur_page_s(0) nor x_cur_page_s(1); x_nxt_page_s(0) <= x_cur_page_s(1); x_wraddr <= std_logic_vector(resize(unsigned(x_nxt_page_s) * to_unsigned(CHANNELS,cnt_ch'length), x_wraddr'length) + int_cnt_ch_s); -- p*C + c x_wren <= wren_s; -- counter process process (clk, rstn) is begin if (rstn = '0') then int_cnt_ch_s <= (others => '0'); elsif (clk = '1' and clk'event) then if (cs_s = IDLE_STATE) then int_cnt_ch_s <= (others => '0'); end if; if (((cs_s = WRITE_STATE) and (sink_valid = '1')) or ((cs_s = START_STATE) and (sink_valid = '1') and (sink_startofpacket = '1'))) then int_cnt_ch_s <= int_cnt_ch_s + 1; end if; end if; end process; -- state memory process (clk, rstn) is begin if (rstn = '0') then cs_s <= IDLE_STATE; elsif (clk = '1' and clk'event) then cs_s <= ns_s; end if; end process; -- next state logic process (cs_s, x_input, valid, sink_valid, sink_endofpacket, sink_startofpacket, input_ack) is begin case cs_s is when IDLE_STATE => if ((x_input = '0') or (valid = '0')) then ns_s <= START_STATE; -- TODO: was WAIT_STATE else ns_s <= IDLE_STATE; end if; when START_STATE => if ((sink_valid = '1') and (sink_startofpacket = '1')) then ns_s <= WRITE_STATE; else ns_s <= START_STATE; end if; when WRITE_STATE => if ((sink_valid = '1') and (sink_endofpacket = '1')) then ns_s <= DONE_STATE; else ns_s <= WRITE_STATE; end if; when DONE_STATE => if (input_ack = '1') then ns_s <= IDLE_STATE; else ns_s <= DONE_STATE; end if; when others => ns_s <= IDLE_STATE; end case; end process; -- state machine output values based on state with cs_s select input_ok_s <= '1' when DONE_STATE, '0' when others; input_ok <= input_ok_s; with cs_s select sink_ready <= '1' when START_STATE, '1' when WRITE_STATE, '0' when others; with cs_s select wren_s <= sink_valid when WRITE_STATE, sink_valid when START_STATE, '0' when others; end behaviour;
mit
58244949bc718d732d0d4d54a42ad4e8
0.46835
3.630807
false
false
false
false
Feuerwerk/fpgaNES
hex_digit.vhd
1
1,873
/* This file is part of fpgaNES. fpgaNES is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. fpgaNES is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with fpgaNES. If not, see <http://www.gnu.org/licenses/>. */ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hex_digit is port ( i_d : in std_logic_vector(3 downto 0); o_q : out std_logic_vector(6 downto 0) ); end hex_digit; architecture behavioral of hex_digit is signal s_q: std_logic_vector(6 downto 0); begin process (i_d) begin case i_d is when "0000" => -- 0 s_q <= "0111111"; when "0001" => -- 1 s_q <= "0000110"; when "0010" => -- 2 s_q <= "1011011"; when "0011" => -- 3 s_q <= "1001111"; when "0100" => -- 4 s_q <= "1100110"; when "0101" => -- 5 s_q <= "1101101"; when "0110" => -- 6 s_q <= "1111101"; when "0111" => -- 7 s_q <= "0000111"; when "1000" => -- 8 s_q <= "1111111"; when "1001" => -- 9 s_q <= "1101111"; when "1010" => -- A s_q <= "1110111"; when "1011" => -- B s_q <= "1111100"; when "1100" => -- C s_q <= "0111001"; when "1101" => -- D s_q <= "1011110"; when "1110" => -- E s_q <= "1111001"; when "1111" => -- F s_q <= "1110001"; when others => s_q <= "0000000"; end case; end process; o_q <= not s_q; end architecture;
gpl-3.0
0b92cf85a8d6007e65ccc3b359c741e2
0.575013
3.080592
false
false
false
false
elionne/easy_bitcoin_wallet
recursive_stack.vhdl
1
1,203
library IEEE; use ieee.std_logic_1164.all; entity recursive_stack is generic ( size: natural := 4); port ( data_in : in natural; data_out : out natural; enable : in std_logic; push_pop: in std_logic; clk : in std_logic ); end recursive_stack; architecture arch_recursive_stack of recursive_stack is type data_stack_type is array (0 to size) of natural; signal data : data_stack_type := (others => 0); signal zero_addr : std_logic := '0'; begin process(clk) variable addr : natural := 0; begin if falling_edge(clk) and enable = '1' then if push_pop = '1' then if addr < size then if zero_addr = '0' then zero_addr <= '1'; else addr := addr + 1; end if; data(addr) <= data_in; data_out <= data_in; end if; else if addr > 0 then addr := addr - 1; else -- if addr = 0 zero_addr <= '0'; end if; data_out <= data(addr); end if; end if; end process; end arch_recursive_stack;
mit
d37a92c60d6938a0981b9d79d7cf57ad
0.491272
3.84345
false
false
false
false
Feuerwerk/fpgaNES
vga_pll.vhd
1
17,827
-- megafunction wizard: %PLL Intel FPGA IP v18.0% -- GENERATION: XML -- vga_pll.vhd -- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity vga_pll is port ( refclk : in std_logic := '0'; -- refclk.clk rst : in std_logic := '0'; -- reset.reset outclk_0 : out std_logic; -- outclk0.clk locked : out std_logic -- locked.export ); end entity vga_pll; architecture rtl of vga_pll is component vga_pll_0002 is port ( refclk : in std_logic := 'X'; -- clk rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic; -- clk locked : out std_logic -- export ); end component vga_pll_0002; begin vga_pll_inst : component vga_pll_0002 port map ( refclk => refclk, -- refclk.clk rst => rst, -- reset.reset outclk_0 => outclk_0, -- outclk0.clk locked => locked -- locked.export ); end architecture rtl; -- of vga_pll -- Retrieval info: <?xml version="1.0"?> --<!-- -- Generated by Altera MegaWizard Launcher Utility version 1.0 -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ -- Copyright (C) 1991-2018 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> -- Retrieval info: <instance entity-name="altera_pll" version="18.0" > -- Retrieval info: <generic name="debug_print_output" value="false" /> -- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" /> -- Retrieval info: <generic name="device_family" value="Cyclone V" /> -- Retrieval info: <generic name="device" value="Unknown" /> -- Retrieval info: <generic name="gui_device_speed_grade" value="2" /> -- Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" /> -- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" /> -- Retrieval info: <generic name="gui_channel_spacing" value="0.0" /> -- Retrieval info: <generic name="gui_operation_mode" value="direct" /> -- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" /> -- Retrieval info: <generic name="gui_fractional_cout" value="32" /> -- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" /> -- Retrieval info: <generic name="gui_use_locked" value="true" /> -- Retrieval info: <generic name="gui_en_adv_params" value="false" /> -- Retrieval info: <generic name="gui_number_of_clocks" value="1" /> -- Retrieval info: <generic name="gui_multiply_factor" value="1" /> -- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" /> -- Retrieval info: <generic name="gui_divide_factor_n" value="1" /> -- Retrieval info: <generic name="gui_cascade_counter0" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency0" value="25.175" /> -- Retrieval info: <generic name="gui_divide_factor_c0" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units0" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift0" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle0" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter1" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c1" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units1" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift1" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle1" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter2" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c2" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units2" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift2" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle2" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter3" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c3" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units3" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift3" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle3" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter4" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c4" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units4" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift4" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle4" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter5" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c5" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units5" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift5" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle5" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter6" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c6" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units6" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift6" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle6" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter7" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c7" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units7" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift7" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle7" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter8" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c8" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units8" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift8" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle8" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter9" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c9" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units9" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift9" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle9" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter10" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c10" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units10" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift10" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle10" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter11" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c11" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units11" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift11" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle11" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter12" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c12" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units12" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift12" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle12" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter13" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c13" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units13" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift13" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle13" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter14" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c14" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units14" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift14" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle14" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter15" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c15" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units15" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift15" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle15" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter16" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c16" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units16" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift16" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle16" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter17" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c17" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units17" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift17" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle17" value="50" /> -- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" /> -- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" /> -- Retrieval info: <generic name="gui_en_reconf" value="false" /> -- Retrieval info: <generic name="gui_en_dps_ports" value="false" /> -- Retrieval info: <generic name="gui_en_phout_ports" value="false" /> -- Retrieval info: <generic name="gui_phout_division" value="1" /> -- Retrieval info: <generic name="gui_mif_generate" value="false" /> -- Retrieval info: <generic name="gui_enable_mif_dps" value="false" /> -- Retrieval info: <generic name="gui_dps_cntr" value="C0" /> -- Retrieval info: <generic name="gui_dps_num" value="1" /> -- Retrieval info: <generic name="gui_dps_dir" value="Positive" /> -- Retrieval info: <generic name="gui_refclk_switch" value="false" /> -- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" /> -- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" /> -- Retrieval info: <generic name="gui_switchover_delay" value="0" /> -- Retrieval info: <generic name="gui_active_clk" value="false" /> -- Retrieval info: <generic name="gui_clk_bad" value="false" /> -- Retrieval info: <generic name="gui_enable_cascade_out" value="false" /> -- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" /> -- Retrieval info: <generic name="gui_enable_cascade_in" value="false" /> -- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" /> -- Retrieval info: </instance> -- IPFS_FILES : vga_pll.vho -- RELATED_FILES: vga_pll.vhd, vga_pll_0002.v
gpl-3.0
565f892bbcf44ecd8688f25c587955be
0.673305
3.005733
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_rst_ps7_0_49M_0/gcd_zynq_snick_rst_ps7_0_49M_0_sim_netlist.vhdl
1
35,723
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 19:44:37 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_rst_ps7_0_49M_0/gcd_zynq_snick_rst_ps7_0_49M_0_sim_netlist.vhdl -- Design : gcd_zynq_snick_rst_ps7_0_49M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg400-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync : entity is "cdc_sync"; end gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => p_1_in, I2 => p_2_in, I3 => \^scndry_out\, I4 => asr_lpf(0), O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync_0 : entity is "cdc_sync"; end gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync_0; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync_0 is signal exr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => exr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => exr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(1), I2 => p_3_out(2), I3 => \^scndry_out\, I4 => p_3_out(0), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_rst_ps7_0_49M_0_upcnt_n : entity is "upcnt_n"; end gcd_zynq_snick_rst_ps7_0_49M_0_upcnt_n; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_rst_ps7_0_49M_0_lpf : entity is "lpf"; end gcd_zynq_snick_rst_ps7_0_49M_0_lpf; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.gcd_zynq_snick_rst_ps7_0_49M_0_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => dcm_locked, I1 => lpf_exr, I2 => lpf_asr, I3 => Q, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_rst_ps7_0_49M_0_sequence_psr : entity is "sequence_psr"; end gcd_zynq_snick_rst_ps7_0_49M_0_sequence_psr; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.gcd_zynq_snick_rst_ps7_0_49M_0_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0090" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9000" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0018" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(0), I2 => seq_cnt(2), I3 => seq_cnt(1), O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0480" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset : entity is "proc_sys_reset"; end gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.gcd_zynq_snick_rst_ps7_0_49M_0_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.gcd_zynq_snick_rst_ps7_0_49M_0_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gcd_zynq_snick_rst_ps7_0_49M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of gcd_zynq_snick_rst_ps7_0_49M_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of gcd_zynq_snick_rst_ps7_0_49M_0 : entity is "gcd_zynq_snick_rst_ps7_0_49M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of gcd_zynq_snick_rst_ps7_0_49M_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of gcd_zynq_snick_rst_ps7_0_49M_0 : entity is "proc_sys_reset,Vivado 2018.2"; end gcd_zynq_snick_rst_ps7_0_49M_0; architecture STRUCTURE of gcd_zynq_snick_rst_ps7_0_49M_0 is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.gcd_zynq_snick_rst_ps7_0_49M_0_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;
mit
efd4ede758450e5c89851a3639b8c43c
0.586485
2.845774
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/iir/bq/filter_generic_iir_biquad.vhdl
1
11,031
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.filter_shared_package.all; entity filter_generic_iir_biquad is generic ( BIQUADS : natural := B; CHANNELS : natural := C; PRECISION : natural := PREC; FPMULT_PIPE_LENGTH : P_T := PM; FPADD_PIPE_LENGTH : P_T := PA; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. ENVELOPE_EN : natural := ENV; ENV_MAC_ID : natural := ENV_MAC; SETZERO_EN : natural := SETZ ); port ( clk : in std_logic; rstn : in std_logic; envelope : in std_logic_vector(CHANNELS-1 downto 0):= (others => '0'); give_rms : in std_logic:= '0'; give_mean : in std_logic:= '0'; set_zero : in std_logic_vector(CHANNELS-1 downto 0):= (others => '0'); sink_data : in std_logic_vector(SINGLE_EXT-1 downto 0); sink_valid : in std_logic; sink_startofpacket : in std_logic; sink_endofpacket : in std_logic; sink_ready : out std_logic; coeff_wren : in std_logic; coeff_wraddr : in COEFF_ADD_T; coeff_data : in DATA_IO_PORT_T; source_data : out std_logic_vector(SINGLE_EXT-1 downto 0); source_valid : out std_logic; source_rms_valid : out std_logic:= '1'; source_mean_valid : out std_logic:= '0'; source_startofpacket : out std_logic; source_endofpacket : out std_logic ); end filter_generic_iir_biquad; architecture structural of filter_generic_iir_biquad is component filter_main_controller is generic ( BIQUADS : natural := B; CHANNELS : natural := C; FPMULT_PIPE_LENGTH : P_T := PM; FPADD_PIPE_LENGTH : P_T := PA; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. ENVELOPE_EN : natural := ENV; ENV_MAC_ID : natural := ENV_MAC; SETZERO_EN : natural := SETZ ); port ( -- Input Ports clk : in std_logic; rstn : in std_logic; envelope : in std_logic_vector(CHANNELS-1 downto 0); give_rms : in std_logic; give_mean : in std_logic; set_zero : in std_logic_vector(CHANNELS-1 downto 0); sink_valid : in std_logic; sink_startofpacket : in std_logic; sink_endofpacket : in std_logic; -- Output ports x_rdaddr : out X_ADD_T; x_rden : out std_logic; x_wraddr : out X_ADD_T; x_wren : out std_logic; coeff_rdaddr : out COEFF_ADD_T; coeff_rden : out std_logic; acc_rdaddr : out ACC_ADD_T; acc_rden : out std_logic; acc_wraddr : out ACC_ADD_T; acc_wren : out std_logic; zero_acc : out std_logic; y_rdaddr : out Y_ADD_T; y_rden : out std_logic; y_wraddr : out Y_ADD_T; y_wren : out std_logic; zero_y : out std_logic; is_abs : out std_logic; mac_x_y_sel : out std_logic; mac_coeff_y_sel : out std_logic; sink_ready : out std_logic; source_valid : out std_logic; source_rms_valid : out std_logic; source_mean_valid : out std_logic; source_startofpacket : out std_logic; source_endofpacket : out std_logic ); end component filter_main_controller; component filter_datapath is generic ( FPMULT_PIPE_LENGTH : P_T := PM; FPADD_PIPE_LENGTH : P_T := PA; PRECISION : natural := PREC ); port ( -- Input ports clk : in std_logic; rstn : in std_logic; aclr : in std_logic; x_rdaddr : in X_ADD_T; x_rden : in std_logic; x_wraddr : in X_ADD_T; x_wren : in std_logic; sink_data : in std_logic_vector(SINGLE_EXT-1 downto 0); coeff_rdaddr : in COEFF_ADD_T; coeff_rden : in std_logic; coeff_wraddr : in COEFF_ADD_T; coeff_wren : in std_logic; coeff_data : in DATA_IO_PORT_T; acc_rdaddr : in ACC_ADD_T; acc_rden : in std_logic; acc_wraddr : in ACC_ADD_T; acc_wren : in std_logic; zero_acc : in std_logic; y_rdaddr : in Y_ADD_T; y_rden : in std_logic; y_wraddr : in Y_ADD_T; y_wren : in std_logic; zero_y : in std_logic; is_abs : in std_logic; mac_x_y_sel : in std_logic; mac_coeff_y_sel : in std_logic; -- Output ports source_data : out std_logic_vector(SINGLE_EXT-1 downto 0) ); end component filter_datapath; -- Signals signal x_rdaddr_s : X_ADD_T; signal x_rden_s : std_logic; signal x_wraddr_s : X_ADD_T; signal x_wren_s : std_logic; signal coeff_rdaddr_s : COEFF_ADD_T; signal coeff_rden_s : std_logic; signal acc_rdaddr_s : ACC_ADD_T; signal acc_rden_s : std_logic; signal acc_wraddr_s : ACC_ADD_T; signal acc_wren_s : std_logic; signal zero_acc_s : std_logic; signal y_rdaddr_s : Y_ADD_T; signal y_rden_s : std_logic; signal y_wraddr_s : Y_ADD_T; signal y_wren_s : std_logic; signal zero_y_s : std_logic; signal is_abs_s : std_logic; signal mac_x_y_sel_s : std_logic; signal mac_coeff_y_sel_s : std_logic; signal aclr_s : std_logic; begin aclr_s <= not rstn; main_controller_inst : component filter_main_controller generic map ( BIQUADS => BIQUADS, CHANNELS => CHANNELS, FPMULT_PIPE_LENGTH => FPMULT_PIPE_LENGTH, FPADD_PIPE_LENGTH => FPADD_PIPE_LENGTH, MAC_FILTER_CH => MAC_FILTER_CH, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN, ENVELOPE_EN => ENVELOPE_EN, ENV_MAC_ID => ENV_MAC_ID, SETZERO_EN => SETZERO_EN ) port map ( clk => clk, rstn => rstn, envelope => envelope, give_rms => give_rms, give_mean => give_mean, set_zero => set_zero, sink_valid => sink_valid, sink_startofpacket => sink_startofpacket, sink_endofpacket => sink_endofpacket, x_rdaddr => x_rdaddr_s, x_rden => x_rden_s, x_wraddr => x_wraddr_s, x_wren => x_wren_s, coeff_rdaddr => coeff_rdaddr_s, coeff_rden => coeff_rden_s, acc_rdaddr => acc_rdaddr_s, acc_rden => acc_rden_s, acc_wraddr => acc_wraddr_s, acc_wren => acc_wren_s, zero_acc => zero_acc_s, y_rdaddr => y_rdaddr_s, y_rden => y_rden_s, y_wraddr => y_wraddr_s, y_wren => y_wren_s, zero_y => zero_y_s, is_abs => is_abs_s, mac_x_y_sel => mac_x_y_sel_s, mac_coeff_y_sel => mac_coeff_y_sel_s, sink_ready => sink_ready, source_valid => source_valid, source_rms_valid => source_rms_valid, source_mean_valid => source_mean_valid, source_startofpacket => source_startofpacket, source_endofpacket => source_endofpacket ); filter_datapath_inst : component filter_datapath generic map ( FPMULT_PIPE_LENGTH => FPMULT_PIPE_LENGTH, FPADD_PIPE_LENGTH => FPADD_PIPE_LENGTH, PRECISION => PRECISION ) port map ( clk => clk, rstn => rstn, aclr => aclr_s, x_rdaddr => x_rdaddr_s, x_rden => x_rden_s, x_wraddr => x_wraddr_s, x_wren => x_wren_s, sink_data => sink_data, coeff_rdaddr => coeff_rdaddr_s, coeff_rden => coeff_rden_s, coeff_wraddr => coeff_wraddr, coeff_wren => coeff_wren, coeff_data => coeff_data, acc_rdaddr => acc_rdaddr_s, acc_rden => acc_rden_s, acc_wraddr => acc_wraddr_s, acc_wren => acc_wren_s, zero_acc => zero_acc_s, y_rdaddr => y_rdaddr_s, y_rden => y_rden_s, y_wraddr => y_wraddr_s, y_wren => y_wren_s, zero_y => zero_y_s, is_abs => is_abs_s, mac_x_y_sel => mac_x_y_sel_s, mac_coeff_y_sel => mac_coeff_y_sel_s, source_data => source_data ); end structural;
mit
6b35648d55e5f760f09b8de08c32b06c
0.428157
3.946691
false
false
false
false
jakubcabal/uart-for-fpga
rtl/comp/uart_clk_div.vhd
2
1,975
-------------------------------------------------------------------------------- -- PROJECT: SIMPLE UART FOR FPGA -------------------------------------------------------------------------------- -- AUTHORS: Jakub Cabal <[email protected]> -- LICENSE: The MIT License, please read LICENSE file -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; entity UART_CLK_DIV is Generic ( DIV_MAX_VAL : integer := 16; DIV_MARK_POS : integer := 1 ); Port ( CLK : in std_logic; -- system clock RST : in std_logic; -- high active synchronous reset -- USER INTERFACE CLEAR : in std_logic; -- clock divider counter clear ENABLE : in std_logic; -- clock divider counter enable DIV_MARK : out std_logic -- output divider mark (divided clock enable) ); end entity; architecture RTL of UART_CLK_DIV is constant CLK_DIV_WIDTH : integer := integer(ceil(log2(real(DIV_MAX_VAL)))); signal clk_div_cnt : unsigned(CLK_DIV_WIDTH-1 downto 0); signal clk_div_cnt_mark : std_logic; begin clk_div_cnt_p : process (CLK) begin if (rising_edge(CLK)) then if (CLEAR = '1') then clk_div_cnt <= (others => '0'); elsif (ENABLE = '1') then if (clk_div_cnt = DIV_MAX_VAL-1) then clk_div_cnt <= (others => '0'); else clk_div_cnt <= clk_div_cnt + 1; end if; end if; end if; end process; clk_div_cnt_mark <= '1' when (clk_div_cnt = DIV_MARK_POS) else '0'; div_mark_p : process (CLK) begin if (rising_edge(CLK)) then DIV_MARK <= ENABLE and clk_div_cnt_mark; end if; end process; end architecture;
mit
2d568afb5ae16035709b74b357c66df6
0.492658
3.989899
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.cache/ip/2018.2/45a3d2c626abd576/gcd_zynq_snick_gcd_0_0_sim_netlist.vhdl
1
128,669
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 19:44:40 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_gcd_0_0_sim_netlist.vhdl -- Design : gcd_zynq_snick_gcd_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg400-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is port ( \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); interrupt : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); CO : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \b_read_reg_102_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); \a_read_reg_107_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); ap_clk : in STD_LOGIC; s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BREADY : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \result_reg_56_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); \p_s_reg_45_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); ap_rst_n : in STD_LOGIC; s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes"; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^a_read_reg_107_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_start : STD_LOGIC; signal ar_hs : STD_LOGIC; signal \^b_read_reg_102_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal int_a0 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \int_a[15]_i_1_n_0\ : STD_LOGIC; signal \int_a[15]_i_3_n_0\ : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_done1 : STD_LOGIC; signal int_ap_done_i_1_n_0 : STD_LOGIC; signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_start3_out : STD_LOGIC; signal int_ap_start_i_10_n_0 : STD_LOGIC; signal int_ap_start_i_1_n_0 : STD_LOGIC; signal int_ap_start_i_5_n_0 : STD_LOGIC; signal int_ap_start_i_6_n_0 : STD_LOGIC; signal int_ap_start_i_7_n_0 : STD_LOGIC; signal int_ap_start_i_8_n_0 : STD_LOGIC; signal int_ap_start_i_9_n_0 : STD_LOGIC; signal int_ap_start_reg_i_2_n_3 : STD_LOGIC; signal int_ap_start_reg_i_4_n_0 : STD_LOGIC; signal int_ap_start_reg_i_4_n_1 : STD_LOGIC; signal int_ap_start_reg_i_4_n_2 : STD_LOGIC; signal int_ap_start_reg_i_4_n_3 : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_auto_restart_i_1_n_0 : STD_LOGIC; signal int_b0 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \int_b[15]_i_1_n_0\ : STD_LOGIC; signal int_gie_i_1_n_0 : STD_LOGIC; signal int_gie_reg_n_0 : STD_LOGIC; signal \int_ier[0]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_1_n_0\ : STD_LOGIC; signal \int_ier[1]_i_2_n_0\ : STD_LOGIC; signal \int_ier_reg_n_0_[0]\ : STD_LOGIC; signal \int_ier_reg_n_0_[1]\ : STD_LOGIC; signal int_isr6_out : STD_LOGIC; signal \int_isr[0]_i_1_n_0\ : STD_LOGIC; signal \int_isr[1]_i_1_n_0\ : STD_LOGIC; signal \int_isr_reg_n_0_[0]\ : STD_LOGIC; signal int_pResult : STD_LOGIC_VECTOR ( 15 downto 0 ); signal int_pResult_ap_vld : STD_LOGIC; signal int_pResult_ap_vld1 : STD_LOGIC; signal int_pResult_ap_vld_i_1_n_0 : STD_LOGIC; signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP of \^out\ : signal is "yes"; signal p_1_in : STD_LOGIC; signal \rdata[0]_i_1_n_0\ : STD_LOGIC; signal \rdata[0]_i_2_n_0\ : STD_LOGIC; signal \rdata[0]_i_3_n_0\ : STD_LOGIC; signal \rdata[0]_i_4_n_0\ : STD_LOGIC; signal \rdata[10]_i_1_n_0\ : STD_LOGIC; signal \rdata[11]_i_1_n_0\ : STD_LOGIC; signal \rdata[12]_i_1_n_0\ : STD_LOGIC; signal \rdata[13]_i_1_n_0\ : STD_LOGIC; signal \rdata[14]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_1_n_0\ : STD_LOGIC; signal \rdata[1]_i_2_n_0\ : STD_LOGIC; signal \rdata[1]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_4_n_0\ : STD_LOGIC; signal \rdata[1]_i_5_n_0\ : STD_LOGIC; signal \rdata[2]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_2_n_0\ : STD_LOGIC; signal \rdata[3]_i_1_n_0\ : STD_LOGIC; signal \rdata[3]_i_2_n_0\ : STD_LOGIC; signal \rdata[4]_i_1_n_0\ : STD_LOGIC; signal \rdata[5]_i_1_n_0\ : STD_LOGIC; signal \rdata[6]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_2_n_0\ : STD_LOGIC; signal \rdata[8]_i_1_n_0\ : STD_LOGIC; signal \rdata[9]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \^s_axi_gcd_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \^s_axi_gcd_bus_rvalid\ : signal is "yes"; signal waddr : STD_LOGIC; signal \waddr_reg_n_0_[0]\ : STD_LOGIC; signal \waddr_reg_n_0_[1]\ : STD_LOGIC; signal \waddr_reg_n_0_[2]\ : STD_LOGIC; signal \waddr_reg_n_0_[3]\ : STD_LOGIC; signal \waddr_reg_n_0_[4]\ : STD_LOGIC; signal \waddr_reg_n_0_[5]\ : STD_LOGIC; signal NLW_int_ap_start_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); signal NLW_int_ap_start_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_int_ap_start_reg_i_4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001"; attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001"; attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_a[15]_i_2\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of int_ap_start_i_3 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_b[15]_i_2\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0"; begin CO(0) <= \^co\(0); SR(0) <= \^sr\(0); \a_read_reg_107_reg[15]\(15 downto 0) <= \^a_read_reg_107_reg[15]\(15 downto 0); \b_read_reg_102_reg[15]\(15 downto 0) <= \^b_read_reg_102_reg[15]\(15 downto 0); \out\(2 downto 0) <= \^out\(2 downto 0); s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0); s_axi_gcd_bus_RVALID(1 downto 0) <= \^s_axi_gcd_bus_rvalid\(1 downto 0); \FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F747" ) port map ( I0 => s_axi_gcd_bus_ARVALID, I1 => \^s_axi_gcd_bus_rvalid\(0), I2 => \^s_axi_gcd_bus_rvalid\(1), I3 => s_axi_gcd_bus_RREADY, O => \FSM_onehot_rstate[1]_i_1_n_0\ ); \FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88F8" ) port map ( I0 => s_axi_gcd_bus_ARVALID, I1 => \^s_axi_gcd_bus_rvalid\(0), I2 => \^s_axi_gcd_bus_rvalid\(1), I3 => s_axi_gcd_bus_RREADY, O => \FSM_onehot_rstate[2]_i_1_n_0\ ); \FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_rstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[1]_i_1_n_0\, Q => \^s_axi_gcd_bus_rvalid\(0), R => \^sr\(0) ); \FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_rstate[2]_i_1_n_0\, Q => \^s_axi_gcd_bus_rvalid\(1), R => \^sr\(0) ); \FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"888BFF8B" ) port map ( I0 => s_axi_gcd_bus_BREADY, I1 => \^out\(2), I2 => \^out\(1), I3 => \^out\(0), I4 => s_axi_gcd_bus_AWVALID, O => \FSM_onehot_wstate[1]_i_1_n_0\ ); \FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_gcd_bus_AWVALID, I1 => \^out\(0), I2 => s_axi_gcd_bus_WVALID, I3 => \^out\(1), O => \FSM_onehot_wstate[2]_i_1_n_0\ ); \FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ap_rst_n, O => \^sr\(0) ); \FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8F88" ) port map ( I0 => s_axi_gcd_bus_WVALID, I1 => \^out\(1), I2 => s_axi_gcd_bus_BREADY, I3 => \^out\(2), O => \FSM_onehot_wstate[3]_i_2_n_0\ ); \FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => '0', Q => \FSM_onehot_wstate_reg_n_0_[0]\, S => \^sr\(0) ); \FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[1]_i_1_n_0\, Q => \^out\(0), R => \^sr\(0) ); \FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[2]_i_1_n_0\, Q => \^out\(1), R => \^sr\(0) ); \FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \FSM_onehot_wstate[3]_i_2_n_0\, Q => \^out\(2), R => \^sr\(0) ); \ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FA30" ) port map ( I0 => \^co\(0), I1 => ap_start, I2 => Q(0), I3 => Q(2), O => D(0) ); \ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00001000" ) port map ( I0 => Q(1), I1 => Q(3), I2 => Q(0), I3 => ap_start, I4 => Q(2), O => D(1) ); \b_read_reg_102[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => Q(0), I1 => ap_start, O => E(0) ); \int_a[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(0), O => int_a0(0) ); \int_a[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(10), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(10), O => int_a0(10) ); \int_a[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(11), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(11), O => int_a0(11) ); \int_a[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(12), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(12), O => int_a0(12) ); \int_a[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(13), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(13), O => int_a0(13) ); \int_a[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(14), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(14), O => int_a0(14) ); \int_a[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0008" ) port map ( I0 => \waddr_reg_n_0_[4]\, I1 => \int_a[15]_i_3_n_0\, I2 => \waddr_reg_n_0_[2]\, I3 => \waddr_reg_n_0_[3]\, O => \int_a[15]_i_1_n_0\ ); \int_a[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(15), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(15), O => int_a0(15) ); \int_a[15]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00001000" ) port map ( I0 => \waddr_reg_n_0_[0]\, I1 => \waddr_reg_n_0_[5]\, I2 => \^out\(1), I3 => s_axi_gcd_bus_WVALID, I4 => \waddr_reg_n_0_[1]\, O => \int_a[15]_i_3_n_0\ ); \int_a[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(1), O => int_a0(1) ); \int_a[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(2), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(2), O => int_a0(2) ); \int_a[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(3), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(3), O => int_a0(3) ); \int_a[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(4), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(4), O => int_a0(4) ); \int_a[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(5), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(5), O => int_a0(5) ); \int_a[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(6), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(6), O => int_a0(6) ); \int_a[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(7), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^a_read_reg_107_reg[15]\(7), O => int_a0(7) ); \int_a[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(8), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(8), O => int_a0(8) ); \int_a[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(9), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^a_read_reg_107_reg[15]\(9), O => int_a0(9) ); \int_a_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(0), Q => \^a_read_reg_107_reg[15]\(0), R => \^sr\(0) ); \int_a_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(10), Q => \^a_read_reg_107_reg[15]\(10), R => \^sr\(0) ); \int_a_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(11), Q => \^a_read_reg_107_reg[15]\(11), R => \^sr\(0) ); \int_a_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(12), Q => \^a_read_reg_107_reg[15]\(12), R => \^sr\(0) ); \int_a_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(13), Q => \^a_read_reg_107_reg[15]\(13), R => \^sr\(0) ); \int_a_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(14), Q => \^a_read_reg_107_reg[15]\(14), R => \^sr\(0) ); \int_a_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(15), Q => \^a_read_reg_107_reg[15]\(15), R => \^sr\(0) ); \int_a_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(1), Q => \^a_read_reg_107_reg[15]\(1), R => \^sr\(0) ); \int_a_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(2), Q => \^a_read_reg_107_reg[15]\(2), R => \^sr\(0) ); \int_a_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(3), Q => \^a_read_reg_107_reg[15]\(3), R => \^sr\(0) ); \int_a_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(4), Q => \^a_read_reg_107_reg[15]\(4), R => \^sr\(0) ); \int_a_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(5), Q => \^a_read_reg_107_reg[15]\(5), R => \^sr\(0) ); \int_a_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(6), Q => \^a_read_reg_107_reg[15]\(6), R => \^sr\(0) ); \int_a_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(7), Q => \^a_read_reg_107_reg[15]\(7), R => \^sr\(0) ); \int_a_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(8), Q => \^a_read_reg_107_reg[15]\(8), R => \^sr\(0) ); \int_a_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_a[15]_i_1_n_0\, D => int_a0(9), Q => \^a_read_reg_107_reg[15]\(9), R => \^sr\(0) ); int_ap_done_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"8FFFFFFF88888888" ) port map ( I0 => Q(2), I1 => \^co\(0), I2 => \^s_axi_gcd_bus_rvalid\(0), I3 => s_axi_gcd_bus_ARVALID, I4 => int_ap_done1, I5 => int_ap_done, O => int_ap_done_i_1_n_0 ); int_ap_done_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => s_axi_gcd_bus_ARADDR(1), I3 => s_axi_gcd_bus_ARADDR(0), I4 => s_axi_gcd_bus_ARADDR(3), I5 => s_axi_gcd_bus_ARADDR(2), O => int_ap_done1 ); int_ap_done_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_done_i_1_n_0, Q => int_ap_done, R => \^sr\(0) ); int_ap_idle_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => Q(0), I1 => ap_start, O => ap_idle ); int_ap_idle_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => ap_idle, Q => int_ap_idle, R => \^sr\(0) ); int_ap_ready_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^co\(0), I1 => Q(2), O => ap_done ); int_ap_ready_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => ap_done, Q => int_ap_ready, R => \^sr\(0) ); int_ap_start_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFBFFF80" ) port map ( I0 => int_auto_restart, I1 => Q(2), I2 => \^co\(0), I3 => int_ap_start3_out, I4 => ap_start, O => int_ap_start_i_1_n_0 ); int_ap_start_i_10: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(0), I1 => \p_s_reg_45_reg[15]\(0), I2 => \p_s_reg_45_reg[15]\(2), I3 => \result_reg_56_reg[15]\(2), I4 => \p_s_reg_45_reg[15]\(1), I5 => \result_reg_56_reg[15]\(1), O => int_ap_start_i_10_n_0 ); int_ap_start_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"00000800" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \waddr_reg_n_0_[2]\, I3 => \int_ier[1]_i_2_n_0\, I4 => \waddr_reg_n_0_[3]\, O => int_ap_start3_out ); int_ap_start_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \p_s_reg_45_reg[15]\(15), I1 => \result_reg_56_reg[15]\(15), O => int_ap_start_i_5_n_0 ); int_ap_start_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(12), I1 => \p_s_reg_45_reg[15]\(12), I2 => \p_s_reg_45_reg[15]\(14), I3 => \result_reg_56_reg[15]\(14), I4 => \p_s_reg_45_reg[15]\(13), I5 => \result_reg_56_reg[15]\(13), O => int_ap_start_i_6_n_0 ); int_ap_start_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(9), I1 => \p_s_reg_45_reg[15]\(9), I2 => \p_s_reg_45_reg[15]\(11), I3 => \result_reg_56_reg[15]\(11), I4 => \p_s_reg_45_reg[15]\(10), I5 => \result_reg_56_reg[15]\(10), O => int_ap_start_i_7_n_0 ); int_ap_start_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(6), I1 => \p_s_reg_45_reg[15]\(6), I2 => \p_s_reg_45_reg[15]\(8), I3 => \result_reg_56_reg[15]\(8), I4 => \p_s_reg_45_reg[15]\(7), I5 => \result_reg_56_reg[15]\(7), O => int_ap_start_i_8_n_0 ); int_ap_start_i_9: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \result_reg_56_reg[15]\(3), I1 => \p_s_reg_45_reg[15]\(3), I2 => \p_s_reg_45_reg[15]\(5), I3 => \result_reg_56_reg[15]\(5), I4 => \p_s_reg_45_reg[15]\(4), I5 => \result_reg_56_reg[15]\(4), O => int_ap_start_i_9_n_0 ); int_ap_start_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_ap_start_i_1_n_0, Q => ap_start, R => \^sr\(0) ); int_ap_start_reg_i_2: unisim.vcomponents.CARRY4 port map ( CI => int_ap_start_reg_i_4_n_0, CO(3 downto 2) => NLW_int_ap_start_reg_i_2_CO_UNCONNECTED(3 downto 2), CO(1) => \^co\(0), CO(0) => int_ap_start_reg_i_2_n_3, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_int_ap_start_reg_i_2_O_UNCONNECTED(3 downto 0), S(3 downto 2) => B"00", S(1) => int_ap_start_i_5_n_0, S(0) => int_ap_start_i_6_n_0 ); int_ap_start_reg_i_4: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => int_ap_start_reg_i_4_n_0, CO(2) => int_ap_start_reg_i_4_n_1, CO(1) => int_ap_start_reg_i_4_n_2, CO(0) => int_ap_start_reg_i_4_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_int_ap_start_reg_i_4_O_UNCONNECTED(3 downto 0), S(3) => int_ap_start_i_7_n_0, S(2) => int_ap_start_i_8_n_0, S(1) => int_ap_start_i_9_n_0, S(0) => int_ap_start_i_10_n_0 ); int_auto_restart_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFFF00200000" ) port map ( I0 => s_axi_gcd_bus_WDATA(7), I1 => \waddr_reg_n_0_[3]\, I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, I4 => s_axi_gcd_bus_WSTRB(0), I5 => int_auto_restart, O => int_auto_restart_i_1_n_0 ); int_auto_restart_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_auto_restart_i_1_n_0, Q => int_auto_restart, R => \^sr\(0) ); \int_b[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(0), O => int_b0(0) ); \int_b[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(10), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(10), O => int_b0(10) ); \int_b[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(11), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(11), O => int_b0(11) ); \int_b[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(12), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(12), O => int_b0(12) ); \int_b[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(13), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(13), O => int_b0(13) ); \int_b[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(14), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(14), O => int_b0(14) ); \int_b[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \waddr_reg_n_0_[3]\, I1 => \waddr_reg_n_0_[4]\, I2 => \int_a[15]_i_3_n_0\, I3 => \waddr_reg_n_0_[2]\, O => \int_b[15]_i_1_n_0\ ); \int_b[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(15), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(15), O => int_b0(15) ); \int_b[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(1), O => int_b0(1) ); \int_b[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(2), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(2), O => int_b0(2) ); \int_b[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(3), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(3), O => int_b0(3) ); \int_b[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(4), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(4), O => int_b0(4) ); \int_b[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(5), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(5), O => int_b0(5) ); \int_b[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(6), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(6), O => int_b0(6) ); \int_b[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(7), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \^b_read_reg_102_reg[15]\(7), O => int_b0(7) ); \int_b[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(8), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(8), O => int_b0(8) ); \int_b[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_gcd_bus_WDATA(9), I1 => s_axi_gcd_bus_WSTRB(1), I2 => \^b_read_reg_102_reg[15]\(9), O => int_b0(9) ); \int_b_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(0), Q => \^b_read_reg_102_reg[15]\(0), R => \^sr\(0) ); \int_b_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(10), Q => \^b_read_reg_102_reg[15]\(10), R => \^sr\(0) ); \int_b_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(11), Q => \^b_read_reg_102_reg[15]\(11), R => \^sr\(0) ); \int_b_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(12), Q => \^b_read_reg_102_reg[15]\(12), R => \^sr\(0) ); \int_b_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(13), Q => \^b_read_reg_102_reg[15]\(13), R => \^sr\(0) ); \int_b_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(14), Q => \^b_read_reg_102_reg[15]\(14), R => \^sr\(0) ); \int_b_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(15), Q => \^b_read_reg_102_reg[15]\(15), R => \^sr\(0) ); \int_b_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(1), Q => \^b_read_reg_102_reg[15]\(1), R => \^sr\(0) ); \int_b_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(2), Q => \^b_read_reg_102_reg[15]\(2), R => \^sr\(0) ); \int_b_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(3), Q => \^b_read_reg_102_reg[15]\(3), R => \^sr\(0) ); \int_b_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(4), Q => \^b_read_reg_102_reg[15]\(4), R => \^sr\(0) ); \int_b_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(5), Q => \^b_read_reg_102_reg[15]\(5), R => \^sr\(0) ); \int_b_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(6), Q => \^b_read_reg_102_reg[15]\(6), R => \^sr\(0) ); \int_b_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(7), Q => \^b_read_reg_102_reg[15]\(7), R => \^sr\(0) ); \int_b_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(8), Q => \^b_read_reg_102_reg[15]\(8), R => \^sr\(0) ); \int_b_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => \int_b[15]_i_1_n_0\, D => int_b0(9), Q => \^b_read_reg_102_reg[15]\(9), R => \^sr\(0) ); int_gie_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \waddr_reg_n_0_[3]\, I3 => \waddr_reg_n_0_[2]\, I4 => \int_ier[1]_i_2_n_0\, I5 => int_gie_reg_n_0, O => int_gie_i_1_n_0 ); int_gie_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => int_gie_i_1_n_0, Q => int_gie_reg_n_0, R => \^sr\(0) ); \int_ier[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFBFFFFF00800000" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, I4 => \waddr_reg_n_0_[3]\, I5 => \int_ier_reg_n_0_[0]\, O => \int_ier[0]_i_1_n_0\ ); \int_ier[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFBFFFFF00800000" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => s_axi_gcd_bus_WSTRB(0), I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[2]\, I4 => \waddr_reg_n_0_[3]\, I5 => \int_ier_reg_n_0_[1]\, O => \int_ier[1]_i_1_n_0\ ); \int_ier[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => \waddr_reg_n_0_[1]\, I1 => s_axi_gcd_bus_WVALID, I2 => \^out\(1), I3 => \waddr_reg_n_0_[5]\, I4 => \waddr_reg_n_0_[0]\, I5 => \waddr_reg_n_0_[4]\, O => \int_ier[1]_i_2_n_0\ ); \int_ier_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[0]_i_1_n_0\, Q => \int_ier_reg_n_0_[0]\, R => \^sr\(0) ); \int_ier_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_ier[1]_i_1_n_0\, Q => \int_ier_reg_n_0_[1]\, R => \^sr\(0) ); \int_isr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F7777777F8888888" ) port map ( I0 => s_axi_gcd_bus_WDATA(0), I1 => int_isr6_out, I2 => \int_ier_reg_n_0_[0]\, I3 => \^co\(0), I4 => Q(2), I5 => \int_isr_reg_n_0_[0]\, O => \int_isr[0]_i_1_n_0\ ); \int_isr[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => s_axi_gcd_bus_WSTRB(0), I1 => \waddr_reg_n_0_[2]\, I2 => \int_ier[1]_i_2_n_0\, I3 => \waddr_reg_n_0_[3]\, O => int_isr6_out ); \int_isr[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F7777777F8888888" ) port map ( I0 => s_axi_gcd_bus_WDATA(1), I1 => int_isr6_out, I2 => \int_ier_reg_n_0_[1]\, I3 => \^co\(0), I4 => Q(2), I5 => p_1_in, O => \int_isr[1]_i_1_n_0\ ); \int_isr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[0]_i_1_n_0\, Q => \int_isr_reg_n_0_[0]\, R => \^sr\(0) ); \int_isr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => \int_isr[1]_i_1_n_0\, Q => p_1_in, R => \^sr\(0) ); int_pResult_ap_vld_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"8FFFFFFF88888888" ) port map ( I0 => Q(2), I1 => \^co\(0), I2 => \^s_axi_gcd_bus_rvalid\(0), I3 => s_axi_gcd_bus_ARVALID, I4 => int_pResult_ap_vld1, I5 => int_pResult_ap_vld, O => int_pResult_ap_vld_i_1_n_0 ); int_pResult_ap_vld_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000001000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(1), I1 => s_axi_gcd_bus_ARADDR(4), I2 => s_axi_gcd_bus_ARADDR(5), I3 => s_axi_gcd_bus_ARADDR(2), I4 => s_axi_gcd_bus_ARADDR(3), I5 => s_axi_gcd_bus_ARADDR(0), O => int_pResult_ap_vld1 ); int_pResult_ap_vld_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => int_pResult_ap_vld_i_1_n_0, Q => int_pResult_ap_vld, R => \^sr\(0) ); \int_pResult_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(0), Q => int_pResult(0), R => \^sr\(0) ); \int_pResult_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(10), Q => int_pResult(10), R => \^sr\(0) ); \int_pResult_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(11), Q => int_pResult(11), R => \^sr\(0) ); \int_pResult_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(12), Q => int_pResult(12), R => \^sr\(0) ); \int_pResult_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(13), Q => int_pResult(13), R => \^sr\(0) ); \int_pResult_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(14), Q => int_pResult(14), R => \^sr\(0) ); \int_pResult_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(15), Q => int_pResult(15), R => \^sr\(0) ); \int_pResult_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(1), Q => int_pResult(1), R => \^sr\(0) ); \int_pResult_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(2), Q => int_pResult(2), R => \^sr\(0) ); \int_pResult_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(3), Q => int_pResult(3), R => \^sr\(0) ); \int_pResult_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(4), Q => int_pResult(4), R => \^sr\(0) ); \int_pResult_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(5), Q => int_pResult(5), R => \^sr\(0) ); \int_pResult_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(6), Q => int_pResult(6), R => \^sr\(0) ); \int_pResult_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(7), Q => int_pResult(7), R => \^sr\(0) ); \int_pResult_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(8), Q => int_pResult(8), R => \^sr\(0) ); \int_pResult_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_done, D => \p_s_reg_45_reg[15]\(9), Q => int_pResult(9), R => \^sr\(0) ); interrupt_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => p_1_in, I1 => \int_isr_reg_n_0_[0]\, I2 => int_gie_reg_n_0, O => interrupt ); \rdata[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata[0]_i_2_n_0\, I1 => s_axi_gcd_bus_ARADDR(2), I2 => \rdata[0]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_gcd_bus_rdata\(0), O => \rdata[0]_i_1_n_0\ ); \rdata[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \int_ier_reg_n_0_[0]\, I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(0), I3 => s_axi_gcd_bus_ARADDR(5), I4 => s_axi_gcd_bus_ARADDR(3), I5 => \rdata[0]_i_4_n_0\, O => \rdata[0]_i_2_n_0\ ); \rdata[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033223000002230" ) port map ( I0 => int_pResult_ap_vld, I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_gie_reg_n_0, I3 => s_axi_gcd_bus_ARADDR(5), I4 => s_axi_gcd_bus_ARADDR(3), I5 => \int_isr_reg_n_0_[0]\, O => \rdata[0]_i_3_n_0\ ); \rdata[0]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(0), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(0), I3 => s_axi_gcd_bus_ARADDR(5), I4 => ap_start, O => \rdata[0]_i_4_n_0\ ); \rdata[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(10), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(10), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(10), O => \rdata[10]_i_1_n_0\ ); \rdata[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(11), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(11), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(11), O => \rdata[11]_i_1_n_0\ ); \rdata[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(12), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(12), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(12), O => \rdata[12]_i_1_n_0\ ); \rdata[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(13), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(13), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(13), O => \rdata[13]_i_1_n_0\ ); \rdata[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(14), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(14), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(14), O => \rdata[14]_i_1_n_0\ ); \rdata[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88888880" ) port map ( I0 => s_axi_gcd_bus_ARVALID, I1 => \^s_axi_gcd_bus_rvalid\(0), I2 => s_axi_gcd_bus_ARADDR(1), I3 => s_axi_gcd_bus_ARADDR(0), I4 => s_axi_gcd_bus_ARADDR(2), O => \rdata[15]_i_1_n_0\ ); \rdata[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^s_axi_gcd_bus_rvalid\(0), I1 => s_axi_gcd_bus_ARVALID, O => ar_hs ); \rdata[15]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(15), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(15), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(15), O => \rdata[15]_i_3_n_0\ ); \rdata[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \rdata[1]_i_2_n_0\, I1 => s_axi_gcd_bus_ARADDR(2), I2 => \rdata[1]_i_3_n_0\, I3 => \rdata[1]_i_4_n_0\, I4 => ar_hs, I5 => \^s_axi_gcd_bus_rdata\(1), O => \rdata[1]_i_1_n_0\ ); \rdata[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00E2FFFF00E20000" ) port map ( I0 => \int_ier_reg_n_0_[1]\, I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(1), I3 => s_axi_gcd_bus_ARADDR(5), I4 => s_axi_gcd_bus_ARADDR(3), I5 => \rdata[1]_i_5_n_0\, O => \rdata[1]_i_2_n_0\ ); \rdata[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(4), I1 => s_axi_gcd_bus_ARADDR(5), I2 => s_axi_gcd_bus_ARADDR(3), I3 => p_1_in, O => \rdata[1]_i_3_n_0\ ); \rdata[1]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => s_axi_gcd_bus_ARADDR(1), I1 => s_axi_gcd_bus_ARADDR(0), O => \rdata[1]_i_4_n_0\ ); \rdata[1]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(1), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(1), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_ap_done, O => \rdata[1]_i_5_n_0\ ); \rdata[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(2), I3 => s_axi_gcd_bus_ARADDR(3), I4 => \rdata[2]_i_2_n_0\, O => \rdata[2]_i_1_n_0\ ); \rdata[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(2), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(2), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_ap_idle, O => \rdata[2]_i_2_n_0\ ); \rdata[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(3), I3 => s_axi_gcd_bus_ARADDR(3), I4 => \rdata[3]_i_2_n_0\, O => \rdata[3]_i_1_n_0\ ); \rdata[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(3), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(3), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_ap_ready, O => \rdata[3]_i_2_n_0\ ); \rdata[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(4), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(4), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(4), O => \rdata[4]_i_1_n_0\ ); \rdata[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(5), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(5), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(5), O => \rdata[5]_i_1_n_0\ ); \rdata[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(6), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(6), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(6), O => \rdata[6]_i_1_n_0\ ); \rdata[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40FF4000" ) port map ( I0 => s_axi_gcd_bus_ARADDR(5), I1 => s_axi_gcd_bus_ARADDR(4), I2 => \^b_read_reg_102_reg[15]\(7), I3 => s_axi_gcd_bus_ARADDR(3), I4 => \rdata[7]_i_2_n_0\, O => \rdata[7]_i_1_n_0\ ); \rdata[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => \^a_read_reg_107_reg[15]\(7), I1 => s_axi_gcd_bus_ARADDR(4), I2 => int_pResult(7), I3 => s_axi_gcd_bus_ARADDR(5), I4 => int_auto_restart, O => \rdata[7]_i_2_n_0\ ); \rdata[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(8), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(8), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(8), O => \rdata[8]_i_1_n_0\ ); \rdata[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0033B8000000B800" ) port map ( I0 => \^b_read_reg_102_reg[15]\(9), I1 => s_axi_gcd_bus_ARADDR(3), I2 => \^a_read_reg_107_reg[15]\(9), I3 => s_axi_gcd_bus_ARADDR(4), I4 => s_axi_gcd_bus_ARADDR(5), I5 => int_pResult(9), O => \rdata[9]_i_1_n_0\ ); \rdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[0]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(0), R => '0' ); \rdata_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[10]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(10), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[11]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(11), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[12]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(12), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[13]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(13), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[14]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(14), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[15]_i_3_n_0\, Q => \^s_axi_gcd_bus_rdata\(15), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[1]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(1), R => '0' ); \rdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[2]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(2), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[3]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(3), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[4]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(4), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[5]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(5), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[6]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(6), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[7]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(7), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[8]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(8), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[9]_i_1_n_0\, Q => \^s_axi_gcd_bus_rdata\(9), R => \rdata[15]_i_1_n_0\ ); \waddr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^out\(0), I1 => s_axi_gcd_bus_AWVALID, O => waddr ); \waddr_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(0), Q => \waddr_reg_n_0_[0]\, R => '0' ); \waddr_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(1), Q => \waddr_reg_n_0_[1]\, R => '0' ); \waddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(2), Q => \waddr_reg_n_0_[2]\, R => '0' ); \waddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(3), Q => \waddr_reg_n_0_[3]\, R => '0' ); \waddr_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(4), Q => \waddr_reg_n_0_[4]\, R => '0' ); \waddr_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_gcd_bus_AWADDR(5), Q => \waddr_reg_n_0_[5]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is port ( ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_AWREADY : out STD_LOGIC; s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WREADY : out STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_ARREADY : out STD_LOGIC; s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BVALID : out STD_LOGIC; s_axi_gcd_bus_BREADY : in STD_LOGIC; s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); interrupt : out STD_LOGIC ); attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 6; attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer; attribute C_S_AXI_GCD_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b1000"; attribute hls_module : string; attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is signal \<const0>\ : STD_LOGIC; signal a : STD_LOGIC_VECTOR ( 15 downto 0 ); signal a_assign_fu_78_p21_out : STD_LOGIC_VECTOR ( 15 downto 0 ); signal a_assign_reg_121 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal a_assign_reg_1210 : STD_LOGIC; signal \a_assign_reg_121[11]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[11]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[11]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[11]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[15]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[3]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_2_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_3_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_4_n_0\ : STD_LOGIC; signal \a_assign_reg_121[7]_i_5_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[11]_i_1_n_3\ : STD_LOGIC; signal \a_assign_reg_121_reg[15]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[15]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[15]_i_1_n_3\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[3]_i_1_n_3\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_0\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_1\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_2\ : STD_LOGIC; signal \a_assign_reg_121_reg[7]_i_1_n_3\ : STD_LOGIC; signal a_read_reg_107 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC; signal ap_CS_fsm_state2 : STD_LOGIC; signal ap_CS_fsm_state3 : STD_LOGIC; signal ap_CS_fsm_state4 : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ap_NS_fsm1 : STD_LOGIC; signal ap_rst_n_inv : STD_LOGIC; signal b : STD_LOGIC_VECTOR ( 15 downto 0 ); signal b_assign_fu_84_p20_out : STD_LOGIC_VECTOR ( 15 downto 0 ); signal b_assign_reg_126 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \b_assign_reg_126[11]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[11]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[11]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[11]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[15]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[3]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_2_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_3_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_4_n_0\ : STD_LOGIC; signal \b_assign_reg_126[7]_i_5_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[11]_i_1_n_3\ : STD_LOGIC; signal \b_assign_reg_126_reg[15]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[15]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[15]_i_1_n_3\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[3]_i_1_n_3\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_0\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_1\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_2\ : STD_LOGIC; signal \b_assign_reg_126_reg[7]_i_1_n_3\ : STD_LOGIC; signal b_read_reg_102 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 ); signal p_s_reg_45 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \p_s_reg_45[0]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[10]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[11]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[12]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[13]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[14]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[15]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[15]_i_2_n_0\ : STD_LOGIC; signal \p_s_reg_45[1]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[2]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[3]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[4]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[5]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[6]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[7]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[8]_i_1_n_0\ : STD_LOGIC; signal \p_s_reg_45[9]_i_1_n_0\ : STD_LOGIC; signal result_reg_56 : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \result_reg_56[15]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal tmp_2_fu_66_p2 : STD_LOGIC; signal tmp_3_fu_72_p2 : STD_LOGIC; signal tmp_3_reg_115 : STD_LOGIC; signal \tmp_3_reg_115[0]_i_10_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_11_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_12_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_13_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_14_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_15_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_16_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_17_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_18_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_3_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_4_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_5_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_6_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_7_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_8_n_0\ : STD_LOGIC; signal \tmp_3_reg_115[0]_i_9_n_0\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_1_n_1\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_1_n_2\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_1_n_3\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_0\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_1\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_2\ : STD_LOGIC; signal \tmp_3_reg_115_reg[0]_i_2_n_3\ : STD_LOGIC; signal \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute FSM_ENCODING : string; attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none"; begin s_axi_gcd_bus_BRESP(1) <= \<const0>\; s_axi_gcd_bus_BRESP(0) <= \<const0>\; s_axi_gcd_bus_RDATA(31) <= \<const0>\; s_axi_gcd_bus_RDATA(30) <= \<const0>\; s_axi_gcd_bus_RDATA(29) <= \<const0>\; s_axi_gcd_bus_RDATA(28) <= \<const0>\; s_axi_gcd_bus_RDATA(27) <= \<const0>\; s_axi_gcd_bus_RDATA(26) <= \<const0>\; s_axi_gcd_bus_RDATA(25) <= \<const0>\; s_axi_gcd_bus_RDATA(24) <= \<const0>\; s_axi_gcd_bus_RDATA(23) <= \<const0>\; s_axi_gcd_bus_RDATA(22) <= \<const0>\; s_axi_gcd_bus_RDATA(21) <= \<const0>\; s_axi_gcd_bus_RDATA(20) <= \<const0>\; s_axi_gcd_bus_RDATA(19) <= \<const0>\; s_axi_gcd_bus_RDATA(18) <= \<const0>\; s_axi_gcd_bus_RDATA(17) <= \<const0>\; s_axi_gcd_bus_RDATA(16) <= \<const0>\; s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0); s_axi_gcd_bus_RRESP(1) <= \<const0>\; s_axi_gcd_bus_RRESP(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \a_assign_reg_121[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(11), I1 => p_s_reg_45(11), O => \a_assign_reg_121[11]_i_2_n_0\ ); \a_assign_reg_121[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(10), I1 => p_s_reg_45(10), O => \a_assign_reg_121[11]_i_3_n_0\ ); \a_assign_reg_121[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(9), I1 => p_s_reg_45(9), O => \a_assign_reg_121[11]_i_4_n_0\ ); \a_assign_reg_121[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(8), I1 => p_s_reg_45(8), O => \a_assign_reg_121[11]_i_5_n_0\ ); \a_assign_reg_121[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(15), I1 => p_s_reg_45(15), O => \a_assign_reg_121[15]_i_2_n_0\ ); \a_assign_reg_121[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(14), I1 => p_s_reg_45(14), O => \a_assign_reg_121[15]_i_3_n_0\ ); \a_assign_reg_121[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(13), I1 => p_s_reg_45(13), O => \a_assign_reg_121[15]_i_4_n_0\ ); \a_assign_reg_121[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(12), I1 => p_s_reg_45(12), O => \a_assign_reg_121[15]_i_5_n_0\ ); \a_assign_reg_121[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(3), I1 => p_s_reg_45(3), O => \a_assign_reg_121[3]_i_2_n_0\ ); \a_assign_reg_121[3]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(2), I1 => p_s_reg_45(2), O => \a_assign_reg_121[3]_i_3_n_0\ ); \a_assign_reg_121[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(1), I1 => p_s_reg_45(1), O => \a_assign_reg_121[3]_i_4_n_0\ ); \a_assign_reg_121[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(0), I1 => p_s_reg_45(0), O => \a_assign_reg_121[3]_i_5_n_0\ ); \a_assign_reg_121[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(7), I1 => p_s_reg_45(7), O => \a_assign_reg_121[7]_i_2_n_0\ ); \a_assign_reg_121[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(6), I1 => p_s_reg_45(6), O => \a_assign_reg_121[7]_i_3_n_0\ ); \a_assign_reg_121[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(5), I1 => p_s_reg_45(5), O => \a_assign_reg_121[7]_i_4_n_0\ ); \a_assign_reg_121[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => result_reg_56(4), I1 => p_s_reg_45(4), O => \a_assign_reg_121[7]_i_5_n_0\ ); \a_assign_reg_121_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(0), Q => a_assign_reg_121(0), R => '0' ); \a_assign_reg_121_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(10), Q => a_assign_reg_121(10), R => '0' ); \a_assign_reg_121_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(11), Q => a_assign_reg_121(11), R => '0' ); \a_assign_reg_121_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \a_assign_reg_121_reg[7]_i_1_n_0\, CO(3) => \a_assign_reg_121_reg[11]_i_1_n_0\, CO(2) => \a_assign_reg_121_reg[11]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[11]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[11]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => result_reg_56(11 downto 8), O(3 downto 0) => a_assign_fu_78_p21_out(11 downto 8), S(3) => \a_assign_reg_121[11]_i_2_n_0\, S(2) => \a_assign_reg_121[11]_i_3_n_0\, S(1) => \a_assign_reg_121[11]_i_4_n_0\, S(0) => \a_assign_reg_121[11]_i_5_n_0\ ); \a_assign_reg_121_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(12), Q => a_assign_reg_121(12), R => '0' ); \a_assign_reg_121_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(13), Q => a_assign_reg_121(13), R => '0' ); \a_assign_reg_121_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(14), Q => a_assign_reg_121(14), R => '0' ); \a_assign_reg_121_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(15), Q => a_assign_reg_121(15), R => '0' ); \a_assign_reg_121_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \a_assign_reg_121_reg[11]_i_1_n_0\, CO(3) => \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\(3), CO(2) => \a_assign_reg_121_reg[15]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[15]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => result_reg_56(14 downto 12), O(3 downto 0) => a_assign_fu_78_p21_out(15 downto 12), S(3) => \a_assign_reg_121[15]_i_2_n_0\, S(2) => \a_assign_reg_121[15]_i_3_n_0\, S(1) => \a_assign_reg_121[15]_i_4_n_0\, S(0) => \a_assign_reg_121[15]_i_5_n_0\ ); \a_assign_reg_121_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(1), Q => a_assign_reg_121(1), R => '0' ); \a_assign_reg_121_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(2), Q => a_assign_reg_121(2), R => '0' ); \a_assign_reg_121_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(3), Q => a_assign_reg_121(3), R => '0' ); \a_assign_reg_121_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \a_assign_reg_121_reg[3]_i_1_n_0\, CO(2) => \a_assign_reg_121_reg[3]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[3]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[3]_i_1_n_3\, CYINIT => '1', DI(3 downto 0) => result_reg_56(3 downto 0), O(3 downto 0) => a_assign_fu_78_p21_out(3 downto 0), S(3) => \a_assign_reg_121[3]_i_2_n_0\, S(2) => \a_assign_reg_121[3]_i_3_n_0\, S(1) => \a_assign_reg_121[3]_i_4_n_0\, S(0) => \a_assign_reg_121[3]_i_5_n_0\ ); \a_assign_reg_121_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(4), Q => a_assign_reg_121(4), R => '0' ); \a_assign_reg_121_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(5), Q => a_assign_reg_121(5), R => '0' ); \a_assign_reg_121_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(6), Q => a_assign_reg_121(6), R => '0' ); \a_assign_reg_121_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(7), Q => a_assign_reg_121(7), R => '0' ); \a_assign_reg_121_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \a_assign_reg_121_reg[3]_i_1_n_0\, CO(3) => \a_assign_reg_121_reg[7]_i_1_n_0\, CO(2) => \a_assign_reg_121_reg[7]_i_1_n_1\, CO(1) => \a_assign_reg_121_reg[7]_i_1_n_2\, CO(0) => \a_assign_reg_121_reg[7]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => result_reg_56(7 downto 4), O(3 downto 0) => a_assign_fu_78_p21_out(7 downto 4), S(3) => \a_assign_reg_121[7]_i_2_n_0\, S(2) => \a_assign_reg_121[7]_i_3_n_0\, S(1) => \a_assign_reg_121[7]_i_4_n_0\, S(0) => \a_assign_reg_121[7]_i_5_n_0\ ); \a_assign_reg_121_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(8), Q => a_assign_reg_121(8), R => '0' ); \a_assign_reg_121_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => a_assign_fu_78_p21_out(9), Q => a_assign_reg_121(9), R => '0' ); \a_read_reg_107_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(0), Q => a_read_reg_107(0), R => '0' ); \a_read_reg_107_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(10), Q => a_read_reg_107(10), R => '0' ); \a_read_reg_107_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(11), Q => a_read_reg_107(11), R => '0' ); \a_read_reg_107_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(12), Q => a_read_reg_107(12), R => '0' ); \a_read_reg_107_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(13), Q => a_read_reg_107(13), R => '0' ); \a_read_reg_107_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(14), Q => a_read_reg_107(14), R => '0' ); \a_read_reg_107_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(15), Q => a_read_reg_107(15), R => '0' ); \a_read_reg_107_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(1), Q => a_read_reg_107(1), R => '0' ); \a_read_reg_107_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(2), Q => a_read_reg_107(2), R => '0' ); \a_read_reg_107_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(3), Q => a_read_reg_107(3), R => '0' ); \a_read_reg_107_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(4), Q => a_read_reg_107(4), R => '0' ); \a_read_reg_107_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(5), Q => a_read_reg_107(5), R => '0' ); \a_read_reg_107_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(6), Q => a_read_reg_107(6), R => '0' ); \a_read_reg_107_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(7), Q => a_read_reg_107(7), R => '0' ); \a_read_reg_107_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(8), Q => a_read_reg_107(8), R => '0' ); \a_read_reg_107_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => a(9), Q => a_read_reg_107(9), R => '0' ); \ap_CS_fsm[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => ap_CS_fsm_state2, I1 => ap_CS_fsm_state4, O => ap_NS_fsm(2) ); \ap_CS_fsm[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ap_CS_fsm_state3, I1 => tmp_2_fu_66_p2, O => a_assign_reg_1210 ); \ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(0), Q => \ap_CS_fsm_reg_n_0_[0]\, S => ap_rst_n_inv ); \ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(1), Q => ap_CS_fsm_state2, R => ap_rst_n_inv ); \ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(2), Q => ap_CS_fsm_state3, R => ap_rst_n_inv ); \ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => a_assign_reg_1210, Q => ap_CS_fsm_state4, R => ap_rst_n_inv ); \b_assign_reg_126[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(11), I1 => result_reg_56(11), O => \b_assign_reg_126[11]_i_2_n_0\ ); \b_assign_reg_126[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(10), I1 => result_reg_56(10), O => \b_assign_reg_126[11]_i_3_n_0\ ); \b_assign_reg_126[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(9), I1 => result_reg_56(9), O => \b_assign_reg_126[11]_i_4_n_0\ ); \b_assign_reg_126[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(8), I1 => result_reg_56(8), O => \b_assign_reg_126[11]_i_5_n_0\ ); \b_assign_reg_126[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(15), I1 => result_reg_56(15), O => \b_assign_reg_126[15]_i_2_n_0\ ); \b_assign_reg_126[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(14), I1 => result_reg_56(14), O => \b_assign_reg_126[15]_i_3_n_0\ ); \b_assign_reg_126[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(13), I1 => result_reg_56(13), O => \b_assign_reg_126[15]_i_4_n_0\ ); \b_assign_reg_126[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(12), I1 => result_reg_56(12), O => \b_assign_reg_126[15]_i_5_n_0\ ); \b_assign_reg_126[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(3), I1 => result_reg_56(3), O => \b_assign_reg_126[3]_i_2_n_0\ ); \b_assign_reg_126[3]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(2), I1 => result_reg_56(2), O => \b_assign_reg_126[3]_i_3_n_0\ ); \b_assign_reg_126[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(1), I1 => result_reg_56(1), O => \b_assign_reg_126[3]_i_4_n_0\ ); \b_assign_reg_126[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(0), I1 => result_reg_56(0), O => \b_assign_reg_126[3]_i_5_n_0\ ); \b_assign_reg_126[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(7), I1 => result_reg_56(7), O => \b_assign_reg_126[7]_i_2_n_0\ ); \b_assign_reg_126[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(6), I1 => result_reg_56(6), O => \b_assign_reg_126[7]_i_3_n_0\ ); \b_assign_reg_126[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(5), I1 => result_reg_56(5), O => \b_assign_reg_126[7]_i_4_n_0\ ); \b_assign_reg_126[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => p_s_reg_45(4), I1 => result_reg_56(4), O => \b_assign_reg_126[7]_i_5_n_0\ ); \b_assign_reg_126_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(0), Q => b_assign_reg_126(0), R => '0' ); \b_assign_reg_126_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(10), Q => b_assign_reg_126(10), R => '0' ); \b_assign_reg_126_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(11), Q => b_assign_reg_126(11), R => '0' ); \b_assign_reg_126_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \b_assign_reg_126_reg[7]_i_1_n_0\, CO(3) => \b_assign_reg_126_reg[11]_i_1_n_0\, CO(2) => \b_assign_reg_126_reg[11]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[11]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[11]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => p_s_reg_45(11 downto 8), O(3 downto 0) => b_assign_fu_84_p20_out(11 downto 8), S(3) => \b_assign_reg_126[11]_i_2_n_0\, S(2) => \b_assign_reg_126[11]_i_3_n_0\, S(1) => \b_assign_reg_126[11]_i_4_n_0\, S(0) => \b_assign_reg_126[11]_i_5_n_0\ ); \b_assign_reg_126_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(12), Q => b_assign_reg_126(12), R => '0' ); \b_assign_reg_126_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(13), Q => b_assign_reg_126(13), R => '0' ); \b_assign_reg_126_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(14), Q => b_assign_reg_126(14), R => '0' ); \b_assign_reg_126_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(15), Q => b_assign_reg_126(15), R => '0' ); \b_assign_reg_126_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \b_assign_reg_126_reg[11]_i_1_n_0\, CO(3) => \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\(3), CO(2) => \b_assign_reg_126_reg[15]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[15]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => p_s_reg_45(14 downto 12), O(3 downto 0) => b_assign_fu_84_p20_out(15 downto 12), S(3) => \b_assign_reg_126[15]_i_2_n_0\, S(2) => \b_assign_reg_126[15]_i_3_n_0\, S(1) => \b_assign_reg_126[15]_i_4_n_0\, S(0) => \b_assign_reg_126[15]_i_5_n_0\ ); \b_assign_reg_126_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(1), Q => b_assign_reg_126(1), R => '0' ); \b_assign_reg_126_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(2), Q => b_assign_reg_126(2), R => '0' ); \b_assign_reg_126_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(3), Q => b_assign_reg_126(3), R => '0' ); \b_assign_reg_126_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \b_assign_reg_126_reg[3]_i_1_n_0\, CO(2) => \b_assign_reg_126_reg[3]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[3]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[3]_i_1_n_3\, CYINIT => '1', DI(3 downto 0) => p_s_reg_45(3 downto 0), O(3 downto 0) => b_assign_fu_84_p20_out(3 downto 0), S(3) => \b_assign_reg_126[3]_i_2_n_0\, S(2) => \b_assign_reg_126[3]_i_3_n_0\, S(1) => \b_assign_reg_126[3]_i_4_n_0\, S(0) => \b_assign_reg_126[3]_i_5_n_0\ ); \b_assign_reg_126_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(4), Q => b_assign_reg_126(4), R => '0' ); \b_assign_reg_126_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(5), Q => b_assign_reg_126(5), R => '0' ); \b_assign_reg_126_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(6), Q => b_assign_reg_126(6), R => '0' ); \b_assign_reg_126_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(7), Q => b_assign_reg_126(7), R => '0' ); \b_assign_reg_126_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \b_assign_reg_126_reg[3]_i_1_n_0\, CO(3) => \b_assign_reg_126_reg[7]_i_1_n_0\, CO(2) => \b_assign_reg_126_reg[7]_i_1_n_1\, CO(1) => \b_assign_reg_126_reg[7]_i_1_n_2\, CO(0) => \b_assign_reg_126_reg[7]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => p_s_reg_45(7 downto 4), O(3 downto 0) => b_assign_fu_84_p20_out(7 downto 4), S(3) => \b_assign_reg_126[7]_i_2_n_0\, S(2) => \b_assign_reg_126[7]_i_3_n_0\, S(1) => \b_assign_reg_126[7]_i_4_n_0\, S(0) => \b_assign_reg_126[7]_i_5_n_0\ ); \b_assign_reg_126_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(8), Q => b_assign_reg_126(8), R => '0' ); \b_assign_reg_126_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => b_assign_fu_84_p20_out(9), Q => b_assign_reg_126(9), R => '0' ); \b_read_reg_102_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(0), Q => b_read_reg_102(0), R => '0' ); \b_read_reg_102_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(10), Q => b_read_reg_102(10), R => '0' ); \b_read_reg_102_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(11), Q => b_read_reg_102(11), R => '0' ); \b_read_reg_102_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(12), Q => b_read_reg_102(12), R => '0' ); \b_read_reg_102_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(13), Q => b_read_reg_102(13), R => '0' ); \b_read_reg_102_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(14), Q => b_read_reg_102(14), R => '0' ); \b_read_reg_102_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(15), Q => b_read_reg_102(15), R => '0' ); \b_read_reg_102_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(1), Q => b_read_reg_102(1), R => '0' ); \b_read_reg_102_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(2), Q => b_read_reg_102(2), R => '0' ); \b_read_reg_102_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(3), Q => b_read_reg_102(3), R => '0' ); \b_read_reg_102_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(4), Q => b_read_reg_102(4), R => '0' ); \b_read_reg_102_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(5), Q => b_read_reg_102(5), R => '0' ); \b_read_reg_102_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(6), Q => b_read_reg_102(6), R => '0' ); \b_read_reg_102_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(7), Q => b_read_reg_102(7), R => '0' ); \b_read_reg_102_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(8), Q => b_read_reg_102(8), R => '0' ); \b_read_reg_102_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ap_NS_fsm1, D => b(9), Q => b_read_reg_102(9), R => '0' ); gcd_gcd_bus_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi port map ( CO(0) => tmp_2_fu_66_p2, D(1 downto 0) => ap_NS_fsm(1 downto 0), E(0) => ap_NS_fsm1, Q(3) => ap_CS_fsm_state4, Q(2) => ap_CS_fsm_state3, Q(1) => ap_CS_fsm_state2, Q(0) => \ap_CS_fsm_reg_n_0_[0]\, SR(0) => ap_rst_n_inv, \a_read_reg_107_reg[15]\(15 downto 0) => a(15 downto 0), ap_clk => ap_clk, ap_rst_n => ap_rst_n, \b_read_reg_102_reg[15]\(15 downto 0) => b(15 downto 0), interrupt => interrupt, \out\(2) => s_axi_gcd_bus_BVALID, \out\(1) => s_axi_gcd_bus_WREADY, \out\(0) => s_axi_gcd_bus_AWREADY, \p_s_reg_45_reg[15]\(15 downto 0) => p_s_reg_45(15 downto 0), \result_reg_56_reg[15]\(15 downto 0) => result_reg_56(15 downto 0), s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0), s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID, s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0), s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY, s_axi_gcd_bus_RDATA(15 downto 0) => \^s_axi_gcd_bus_rdata\(15 downto 0), s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY, s_axi_gcd_bus_RVALID(1) => s_axi_gcd_bus_RVALID, s_axi_gcd_bus_RVALID(0) => s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_WDATA(15 downto 0) => s_axi_gcd_bus_WDATA(15 downto 0), s_axi_gcd_bus_WSTRB(1 downto 0) => s_axi_gcd_bus_WSTRB(1 downto 0), s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID ); \p_s_reg_45[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(0), I1 => b_read_reg_102(0), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[0]_i_1_n_0\ ); \p_s_reg_45[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(10), I1 => b_read_reg_102(10), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[10]_i_1_n_0\ ); \p_s_reg_45[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(11), I1 => b_read_reg_102(11), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[11]_i_1_n_0\ ); \p_s_reg_45[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(12), I1 => b_read_reg_102(12), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[12]_i_1_n_0\ ); \p_s_reg_45[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(13), I1 => b_read_reg_102(13), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[13]_i_1_n_0\ ); \p_s_reg_45[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(14), I1 => b_read_reg_102(14), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[14]_i_1_n_0\ ); \p_s_reg_45[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"74" ) port map ( I0 => tmp_3_reg_115, I1 => ap_CS_fsm_state4, I2 => ap_CS_fsm_state2, O => \p_s_reg_45[15]_i_1_n_0\ ); \p_s_reg_45[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(15), I1 => b_read_reg_102(15), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[15]_i_2_n_0\ ); \p_s_reg_45[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(1), I1 => b_read_reg_102(1), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[1]_i_1_n_0\ ); \p_s_reg_45[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(2), I1 => b_read_reg_102(2), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[2]_i_1_n_0\ ); \p_s_reg_45[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(3), I1 => b_read_reg_102(3), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[3]_i_1_n_0\ ); \p_s_reg_45[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(4), I1 => b_read_reg_102(4), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[4]_i_1_n_0\ ); \p_s_reg_45[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(5), I1 => b_read_reg_102(5), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[5]_i_1_n_0\ ); \p_s_reg_45[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(6), I1 => b_read_reg_102(6), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[6]_i_1_n_0\ ); \p_s_reg_45[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(7), I1 => b_read_reg_102(7), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[7]_i_1_n_0\ ); \p_s_reg_45[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(8), I1 => b_read_reg_102(8), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[8]_i_1_n_0\ ); \p_s_reg_45[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => b_assign_reg_126(9), I1 => b_read_reg_102(9), I2 => ap_CS_fsm_state4, O => \p_s_reg_45[9]_i_1_n_0\ ); \p_s_reg_45_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[0]_i_1_n_0\, Q => p_s_reg_45(0), R => '0' ); \p_s_reg_45_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[10]_i_1_n_0\, Q => p_s_reg_45(10), R => '0' ); \p_s_reg_45_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[11]_i_1_n_0\, Q => p_s_reg_45(11), R => '0' ); \p_s_reg_45_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[12]_i_1_n_0\, Q => p_s_reg_45(12), R => '0' ); \p_s_reg_45_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[13]_i_1_n_0\, Q => p_s_reg_45(13), R => '0' ); \p_s_reg_45_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[14]_i_1_n_0\, Q => p_s_reg_45(14), R => '0' ); \p_s_reg_45_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[15]_i_2_n_0\, Q => p_s_reg_45(15), R => '0' ); \p_s_reg_45_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[1]_i_1_n_0\, Q => p_s_reg_45(1), R => '0' ); \p_s_reg_45_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[2]_i_1_n_0\, Q => p_s_reg_45(2), R => '0' ); \p_s_reg_45_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[3]_i_1_n_0\, Q => p_s_reg_45(3), R => '0' ); \p_s_reg_45_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[4]_i_1_n_0\, Q => p_s_reg_45(4), R => '0' ); \p_s_reg_45_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[5]_i_1_n_0\, Q => p_s_reg_45(5), R => '0' ); \p_s_reg_45_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[6]_i_1_n_0\, Q => p_s_reg_45(6), R => '0' ); \p_s_reg_45_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[7]_i_1_n_0\, Q => p_s_reg_45(7), R => '0' ); \p_s_reg_45_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[8]_i_1_n_0\, Q => p_s_reg_45(8), R => '0' ); \p_s_reg_45_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \p_s_reg_45[15]_i_1_n_0\, D => \p_s_reg_45[9]_i_1_n_0\, Q => p_s_reg_45(9), R => '0' ); \result_reg_56[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(0), I1 => a_read_reg_107(0), I2 => ap_CS_fsm_state4, O => p_1_in(0) ); \result_reg_56[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(10), I1 => a_read_reg_107(10), I2 => ap_CS_fsm_state4, O => p_1_in(10) ); \result_reg_56[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(11), I1 => a_read_reg_107(11), I2 => ap_CS_fsm_state4, O => p_1_in(11) ); \result_reg_56[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(12), I1 => a_read_reg_107(12), I2 => ap_CS_fsm_state4, O => p_1_in(12) ); \result_reg_56[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(13), I1 => a_read_reg_107(13), I2 => ap_CS_fsm_state4, O => p_1_in(13) ); \result_reg_56[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(14), I1 => a_read_reg_107(14), I2 => ap_CS_fsm_state4, O => p_1_in(14) ); \result_reg_56[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => tmp_3_reg_115, I1 => ap_CS_fsm_state4, I2 => ap_CS_fsm_state2, O => \result_reg_56[15]_i_1_n_0\ ); \result_reg_56[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(15), I1 => a_read_reg_107(15), I2 => ap_CS_fsm_state4, O => p_1_in(15) ); \result_reg_56[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(1), I1 => a_read_reg_107(1), I2 => ap_CS_fsm_state4, O => p_1_in(1) ); \result_reg_56[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(2), I1 => a_read_reg_107(2), I2 => ap_CS_fsm_state4, O => p_1_in(2) ); \result_reg_56[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(3), I1 => a_read_reg_107(3), I2 => ap_CS_fsm_state4, O => p_1_in(3) ); \result_reg_56[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(4), I1 => a_read_reg_107(4), I2 => ap_CS_fsm_state4, O => p_1_in(4) ); \result_reg_56[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(5), I1 => a_read_reg_107(5), I2 => ap_CS_fsm_state4, O => p_1_in(5) ); \result_reg_56[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(6), I1 => a_read_reg_107(6), I2 => ap_CS_fsm_state4, O => p_1_in(6) ); \result_reg_56[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(7), I1 => a_read_reg_107(7), I2 => ap_CS_fsm_state4, O => p_1_in(7) ); \result_reg_56[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(8), I1 => a_read_reg_107(8), I2 => ap_CS_fsm_state4, O => p_1_in(8) ); \result_reg_56[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => a_assign_reg_121(9), I1 => a_read_reg_107(9), I2 => ap_CS_fsm_state4, O => p_1_in(9) ); \result_reg_56_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(0), Q => result_reg_56(0), R => '0' ); \result_reg_56_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(10), Q => result_reg_56(10), R => '0' ); \result_reg_56_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(11), Q => result_reg_56(11), R => '0' ); \result_reg_56_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(12), Q => result_reg_56(12), R => '0' ); \result_reg_56_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(13), Q => result_reg_56(13), R => '0' ); \result_reg_56_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(14), Q => result_reg_56(14), R => '0' ); \result_reg_56_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(15), Q => result_reg_56(15), R => '0' ); \result_reg_56_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(1), Q => result_reg_56(1), R => '0' ); \result_reg_56_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(2), Q => result_reg_56(2), R => '0' ); \result_reg_56_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(3), Q => result_reg_56(3), R => '0' ); \result_reg_56_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(4), Q => result_reg_56(4), R => '0' ); \result_reg_56_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(5), Q => result_reg_56(5), R => '0' ); \result_reg_56_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(6), Q => result_reg_56(6), R => '0' ); \result_reg_56_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(7), Q => result_reg_56(7), R => '0' ); \result_reg_56_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(8), Q => result_reg_56(8), R => '0' ); \result_reg_56_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => \result_reg_56[15]_i_1_n_0\, D => p_1_in(9), Q => result_reg_56(9), R => '0' ); \tmp_3_reg_115[0]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(8), I1 => p_s_reg_45(8), I2 => result_reg_56(9), I3 => p_s_reg_45(9), O => \tmp_3_reg_115[0]_i_10_n_0\ ); \tmp_3_reg_115[0]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(6), I1 => p_s_reg_45(6), I2 => p_s_reg_45(7), I3 => result_reg_56(7), O => \tmp_3_reg_115[0]_i_11_n_0\ ); \tmp_3_reg_115[0]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(4), I1 => p_s_reg_45(4), I2 => p_s_reg_45(5), I3 => result_reg_56(5), O => \tmp_3_reg_115[0]_i_12_n_0\ ); \tmp_3_reg_115[0]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(2), I1 => p_s_reg_45(2), I2 => p_s_reg_45(3), I3 => result_reg_56(3), O => \tmp_3_reg_115[0]_i_13_n_0\ ); \tmp_3_reg_115[0]_i_14\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(0), I1 => p_s_reg_45(0), I2 => p_s_reg_45(1), I3 => result_reg_56(1), O => \tmp_3_reg_115[0]_i_14_n_0\ ); \tmp_3_reg_115[0]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(6), I1 => p_s_reg_45(6), I2 => result_reg_56(7), I3 => p_s_reg_45(7), O => \tmp_3_reg_115[0]_i_15_n_0\ ); \tmp_3_reg_115[0]_i_16\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(4), I1 => p_s_reg_45(4), I2 => result_reg_56(5), I3 => p_s_reg_45(5), O => \tmp_3_reg_115[0]_i_16_n_0\ ); \tmp_3_reg_115[0]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(2), I1 => p_s_reg_45(2), I2 => result_reg_56(3), I3 => p_s_reg_45(3), O => \tmp_3_reg_115[0]_i_17_n_0\ ); \tmp_3_reg_115[0]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(0), I1 => p_s_reg_45(0), I2 => result_reg_56(1), I3 => p_s_reg_45(1), O => \tmp_3_reg_115[0]_i_18_n_0\ ); \tmp_3_reg_115[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(14), I1 => p_s_reg_45(14), I2 => result_reg_56(15), I3 => p_s_reg_45(15), O => \tmp_3_reg_115[0]_i_3_n_0\ ); \tmp_3_reg_115[0]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(12), I1 => p_s_reg_45(12), I2 => p_s_reg_45(13), I3 => result_reg_56(13), O => \tmp_3_reg_115[0]_i_4_n_0\ ); \tmp_3_reg_115[0]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(10), I1 => p_s_reg_45(10), I2 => p_s_reg_45(11), I3 => result_reg_56(11), O => \tmp_3_reg_115[0]_i_5_n_0\ ); \tmp_3_reg_115[0]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"2F02" ) port map ( I0 => result_reg_56(8), I1 => p_s_reg_45(8), I2 => p_s_reg_45(9), I3 => result_reg_56(9), O => \tmp_3_reg_115[0]_i_6_n_0\ ); \tmp_3_reg_115[0]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(14), I1 => p_s_reg_45(14), I2 => p_s_reg_45(15), I3 => result_reg_56(15), O => \tmp_3_reg_115[0]_i_7_n_0\ ); \tmp_3_reg_115[0]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(12), I1 => p_s_reg_45(12), I2 => result_reg_56(13), I3 => p_s_reg_45(13), O => \tmp_3_reg_115[0]_i_8_n_0\ ); \tmp_3_reg_115[0]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => result_reg_56(10), I1 => p_s_reg_45(10), I2 => result_reg_56(11), I3 => p_s_reg_45(11), O => \tmp_3_reg_115[0]_i_9_n_0\ ); \tmp_3_reg_115_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => a_assign_reg_1210, D => tmp_3_fu_72_p2, Q => tmp_3_reg_115, R => '0' ); \tmp_3_reg_115_reg[0]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \tmp_3_reg_115_reg[0]_i_2_n_0\, CO(3) => tmp_3_fu_72_p2, CO(2) => \tmp_3_reg_115_reg[0]_i_1_n_1\, CO(1) => \tmp_3_reg_115_reg[0]_i_1_n_2\, CO(0) => \tmp_3_reg_115_reg[0]_i_1_n_3\, CYINIT => '0', DI(3) => \tmp_3_reg_115[0]_i_3_n_0\, DI(2) => \tmp_3_reg_115[0]_i_4_n_0\, DI(1) => \tmp_3_reg_115[0]_i_5_n_0\, DI(0) => \tmp_3_reg_115[0]_i_6_n_0\, O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \tmp_3_reg_115[0]_i_7_n_0\, S(2) => \tmp_3_reg_115[0]_i_8_n_0\, S(1) => \tmp_3_reg_115[0]_i_9_n_0\, S(0) => \tmp_3_reg_115[0]_i_10_n_0\ ); \tmp_3_reg_115_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \tmp_3_reg_115_reg[0]_i_2_n_0\, CO(2) => \tmp_3_reg_115_reg[0]_i_2_n_1\, CO(1) => \tmp_3_reg_115_reg[0]_i_2_n_2\, CO(0) => \tmp_3_reg_115_reg[0]_i_2_n_3\, CYINIT => '0', DI(3) => \tmp_3_reg_115[0]_i_11_n_0\, DI(2) => \tmp_3_reg_115[0]_i_12_n_0\, DI(1) => \tmp_3_reg_115[0]_i_13_n_0\, DI(0) => \tmp_3_reg_115[0]_i_14_n_0\, O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\(3 downto 0), S(3) => \tmp_3_reg_115[0]_i_15_n_0\, S(2) => \tmp_3_reg_115[0]_i_16_n_0\, S(1) => \tmp_3_reg_115[0]_i_17_n_0\, S(0) => \tmp_3_reg_115[0]_i_18_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_AWREADY : out STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WREADY : out STD_LOGIC; s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BVALID : out STD_LOGIC; s_axi_gcd_bus_BREADY : in STD_LOGIC; s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_ARREADY : out STD_LOGIC; s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_zynq_snick_gcd_0_0,gcd,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute IP_DEFINITION_SOURCE : string; attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HLS"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd,Vivado 2018.2"; attribute hls_module : string; attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer; attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of inst : label is 6; attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer; attribute C_S_AXI_GCD_BUS_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer; attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of inst : label is 4; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4; attribute ap_ST_fsm_state1 : string; attribute ap_ST_fsm_state1 of inst : label is "4'b0001"; attribute ap_ST_fsm_state2 : string; attribute ap_ST_fsm_state2 of inst : label is "4'b0010"; attribute ap_ST_fsm_state3 : string; attribute ap_ST_fsm_state3 of inst : label is "4'b0100"; attribute ap_ST_fsm_state4 : string; attribute ap_ST_fsm_state4 of inst : label is "4'b1000"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST"; attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}"; attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT"; attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_gcd_bus_RREADY : signal is "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA"; attribute X_INTERFACE_INFO of s_axi_gcd_bus_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd port map ( ap_clk => ap_clk, ap_rst_n => ap_rst_n, interrupt => interrupt, s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0), s_axi_gcd_bus_ARREADY => s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID, s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0), s_axi_gcd_bus_AWREADY => s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY, s_axi_gcd_bus_BRESP(1 downto 0) => s_axi_gcd_bus_BRESP(1 downto 0), s_axi_gcd_bus_BVALID => s_axi_gcd_bus_BVALID, s_axi_gcd_bus_RDATA(31 downto 0) => s_axi_gcd_bus_RDATA(31 downto 0), s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY, s_axi_gcd_bus_RRESP(1 downto 0) => s_axi_gcd_bus_RRESP(1 downto 0), s_axi_gcd_bus_RVALID => s_axi_gcd_bus_RVALID, s_axi_gcd_bus_WDATA(31 downto 0) => s_axi_gcd_bus_WDATA(31 downto 0), s_axi_gcd_bus_WREADY => s_axi_gcd_bus_WREADY, s_axi_gcd_bus_WSTRB(3 downto 0) => s_axi_gcd_bus_WSTRB(3 downto 0), s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID ); end STRUCTURE;
mit
4d254222be76e9dfe1a1fc04426e08bc
0.513364
2.509146
false
false
false
false
kuba-moo/VHDL-lib
reg_master_uart.vhd
2
5,493
-- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- -- Copyright (C) 2014 Jakub Kicinski <[email protected]> library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.math_real.all; use work.globals.all; -- UART interface for registers entity reg_master_uart is generic (REQ_SIZE : integer); -- #bytes per req port (Clk : in std_logic; Rst : in std_logic; RxByte : in byte_t; RxValid : in std_logic; TxByte : out byte_t; TxKick : out std_logic; TxBusy : in std_logic; BusO : out reg_bus_t; BusI : in reg_bus_t); end reg_master_uart; -- Operation: -- 1. receive Request from UART; -- 2. convert Request to reg_bus_t format; -- 3. send Request onto bus; -- 4. read Response from the bus (bus is looped); -- 5. convert Response to Request format; -- 6. send Response to UART. -- -- All UART frames have identical format. -- - in read requests data is treated as default value (value which will -- be returned if no register matches the address -- - in write responses data is just an echo of the request and should NOT -- be treated as new value of the register -- -- Request bit format: -- offset | field -- ---------------+------------------------------ -- 0 | read(0)/write(1) -- 1 - REG_ADDR_W | address -- ------------align-to-byte-boundary------------ -- REQ_SIZE * 8 | data (default value for read) -- -- -- WARNING: generating ny operation targeting invalid address (read or write -- that encompasses address with all 1's) will HUNG the bus master!!! architecture Behavioral of reg_master_uart is constant REQ_HDR_LEN : integer := integer(ceil(real(1 + REG_ADDR_W)/8.0)); constant REQ_MAX_LEN : integer := REQ_HDR_LEN + REQ_SIZE; type state_t is (WAIT_REQ, EMIT, WAIT_LOOP, RESPOND, WAIT_UART); subtype req_buffer_t is std_logic_vector(REQ_MAX_LEN*8 - 1 downto 0); constant ReqRWBit : integer := 0; subtype ReqAddr is natural range REG_ADDR_W downto 1; signal state, NEXT_state : state_t; signal cnt, NEXT_cnt : integer range 0 to REQ_MAX_LEN := 0; signal req_buf, NEXT_req_buf : req_buffer_t; signal res_cnt, NEXT_res_cnt : integer range 0 to REQ_MAX_LEN; begin NEXT_fsm : process (state, cnt, req_buf, res_cnt, RxValid, RxByte, TxBusy, BusI, NEXT_cnt) begin NEXT_state <= state; NEXT_cnt <= cnt; NEXT_req_buf <= req_buf; NEXT_res_cnt <= res_cnt; TxByte <= req_buf(cnt*8 + 7 downto cnt*8); TxKick <= '0'; BusO.wr <= req_buf(ReqRWBit); BusO.addr <= reg_addr_invl; BusO.data <= (others => '0'); if BusI.addr /= reg_addr_invl then -- data coming back NEXT_req_buf((res_cnt + REQ_HDR_LEN)*8 + 7 downto (res_cnt + REQ_HDR_LEN)*8) <= BusI.data; NEXT_res_cnt <= res_cnt + 1; end if; case state is when WAIT_REQ => if RxValid = '1' then NEXT_req_buf(cnt*8 + 7 downto cnt*8) <= RxByte; NEXT_cnt <= cnt + 1; end if; if cnt = REQ_MAX_LEN then NEXT_state <= EMIT; NEXT_cnt <= 0; NEXT_res_cnt <= 0; end if; when EMIT => NEXT_cnt <= cnt + 1; BusO.addr <= CONV_std_logic_vector(cnt + CONV_integer(req_buf(ReqAddr)), REG_ADDR_W); BusO.data <= req_buf((cnt + REQ_HDR_LEN)*8 + 7 downto (cnt + REQ_HDR_LEN)*8); if NEXT_cnt = REQ_SIZE then -- wait until data loops back NEXT_state <= WAIT_LOOP; end if; when WAIT_LOOP => if res_cnt = REQ_SIZE then NEXT_state <= RESPOND; NEXT_cnt <= 0; end if; when RESPOND => NEXT_state <= WAIT_UART; NEXT_cnt <= cnt + 1; TxKick <= '1'; when WAIT_UART => if TxBusy = '0' then NEXT_state <= RESPOND; end if; if cnt = REQ_MAX_LEN then NEXT_state <= WAIT_REQ; NEXT_cnt <= 0; end if; end case; end process; fsm : process (Clk) begin if rising_edge(Clk) then state <= NEXT_state; cnt <= NEXT_cnt; req_buf <= NEXT_req_buf; res_cnt <= NEXT_res_cnt; if Rst = '1' then state <= WAIT_REQ; cnt <= 0; end if; end if; end process; end Behavioral;
gpl-3.0
862190cadece5df470c57847f7b8913b
0.534863
3.716509
false
false
false
false
astoria-d/super-duper-nes
duper_cartridge/simulation/bbb2nes_testbench.vhd
1
10,603
library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_unsigned.all; entity nes2bbb_testbench is end nes2bbb_testbench; architecture stimulus of nes2bbb_testbench is constant powerup_time : time := 1500 ns; constant reset_time : time := 1800 ns; --DE1 base clock = 50 MHz constant base_clock_time : time := 20 ns; --i2c normal clock speed 100 KHz constant i2c_clock_time : time := 10 us; --i2c clock timing.. constant i2c_clk_0 : std_logic_vector(1 downto 0) := "00"; constant i2c_clk_1 : std_logic_vector(1 downto 0) := "01"; constant i2c_clk_2 : std_logic_vector(1 downto 0) := "10"; constant i2c_clk_3 : std_logic_vector(1 downto 0) := "11"; ---https://wiki.nesdev.com/w/index.php/Clock_rate --nes cpu clock = 1.789773 MHz constant nes_clock_time : time := 558 ns; constant bus_cycle : integer := 3; ---fifo status register ---bit ---7 always 0 ---6 always 0 ---5 read fifo full ---4 read fifo empty ---3 always 0 ---2 always 0 ---1 write fifo full ---0 write fifo empty constant wfifo_empty_bit : integer := 0; constant wfifo_full_bit : integer := 1; constant rfifo_empty_bit : integer := 4; constant rfifo_full_bit : integer := 5; constant i2c_read : std_logic := '1'; constant i2c_write : std_logic := '0'; component duper_cartridge port ( pi_reset_n : in std_logic; pi_base_clk : in std_logic; --nes side pi_phi2 : in std_logic; pi_prg_ce_n : in std_logic; pi_prg_r_nw : in std_logic; pi_prg_addr : in std_logic_vector(14 downto 0); pio_prg_data : inout std_logic_vector(7 downto 0); pi_chr_ce_n : in std_logic; pi_chr_oe_n : in std_logic; pi_chr_we_n : in std_logic; pi_chr_addr : in std_logic_vector(12 downto 0); po_chr_data : out std_logic_vector(7 downto 0); --i2c side pi_i2c_scl : in std_logic; pio_i2c_sda : inout std_logic; --bbb gpio po_nes_f_full : out std_logic; po_bbb_f_empty : out std_logic; po_dbg_cnt : out std_logic_vector (63 downto 0) ); end component ; signal reset_input : std_logic; signal base_clk : std_logic; signal phi2 : std_logic; signal prg_ce_n : std_logic; signal prg_r_nw : std_logic; signal prg_addr : std_logic_vector(14 downto 0); signal prg_data : std_logic_vector(7 downto 0); signal chr_ce_n : std_logic; signal chr_oe_n : std_logic; signal chr_we_n : std_logic; signal chr_addr : std_logic_vector(12 downto 0); signal chr_data : std_logic_vector(7 downto 0); signal i2c_scl : std_logic; signal i2c_scl_x4 : std_logic; signal i2c_scl_type : std_logic_vector(1 downto 0); signal i2c_sda : std_logic; signal nes_f_full : std_logic; signal bbb_f_empty : std_logic; signal dbg_cnt : std_logic_vector (63 downto 0); signal reg_rom_data : std_logic_vector(7 downto 0); signal reg_bbb_data : std_logic_vector (7 downto 0); signal start_scl : std_logic; signal step_cnt : integer range 0 to 65535 := 0; signal stage_cnt : integer range 0 to 65535 := 0; signal i2c_step_cnt : integer range 0 to 65535 := 0; signal addr_index : integer range 0 to 65535 := 0; signal data_index : integer range 0 to 65535 := 0; begin ---chrrom side disabled.. chr_ce_n <= 'Z'; chr_oe_n <= 'Z'; chr_we_n <= 'Z'; chr_addr <= (others => 'Z'); chr_data <= (others => 'Z'); sim_board : duper_cartridge port map ( reset_input, base_clk, phi2, prg_ce_n, prg_r_nw, prg_addr, prg_data, chr_ce_n, chr_oe_n, chr_we_n, chr_addr, chr_data, i2c_scl, i2c_sda, nes_f_full, bbb_f_empty, dbg_cnt); --- input reset. reset_p: process begin reset_input <= '1'; wait for powerup_time; reset_input <= '0'; wait for reset_time; reset_input <= '1'; wait; end process; --- generate base clock. clock_p1 : process begin base_clk <= '1'; wait for base_clock_time / 2; base_clk <= '0'; wait for base_clock_time / 2; end process; --- phi clock. clock_phi : process begin phi2 <= '1'; wait for nes_clock_time / 2; phi2 <= '0'; wait for nes_clock_time / 2; end process; --- i2c base clock. clock_i2c_base : process begin i2c_scl_x4 <= '1'; wait for i2c_clock_time / 8; i2c_scl_x4 <= '0'; wait for i2c_clock_time / 8; end process; --- i2c clock. clock_i2c : process (reset_input, i2c_scl_x4) begin if (reset_input = '0') then i2c_scl_type <= i2c_clk_0; i2c_scl <= '1'; elsif (rising_edge(i2c_scl_x4)) then i2c_scl_type <= i2c_scl_type + 1; if(start_scl = '1') then if (i2c_scl_type = i2c_clk_0) then i2c_scl <= '1'; elsif (i2c_scl_type = i2c_clk_2) then i2c_scl <= '0'; end if; else i2c_scl <= '1'; end if; end if; end process; --- cpu bus emulation... emu_cpu : process (reset_input, phi2) procedure mem_read ( addr : in std_logic_vector (14 downto 0) ) is begin prg_ce_n <= '0'; prg_r_nw <= '1'; prg_addr <= addr; prg_data <= (others => 'Z'); end; procedure bus_wait is begin prg_ce_n <= '1'; prg_r_nw <= 'Z'; prg_addr <= (others => 'Z'); prg_data <= (others => 'Z'); end; begin if (reset_input = '0') then stage_cnt <= 0; step_cnt <= 0; elsif (rising_edge(phi2)) then ---stage 0: initialize.... if (stage_cnt = 0) then if (step_cnt = 10) then stage_cnt <= stage_cnt + 1; step_cnt <= 0; else step_cnt <= step_cnt + 1; end if; ---stage 1: rom read..... elsif (stage_cnt = 1) then if (step_cnt < 500) then if (step_cnt mod bus_cycle = 0) then --check status. mem_read (conv_std_logic_vector(16#fff8#, 15)); else bus_wait; end if; elsif (step_cnt < 2000) then if (step_cnt mod bus_cycle = 0) then --read fifo. mem_read (conv_std_logic_vector(16#fff9#, 15)); else bus_wait; end if; end if; step_cnt <= step_cnt + 1; end if; end if; end process; --- i2c bus emulation... i2c_cpu : process (reset_input, i2c_scl_x4) procedure increment_cnt is begin if (i2c_scl_type = i2c_clk_0) then i2c_step_cnt <= i2c_step_cnt + 1; end if; end; procedure start_seq is begin if (i2c_scl_type = i2c_clk_1) then i2c_sda <= '0'; end if; end; procedure output_addr ( i : in integer; addr : in std_logic_vector (6 downto 0) ) is begin if (i2c_scl_type = i2c_clk_3) then i2c_sda <= addr(i); end if; end; procedure set_rw ( rw : in std_logic ) is begin if (i2c_scl_type = i2c_clk_3) then i2c_sda <= rw; end if; end; procedure ack_wait is begin if (i2c_scl_type = i2c_clk_3) then i2c_sda <= 'Z'; end if; end; procedure output_data ( i : in integer; data : in std_logic_vector (7 downto 0) ) is begin if (i2c_scl_type = i2c_clk_3 and (i >= 0 and i < 8)) then i2c_sda <= data(i); end if; end; begin if (reset_input = '0') then i2c_step_cnt <= 0; i2c_sda <= '1'; start_scl <= '0'; addr_index <= 0; data_index <= 0; elsif (rising_edge(i2c_scl_x4)) then ---stage 1: i2c read..... if (stage_cnt = 1) then increment_cnt; if (i2c_step_cnt < 3) then start_scl <= '1'; elsif (i2c_step_cnt = 3) then addr_index <= i2c_step_cnt + 1; elsif (i2c_step_cnt = addr_index) then --start up seq... start_seq; --set i2c addr... --addr output with write..... --0x44 = 100 0101. output_addr(6 - i2c_step_cnt + addr_index, conv_std_logic_vector(16#44#, 7)); elsif (i2c_step_cnt <= addr_index + 6) then output_addr(6 - i2c_step_cnt + addr_index, conv_std_logic_vector(16#44#, 7)); elsif (i2c_step_cnt = addr_index + 7) then set_rw(i2c_write); elsif (i2c_step_cnt = addr_index + 8) then --wait ack... ack_wait; data_index <= i2c_step_cnt + 1; elsif (i2c_step_cnt = data_index + 9) then if (i2c_scl_type = i2c_clk_2) then ---infinete repeat... data_index <= data_index + 9; end if; elsif (i2c_step_cnt < data_index + 9) then output_data(7 - i2c_step_cnt + data_index, conv_std_logic_vector(data_index mod 256, 8)); if (i2c_step_cnt = data_index + 8) then ack_wait; end if; end if; end if; end if; end process; end stimulus;
apache-2.0
7a323a375ed4db1f8d69555b02d50e3e
0.467981
3.349021
false
false
false
false
natsutan/NPU
fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_16_16/synth/mult_16_16.vhd
1
5,692
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:mult_gen:12.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY mult_gen_v12_0_12; USE mult_gen_v12_0_12.mult_gen_v12_0_12; ENTITY mult_16_16 IS PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END mult_16_16; ARCHITECTURE mult_16_16_arch OF mult_16_16 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_16_16_arch: ARCHITECTURE IS "yes"; COMPONENT mult_gen_v12_0_12 IS GENERIC ( C_VERBOSITY : INTEGER; C_MODEL_TYPE : INTEGER; C_OPTIMIZE_GOAL : INTEGER; C_XDEVICEFAMILY : STRING; C_HAS_CE : INTEGER; C_HAS_SCLR : INTEGER; C_LATENCY : INTEGER; C_A_WIDTH : INTEGER; C_A_TYPE : INTEGER; C_B_WIDTH : INTEGER; C_B_TYPE : INTEGER; C_OUT_HIGH : INTEGER; C_OUT_LOW : INTEGER; C_MULT_TYPE : INTEGER; C_CE_OVERRIDES_SCLR : INTEGER; C_CCM_IMP : INTEGER; C_B_VALUE : STRING; C_HAS_ZERO_DETECT : INTEGER; C_ROUND_OUTPUT : INTEGER; C_ROUND_PT : INTEGER ); PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); CE : IN STD_LOGIC; SCLR : IN STD_LOGIC; P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT mult_gen_v12_0_12; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF mult_16_16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF mult_16_16_arch : ARCHITECTURE IS "mult_16_16,mult_gen_v12_0_12,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF mult_16_16_arch: ARCHITECTURE IS "mult_16_16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=4,C_A_WIDTH=16,C_A_TYPE=0,C_B_WIDTH=16,C_B_TYPE=0,C_OUT_HIGH=31,C_OUT_LOW=24,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA"; BEGIN U0 : mult_gen_v12_0_12 GENERIC MAP ( C_VERBOSITY => 0, C_MODEL_TYPE => 0, C_OPTIMIZE_GOAL => 1, C_XDEVICEFAMILY => "kintexu", C_HAS_CE => 0, C_HAS_SCLR => 0, C_LATENCY => 4, C_A_WIDTH => 16, C_A_TYPE => 0, C_B_WIDTH => 16, C_B_TYPE => 0, C_OUT_HIGH => 31, C_OUT_LOW => 24, C_MULT_TYPE => 0, C_CE_OVERRIDES_SCLR => 0, C_CCM_IMP => 0, C_B_VALUE => "10000001", C_HAS_ZERO_DETECT => 0, C_ROUND_OUTPUT => 0, C_ROUND_PT => 0 ) PORT MAP ( CLK => CLK, A => A, B => B, CE => '1', SCLR => '0', P => P ); END mult_16_16_arch;
bsd-3-clause
ff438a9069326f2e8fc52030aed7c4d7
0.678496
3.348235
false
false
false
false
Feuerwerk/fpgaNES
data_path.vhd
1
3,730
/* This file is part of fpgaNES. fpgaNES is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. fpgaNES is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with fpgaNES. If not, see <http://www.gnu.org/licenses/>. */ -- this component get accessed by the cpu if a value should be read from -- memory or be written to. it covers the complete cpu address space -- and redirects the requests to the specific sub modules like -- the program ROM, the RAM, the PPU- or APU-ports library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity data_path is port ( i_clk : in std_logic; i_clk_enable : in std_logic := '1'; i_reset_n : in std_logic; i_sync : in std_logic; i_addr : in std_logic_vector(15 downto 0); i_data : in std_logic_vector(7 downto 0); i_write_enable : in std_logic; i_ppu_q : in std_logic_vector(7 downto 0); i_apu_q : in std_logic_vector(7 downto 0); i_prg_q : in std_logic_vector(7 downto 0); i_pio_q : in std_logic_vector(7 downto 0); o_prg_addr : out std_logic_vector(14 downto 0); o_prg_cs_n : out std_logic; o_ppu_addr : out std_logic_vector(2 downto 0); o_ppu_cs_n : out std_logic; o_apu_addr : out std_logic_vector(4 downto 0); o_apu_cs_n : out std_logic; o_pio_addr : out std_logic_vector(2 downto 0); o_pio_cs_n : out std_logic; o_q : out std_logic_vector(7 downto 0) ); end data_path; architecture behavioral of data_path is component datamem is port ( address : in std_logic_vector(10 downto 0); clken : in std_logic := '1'; clock : in std_logic := '1'; data : in std_logic_vector(7 downto 0); wren : in std_logic; q : out std_logic_vector(7 downto 0) ); end component; type addr_type_t is (nop, ram, rom, ppu, apu, pio); signal s_prgram_addr : std_logic_vector(10 downto 0); signal s_prgram_q : std_logic_vector(7 downto 0); signal s_prgram_write_enable : std_logic; signal s_curr_addr : std_logic_vector(15 downto 0); signal s_ppu_addr : std_logic_vector(14 downto 0); signal s_addr_type : addr_type_t; signal s_addr_type_d : addr_type_t := nop; begin prgram : datamem port map ( address => s_prgram_addr, clken => i_clk_enable, clock => i_clk, data => i_data, wren => s_prgram_write_enable, q => s_prgram_q ); process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then s_addr_type_d <= s_addr_type; end if; end if; end process; s_addr_type <= ppu when i_addr(15 downto 13) = "001" else ram when i_addr(15 downto 13) = "000" else pio when i_addr(15 downto 3) = "0100000000011" else apu when i_addr(15 downto 5) = "01000000000" else rom; with s_addr_type_d select o_q <= s_prgram_q when ram, i_ppu_q when ppu, i_apu_q when apu, i_pio_q when pio, i_prg_q when others; s_prgram_addr <= i_addr(10 downto 0); s_prgram_write_enable <= i_write_enable when s_addr_type = ram else '0'; o_ppu_addr <= i_addr(2 downto 0); o_apu_addr <= i_addr(4 downto 0); o_prg_addr <= i_addr(14 downto 0); o_pio_addr <= i_addr(2 downto 0); o_pio_cs_n <= not i_clk_enable when s_addr_type = pio else '1'; o_ppu_cs_n <= not i_sync when s_addr_type = ppu else '1'; o_apu_cs_n <= not i_clk_enable when s_addr_type = apu else '1'; o_prg_cs_n <= i_sync nand i_addr(15); end;
gpl-3.0
af3c088ba37de05dfb030d2a4499c4bb
0.670509
2.720642
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.cache/ip/2018.2/ad4f3760cb81ab99/zybo_zynq_design_rst_ps7_0_100M_0_sim_netlist.vhdl
1
35,484
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Sun Sep 22 02:34:31 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_rst_ps7_0_100M_0_sim_netlist.vhdl -- Design : zybo_zynq_design_rst_ps7_0_100M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => p_1_in, I2 => p_2_in, I3 => \^scndry_out\, I4 => asr_lpf(0), O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is signal exr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => exr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => exr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(1), I2 => p_3_out(2), I3 => \^scndry_out\, I4 => p_3_out(0), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => dcm_locked, I1 => lpf_exr, I2 => lpf_asr, I3 => Q, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0090" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9000" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0018" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(0), I2 => seq_cnt(2), I3 => seq_cnt(1), O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0480" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zybo_zynq_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;
mit
5f64558e7503c120abfdcc729572cd7b
0.588941
2.919292
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_rst_ps7_0_49M_0/sim/gcd_zynq_snick_rst_ps7_0_49M_0.vhd
2
7,307
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_12; USE proc_sys_reset_v5_0_12.proc_sys_reset; ENTITY gcd_zynq_snick_rst_ps7_0_49M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END gcd_zynq_snick_rst_ps7_0_49M_0; ARCHITECTURE gcd_zynq_snick_rst_ps7_0_49M_0_arch OF gcd_zynq_snick_rst_ps7_0_49M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF gcd_zynq_snick_rst_ps7_0_49M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END gcd_zynq_snick_rst_ps7_0_49M_0_arch;
mit
925d452eb93c817613b4228e017c6cd9
0.725469
3.610178
false
false
false
false
Feuerwerk/fpgaNES
ppu.vhd
1
43,716
/* This file is part of fpgaNES. fpgaNES is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. fpgaNES is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with fpgaNES. If not, see <http://www.gnu.org/licenses/>. */ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.common.all; entity parallel_serial_shifter is generic ( width: integer := 8; size: integer := 8 ); port ( i_clk: in std_logic; i_clk_enable : in std_logic := '1'; i_load: in std_logic; i_enable: in std_logic; i_data: in std_logic_vector(size - 1 downto 0); o_q: out std_logic_vector(size - 1 downto 0) ); end parallel_serial_shifter; architecture behavioral of parallel_serial_shifter is signal s_buffer: std_logic_vector(width - 1 downto 0); begin process (i_clk, i_clk_enable) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_enable = '1' and i_load = '1' then s_buffer <= s_buffer(width - 2 downto size) & i_data & '0'; elsif i_enable = '1' then s_buffer <= s_buffer(width - 2 downto 0) & '0'; elsif i_load = '1' then s_buffer(size - 1 downto 0) <= i_data; end if; end if; end if; end process; o_q <= reverse_vector(s_buffer(width - 1 downto width - size)); end architecture; /*****************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity sprite_renderer is port ( i_sprite_x : in std_logic_vector(7 downto 0); i_line_x : in std_logic_vector(7 downto 0); i_tile_low : in std_logic_vector(7 downto 0); i_tile_high : in std_logic_vector(7 downto 0); i_enable : in std_logic; i_first_col : in std_logic; o_pixel : out std_logic_vector(1 downto 0) ); end sprite_renderer; architecture behavioral of sprite_renderer is signal s_offset : integer range 0 to 7; signal s_sprite_right : std_logic_vector(8 downto 0); signal s_draw_n : boolean; begin s_offset <= to_integer(unsigned(i_sprite_x(2 downto 0) - i_line_x(2 downto 0) - "001")); s_sprite_right <= ('0' & i_sprite_x) + "000001000"; s_draw_n <= (i_first_col = '0') and (i_line_x(7 downto 3) = "00000"); o_pixel <= "00" when (i_enable = '0') or s_draw_n or (i_line_x < i_sprite_x) or (i_line_x >= s_sprite_right) else i_tile_high(s_offset) & i_tile_low(s_offset); end architecture; /*****************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.common.all; entity ppu is port ( i_clk : in std_logic; i_clk_enable : in std_logic := '1'; i_reset_n : in std_logic := '1'; i_video_mode : in video_mode_t := ntsc; i_addr : in std_logic_vector(2 downto 0) := "000"; i_data : in std_logic_vector(7 downto 0) := x"00"; i_write_enable : in std_logic := '0'; i_cs_n : in std_logic := '0'; i_chr_data : in std_logic_vector(7 downto 0) := x"00"; o_q : out std_logic_vector(7 downto 0); o_int_n : out std_logic; o_vga_addr : out std_logic_vector(15 downto 0); o_vga_data : out std_logic_vector(8 downto 0); o_vga_write_enable : out std_logic; o_chr_addr : out std_logic_vector(13 downto 0); o_chr_read_enable : out std_logic; o_chr_write_enable : out std_logic; o_chr_q : out std_logic_vector(7 downto 0) ); end ppu; architecture behavioral of ppu is component parallel_serial_shifter is generic ( width: integer := 8; size: integer := 8 ); port ( i_clk : in std_logic; i_clk_enable : in std_logic := '1'; i_load : in std_logic; i_enable : in std_logic; i_data : in std_logic_vector(7 downto 0); o_q : out std_logic_vector(7 downto 0) ); end component; component spritemem is port ( address : in std_logic_vector(7 downto 0); clken : in std_logic := '1'; clock : in std_logic := '1'; data : in std_logic_vector(7 downto 0); wren : in std_logic := '0'; q : out std_logic_vector(7 downto 0) ); end component; component soamem is port ( address : in std_logic_vector(4 downto 0); clken : in std_logic := '1'; clock : in std_logic := '1'; data : in std_logic_vector(7 downto 0); wren : in std_logic; q : out std_logic_vector(7 downto 0) ); end component; component sprite_renderer is port ( i_sprite_x : in std_logic_vector(7 downto 0); i_line_x : in std_logic_vector(7 downto 0); i_tile_low : in std_logic_vector(7 downto 0); i_tile_high : in std_logic_vector(7 downto 0); i_enable : in std_logic; i_first_col : in std_logic; o_pixel : out std_logic_vector(1 downto 0) ); end component; function to_pal_idx(addr: std_logic_vector(4 downto 0)) return integer is begin if (addr(4) = '1') and (addr(1 downto 0) = "00") then return to_integer(unsigned('0' & addr(3 downto 0))); else return to_integer(unsigned(addr)); end if; end; type sprite_t is record x : std_logic_vector(7 downto 0); tile_low : std_logic_vector(7 downto 0); tile_high : std_logic_vector(7 downto 0); priority : std_logic; palette : std_logic_vector(1 downto 0); pixel : std_logic_vector(1 downto 0); end record; type io_state_t is (idle, ppuctrl, ppumask, ppustatus, oamaddr, oamdata_read, oamdata_write, ppuscroll_x, ppuscroll_y, ppuaddr_hi, ppuaddr_lo, ppudata_read, ppudata_write); type sprite_memory_t is (oam, soa); type sprite_state_t is (idle, clear1, clear2, ev_y1, ev_y2, ev_tile1, ev_tile2, ev_attr1, ev_attr2, ev_x1, ev_x2, of_y1, of_y2, of_title1, of_title2, of_attr1, of_attr2, of_x1, of_x2, wait1a, wait1b, wait_eol, gf1, gf2, gf3, gf4, ftl1, ftl2, fth1, fth2); type background_state_t is (idle, nt1, nt2, at1, at2, tl1, tl2, th1, th2); type sprite_list_t is array (0 to 7) of sprite_t; type byte_array_t is array (0 to 31) of std_logic_vector(5 downto 0); constant NULL_SPRITE : sprite_t := (x => x"00", tile_low => x"00", tile_high => x"00", priority => '0', palette => "00", pixel => "00"); constant SKIP_DOT_CYCLE : integer := 339; constant ENABLE_NMI_WRITE_CYCLE : integer := 0; constant PPUSTATUS_READ_CYCLE : integer := 1; -- 0 constant VBLANK_SET_CYCLE : integer := 0; -- 1 constant VBLANK_CLEAR_CYCLE : integer := 0; -- 1 constant SPR0HIT_CLEAR_CYCLE : integer := 0; -- 0 constant SPROVFW_CLEAR_CYCLE : integer := 0; -- 0 constant MAX_DECAY : integer := 3192000; type decay_array_t is array (0 to 7) of integer range 0 to MAX_DECAY; signal s_io_state : io_state_t := idle; signal s_io_data : std_logic_vector(7 downto 0) := x"00"; signal s_io_mem : std_logic_vector(7 downto 0) := x"00"; signal s_io_cycle : integer range 0 to 7 := 0; signal s_io_latch : boolean := true; signal s_sprites : sprite_list_t := (others => NULL_SPRITE); signal s_spr_mem : sprite_memory_t := oam; signal s_spr_mem_d : sprite_memory_t := oam; signal s_oam_clk_enable : std_logic; signal s_oam_addr : std_logic_vector(7 downto 0) := x"00"; signal s_oam_write_enable : std_logic; signal s_oam_eff_q : std_logic_vector(7 downto 0); signal s_oam_q : std_logic_vector(7 downto 0); signal s_soa_clk_enable : std_logic; signal s_soa_addr : std_logic_vector(4 downto 0) := (others => '0'); signal s_soa_q : std_logic_vector(7 downto 0) := (others => '0'); signal s_soa_write_enable : std_logic := '0'; signal s_spr_addr : std_logic_vector(15 downto 0) := (others => '0'); signal s_bkg_addr : std_logic_vector(15 downto 0) := (others => '0'); signal s_spr_read_enable : std_logic := '0'; signal s_bkg_read_enable : std_logic := '0'; signal s_video_addr : std_logic_vector(15 downto 0) := (others => '0'); signal s_video_read_enable : std_logic; signal s_video_write_enable : std_logic; signal s_xpos : std_logic_vector(7 downto 0); signal s_ypos : std_logic_vector(7 downto 0); signal s_cycle : integer range 0 to 340 := 0; signal s_line : integer range 0 to 311 := 311; signal s_max_line : integer range 0 to 311 := 261; signal s_new_max_line : integer range 0 to 311; signal s_tile_index : std_logic_vector(7 downto 0); signal s_background_half : std_logic := '0'; signal s_sprite_half : std_logic := '0'; signal s_shifter_enable : std_logic := '0'; signal s_shifter_load : std_logic := '0'; signal s_render : boolean; signal s_tl_data : std_logic_vector(7 downto 0) := (others => '0'); signal s_tl_q : std_logic_vector(7 downto 0); signal s_th_data : std_logic_vector(7 downto 0) := (others => '0'); signal s_th_q : std_logic_vector(7 downto 0); signal s_bl_q : std_logic_vector(7 downto 0); signal s_bh_q : std_logic_vector(7 downto 0); signal s_background_palette_index: std_logic_vector(1 downto 0); signal s_new_background_palette_index : std_logic_vector(1 downto 0); signal s_color : std_logic_vector(5 downto 0); signal s_palette_color : std_logic_vector(5 downto 0); signal s_bkg_state : background_state_t := idle; signal s_spr_state : sprite_state_t := idle; signal s_out_addr : std_logic_vector(15 downto 0) := x"0000"; signal s_out_data : std_logic_vector(8 downto 0); signal s_out_color : std_logic_vector(5 downto 0); signal s_out_write_enable : std_logic := '0'; signal s_visible_line : boolean; signal s_visible_or_prescan_line : boolean; signal s_prescan_line : boolean; signal s_background_pixel : std_logic_vector(1 downto 0); signal s_winning_sprite : sprite_t; signal s_spr_idx : integer range 0 to 7 := 0; signal s_spr_fill : integer range -1 to 7 := -1; signal s_sprite_y : std_logic_vector(8 downto 0) := (others => '0'); signal s_sprite_tile : std_logic_vector(7 downto 0) := (others => '0'); signal s_sprite_disable : std_logic; signal s_sprite_0_hit : std_logic := '0'; signal s_sprite_0_visible : boolean := false; signal s_new_sprite_0_visible : boolean := false; signal s_sprite_overflow : std_logic := '0'; signal s_sprite_flip_horizontal : std_logic := '0'; signal s_tile_data : std_logic_vector(7 downto 0); signal s_enable_background : std_logic := '0'; signal s_enable_sprites : std_logic := '0'; signal s_render_first_bkg_col : std_logic := '0'; signal s_render_first_spr_col : std_logic := '0'; signal s_big_sprites : std_logic := '0'; signal s_sprite_online : boolean; signal s_sprite_line_lower_test : boolean; signal s_sprite_line_upper_test : boolean; signal s_sprite_line_test_height : std_logic_vector(7 downto 0); signal s_inner_tile_pos : std_logic_vector(3 downto 0); signal s_next_tile_addr : std_logic_vector(12 downto 0); signal s_tile_addr : std_logic_vector(15 downto 0); signal s_attr_addr : std_logic_vector(15 downto 0); signal s_tile_lo_addr : std_logic_vector(15 downto 0); signal s_tile_hi_addr : std_logic_vector(15 downto 0); signal s_q : std_logic_vector(7 downto 0) := x"00"; signal s_perform_oam_write_access : boolean; signal s_perform_oam_access : boolean; signal s_vblank : std_logic := '0'; signal s_enable_nmi : std_logic := '0'; signal s_vram_inc : std_logic := '0'; signal s_vram_addr_t : std_logic_vector(14 downto 0) := 15x"0000"; signal s_vram_addr_v : std_logic_vector(14 downto 0) := 15x"0000"; signal s_fine_scroll_x : integer range 0 to 7 := 0; signal s_palette_access : boolean; signal s_palette_index : std_logic_vector(4 downto 0); signal s_palette_quadrant : std_logic_vector(1 downto 0); signal s_palette_mem : byte_array_t := ( 6x"09", 6x"01", 6x"00", 6x"01", 6x"00", 6x"02", 6x"02", 6x"0D", 6x"08", 6x"10", 6x"08", 6x"24", 6x"00", 6x"00", 6x"04", 6x"2C", 6x"09", 6x"01", 6x"34", 6x"03", 6x"00", 6x"04", 6x"00", 6x"14", 6x"08", 6x"3A", 6x"00", 6x"02", 6x"00", 6x"20", 6x"2C", 6x"08" ); signal s_hblank_cycle : boolean; signal s_first_col_n : boolean; --signal s_vram_bkg_inc : boolean; signal s_frame_latch : boolean := true; signal s_enable_rendering : boolean; signal s_enable_shortcut : boolean := false; signal s_new_enable_shortcut : boolean; signal s_greyscale : std_logic := '0'; signal s_color_emphasize : std_logic_vector(2 downto 0) := "000"; signal s_skip_dot : boolean; signal s_last_cycle : boolean; signal s_q_decay : decay_array_t := (others => 0); signal s_decay_mask : std_logic_vector(7 downto 0) := (others => '0'); signal s_oam_data : std_logic_vector(7 downto 0); begin oamem: spritemem port map ( clock => i_clk, clken => s_oam_clk_enable, address => s_oam_addr, data => s_oam_data, wren => s_oam_write_enable, q => s_oam_q ); soam: soamem port map ( clock => i_clk, clken => s_soa_clk_enable, address => s_soa_addr, data => s_oam_eff_q, wren => s_soa_write_enable, q => s_soa_q ); tl_shifter: parallel_serial_shifter generic map (16, 8) port map ( i_clk => i_clk, i_clk_enable => i_clk_enable, i_load => s_shifter_load, i_enable => s_shifter_enable, i_data => s_tl_data, o_q => s_tl_q ); th_shifter: parallel_serial_shifter generic map (16, 8) port map ( i_clk => i_clk, i_clk_enable => i_clk_enable, i_load => s_shifter_load, i_enable => s_shifter_enable, i_data => i_chr_data, o_q => s_th_q ); bl_shifter: parallel_serial_shifter generic map (16, 8) port map ( i_clk => i_clk, i_clk_enable => i_clk_enable, i_load => s_shifter_load, i_enable => s_shifter_enable, i_data => s_new_background_palette_index(0) & s_new_background_palette_index(0) & s_new_background_palette_index(0) & s_new_background_palette_index(0) & s_new_background_palette_index(0) & s_new_background_palette_index(0) & s_new_background_palette_index(0) & s_new_background_palette_index(0), o_q => s_bl_q ); bh_shifter: parallel_serial_shifter generic map (16, 8) port map ( i_clk => i_clk, i_clk_enable => i_clk_enable, i_load => s_shifter_load, i_enable => s_shifter_enable, i_data => s_new_background_palette_index(1) & s_new_background_palette_index(1) & s_new_background_palette_index(1) & s_new_background_palette_index(1) & s_new_background_palette_index(1) & s_new_background_palette_index(1) & s_new_background_palette_index(1) & s_new_background_palette_index(1), o_q => s_bh_q ); spr_gen: for i in 0 to 7 generate spr: sprite_renderer port map ( i_sprite_x => s_sprites(i).x, i_line_x => s_xpos, i_tile_low => s_sprites(i).tile_low, i_tile_high => s_sprites(i).tile_high, i_enable => s_enable_sprites, i_first_col => s_render_first_spr_col, o_pixel => s_sprites(i).pixel ); end generate; -- IO process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then s_decay_mask <= (others => '0'); if i_reset_n = '0' then s_q <= x"00"; s_io_data <= x"00"; s_io_state <= idle; s_io_latch <= true; s_q_decay <= (others => 0); else for i in 0 to 7 loop if s_decay_mask(i) = '1' then s_q_decay(i) <= MAX_DECAY; elsif s_q_decay(i) /= 0 then s_q_decay(i) <= s_q_decay(i) - 1; else s_q(i) <= '0'; end if; end loop; case s_io_state is when idle => if i_cs_n = '0' then s_io_data <= i_data; s_io_cycle <= 0; if i_write_enable = '1' then s_q <= i_data; s_decay_mask <= (others => '1'); end if; case i_addr is when "000" => -- PPUCTRL if i_write_enable = '1' then s_io_state <= ppuctrl; end if; when "001" => -- PPUMASK if i_write_enable = '1' then s_io_state <= ppumask; end if; when "010" => -- PPUSTATUS if i_write_enable = '0' then s_io_state <= ppustatus; s_io_latch <= true; end if; when "011" => -- OAMADDR if i_write_enable = '1' then s_io_state <= oamaddr; s_io_data <= i_data; end if; when "100" => -- OAMDATA if i_write_enable = '1' then s_io_state <= oamdata_write; else s_io_state <= oamdata_read; end if; when "101" => -- PPUSCROLL if i_write_enable = '1' then if s_io_latch then s_io_state <= ppuscroll_x; else s_io_state <= ppuscroll_y; end if; s_io_latch <= not s_io_latch; end if; when "110" => -- PPUADDR if i_write_enable = '1' then if s_io_latch then s_io_state <= ppuaddr_hi; else s_io_state <= ppuaddr_lo; end if; s_io_latch <= not s_io_latch; end if; when "111" => -- PPUDATA if i_write_enable = '1' then s_io_state <= ppudata_write; else s_io_state <= ppudata_read; end if; when others => end case; end if; when oamdata_read => if s_io_cycle = 1 then s_io_state <= idle; s_decay_mask <= (others => '1'); if s_spr_mem_d = oam then s_q <= s_oam_eff_q; else s_q <= s_soa_q; end if; else s_io_cycle <= s_io_cycle + 1; end if; when ppustatus => if s_io_cycle = 2 then s_io_state <= idle; else if s_io_cycle = PPUSTATUS_READ_CYCLE then s_q(7 downto 5) <= s_vblank & s_sprite_0_hit & s_sprite_overflow; s_decay_mask(7 downto 5) <= (others => '1'); end if; s_io_cycle <= s_io_cycle + 1; end if; when oamaddr | oamdata_write | ppuctrl | ppuscroll_x | ppuscroll_y | ppumask | ppuaddr_hi => if s_io_cycle = 1 then s_io_state <= idle; else s_io_cycle <= s_io_cycle + 1; end if; when ppudata_read => if s_io_cycle = 5 then s_io_state <= idle; s_io_mem <= i_chr_data; else if s_io_cycle = 1 then if s_palette_access then s_q(5 downto 0) <= s_palette_mem(to_pal_idx(s_vram_addr_v(4 downto 0))); s_decay_mask(5 downto 0) <= (others => '1'); else s_q <= s_io_mem; s_decay_mask <= (others => '1'); end if; end if; s_io_cycle <= s_io_cycle + 1; end if; when ppuaddr_lo => if s_io_cycle = 2 then s_io_state <= idle; else s_io_cycle <= s_io_cycle + 1; end if; when ppudata_write => if s_io_cycle = 7 then s_io_state <= idle; else s_io_cycle <= s_io_cycle + 1; end if; end case; end if; end if; end if; end process; -- Zeilen & Zyklen process (i_video_mode) begin case i_video_mode is when ntsc => s_new_max_line <= 261; s_new_enable_shortcut <= true; when pal => s_new_max_line <= 311; s_new_enable_shortcut <= false; end case; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_line <= s_new_max_line; s_max_line <= s_new_max_line; s_enable_shortcut <= s_new_enable_shortcut; s_cycle <= 0; s_frame_latch <= true; else if s_last_cycle then s_cycle <= 0; if s_prescan_line then s_line <= 0; s_max_line <= s_new_max_line; s_frame_latch <= not s_frame_latch; s_enable_shortcut <= s_new_enable_shortcut; if s_skip_dot then s_cycle <= 1; end if; else s_line <= s_line + 1; end if; else s_cycle <= s_cycle + 1; end if; end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_skip_dot <= false; elsif s_prescan_line and s_last_cycle then s_skip_dot <= false; elsif s_prescan_line and (s_cycle = SKIP_DOT_CYCLE) and s_frame_latch and s_enable_rendering and s_enable_shortcut then s_skip_dot <= true; end if; end if; end if; end process; -- Enable Rendering process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_greyscale <= '0'; elsif s_io_state = ppumask then s_greyscale <= s_io_data(0); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_render_first_bkg_col <= '0'; elsif s_io_state = ppumask then s_render_first_bkg_col <= s_io_data(1); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_render_first_spr_col <= '0'; elsif s_io_state = ppumask then s_render_first_spr_col <= s_io_data(2); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_enable_background <= '0'; elsif s_io_state = ppumask then s_enable_background <= s_io_data(3); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_enable_sprites <= '0'; elsif s_io_state = ppumask then s_enable_sprites <= s_io_data(4); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_color_emphasize <= "000"; elsif s_io_state = ppumask then case i_video_mode is when ntsc => s_color_emphasize <= s_io_data(7 downto 5); when pal => s_color_emphasize <= s_io_data(7) & s_io_data(5) & s_io_data(6); end case; end if; end if; end if; end process; -- Setup process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_vram_inc <= '0'; elsif s_io_state = ppuctrl then s_vram_inc <= s_io_data(2); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_sprite_half <= '0'; elsif s_io_state = ppuctrl then s_sprite_half <= s_io_data(3); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_background_half <= '0'; elsif s_io_state = ppuctrl then s_background_half <= s_io_data(4); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_big_sprites <= '0'; elsif s_io_state = ppuctrl then s_big_sprites <= s_io_data(5); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_enable_nmi <= '0'; elsif (s_io_state = ppuctrl) and (s_io_cycle = ENABLE_NMI_WRITE_CYCLE) then s_enable_nmi <= s_io_data(7); end if; end if; end if; end process; -- VRAM Adressierung process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_vram_addr_t <= 15x"0000"; elsif s_io_state = ppuaddr_hi then s_vram_addr_t(14) <= '0'; s_vram_addr_t(13 downto 8) <= s_io_data(5 downto 0); elsif (s_io_state = ppuaddr_lo) and (s_io_cycle = 0) then s_vram_addr_t(7 downto 0) <= s_io_data; elsif s_io_state = ppuscroll_x then s_vram_addr_t(4 downto 0) <= s_io_data(7 downto 3); elsif s_io_state = ppuscroll_y then s_vram_addr_t(14 downto 12) <= s_io_data(2 downto 0); s_vram_addr_t(9 downto 5) <= s_io_data(7 downto 3); elsif s_io_state = ppuctrl then s_vram_addr_t(11 downto 10) <= s_io_data(1 downto 0); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_fine_scroll_x <= 0; elsif s_io_state = ppuscroll_x then s_fine_scroll_x <= to_integer(unsigned(s_io_data(2 downto 0))); end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_vram_addr_v <= 15x"0000"; elsif (s_io_state = ppuaddr_lo) and (s_io_cycle = 2) then s_vram_addr_v <= s_vram_addr_t; elsif ((s_io_state = ppudata_write) and (s_io_cycle = 7)) or ((s_io_state = ppudata_read) and (s_io_cycle = 5)) then if s_vram_inc = '0' then s_vram_addr_v <= s_vram_addr_v + 15x"0001"; else s_vram_addr_v <= s_vram_addr_v + 15x"0020"; end if; s_vram_addr_v(14) <= '0'; elsif s_enable_rendering and s_visible_or_prescan_line then if std_logic_vector(to_unsigned(s_cycle, 3)) = "111" and not s_hblank_cycle then -- Horizontal LoopyV increment if s_vram_addr_v(4 downto 0) = "11111" then s_vram_addr_v(4 downto 0) <= "00000"; s_vram_addr_v(10) <= not s_vram_addr_v(10); else s_vram_addr_v(4 downto 0) <= s_vram_addr_v(4 downto 0) + "00001"; end if; end if; if s_cycle = 255 then -- Vertical LoopyV increment if s_vram_addr_v(14 downto 12) = "111" then s_vram_addr_v(14 downto 12) <= "000"; if s_vram_addr_v(9 downto 5) = "11101" then -- 29 s_vram_addr_v(11) <= not s_vram_addr_v(11); s_vram_addr_v(9 downto 5) <= "00000"; elsif s_vram_addr_v(9 downto 5) = "11111" then -- 31 s_vram_addr_v(9 downto 5) <= "00000"; else s_vram_addr_v(9 downto 5) <= s_vram_addr_v(9 downto 5) + "00001"; end if; else s_vram_addr_v(14 downto 12) <= s_vram_addr_v(14 downto 12) + "001"; end if; elsif s_cycle = 256 then -- Horizontal LoopyV <= Horizontal LoopyT s_vram_addr_v(10) <= s_vram_addr_t(10); s_vram_addr_v(4 downto 0) <= s_vram_addr_t(4 downto 0); elsif (s_cycle >= 279) and (s_cycle <= 303) and s_prescan_line then -- Vertical LoopyV <= Vertical LoopyT s_vram_addr_v(9 downto 5) <= s_vram_addr_t(9 downto 5); s_vram_addr_v(14 downto 11) <= s_vram_addr_t(14 downto 11); end if; end if; end if; end if; end process; -- Palette process (i_clk) variable index : integer range 0 to 31; begin if rising_edge(i_clk) then if i_clk_enable = '1' then if (s_io_state = ppudata_write) and s_palette_access and (s_io_cycle = 1) then index := to_pal_idx(s_vram_addr_v(4 downto 0)); s_palette_mem(index) <= s_io_data(5 downto 0); end if; end if; end if; end process; -- Hintergrund rendern process (i_clk) variable ypos : std_logic_vector(7 downto 0); begin if rising_edge(i_clk) then if i_clk_enable = '1' then s_shifter_load <= '0'; s_bkg_read_enable <= '0'; if i_reset_n = '0' then s_bkg_state <= idle; else case s_bkg_state is when idle => s_bkg_state <= nt1; s_bkg_addr <= s_tile_addr; when nt1 => -- Name Table s_bkg_state <= nt2; s_bkg_read_enable <= '1'; when nt2 => s_bkg_addr <= s_attr_addr; s_bkg_state <= at1; when at1 => -- Attribute Table s_tile_index <= i_chr_data; s_bkg_state <= at2; s_bkg_read_enable <= '1'; when at2 => if not s_last_cycle then s_bkg_state <= tl1; s_bkg_addr <= s_tile_lo_addr; elsif s_skip_dot then s_bkg_state <= nt1; s_bkg_addr <= s_tile_addr; else s_bkg_state <= idle; end if; when tl1 => -- Tile low s_bkg_state <= tl2; s_bkg_read_enable <= '1'; case s_palette_quadrant is when "00" => s_new_background_palette_index <= i_chr_data(1 downto 0); when "01" => s_new_background_palette_index <= i_chr_data(3 downto 2); when "10" => s_new_background_palette_index <= i_chr_data(5 downto 4); when "11" => s_new_background_palette_index <= i_chr_data(7 downto 6); when others => s_new_background_palette_index <= "00"; end case; when tl2 => s_bkg_state <= th1; s_bkg_addr <= s_tile_hi_addr; when th1 => -- Tile high s_bkg_state <= th2; s_bkg_read_enable <= '1'; s_tl_data <= i_chr_data; when th2 => s_shifter_load <= '1'; s_bkg_state <= nt1; s_bkg_addr <= s_tile_addr; when others => s_bkg_state <= idle; end case; end if; end if; end if; end process; s_shifter_enable <= '0' when (s_cycle > 336) or (s_cycle = 0) else '1'; -- Sprites rendern process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then s_spr_read_enable <= '0'; s_spr_fill <= -1; s_soa_write_enable <= '0'; if i_reset_n = '0' then s_spr_state <= idle; s_spr_mem <= soa; s_soa_addr <= "00000"; s_oam_addr <= x"00"; for i in 0 to 7 loop s_sprites(i).tile_low <= x"00"; s_sprites(i).tile_high <= x"00"; end loop; else if s_spr_fill /= -1 then s_sprites(s_spr_fill).tile_high <= s_tile_data; end if; if s_perform_oam_access then s_oam_addr <= s_oam_addr + x"01"; end if; if (s_io_state = oamaddr) and (s_io_cycle = 1) then s_oam_addr <= s_io_data; end if; -- Sprite Overflow zu Beginn eines neuen Frames zurücksetzen if s_prescan_line and (s_cycle = SPROVFW_CLEAR_CYCLE) then s_sprite_overflow <= '0'; end if; -- OAMADDR wird bei allen sichtbaren und der Prerender-Zeile von Zyklus 257 bis 320 bei jedem Tick auf 0 gesetzt if s_visible_or_prescan_line and s_hblank_cycle and s_enable_rendering then s_oam_addr <= x"00"; end if; case s_spr_state is when idle => if s_visible_line and s_enable_rendering then s_spr_state <= clear1; s_soa_addr <= "00000"; s_spr_mem <= oam; else s_spr_mem <= oam; s_spr_state <= wait_eol; end if; when clear1 => s_spr_mem <= soa; s_soa_write_enable <= '1'; s_spr_state <= clear2; when clear2 => s_soa_addr <= s_soa_addr + "00001"; s_spr_mem <= oam; if s_soa_addr = "11111" then s_spr_state <= ev_y1; s_new_sprite_0_visible <= false; else s_spr_state <= clear1; end if; when ev_y1 => s_spr_mem <= soa; s_soa_write_enable <= '1'; s_spr_state <= ev_y2; when ev_y2 => s_spr_mem <= oam; if s_sprite_online then s_oam_addr <= s_oam_addr + x"01"; -- Adresse für Tile Index s_soa_addr <= s_soa_addr + "00001"; s_spr_state <= ev_tile1; if s_oam_addr = x"00" then s_new_sprite_0_visible <= true; end if; else s_oam_addr <= s_oam_addr + x"04"; -- Adresse für nächste Y-Position if s_oam_addr = x"fc" then s_spr_state <= wait1a; else s_spr_state <= ev_y1; end if; end if; when ev_tile1 => s_spr_mem <= soa; s_soa_write_enable <= '1'; s_spr_state <= ev_tile2; when ev_tile2 => s_spr_mem <= oam; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für Attribute s_soa_addr <= s_soa_addr + "00001"; s_spr_state <= ev_attr1; when ev_attr1 => s_spr_mem <= soa; s_soa_write_enable <= '1'; s_spr_state <= ev_attr2; when ev_attr2 => s_spr_mem <= oam; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für X-Position s_soa_addr <= s_soa_addr + "00001"; s_spr_state <= ev_x1; when ev_x1 => s_spr_mem <= soa; s_soa_write_enable <= '1'; s_spr_state <= ev_x2; when ev_x2 => s_spr_mem <= oam; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für Y-Position s_soa_addr <= s_soa_addr + "00001"; if s_soa_addr = "11111" then s_spr_state <= of_y1; elsif s_oam_addr = x"ff" then s_spr_state <= wait1a; else s_spr_state <= ev_y1; end if; when of_y1 => s_spr_state <= of_y2; when of_y2 => s_spr_mem <= oam; if s_sprite_online then s_sprite_overflow <= '1'; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für Tile Index s_spr_state <= of_title1; else s_spr_state <= of_y1; -- Adresse für Y-Position, Overflow-Bug: korrekt währe x"04" if s_oam_addr(1 downto 0) = "11" then s_oam_addr <= s_oam_addr + x"01"; if s_oam_addr = x"ff" then s_spr_state <= wait1a; end if; else s_oam_addr <= s_oam_addr + x"05"; if s_oam_addr >= x"fb" then s_spr_state <= wait1a; end if; end if; end if; when of_title1 => s_spr_state <= of_title2; when of_title2 => s_spr_mem <= oam; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für Attr Index s_spr_state <= of_attr1; when of_attr1 => s_spr_state <= of_attr2; when of_attr2 => s_spr_mem <= oam; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für X-Position s_spr_state <= of_x1; when of_x1 => s_spr_state <= of_x2; when of_x2 => s_spr_mem <= oam; s_oam_addr <= s_oam_addr + x"01"; -- Adresse für Y-Position s_spr_state <= of_y1; when wait1a => s_spr_mem <= soa; s_spr_state <= wait1b; when wait1b => s_oam_addr <= s_oam_addr + x"04"; s_spr_mem <= oam; s_spr_state <= wait1a; when gf1 => s_spr_state <= gf2; s_soa_addr <= s_soa_addr + "00001"; -- Adresse für Tile Index when gf2 => s_sprite_y <= ('0' & s_ypos) - ('0' & s_soa_q); -- Y-Position s_spr_state <= gf3; s_soa_addr <= s_soa_addr + "00001"; -- Adresse für Attribute when gf3 => s_sprite_tile <= s_soa_q; -- Tile Index s_spr_state <= gf4; s_soa_addr <= s_soa_addr + "00001"; -- Adresse für X-Position when gf4 => s_spr_addr <= "000" & s_next_tile_addr; s_spr_state <= ftl1; s_sprites(s_spr_idx).palette <= s_soa_q(1 downto 0); -- Attribute s_sprites(s_spr_idx).priority <= s_soa_q(5); s_sprite_flip_horizontal <= s_soa_q(6); when ftl1 => s_spr_state <= ftl2; s_sprites(s_spr_idx).x <= s_soa_q; -- X-Position s_spr_read_enable <= '1'; when ftl2 => s_spr_addr(3) <= '1'; -- +8 Bytes s_spr_state <= fth1; when fth1 => s_sprites(s_spr_idx).tile_low <= s_tile_data; s_oam_addr <= x"00"; s_spr_state <= fth2; s_spr_read_enable <= '1'; when fth2 => s_spr_fill <= s_spr_idx; s_spr_mem <= soa; if s_soa_addr = "11111" then s_spr_state <= wait_eol; s_soa_addr <= "00000"; else s_spr_idx <= s_spr_idx + 1; s_spr_state <= gf1; s_soa_addr <= s_soa_addr + "00001"; -- Adresse für Y-Position end if; when wait_eol => if s_last_cycle then if s_skip_dot then s_spr_state <= clear1; s_soa_addr <= "00000"; s_spr_mem <= oam; else s_spr_state <= idle; end if; end if; end case; if s_cycle = 256 then s_sprite_0_visible <= s_new_sprite_0_visible; s_new_sprite_0_visible <= false; end if; if (s_cycle = 256) and (s_spr_state /= wait_eol) then s_spr_idx <= 0; s_spr_state <= gf1; s_soa_addr <= "00000"; -- Adresse für Y-Position s_spr_mem <= soa; for i in 0 to 7 loop s_sprites(i).tile_low <= x"00"; s_sprites(i).tile_high <= x"00"; end loop; end if; end if; end if; end if; end process; process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_spr_mem_d <= oam; else s_spr_mem_d <= s_spr_mem; end if; end if; end if; end process; -- VBlank process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_vblank <= '0'; elsif s_prescan_line and (s_cycle = VBLANK_CLEAR_CYCLE) then s_vblank <= '0'; elsif (s_io_state = ppustatus) and (s_io_cycle = PPUSTATUS_READ_CYCLE) then s_vblank <= '0'; -- VBlank zurücksetzen wenn PPUSTATUS gelesen wird elsif (s_line = 241) and (s_cycle = VBLANK_SET_CYCLE) then s_vblank <= '1'; end if; end if; end if; end process; -- Sprite 0 Hit process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_sprite_0_hit <= '0'; else if s_visible_line and (s_cycle >= 1) and (s_cycle < 256) then -- Es ist Absicht, dass hier nicht von 1 - 256 gegangen wird if s_sprite_0_visible and (s_sprites(0).pixel /= "00") and (s_background_pixel /= "00") then s_sprite_0_hit <= '1'; end if; elsif s_prescan_line and (s_cycle = SPR0HIT_CLEAR_CYCLE) then s_sprite_0_hit <= '0'; end if; end if; end if; end if; end process; -- Ausgabe an Framebuffer process (i_clk) begin if rising_edge(i_clk) then if i_clk_enable = '1' then if i_reset_n = '0' then s_out_addr <= x"0000"; elsif not s_visible_line then s_out_addr <= x"0000"; elsif s_render then s_out_addr <= s_out_addr + x"0001"; end if; end if; end if; end process; s_winning_sprite <= s_sprites(0) when s_sprites(0).pixel /= "00" else s_sprites(1) when s_sprites(1).pixel /= "00" else s_sprites(2) when s_sprites(2).pixel /= "00" else s_sprites(3) when s_sprites(3).pixel /= "00" else s_sprites(4) when s_sprites(4).pixel /= "00" else s_sprites(5) when s_sprites(5).pixel /= "00" else s_sprites(6) when s_sprites(6).pixel /= "00" else s_sprites(7) when s_sprites(7).pixel /= "00" else NULL_SPRITE; s_palette_index <= '1' & s_winning_sprite.palette & s_winning_sprite.pixel when (s_winning_sprite.pixel /= "00") and (s_winning_sprite.priority = '0') else '0' & s_background_palette_index & s_background_pixel when (s_background_pixel /= "00") else '1' & s_winning_sprite.palette & s_winning_sprite.pixel when (s_winning_sprite.pixel /= "00") else "00000"; s_sprite_line_test_height <= x"08" when s_big_sprites = '0' else x"10"; s_sprite_line_lower_test <= s_ypos >= s_oam_eff_q; s_sprite_line_upper_test <= ('0' & s_ypos) < (('0' & s_oam_eff_q) + ('0' & s_sprite_line_test_height)); s_sprite_online <= s_sprite_line_lower_test and s_sprite_line_upper_test; s_sprite_disable <= s_sprite_y(8) or s_sprite_y(7) or s_sprite_y(6) or s_sprite_y(5) or s_sprite_y(4); s_inner_tile_pos <= not s_sprite_y(3 downto 0) when s_soa_q(7) = '1' else s_sprite_y(3 downto 0); -- vertical flip s_next_tile_addr <= s_sprite_half & s_sprite_tile & '0' & s_inner_tile_pos(2 downto 0) when s_big_sprites = '0' else s_sprite_tile(0) & s_sprite_tile(7 downto 1) & s_inner_tile_pos(3) & '0' & s_inner_tile_pos(2 downto 0); s_tile_data <= x"00" when s_sprite_disable = '1' else reverse_vector(i_chr_data) when s_sprite_flip_horizontal = '1' else i_chr_data; s_video_addr <= s_spr_addr when s_visible_or_prescan_line and s_hblank_cycle and s_enable_rendering else s_bkg_addr when s_visible_or_prescan_line and not s_hblank_cycle and s_enable_rendering else '0' & s_vram_addr_v; s_video_read_enable <= s_spr_read_enable when s_visible_or_prescan_line and s_hblank_cycle and s_enable_rendering else s_bkg_read_enable when s_visible_or_prescan_line and not s_hblank_cycle and s_enable_rendering else '1' when (s_io_state = ppudata_read) and (s_io_cycle = 4) else '0'; s_video_write_enable <= '1' when (s_io_state = ppudata_write) and (s_io_cycle = 7) and not s_palette_access else '0'; s_xpos <= std_logic_vector(to_unsigned(s_cycle - 1, 8)) when s_render else x"ff"; s_ypos <= std_logic_vector(to_unsigned(s_line, 8)); s_out_write_enable <= '1' when s_visible_line and s_render else '0'; s_render <= (s_cycle >= 1) and (s_cycle < 257); s_visible_line <= s_line < 240; s_prescan_line <= s_line = s_max_line; s_visible_or_prescan_line <= s_visible_line or s_prescan_line; s_last_cycle <= s_cycle = 340; s_hblank_cycle <= (s_cycle > 256) and (s_cycle < 321); --s_vram_bkg_inc <= std_logic_vector(to_unsigned(s_cycle - 1, 3)) = "110"; s_out_color <= s_palette_color and 6x"30" when s_greyscale = '1' else s_palette_color; s_out_data <= s_color_emphasize & s_out_color; s_oam_write_enable <= '1' when s_perform_oam_write_access else '0'; s_perform_oam_write_access <= (s_io_state = oamdata_write) and (s_io_cycle = 1); s_perform_oam_access <= s_perform_oam_write_access; s_enable_rendering <= (s_enable_background = '1') or (s_enable_sprites = '1'); s_palette_quadrant <= s_vram_addr_v(6) & s_vram_addr_v(1); s_tile_addr <= "0010" & s_vram_addr_v(11 downto 0); s_attr_addr <= "0010" & s_vram_addr_v(11 downto 10) & "1111" & s_vram_addr_v(9 downto 7) & s_vram_addr_v(4 downto 2); s_tile_lo_addr <= "000" & s_background_half & s_tile_index & '0' & s_vram_addr_v(14 downto 12); s_tile_hi_addr <= "000" & s_background_half & s_tile_index & '1' & s_vram_addr_v(14 downto 12); s_background_pixel <= s_th_q(s_fine_scroll_x) & s_tl_q(s_fine_scroll_x) when (s_enable_background = '1') and ((s_render_first_bkg_col = '1') or (s_xpos(7 downto 3) /= "00000")) else "00"; s_background_palette_index <= s_bh_q(s_fine_scroll_x) & s_bl_q(s_fine_scroll_x); s_palette_color <= s_palette_mem(to_pal_idx(s_palette_index)); s_palette_access <= s_vram_addr_v(14 downto 8) = 7x"3f"; s_oam_data <= s_io_data(7 downto 5) & "000" & s_io_data(1 downto 0) when s_oam_addr(1 downto 0) = "10" else s_io_data; s_oam_eff_q <= x"ff" when (s_spr_state = clear1) or (s_spr_state = clear2) else s_oam_q; s_oam_clk_enable <= i_clk_enable when s_spr_mem = oam else '0'; s_soa_clk_enable <= i_clk_enable when s_spr_mem = soa else '0'; o_q <= s_q; o_int_n <= s_vblank nand s_enable_nmi; o_vga_addr <= s_out_addr; o_vga_data <= s_out_data; o_vga_write_enable <= s_out_write_enable; o_chr_addr <= s_video_addr(13 downto 0); o_chr_q <= s_io_data; o_chr_read_enable <= s_video_read_enable; o_chr_write_enable <= s_video_write_enable; end architecture;
gpl-3.0
1b30db35472ff960a97a1b0ad35144b5
0.570543
2.62476
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.cache/ip/2018.2/abb00b3e1f316b47/gcd_zynq_snick_rst_ps7_0_49M_0_sim_netlist.vhdl
1
35,472
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 19:44:37 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_rst_ps7_0_49M_0_sim_netlist.vhdl -- Design : gcd_zynq_snick_rst_ps7_0_49M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg400-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => p_1_in, I2 => p_2_in, I3 => \^scndry_out\, I4 => asr_lpf(0), O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is signal exr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => exr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => exr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(1), I2 => p_3_out(2), I3 => \^scndry_out\, I4 => p_3_out(0), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => dcm_locked, I1 => lpf_exr, I2 => lpf_asr, I3 => Q, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0090" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9000" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0018" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(0), I2 => seq_cnt(2), I3 => seq_cnt(1), O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0480" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_zynq_snick_rst_ps7_0_49M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;
mit
32d50299a062f625b8a1df78076ec87d
0.588802
2.917105
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/iir/bq/filter_main_controller.vhd
1
21,057
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.filter_shared_package.all; entity filter_main_controller is generic ( BIQUADS : natural := B; CHANNELS : natural := C; FPMULT_PIPE_LENGTH : P_T := PM; FPADD_PIPE_LENGTH : P_T := PA; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. ENVELOPE_EN : natural := ENV; ENV_MAC_ID : natural := ENV_MAC; SETZERO_EN : natural := SETZ ); port ( -- Input Ports clk : in std_logic; rstn : in std_logic; envelope : in std_logic_vector(CHANNELS-1 downto 0); give_rms : in std_logic; give_mean : in std_logic; set_zero : in std_logic_vector(CHANNELS-1 downto 0); sink_valid : in std_logic; sink_startofpacket : in std_logic; sink_endofpacket : in std_logic; -- Output ports x_rdaddr : out X_ADD_T; x_rden : out std_logic; x_wraddr : out X_ADD_T; x_wren : out std_logic; coeff_rdaddr : out COEFF_ADD_T; coeff_rden : out std_logic; acc_rdaddr : out ACC_ADD_T; acc_rden : out std_logic; acc_wraddr : out ACC_ADD_T; acc_wren : out std_logic; zero_acc : out std_logic; y_rdaddr : out Y_ADD_T; y_rden : out std_logic; y_wraddr : out Y_ADD_T; y_wren : out std_logic; zero_y : out std_logic; is_abs : out std_logic; mac_x_y_sel : out std_logic; mac_coeff_y_sel : out std_logic; sink_ready : out std_logic; source_valid : out std_logic; source_rms_valid : out std_logic; source_mean_valid : out std_logic; source_startofpacket : out std_logic; source_endofpacket : out std_logic ); end filter_main_controller; architecture structure of filter_main_controller is component filter_counters is generic ( FPMULT_PIPE_LENGTH : P_T := PM; FPADD_PIPE_LENGTH : P_T := PA; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( -- Input ports clk : in std_logic; rstn : in std_logic; input_ok : in std_logic; -- Output ports input_ack : out std_logic; valid : out std_logic; valid_delay : out std_logic; -- valid_s [PIPDELAY] valid_acc : out std_logic; -- valid_s [ACCDELAY] cnt_mac : out std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_ch : out std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); cnt_delay_mac : out std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); -- SR [PIPDELAY] cnt_delay_ch : out std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); -- SR [PIPDELAY] cnt_acc_mac : out std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); -- SR [ACCDELAY] cnt_acc_ch : out std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0) -- SR [ACCDELAY] ); end component filter_counters; component filter_in_data_controller is generic ( MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( clk : in std_logic; rstn : in std_logic; cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); x_input : in std_logic; valid : in std_logic; sink_valid : in std_logic; sink_endofpacket : in std_logic; sink_startofpacket : in std_logic; input_ack : in std_logic; sink_ready : out std_logic; input_ok : out std_logic; x_rdaddr : out X_ADD_T; x_rden : out std_logic; x_wraddr : out X_ADD_T; x_wren : out std_logic ); end component filter_in_data_controller; component filter_coeff_controller is generic ( MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); valid : in std_logic; coeff_rdaddr : out COEFF_ADD_T; coeff_rden : out std_logic ); end component filter_coeff_controller; component filter_out_data_controller is generic ( BIQUADS : natural := B; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( clk : in std_logic; rstn : in std_logic; cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); cnt_delay_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_delay_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); y_input : in std_logic; input_ok : in std_logic; valid_delay : in std_logic; y_rdaddr : out Y_ADD_T; y_rden : out std_logic; y_wraddr : out Y_ADD_T; y_wren : out std_logic ); end component filter_out_data_controller; component filter_mac_mem_controller is generic ( BIQUADS : natural := B; MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled. CHANNELS : natural := C ); port ( cnt_delay_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_delay_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); cnt_acc_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); cnt_acc_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); valid_delay : in std_logic; valid_acc : in std_logic; zero_acc_misc : in std_logic; acc_rdaddr : out ACC_ADD_T; acc_rden : out std_logic; acc_wraddr : out ACC_ADD_T; acc_wren : out std_logic; zero_acc : out std_logic ); end component filter_mac_mem_controller; component filter_extra_functions is generic ( MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation CHANNELS : natural := C; ENVELOPE_EN : natural := ENV; ENV_MAC_ID : natural := ENV_MAC; SETZERO_EN : natural := SETZ; RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled. MEAN_CH_EN : natural := MEAN -- Enable flag for MEAN function. 0-disabled 1- enabled. ); port ( -- Input ports clk : in std_logic; rstn : in std_logic; cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH + RMS_CH_EN + MEAN_CH_EN))))-1 downto 0); cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); cnt_delay_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH + RMS_CH_EN + MEAN_CH_EN))))-1 downto 0); cnt_delay_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); give_rms : in std_logic; give_mean : in std_logic; envelope : in std_logic_vector(CHANNELS-1 downto 0); set_zero : in std_logic_vector(CHANNELS-1 downto 0); valid_delay : in std_logic; output : in std_logic; -- Output ports source_rms_valid : out std_logic; source_mean_valid : out std_logic; zero_y : out std_logic; zero_acc_misc : out std_logic; is_abs : out std_logic; cond : out std_logic ); end component filter_extra_functions; -- Counter Signals signal input_ok_s : std_logic; signal input_ack_s : std_logic; signal valid_s : std_logic; signal valid_delay_s : std_logic; signal valid_acc_s : std_logic; signal cnt_mac_s : std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); signal cnt_ch_s : std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); signal cnt_delay_mac_s : std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); signal cnt_delay_ch_s : std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); signal cnt_acc_mac_s : std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0); signal cnt_acc_ch_s : std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0); -- X ctrl signals signal xy_input_s : std_logic; -- Y ctrl signals signal mac_x_y_sel_s: std_logic; -- Acc ctrl signals signal zero_acc_misc_s : std_logic; -- Misc functions signals signal cond_s : std_logic; -- Other signals signal tmp_cnt_delay_ch_s : unsigned(cnt_delay_ch_s'range); signal output_s : std_logic; -- Valid Signals signal source_valid_s : std_logic; signal source_startofpacket_s : std_logic; signal source_endofpacket_s : std_logic; begin -- Component Instantiation Statement (optional) filter_counters_inst : component filter_counters generic map ( FPMULT_PIPE_LENGTH => FPMULT_PIPE_LENGTH, FPADD_PIPE_LENGTH => FPADD_PIPE_LENGTH, MAC_FILTER_CH => MAC_FILTER_CH, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN, CHANNELS => CHANNELS ) port map ( clk => clk, rstn => rstn, input_ok => input_ok_s, input_ack => input_ack_s, valid => valid_s, valid_delay => valid_delay_s, valid_acc => valid_acc_s, cnt_mac => cnt_mac_s, cnt_ch => cnt_ch_s, cnt_delay_mac => cnt_delay_mac_s, cnt_delay_ch => cnt_delay_ch_s, cnt_acc_mac => cnt_acc_mac_s, cnt_acc_ch => cnt_acc_ch_s ); filter_in_data_controller_inst : component filter_in_data_controller generic map ( MAC_FILTER_CH => MAC_FILTER_CH, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN, CHANNELS => CHANNELS ) port map ( clk => clk, rstn => rstn, cnt_mac => cnt_mac_s, cnt_ch => cnt_ch_s, x_input => xy_input_s, valid => valid_s, sink_valid => sink_valid, sink_endofpacket => sink_endofpacket, sink_startofpacket => sink_startofpacket, input_ack => input_ack_s, sink_ready => sink_ready, input_ok => input_ok_s, x_rdaddr => x_rdaddr, x_rden => x_rden, x_wraddr => x_wraddr, x_wren => x_wren ); filter_coeff_controller_inst : component filter_coeff_controller generic map ( MAC_FILTER_CH => MAC_FILTER_CH, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN, CHANNELS => CHANNELS ) port map ( cnt_mac => cnt_mac_s, cnt_ch => cnt_ch_s, valid => valid_s, coeff_rdaddr => coeff_rdaddr, coeff_rden => coeff_rden ); filter_out_data_controller_inst : component filter_out_data_controller generic map ( BIQUADS => BIQUADS, CHANNELS => CHANNELS, MAC_FILTER_CH => MAC_FILTER_CH, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN ) port map ( clk => clk, rstn => rstn, cnt_mac => cnt_mac_s, cnt_ch => cnt_ch_s, cnt_delay_mac => cnt_delay_mac_s, cnt_delay_ch => cnt_delay_ch_s, y_input => xy_input_s, input_ok => input_ok_s, valid_delay => valid_delay_s, y_rdaddr => y_rdaddr, y_rden => y_rden, y_wraddr => y_wraddr, y_wren => y_wren ); filter_mac_mem_controller_inst : component filter_mac_mem_controller generic map ( BIQUADS => BIQUADS, CHANNELS => CHANNELS, MAC_FILTER_CH => MAC_FILTER_CH, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN ) port map ( cnt_delay_mac => cnt_delay_mac_s, cnt_delay_ch => cnt_delay_ch_s, cnt_acc_mac => cnt_acc_mac_s, cnt_acc_ch => cnt_acc_ch_s, valid_delay => valid_delay_s, valid_acc => valid_acc_s, zero_acc_misc => zero_acc_misc_s, acc_rdaddr => acc_rdaddr, acc_rden => acc_rden, acc_wraddr => acc_wraddr, acc_wren => acc_wren, zero_acc => zero_acc ); filter_extra_functions_inst : component filter_extra_functions generic map ( CHANNELS => CHANNELS, MAC_FILTER_CH => MAC_FILTER_CH, ENVELOPE_EN => ENVELOPE_EN, ENV_MAC_ID => ENV_MAC_ID, SETZERO_EN => SETZERO_EN, RMS_CH_EN => RMS_CH_EN, MEAN_CH_EN => MEAN_CH_EN ) port map ( clk => clk, rstn => rstn, cnt_mac => cnt_mac_s, cnt_ch => cnt_ch_s, cnt_delay_mac => cnt_delay_mac_s, cnt_delay_ch => cnt_delay_ch_s, give_rms => give_rms, give_mean => give_mean, envelope => envelope, set_zero => set_zero, valid_delay => valid_delay_s, output => output_s, source_rms_valid => source_rms_valid, source_mean_valid => source_mean_valid, zero_y => zero_y, zero_acc_misc => zero_acc_misc_s, is_abs => is_abs, cond => cond_s ); -- Request x and y inputs and also set select signal for x(1) or y(0) x_y_input : process(cnt_mac_s) variable tmp_cnt_mac : natural; variable tmp_xy_input : std_logic; begin tmp_cnt_mac := to_integer(unsigned(cnt_mac_s)); tmp_xy_input := '0'; if(tmp_cnt_mac <= 2) then tmp_xy_input := '1'; end if; xy_input_s <= tmp_xy_input; mac_x_y_sel_s <= tmp_xy_input; end process x_y_input; -- valid output after all biquad computations Output_Memless : process(cnt_delay_mac_s,valid_delay_s) variable tmp_cnt_delay_mac : natural; variable tmp_output : std_logic; begin tmp_cnt_delay_mac := to_integer(unsigned(cnt_delay_mac_s)); tmp_output := '0'; if tmp_cnt_delay_mac = MAC_FILTER_CH - 1 then tmp_output := valid_delay_s; end if; output_s <= tmp_output; mac_coeff_y_sel <= not tmp_output; end process Output_Memless; tmp_cnt_delay_ch_s <= unsigned(cnt_delay_ch_s); Src_Valid : process (clk, rstn) is begin if (rstn = '0') then source_valid_s <= '0'; source_startofpacket_s <= '0'; source_endofpacket_s <= '0'; elsif (rising_edge(clk)) then source_valid_s <= '0'; source_startofpacket_s <= '0'; source_endofpacket_s <= '0'; if (cond_s = '1') then if (tmp_cnt_delay_ch_s = 0) then source_startofpacket_s <= '1'; elsif (tmp_cnt_delay_ch_s = CHANNELS - 1) then source_endofpacket_s <= '1'; end if; if (tmp_cnt_delay_ch_s < CHANNELS) then source_valid_s <= output_s; end if; end if; end if; end process Src_Valid; --Output process Output: process(clk, rstn) begin if (rstn = '0') then source_valid <= '0'; source_startofpacket <= '0'; source_endofpacket <= '0'; mac_x_y_sel <= '0'; elsif (rising_edge(clk)) then source_valid <= source_valid_s; source_startofpacket <= source_startofpacket_s; source_endofpacket <= source_endofpacket_s; mac_x_y_sel <= mac_x_y_sel_s; end if; end process Output; end structure;
mit
877f155275ac541d6ed5d6945ebd90f4
0.474522
3.792004
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/aluseq/alu.vhdl
1
3,745
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu is generic( W : natural := 4 ); port (i_data_a : in std_logic_vector(W-1 downto 0); -- input data A i_data_b : in std_logic_vector(W-1 downto 0); -- input data B i_data_carry : in std_logic; -- carry in or borrow in i_ctrl : in std_logic_vector(3 downto 0); -- control signals o_data_c : out std_logic_vector(W-1 downto 0); -- output data C o_data_carry : out std_logic; -- carry out or borrow out o_data_comp : out std_logic_vector(1 downto 0) -- output comparison ); end alu; architecture behavioral of alu is begin comb_memless_process: process ( i_data_a, i_data_b, i_data_carry, i_ctrl ) variable temp_carry: std_logic_vector(W downto 0) := ( others => '0' ); begin o_data_c <= (others => '0'); o_data_carry <= '0'; o_data_comp <= (others => '0'); case i_ctrl is when "0001" => -- ripple carry adder: {sum, cout} = a+b+cin temp_carry(0) := i_data_carry; for i in 0 to W-1 loop -- sum(k) = a(k) xor b(k) xor c(k) o_data_c(i) <= i_data_a(i) xor i_data_b(i) xor temp_carry(i); -- cout(k+1) = a(k).b(k) + b(k).c(k) + c(k).a(k) temp_carry(i+1) := ( i_data_a(i) and i_data_b(i) ) or ( i_data_b(i) and temp_carry(i) ) or ( temp_carry(i) and i_data_a(i) ); end loop; o_data_carry <= temp_carry(W); when "0010" => -- full subtraction: {diff, bout} = a-b-bin temp_carry(0) := i_data_carry; for i in 0 to W-1 loop -- diff(k) = a(k) xor b(k) xor c(k) o_data_c(i) <= i_data_a(i) xor i_data_b(i) xor temp_carry(i); -- bout(k+1) = !a(k).b(k) + b(k).c(k) + c(k).!a(k) temp_carry(i+1) := ( ( NOT i_data_a(i) ) AND i_data_b(i) ) OR ( i_data_b(i) AND temp_carry(i) ) OR ( temp_carry(i) AND ( NOT i_data_a(i) ) ); end loop; o_data_carry <= temp_carry(W); when "0011" => -- comparator: comp_out = 1 if A > B if( i_data_a > i_data_b ) then o_data_comp <= "01"; else o_data_comp <= "00"; end if; when "0100" => -- comparator: comp_out = 1 if A < B if( i_data_a < i_data_b ) then o_data_comp <= "01"; else o_data_comp <= ( others => '0' ); end if; when "0101" => -- comparator: comp_out = 1 if A = B if( i_data_a = i_data_b ) then o_data_comp <= "01"; else o_data_comp <= ( others => '0' ); end if; when "0110" => -- logical right shift A by B[1:0] o_data_c <= std_logic_vector( unsigned(i_data_a) srl to_integer( unsigned( i_data_b(1 downto 0) ) ) ); when "0111" => -- logical left shift A by B o_data_c <= std_logic_vector( unsigned(i_data_a) sll to_integer( unsigned( i_data_b(1 downto 0) ) ) ); when others => -- NOP end case; end process comb_memless_process; end behavioral;
mit
d28c6126d24a258753a6a946b0a93bcd
0.417891
3.39221
false
false
false
false
astoria-d/super-duper-nes
test/voltage_test01/voltage_test01.vhd
1
1,838
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.conv_integer; use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_unsigned.all; -- -- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board -- All of the components are assembled and instanciated on this board. -- entity voltage_test01 is port ( pi_base_clk : in std_logic; pi_sw : in std_logic_vector(9 downto 0); pi_btn_n : in std_logic_vector(3 downto 0); po_led_r : out std_logic_vector(9 downto 0); po_led_g : out std_logic_vector(7 downto 0); po_gpio0 : out std_logic_vector(3 downto 0); po_gpio1 : out std_logic_vector(9 downto 0) ); end voltage_test01; architecture rtl of voltage_test01 is --slow down button update timing. constant FREQ_DEVIDE : integer := 1000000; signal reg_btn_flg : integer range 0 to FREQ_DEVIDE; signal reg_key3_cnt : std_logic_vector(7 downto 0); signal wr_rst_n : std_logic; begin wr_rst_n <= pi_btn_n(0); po_led_g <= reg_key3_cnt; po_led_r <= pi_sw; po_gpio0 <= pi_btn_n; po_gpio1 <= pi_sw; --key3 button proc. key3_cnt_p : process (wr_rst_n, pi_base_clk) begin if (wr_rst_n = '0') then reg_key3_cnt <= (others => '0'); elsif (rising_edge(pi_base_clk)) then if (pi_btn_n(3) = '0' and reg_btn_flg = 0) then reg_key3_cnt <= reg_key3_cnt + 1; end if; end if; end process; -- led_flg_p : process (wr_rst_n, pi_base_clk) begin if (wr_rst_n = '0') then reg_btn_flg <= 0; elsif (rising_edge(pi_base_clk)) then reg_btn_flg <= reg_btn_flg + 1; end if; end process; end rtl;
apache-2.0
5f6297f10213da9b371d94cd1b12fcb8
0.563112
2.993485
false
false
false
false
drhodes/jade2hdl
test-data/vhdl/simple/simple.vhdl
1
633
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- Unsigned entity simple is end simple; architecture behaviour of simple is signal clk : std_logic := '0'; signal sigterm : std_logic := '0'; signal counter : unsigned(7 downto 0) := x"00"; begin process begin wait for 5 us; clkloop : loop wait for 1 us; clk <= not clk; if sigterm = '1' then exit; end if; end loop clkloop; wait for 5 us; wait; end process; process (clk) begin if rising_edge(clk) then if counter = 16 then sigterm <= '1'; end if; counter <= counter + 1; end if; end process; end behaviour;
bsd-3-clause
a4eab70f808491880c2fb568f4cc0f28
0.64613
2.864253
false
false
false
false
dtysky/DDR2_CONTROLLER
DDR2SIM.vhd
1
8,188
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use ieee.std_logic_unsigned.all; library std; use std.textio.all; use ieee.std_logic_textio.all; entity DDR2SIM is end entity; architecture TESTBENCH of DDR2SIM is component DDR2_CONTROL is port ( pll_lock:in std_logic; clk_control_p,clk_control_n,clk_out_p,clk_out_n:in std_logic; clk_data:in std_logic; clk,n_clk:out std_logic; cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1'; udm,ldm:out std_logic:='0'; udqs_in,ldqs_in:in std_logic:='1'; udqs_out,ldqs_out:out std_logic:='1'; dqs_en:out std_logic:='0'; odt:out std_logic:='0'; bank:out std_logic_vector(2 downto 0); addr:out std_logic_vector(12 downto 0); ram_data_in:in std_logic_vector(15 downto 0):=x"0000"; ram_data_out:out std_logic_vector(15 downto 0):=x"0000"; ram_data_en:out std_logic:='0'; ram_reset:in std_logic:='0'; wr_rqu,rd_rqu:in std_logic:='0'; wr_ready,rd_ready:out std_logic:='0'; wr_end,rd_end:out std_logic:='0'; udm_in,ldm_in:in std_logic:='0'; write_num:in std_logic_vector(15 downto 0); read_num:in std_logic_vector(15 downto 0); data_other_in:in std_logic_vector(15 downto 0); data_other_out:out std_logic_vector(15 downto 0); bank_other:in std_logic_vector(2 downto 0); addr_other_row:in std_logic_vector(12 downto 0); addr_other_col:in std_logic_vector(9 downto 0) ); end component; component DDR2 is port ( ck:in std_logic; ck_n:in std_logic; cke:in std_logic; cs_n:in std_logic; ras_n:in std_logic; cas_n:in std_logic; we_n:in std_logic; dm_rdqs:inout std_logic_vector(1 downto 0); ba:in std_logic_vector(2 downto 0); addr:in std_logic_vector(12 downto 0); dq:inout std_logic_vector(15 downto 0); dqs:inout std_logic_vector(1 downto 0); dqs_n:inout std_logic_vector(1 downto 0); rdqs_n:out std_logic_vector(1 downto 0); odt:in std_logic ); end component; signal clk_c_0,clk_c_90,clk_c_180,clk_c_270,clk_d_0,clk_d_180,pll_lock:std_logic; signal ddr_clk,ddr_clk_n:std_logic; signal cke,n_cs,n_ras,n_cas,n_we:std_logic; signal dm:std_logic_vector(1 downto 0); signal dqs,dqs_in,dqs_out:std_logic_vector(1 downto 0); signal dqs_en:std_logic; signal odt:std_logic; signal bank:std_logic_vector(2 downto 0); signal addr:std_logic_vector(12 downto 0); signal data,data_in,data_out:std_logic_vector(15 downto 0); signal data_en:std_logic; signal ram_reset:std_logic; signal wr_rqu,rd_rqu:std_logic; signal wr_ready,rd_ready:std_logic; signal wr_end,rd_end:std_logic; signal ot_dm:std_logic_vector(1 downto 0); signal wr_num,rd_num:std_logic_vector(15 downto 0); signal ot_data_in,ot_data_out:std_logic_vector(15 downto 0); signal ot_bank:std_logic_vector(2 downto 0); signal ot_addr_row:std_logic_vector(12 downto 0); signal ot_addr_col:std_logic_vector(9 downto 0); signal dqs_n,rdqs_n:std_logic_vector(1 downto 0); constant clk_period:time:=6000 ps; constant clk_period2:time:=3000 ps; signal clk_self:std_logic; begin DDR2C:DDR2_CONTROL port map ( pll_lock=>pll_lock, clk_control_p=>clk_c_0,clk_control_n=>clk_c_180,clk_out_p=>clk_c_0,clk_out_n=>clk_c_180, clk_data=>clk_d_0, clk=>ddr_clk,n_clk=>ddr_clk_n, cke=>cke,n_cs=>n_cs,n_ras=>n_ras,n_cas=>n_cas,n_we=>n_we, udm=>dm(1),ldm=>dm(0), udqs_in=>dqs_in(1),ldqs_in=>dqs_in(0), udqs_out=>dqs_out(1),ldqs_out=>dqs_out(0), dqs_en=>dqs_en, odt=>odt, bank=>bank,addr=>addr, ram_data_in=>data_in(15 downto 0), ram_data_out=>data_out(15 downto 0), ram_data_en=>data_en, ram_reset=>ram_reset, wr_rqu=>wr_rqu,rd_rqu=>rd_rqu, wr_ready=>wr_ready,rd_ready=>rd_ready, wr_end=>wr_end,rd_end=>rd_end, udm_in=>ot_dm(1),ldm_in=>ot_dm(0), write_num=>wr_num,read_num=>rd_num, bank_other=>ot_bank, addr_other_row=>ot_addr_row, addr_other_col=>ot_addr_col, data_other_in=>ot_data_in, data_other_out=>ot_data_out ); DDR2M:DDR2 port map ( ck=>ddr_clk, ck_n=>ddr_clk_n, cke=>cke, cs_n=>n_cs, ras_n=>n_ras, cas_n=>n_cas, we_n=>n_we, dm_rdqs=>dm, ba=>bank, addr=>addr, dq=>data, dqs=>dqs, dqs_n=>dqs_n, rdqs_n=>rdqs_n, odt=>odt ); clk_0:process begin clk_c_0<='1'; wait for clk_period/2; clk_c_0<='0'; wait for clk_period/2; end process; clk_180:process begin clk_c_180<='0'; wait for clk_period/2; clk_c_180<='1'; wait for clk_period/2; end process; clk_90:process begin wait for clk_period/4; clk_c_90<='0'; wait for clk_period/2; clk_c_90<='1'; wait for clk_period/4; end process; clk_270:process begin wait for clk_period/4; clk_c_270<='1'; wait for clk_period/2; clk_c_270<='0'; wait for clk_period/4; end process; clk_data_0:process begin clk_d_0<='1'; clk_self<='1'; wait for clk_period2/2; clk_d_0<='0'; clk_self<='0'; wait for clk_period2/2; end process; clk_data_180:process begin clk_d_180<='0'; wait for clk_period2/2; clk_d_180<='1'; wait for clk_period2/2; end process; pll_lock<='1'; with dqs_en select dqs(1) <= dqs_out(1) when '1', 'Z' when others; dqs_in(1)<=dqs(1); with dqs_en select dqs(0) <= dqs_out(0) when '1', 'Z' when others; dqs_in(0)<=dqs(0); with data_en select data <= data_out when '1', "ZZZZZZZZZZZZZZZZ" when others; data_in<=data; main:process file ddr2_data_text_w,ddr2_data_text_r,ddr2_data_text_st:text; variable fstin,fstout,fstst:FILE_OPEN_STATUS; variable ddr2_data_line:line; variable ddr2_data_sim:std_logic_vector(15 downto 0); variable ddr2_row_sim:std_logic_vector(12 downto 0); variable ddr2_col_sim:std_logic_vector(9 downto 0); variable ddr2_bank_sim:std_logic_vector(2 downto 0); variable con:integer range 0 to 7:=0; begin file_open(fstst ,ddr2_data_text_st ,"textfile_st.dat",read_mode); file_open(fstin ,ddr2_data_text_r ,"textfile_r.dat",read_mode); file_open(fstout ,ddr2_data_text_w ,"textfile_w.dat",write_mode); while (con<6) loop wait until rising_edge(clk_self); --每个时钟读一行 --------write-------- if con=0 then if not endfile(ddr2_data_text_st) then ot_dm<="00"; wr_num<=x"0080"; readline(ddr2_data_text_st,ddr2_data_line); read(ddr2_data_line,ddr2_bank_sim); ot_bank<=ddr2_bank_sim; readline(ddr2_data_text_st,ddr2_data_line); read(ddr2_data_line,ddr2_col_sim); ot_addr_col<=ddr2_col_sim; readline(ddr2_data_text_st,ddr2_data_line); read(ddr2_data_line,ddr2_row_sim); ot_addr_row<=ddr2_row_sim; wr_rqu<='1'; con:=con+1; else file_close(ddr2_data_text_st); file_open(fstst ,ddr2_data_text_st ,"textfile_st.dat",read_mode); con:=3; end if; elsif con=1 then if wr_ready='1' then readline(ddr2_data_text_r,ddr2_data_line); read(ddr2_data_line,ddr2_data_sim); if ddr2_data_sim=x"FFFF" then con:=con+1; else ot_data_in<=ddr2_data_sim; end if; end if; elsif con=2 then if wr_end='1' then wr_rqu<='0'; con:=0; end if; --------read-------- elsif con=3 then if not endfile(ddr2_data_text_st) then ot_dm<="00"; rd_num<=x"0080"; readline(ddr2_data_text_st,ddr2_data_line); read(ddr2_data_line,ddr2_bank_sim); ot_bank<=ddr2_bank_sim; readline(ddr2_data_text_st,ddr2_data_line); read(ddr2_data_line,ddr2_col_sim); ot_addr_col<=ddr2_col_sim; readline(ddr2_data_text_st,ddr2_data_line); read(ddr2_data_line,ddr2_row_sim); ot_addr_row<=ddr2_row_sim; rd_rqu<='1'; con:=con+1; else con:=6; end if; elsif con=4 then if rd_ready='1' then ddr2_data_sim:=ot_data_out; write(ddr2_data_line,ddr2_data_sim); writeline(ddr2_data_text_w,ddr2_data_line); con:=5; end if; elsif con=5 then if rd_ready='1' then ddr2_data_sim:=ot_data_out; if ddr2_data_sim="ZZZZZZZZZZZZZZZZ" or ddr2_data_sim="XXXXXXXXXXXXXXXX" then null; else write(ddr2_data_line,ddr2_data_sim); writeline(ddr2_data_text_w,ddr2_data_line); end if; elsif rd_end='1' then rd_rqu<='0'; con:=3; end if; end if; end loop; file_close(ddr2_data_text_st); file_close(ddr2_data_text_r); file_close(ddr2_data_text_w); wait; end process; end TESTBENCH;
mit
0d391d71a601cbe759618eee3c7946a3
0.654637
2.341449
false
false
false
false
astoria-d/super-duper-nes
test/rom_test01/prg_rom.vhd
1
2,518
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.conv_integer; entity prg_rom is port ( pi_base_clk : in std_logic; pi_ce_n : in std_logic; pi_oe_n : in std_logic; pi_addr : in std_logic_vector (14 downto 0); po_data : out std_logic_vector (7 downto 0) ); end prg_rom; architecture rtl of prg_rom is --constant PROM_SIZE : integer := 15; constant PROM_SIZE : integer := 13; --PROG ROM is 32k subtype rom_data is std_logic_vector (7 downto 0); type rom_array is array (0 to 2**PROM_SIZE - 1) of rom_data; --for Quartus II environment signal p_rom : rom_array; attribute ram_init_file : string; --attribute ram_init_file of p_rom : signal is "sample1-prg.hex"; attribute ram_init_file of p_rom : signal is "sample1-prg-8k.hex"; signal reg_out_n : std_logic; begin p : process (pi_ce_n, pi_oe_n, pi_addr) begin if (pi_ce_n = '0' and pi_oe_n = '0') then po_data <= p_rom(conv_integer(pi_addr(PROM_SIZE - 1 downto 0))); else po_data <= (others => 'Z'); end if; end process; end rtl; --------------------------------------------------- --------------------------------------------------- --------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.conv_integer; entity chr_rom is port ( pi_base_clk : in std_logic; pi_ce_n : in std_logic; pi_oe_n : in std_logic; pi_addr : in std_logic_vector (12 downto 0); po_data : out std_logic_vector (7 downto 0) ); end chr_rom; architecture rtl of chr_rom is --constant CROM_SIZE : integer := 13; constant CROM_SIZE : integer := 12; subtype rom_data is std_logic_vector (7 downto 0); type rom_array is array (0 to 2**CROM_SIZE - 1) of rom_data; --for Quartus II environment signal p_rom : rom_array; attribute ram_init_file : string; --attribute ram_init_file of p_rom : signal is "sample1-chr.hex"; attribute ram_init_file of p_rom : signal is "sample1-chr-4k.hex"; begin p : process (pi_base_clk) begin if (rising_edge(pi_base_clk)) then if (pi_ce_n = '0' and pi_oe_n = '0') then po_data <= p_rom(conv_integer(pi_addr(CROM_SIZE - 1 downto 0))); else po_data <= (others => 'Z'); end if; end if; end process; end rtl;
apache-2.0
5585da9272a6a525dd36382d67844469
0.544877
3.219949
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
vhdl/filter/fir_picoblaze/ssg_display.vhdl
1
5,492
-- Author: Varun Nagpal -- Net Id: vxn180010 -- [TITLE] -- [DATE] -- -- DESIGN: -- -- IN : -- OUT: library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use ieee.std_logic_unsigned.all; use work.ssg_display_shared_package.all; entity ssg_display is port (clk : in std_logic; rst : in std_logic; in_bcds_p : in std_logic_vector(15 downto 0);-- Four BCD numbers that can be displayed by the four 7-segment digits in_dps_p : in DP_T; -- enable/disable input signals for the decimal point of a digit out_seg_p : out SEG_T; -- enable output signals for seven led segments(cathode) of currently refreshed digit out_dp_p : out std_logic; -- enable ouput signal for the decimal point of currently refreshed digit out_digits_en_p : out DIGITS_EN_T -- enable signals for K=4 digits. only one digit out of K=4 digits is enabled for refresh duration ); end ssg_display; architecture rtl of ssg_display is signal seg_sig : SEG_T; -- 7-digits corresponding to 7-LED segments of a 7-segment display signal digits_en_sig : DIGITS_EN_T; -- Active low Anode Enable Signals: AN[K-1 downto 0] signal current_bcd_sig : BCD_T; -- 4-bit BCD encoding of a digit signal clk_enable_sig : std_logic; signal cnt_reg : CC_CNT_T; signal current_state_reg : FSM_STATE_T; signal next_state_sig : FSM_STATE_T; begin -- Generate a clock enable signal -- This clock on NEXSYS3 running has frequency of 100 MHz -- or period of 10ns. We need to generate clock enable signal -- every 4 ms or @ 250 Hz. This corresponds to ~400000 cc -- log2(400000) = 18.609 = ceil(log2(925283.368)) = 19. -- Thus we can use a 19-bit counter to generate a clock enable signal gen_clk_enable_mem: process(clk, rst) variable cnt_temp: CC_CNT_T; begin if rst = '1' then cnt_temp := ( others => '0'); elsif clk'event and clk = '1' then cnt_temp := cnt_temp + 1; if( cnt_temp = CC_CNT_MAX_U ) then cnt_temp := (others => '0'); end if; end if; cnt_reg <= cnt_temp; end process gen_clk_enable_mem; clk_enable_sig <= '1' when cnt_reg = (CC_CNT_MAX_U-1) else '0'; -- Generate enable signals for K-digits (segmented) fsm_current_state_mem: process (clk, rst) begin if rst = '1' then current_state_reg <= (others => DISABLE_DIGIT); -- force one-hot (not) encoding. current_state_reg(0) <= ENABLE_DIGIT; -- initial state is 1111..10 (NOT of 0000..01 since segmented display is common anode type) elsif clk'event and clk ='1' then current_state_reg <= next_state_sig; end if; end process fsm_current_state_mem; -- TBU: needs to be fixed or rewritten in standard style though it seems fine. -- Look at EE254L_Nexys3_Basic_IO_Introduction.pdf , lab8.pdf (ENEE 245: Digital Circuits & Systems Lab — Lab 8) -- and FPGA protyping book by Pong Chu for ideas fsm_next_state_oup_comb: process(current_state_reg, clk_enable_sig) begin if clk_enable_sig = '1' then next_state_sig <= current_state_reg(current_state_reg'HIGH-1 downto current_state_reg'LOW) & current_state_reg(current_state_reg'HIGH); else next_state_sig <= current_state_reg; end if; end process fsm_next_state_oup_comb; -- combinational output digits_en_sig <= next_state_sig; -- Multiplexer to switch between 4-bit BCD encoding sets of K-digits switches_to_bcd_mux_comb: process (digits_en_sig, in_bcds_p, in_dps_p) variable temp_bcd : BCD_T; variable temp_dp : std_logic; begin temp_bcd := (others => '0'); temp_dp := DISABLE_DP; for I in digits_en_sig'RANGE loop if ( digits_en_sig(I) = ENABLE_DIGIT ) then temp_bcd := in_bcds_p( BCD_CNT*(I+1) - 1 downto BCD_CNT*I); temp_dp := in_dps_p(I); end if; end loop; current_bcd_sig <= temp_bcd; out_dp_p <= temp_dp; end process switches_to_bcd_mux_comb; -- Segment decoder segment_decoder_comb: process (current_bcd_sig) variable temp_bcd : BCD_T; variable temp_seg : SEG_T; begin temp_bcd := current_bcd_sig; temp_seg := NOT SEG_OFF; -- Decode 4-bits (switches) representing a 4-bit BCD encoding of a -- (hexa)decimal number and output a 7-bit code that lights up -- appropriate LEDs of a single segmented display to display the -- (hexa)decimal digit. case temp_bcd is when x"0" => temp_seg := NOT SEG_NUM_D0; -- complemented since segment type on NEXSYS 3 is common anode(always H), so cathode leds are active low when x"1" => temp_seg := NOT SEG_NUM_D1; when x"2" => temp_seg := NOT SEG_NUM_D2; when x"3" => temp_seg := NOT SEG_NUM_D3; when x"4" => temp_seg := NOT SEG_NUM_D4; when x"5" => temp_seg := NOT SEG_NUM_D5; when x"6" => temp_seg := NOT SEG_NUM_D6; when x"7" => temp_seg := NOT SEG_NUM_D7; when x"8" => temp_seg := NOT SEG_NUM_D8; when x"9" => temp_seg := NOT SEG_NUM_D9; when x"A" => temp_seg := NOT SEG_NUM_XA; when x"B" => temp_seg := NOT SEG_NUM_XB; when x"C" => temp_seg := NOT SEG_NUM_XC; when x"D" => temp_seg := NOT SEG_NUM_XD; when x"E" => temp_seg := NOT SEG_NUM_XE; when x"F" => temp_seg := NOT SEG_NUM_XF; when others => temp_seg := NOT SEG_OFF; end case; seg_sig <= temp_seg; end process segment_decoder_comb; out_seg_p <= seg_sig; out_digits_en_p <= digits_en_sig; end rtl;
mit
a448137131e1797d3ac23860f92f1cb4
0.635337
2.829897
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/gcd/gcd.cache/ip/2018.2/ad4f3760cb81ab99/gcd_block_design_rst_ps7_0_100M_0_sim_netlist.vhdl
1
35,484
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Sun Sep 22 03:32:34 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_rst_ps7_0_100M_0_sim_netlist.vhdl -- Design : gcd_block_design_rst_ps7_0_100M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => p_1_in, I2 => p_2_in, I3 => \^scndry_out\, I4 => asr_lpf(0), O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is signal exr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => exr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => exr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(1), I2 => p_3_out(2), I3 => \^scndry_out\, I4 => p_3_out(0), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => dcm_locked, I1 => lpf_exr, I2 => lpf_asr, I3 => Q, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0090" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9000" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(4), I2 => seq_cnt(3), I3 => seq_cnt(5), O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0018" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(0), I2 => seq_cnt(2), I3 => seq_cnt(1), O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0480" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_block_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;
mit
ba44849935a2c0e9b11c04b60f785eea
0.588941
2.919533
false
false
false
false
erevejach14/Arquitectura
suma/suma.vhd
1
820
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_1164.ALL; entity suma is port( cin : in std_logic; x : in std_logic_vector( 3 downto 0); y : in std_logic_vector( 3 downto 0); s : out std_logic_vector( 3 downto 0); cout : out std_logic); end; architecture hola of suma is signal c : std_logic_vector( 0 to 4); begin c(0) <= cin; --i = 0 s(0) <= c(0) xor x(0) xor y(0); c(1) <= (x(0) and y(0)) or (c(0) and (x(0) xor y(0))); --i = 1 s(1) <= c(1) xor x(1) xor y(1); c(2) <= (x(1) and y(1)) or (c(1) and (x(1) xor y(1))); --i = 2 s(2) <= c(2) xor x(2) xor y(2); c(3) <= (x(2) and y(2)) or (c(2) and (x(2) xor y(2))); --i = 3 s(3) <= c(3) xor x(3) xor y(3); c(4) <= (x(3) and y(3)) or (c(3) and (x(3) xor y(3))); cout <= c(4); end hola;
gpl-3.0
ef11336e765d4c28c77a53c871f27732
0.523171
2.034739
false
false
false
false
varunnagpaal/Digital-Hardware-Modelling
xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ipshared/f86a/hdl/proc_sys_reset_v5_0_vh_rfs.vhd
7
71,590
------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- upcnt_n - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: upcnt_n.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- upcnt_n.vhd -- lpf.vhd -- sequence.vhd ------------------------------------------------------------------------------- -- Author: Kurt Conover -- History: -- Kurt Conover 11/07/01 -- First Release -- -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- C_SIZE -- Number of bits in counter -- -- -- Definition of Ports: -- Data -- parallel data input -- Cnt_en -- count enable -- Load -- Load Data -- Clr -- reset -- Clk -- Clock -- Qout -- Count output -- ------------------------------------------------------------------------------- entity upcnt_n is generic( C_SIZE : Integer ); port( Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); Cnt_en : in STD_LOGIC; Load : in STD_LOGIC; Clr : in STD_LOGIC; Clk : in STD_LOGIC; Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) ); end upcnt_n; architecture imp of upcnt_n is constant CLEAR : std_logic := '0'; signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1'); begin process(Clk) begin if (Clk'event) and Clk = '1' then -- Clear output register if (Clr = CLEAR) then q_int <= (others => '0'); -- Load in start value elsif (Load = '1') then q_int <= UNSIGNED(Data); -- If count enable is high elsif Cnt_en = '1' then q_int <= q_int + 1; end if; end if; end process; Qout <= STD_LOGIC_VECTOR(q_int); end imp; ------------------------------------------------------------------------------- -- sequence - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2012 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: proc_sys_reset.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- -- upcnt_n.vhd -- -- lpf.vhd -- -- sequence.vhd ------------------------------------------------------------------------------- -- Filename: sequence.vhd -- -- Description: -- This file control the sequencing coming out of a reset. -- The sequencing is as follows: -- Bus_Struct_Reset comes out of reset first. Either when the -- external or auxiliary reset goes inactive or 16 clocks -- after a PPC Chip_Reset_Request, or 30 clocks after a PPC -- System_Reset_Request. -- Peripheral_Reset comes out of reset 16 clocks after -- Bus_Struct_Reset. -- The PPC resetcore, comes out of reset -- 16 clocks after Peripheral_Reset. -- The PPC resetchip and resetsystem come out of reset -- at the same time as Bus_Struct_Reset. ------------------------------------------------------------------------------- -- Author: Kurt Conover -- History: -- Kurt Conover 11/12/01 -- First Release -- LC Whittle 10/11/2004 -- Update for NCSim -- rolandp 04/16/2007 -- v2.00a -- -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library unisim; use unisim.vcomponents.all; library proc_sys_reset_v5_0_12; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- -- Definition of Ports: -- Lpf_reset -- Low Pass Filtered in -- System_Reset_Req -- System Reset Request -- Chip_Reset_Req -- Chip Reset Request -- Slowest_Sync_Clk -- Clock -- Bsr_out -- Bus Structure Reset out -- Pr_out -- Peripheral Reset out -- Core_out -- Core reset out -- Chip_out -- Chip reset out -- Sys_out -- System reset out -- MB_out -- MB reset out -- ------------------------------------------------------------------------------- entity sequence_psr is port( Lpf_reset : in std_logic; -- System_Reset_Req : in std_logic; -- Chip_Reset_Req : in std_logic; Slowest_Sync_Clk : in std_logic; Bsr_out : out std_logic; Pr_out : out std_logic; -- Core_out : out std_logic; -- Chip_out : out std_logic; -- Sys_out : out std_logic; MB_out : out std_logic ); end sequence_psr; architecture imp of sequence_psr is constant CLEAR : std_logic := '0'; constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12 constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25 constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28 constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41 constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44 constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57 constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP; constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS; constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP; constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS; signal bsr : std_logic := '1'; signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0'); signal pr : std_logic := '1'; signal pr_dec : std_logic_vector(2 downto 0) := (others => '0'); signal Core : std_logic := '1'; signal core_dec : std_logic_vector(2 downto 0) := (others => '0'); signal Chip : std_logic := '0'; signal chip_dec : std_logic_vector(2 downto 0) := (others => '0'); signal Sys : std_logic := '0'; signal sys_dec : std_logic_vector(2 downto 0) := (others => '0'); signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req signal seq_cnt : std_logic_vector(5 downto 0); signal seq_cnt_en : std_logic := '0'; signal seq_clr : std_logic := '0'; signal ris_edge : std_logic := '0'; signal sys_edge : std_logic := '0'; signal from_sys : std_logic; ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- begin Pr_out <= pr; Bsr_out <= bsr; MB_out <= core; -- Core_out <= core; -- Chip_out <= chip or sys; -- Sys_out <= sys; ------------------------------------------------------------------------------- -- This process remembers that the reset was caused be -- System_Reset_Req ------------------------------------------------------------------------------- SYS_FROM_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then --if Lpf_reset='1' or system_reset_req_d3='1' then if (Lpf_reset = '1') then from_sys <= '1'; --elsif Chip_Reset_Req_d3='1' then -- from_sys <= '0'; elsif (Core = '0') then from_sys <='0'; end if; end if; end process; ------------------------------------------------------------------------------- -- This instantiates a counter to control the sequencing ------------------------------------------------------------------------------- SEQ_COUNTER : entity proc_sys_reset_v5_0_12.UPCNT_N generic map (C_SIZE => 6) port map( Data => "000000", Cnt_en => seq_cnt_en, Load => '0', Clr => seq_clr, Clk => Slowest_sync_clk, Qout => seq_cnt ); ------------------------------------------------------------------------------- -- SEQ_CNT_EN_PROCESS ------------------------------------------------------------------------------- -- This generates the reset pulse and the count enable to core reset counter -- count until all outputs are inactive ------------------------------------------------------------------------------- SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if (Lpf_reset='1' --or --System_Reset_Req_d3='1' or --Chip_Reset_Req_d3='1' or --ris_edge = '1' ) then seq_cnt_en <= '1'; elsif (Core='0') then -- Core always present and always last seq_cnt_en <= '0'; end if; end if; end process; ------------------------------------------------------------------------------- -- SEQ_CLR_PROCESS ------------------------------------------------------------------------------- -- This generates the reset to the sequence counter -- Clear the counter on a rising edge of chip or system request or low pass -- filter output ------------------------------------------------------------------------------- SEQ_CLR_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if ris_edge = '1' or Lpf_reset = '1' then if (Lpf_reset = '1') then seq_clr <= '0'; else seq_clr <= '1'; end if; end if; end process; ------------------------------------------------------------------------------- -- This process defines the Peripheral_Reset output signal ------------------------------------------------------------------------------- PR_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then --if ris_edge = '1' or Lpf_reset = '1' then if (Lpf_reset = '1') then pr <= '1'; elsif (pr_dec(2) = '1') then pr <= '0'; end if; end if; end process; ------------------------------------------------------------------------------- -- This process decodes the sequence counter for PR to use ------------------------------------------------------------------------------- PR_DECODE_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if ( (seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0') or (seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1') ) then pr_dec(0) <= '1'; else pr_dec(0) <= '0'; end if; if ( (seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0') or (seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1') )then pr_dec(1) <= '1'; else pr_dec(1) <= '0'; end if; pr_dec(2) <= pr_dec(1) and pr_dec(0); end if; end process; ------------------------------------------------------------------------------- -- This process defines the Bus_Struct_Reset output signal ------------------------------------------------------------------------------- BSR_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then --if ris_edge = '1' or Lpf_reset = '1' then if (Lpf_reset = '1') then bsr <= '1'; elsif (bsr_dec(2) = '1') then bsr <= '0'; end if; end if; end process; ------------------------------------------------------------------------------- -- This process decodes the sequence counter for BSR to use ------------------------------------------------------------------------------- BSR_DECODE_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if ( (seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0') or (seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1') )then bsr_dec(0) <= '1'; else bsr_dec(0) <= '0'; end if; if ( (seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0') or (seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1') )then bsr_dec(1) <= '1'; else bsr_dec(1) <= '0'; end if; bsr_dec(2) <= bsr_dec(1) and bsr_dec(0); end if; end process; ------------------------------------------------------------------------------- -- This process defines the Peripheral_Reset output signal ------------------------------------------------------------------------------- CORE_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if ris_edge = '1' or Lpf_reset = '1' then if (Lpf_reset = '1') then core <= '1'; elsif (core_dec(2) = '1') then core <= '0'; end if; end if; end process; ------------------------------------------------------------------------------- -- This process decodes the sequence counter for PR to use ------------------------------------------------------------------------------- CORE_DECODE_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if ( (seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0') or (seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1') )then core_dec(0) <= '1'; else core_dec(0) <= '0'; end if; if ( (seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0') or (seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1') )then core_dec(1) <= '1'; else core_dec(1) <= '0'; end if; core_dec(2) <= core_dec(1) and core_dec(0); end if; end process; --------------------------------------------------------------------------------- ---- This process defines the Chip output signal --------------------------------------------------------------------------------- -- CHIP_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- -- if ris_edge = '1' or Lpf_reset = '1' then -- if Lpf_reset = '1' then -- chip <= '1'; -- elsif chip_dec(2) = '1' then -- chip <= '0'; -- end if; -- end if; -- end process; -- --------------------------------------------------------------------------------- ---- This process decodes the sequence counter for Chip to use ---- sys is overlapping the chip reset and thus no need to decode this here --------------------------------------------------------------------------------- -- CHIP_DECODE_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then -- chip_dec(0) <= '1'; -- else -- chip_dec(0) <= '0'; -- end if; -- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then -- chip_dec(1) <= '1'; -- else -- chip_dec(1) <= '0'; -- end if; -- chip_dec(2) <= chip_dec(1) and chip_dec(0); -- end if; -- end process; --------------------------------------------------------------------------------- ---- This process defines the Sys output signal --------------------------------------------------------------------------------- -- SYS_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if sys_edge = '1' or Lpf_reset = '1' then -- sys <= '1'; -- elsif sys_dec(2) = '1' then -- sys <= '0'; -- end if; -- end if; -- end process; -- --------------------------------------------------------------------------------- ---- This process decodes the sequence counter for Sys to use --------------------------------------------------------------------------------- -- SYS_DECODE_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or -- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then -- sys_dec(0) <= '1'; -- else -- sys_dec(0) <= '0'; -- end if; -- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or -- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then -- sys_dec(1) <= '1'; -- else -- sys_dec(1) <= '0'; -- end if; -- sys_dec(2) <= sys_dec(1) and sys_dec(0); -- end if; -- end process; -- --------------------------------------------------------------------------------- ---- This process delays signals so the the edge can be detected and used --------------------------------------------------------------------------------- -- DELAY_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- chip_reset_req_d1 <= Chip_Reset_Req ; -- chip_reset_req_d2 <= chip_Reset_Req_d1 ; -- chip_reset_req_d3 <= chip_Reset_Req_d2 ; -- system_reset_req_d1 <= System_Reset_Req; -- system_reset_req_d2 <= system_Reset_Req_d1; -- system_reset_req_d3 <= system_Reset_Req_d2; -- end if; -- end process; ------------------------------------------------------------------------------- -- This process creates a signal that goes high on the rising edge of either -- Chip_Reset_Req or System_Reset_Req ------------------------------------------------------------------------------- -- RIS_EDGE_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge -- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then -- ris_edge <= '1'; -- else -- ris_edge <='0'; -- end if; -- end if; -- end process; ------------------------------------------------------------------------------- -- This process creates a signal that goes high on the rising edge of -- System_Reset_Req ------------------------------------------------------------------------------- -- SYS_EDGE_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- if (system_reset_req_d3='0' and system_reset_req_d2='1') then -- sys_edge <= '1'; -- else -- sys_edge <='0'; -- end if; -- end if; -- end process; end architecture imp; ------------------------------------------------------------------------------- -- lpf - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2012 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: lpf.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- upcnt_n.vhd -- lpf.vhd -- sequence.vhd ------------------------------------------------------------------------------- -- Author: Kurt Conover -- History: -- Kurt Conover 11/08/01 -- First Release -- -- KC 02/25/2002 -- Added Dcm_locked as an input -- -- Added Power on reset srl_time_out -- -- KC 08/26/2003 -- Added attribute statements for power on -- reset SRL -- -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library lib_cdc_v1_0_2; --use lib_cdc_v1_0_2.all; library Unisim; use Unisim.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting -- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting -- C_EXT_RESET_HIGH -- External Reset Active High or Active Low -- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low -- -- Definition of Ports: -- Slowest_sync_clk -- Clock -- External_System_Reset -- External Reset Input -- Auxiliary_System_Reset -- Auxiliary Reset Input -- Dcm_locked -- DCM Locked, hold system in reset until 1 -- Lpf_reset -- Low Pass Filtered Output -- ------------------------------------------------------------------------------- entity lpf is generic( C_EXT_RST_WIDTH : Integer; C_AUX_RST_WIDTH : Integer; C_EXT_RESET_HIGH : std_logic; C_AUX_RESET_HIGH : std_logic ); port( MB_Debug_Sys_Rst : in std_logic; Dcm_locked : in std_logic; External_System_Reset : in std_logic; Auxiliary_System_Reset : in std_logic; Slowest_Sync_Clk : in std_logic; Lpf_reset : out std_logic ); end lpf; architecture imp of lpf is component SRL16 is -- synthesis translate_off generic ( INIT : bit_vector ); -- synthesis translate_on port (D : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16; constant CLEAR : std_logic := '0'; signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1) := (others => '0'); -- LPF DFF signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1) := (others => '0'); -- LPF DFF signal exr_and : std_logic := '0'; -- varible input width "and" gate signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate signal asr_and : std_logic := '0'; -- varible input width "and" gate signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate signal lpf_int : std_logic := '0'; -- internal Lpf_reset signal lpf_exr : std_logic := '0'; signal lpf_asr : std_logic := '0'; signal srl_time_out : std_logic; attribute INIT : string; attribute INIT of POR_SRL_I: label is "FFFF"; begin Lpf_reset <= lpf_int; ------------------------------------------------------------------------------- -- Power On Reset Generation ------------------------------------------------------------------------------- -- This generates a reset for the first 16 clocks after a power up ------------------------------------------------------------------------------- POR_SRL_I: SRL16 -- synthesis translate_off generic map ( INIT => X"FFFF") -- synthesis translate_on port map ( D => '0', CLK => Slowest_sync_clk, A0 => '1', A1 => '1', A2 => '1', A3 => '1', Q => srl_time_out); ------------------------------------------------------------------------------- -- LPF_OUTPUT_PROCESS ------------------------------------------------------------------------------- -- This generates the reset pulse and the count enable to core reset counter -- --ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate --begin LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked; end if; end process LPF_OUTPUT_PROCESS; --end generate ACTIVE_HIGH_LPF_EXT; --ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate --begin --LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- lpf_int <= not (lpf_exr or -- lpf_asr or -- srl_time_out)or -- not Dcm_locked; -- end if; -- end process; --end generate ACTIVE_LOW_LPF_EXT; EXR_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if exr_and = '1' then lpf_exr <= '1'; elsif (exr_and = '0' and exr_nand = '1') then lpf_exr <= '0'; end if; end if; end process EXR_OUTPUT_PROCESS; ASR_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if asr_and = '1' then lpf_asr <= '1'; elsif (asr_and = '0' and asr_nand = '1') then lpf_asr <= '0'; end if; end if; end process ASR_OUTPUT_PROCESS; ------------------------------------------------------------------------------- -- This If-generate selects an active high input for External System Reset ------------------------------------------------------------------------------- ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate begin ----------------------------------- exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst; ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => 2, C_MTBF_STAGES => 4 ) port map( prmry_aclk => '1', prmry_resetn => '1',--S_AXI_ARESETN, prmry_in => exr_d1, prmry_ack => open, scndry_out => exr_lpf(0), scndry_aclk => Slowest_Sync_Clk, scndry_resetn => '1', --S_AXIS_ARESETN, prmry_vect_in => "00", scndry_vect_out => open ); ----------------------------------- end generate ACTIVE_HIGH_EXT; ------------------------------------------------------------------------------- -- This If-generate selects an active low input for External System Reset ------------------------------------------------------------------------------- ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate begin exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst; ------------------------------------- ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => 2, C_MTBF_STAGES => 4 ) port map( prmry_aclk => '1', prmry_resetn => '1',--S_AXI_ARESETN, prmry_in => exr_d1, prmry_ack => open, scndry_out => exr_lpf(0), scndry_aclk => Slowest_Sync_Clk, scndry_resetn => '1', --S_AXIS_ARESETN, prmry_vect_in => "00", scndry_vect_out => open ); ------------------------------------- end generate ACTIVE_LOW_EXT; ------------------------------------------------------------------------------- -- This If-generate selects an active high input for Auxiliary System Reset ------------------------------------------------------------------------------- ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate begin asr_d1 <= Auxiliary_System_Reset; ------------------------------------- ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => 2, C_MTBF_STAGES => 4 ) port map( prmry_aclk => '1', prmry_resetn => '1',--S_AXI_ARESETN, prmry_in => asr_d1, prmry_ack => open, scndry_out => asr_lpf(0), scndry_aclk => Slowest_Sync_Clk, scndry_resetn => '1', --S_AXIS_ARESETN, prmry_vect_in => "00", scndry_vect_out => open ); ------------------------------------- end generate ACTIVE_HIGH_AUX; ------------------------------------------------------------------------------- -- This If-generate selects an active low input for Auxiliary System Reset ------------------------------------------------------------------------------- ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate begin ------------------------------------- asr_d1 <= not Auxiliary_System_Reset; ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => 2, C_MTBF_STAGES => 4 ) port map( prmry_aclk => '1', prmry_resetn => '1',--S_AXI_ARESETN, prmry_in => asr_d1, prmry_ack => open, scndry_out => asr_lpf(0), scndry_aclk => Slowest_Sync_Clk, scndry_resetn => '1', --S_AXIS_ARESETN, prmry_vect_in => "00", scndry_vect_out => open ); ------------------------------------- end generate ACTIVE_LOW_AUX; ------------------------------------------------------------------------------- -- This For-generate creates the low pass filter D-Flip Flops ------------------------------------------------------------------------------- EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate begin ---------------------------------------- EXT_LPF_DFF : process (Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then exr_lpf(i) <= exr_lpf(i-1); end if; end process; ---------------------------------------- end generate EXT_LPF; ------------------------------------------------------------------------------------------ -- Implement the 'AND' function on the for the LPF ------------------------------------------------------------------------------------------ EXT_LPF_AND : process (exr_lpf) Variable loop_and : std_logic; Variable loop_nand : std_logic; Begin loop_and := '1'; loop_nand := '1'; for j in 0 to C_EXT_RST_WIDTH - 1 loop loop_and := loop_and and exr_lpf(j); loop_nand := loop_nand and not exr_lpf(j); End loop; exr_and <= loop_and; exr_nand <= loop_nand; end process; ------------------------------------------------------------------------------- -- This For-generate creates the low pass filter D-Flip Flops ------------------------------------------------------------------------------- AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate begin ---------------------------------------- AUX_LPF_DFF : process (Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_lpf(k) <= asr_lpf(k-1); end if; end process; ---------------------------------------- end generate AUX_LPF; ------------------------------------------------------------------------------------------ -- Implement the 'AND' function on the for the LPF ------------------------------------------------------------------------------------------ AUX_LPF_AND : process (asr_lpf) Variable aux_loop_and : std_logic; Variable aux_loop_nand : std_logic; Begin aux_loop_and := '1'; aux_loop_nand := '1'; for m in 0 to C_AUX_RST_WIDTH - 1 loop aux_loop_and := aux_loop_and and asr_lpf(m); aux_loop_nand := aux_loop_nand and not asr_lpf(m); End loop; asr_and <= aux_loop_and; asr_nand <= aux_loop_nand; end process; end imp; ------------------------------------------------------------------------------- -- proc_sys_reset - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2012 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: proc_sys_reset.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- upcnt_n.vhd -- lpf.vhd -- sequence.vhd ------------------------------------------------------------------------------- -- Author: rolandp -- History: -- kc 11/07/01 -- First version -- -- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to -- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to -- C_AUX_RESET_HIGH to match generics used in -- MicroBlaze. Added the DCM Lock as an input -- to keep reset active until after the Lock -- is valid. -- lcw 10/11/2004 -- Updated for NCSim -- Ravi 09/14/2006 -- Added Attributes for synthesis -- rolandp 04/16/2007 -- version 2.00a -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ -- ~~~~~~~ -- SK 05/12/11 -- ^^^^^^^ -- 1. Updated the core so remove the support for PPC related functionality. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; library proc_sys_reset_v5_0_12; use proc_sys_reset_v5_0_12.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting -- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting -- C_EXT_RESET_HIGH -- External Reset Active High or Active Low -- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low -- C_NUM_BUS_RST -- Number of Bus Structures reset to generate -- C_NUM_PERP_RST -- Number of Peripheral resets to generate -- -- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect -- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral -- Definition of Ports: -- slowest_sync_clk -- Clock -- ext_reset_in -- External Reset Input -- aux_reset_in -- Auxiliary Reset Input -- mb_debug_sys_rst -- MDM Reset Input -- dcm_locked -- DCM Locked, hold system in reset until 1 -- mb_reset -- MB core reset out -- bus_struct_reset -- Bus structure reset out -- peripheral_reset -- Peripheral reset out -- interconnect_aresetn -- Interconnect Bus structure registered rst out -- peripheral_aresetn -- Active Low Peripheral registered reset out ------------------------------------------------------------------------------- entity proc_sys_reset is generic ( C_FAMILY : string := "virtex7"; C_EXT_RST_WIDTH : integer := 4; C_AUX_RST_WIDTH : integer := 4; C_EXT_RESET_HIGH : std_logic := '0'; -- High active input C_AUX_RESET_HIGH : std_logic := '1'; -- High active input C_NUM_BUS_RST : integer := 1; C_NUM_PERP_RST : integer := 1; C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010 C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010 ); port ( slowest_sync_clk : in std_logic; ext_reset_in : in std_logic; aux_reset_in : in std_logic; -- from MDM mb_debug_sys_rst : in std_logic; -- DCM locked information dcm_locked : in std_logic := '1'; -- -- from PPC -- Core_Reset_Req_0 : in std_logic; -- Chip_Reset_Req_0 : in std_logic; -- System_Reset_Req_0 : in std_logic; -- Core_Reset_Req_1 : in std_logic; -- Chip_Reset_Req_1 : in std_logic; -- System_Reset_Req_1 : in std_logic; -- RstcPPCresetcore_0 : out std_logic := '0'; -- RstcPPCresetchip_0 : out std_logic := '0'; -- RstcPPCresetsys_0 : out std_logic := '0'; -- RstcPPCresetcore_1 : out std_logic := '0'; -- RstcPPCresetchip_1 : out std_logic := '0'; -- RstcPPCresetsys_1 : out std_logic := '0'; -- to Microblaze active high reset mb_reset : out std_logic; -- active high resets bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1) := (others => '0'); peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1) := (others => '0'); -- active low resets interconnect_aresetn : out std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1)) := (others => '1'); peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1)) := (others => '1') ); end entity proc_sys_reset; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture imp of proc_sys_reset is ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Signal and Type Declarations -- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req constant T : std_logic := C_EXT_RESET_HIGH; signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0 signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1 signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output signal lpf_reset : std_logic; -- Low pass filtered ext or aux --signal Chip_Reset_Req : std_logic := '0'; --signal System_Reset_Req : std_logic := '0'; signal Bsr_out : std_logic; signal Pr_out : std_logic; -- signal Core_out : std_logic; -- signal Chip_out : std_logic; -- signal Sys_out : std_logic; signal MB_out : std_logic := C_EXT_RESET_HIGH; signal MB_out1 : std_logic := C_EXT_RESET_HIGH; signal pr_outn : std_logic; signal bsr_outn : std_logic; ------------------------------------------------------------------------------- -- Attributes to synthesis ------------------------------------------------------------------------------- attribute equivalent_register_removal: string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; begin ------------------------------------------------------------------------------- -- --------------------- -- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze -- --------------------- -- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate -- begin -- mb_reset <= MB_out1; -- MB_Reset_PROCESS1: process (slowest_sync_clk) -- begin -- if (slowest_sync_clk'event and slowest_sync_clk = '1') then -- MB_out1 <= MB_out; -- end if; -- end process; FDRE_inst : FDRE generic map ( INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => mb_reset, -- Data output C => slowest_sync_clk, -- Clock input CE => '1', -- Clock enable input R => '0', -- Synchronous reset input D => MB_out -- Data input ); -- ---------------------------------------------------------------------------- -- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s) -- ---------------------------------------------------------------------------- BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate FDRE_BSR : FDRE generic map ( INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => bus_struct_reset(i), -- Data output C => slowest_sync_clk, -- Clock input CE => '1', -- Clock enable input R => '0', -- Synchronous reset input D => Bsr_out -- Data input ); -- BSR_DFF : process (slowest_sync_clk) -- begin -- if (slowest_sync_clk'event and slowest_sync_clk = '1') then -- bus_struct_reset(i) <= Bsr_out; -- end if; -- end process; end generate BSR_OUT_DFF; -- --------------------------------------------------------------------------- -- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s) -- --------------------------------------------------------------------------- bsr_outn <= not(Bsr_out); ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate FDRE_BSR_N : FDRE generic map ( INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => interconnect_aresetn(i), -- Data output C => slowest_sync_clk, -- Clock input CE => '1', -- Clock enable input R => '0', -- Synchronous reset input D => bsr_outn -- Data input ); -- BSR_DFF : process (slowest_sync_clk) -- begin -- if (slowest_sync_clk'event and slowest_sync_clk = '1') then -- interconnect_aresetn(i) <= not (Bsr_out); -- end if; -- end process; end generate ACTIVE_LOW_BSR_OUT_DFF; ------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s) -- ---------------------------------------------------------------------------- PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate FDRE_PER : FDRE generic map ( INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => peripheral_reset(i), -- Data output C => slowest_sync_clk, -- Clock input CE => '1', -- Clock enable input R => '0', -- Synchronous reset input D => Pr_out -- Data input ); -- PR_DFF : process (slowest_sync_clk) -- begin -- if (slowest_sync_clk'event and slowest_sync_clk = '1') then -- peripheral_reset(i) <= Pr_out; -- end if; -- end process; end generate PR_OUT_DFF; -- ---------------------------------------------------------------------------- -- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s) -- ---A------------------------------------------------------------------------- pr_outn <= not(Pr_out); ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate FDRE_PER_N : FDRE generic map ( INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => peripheral_aresetn(i), -- Data output C => slowest_sync_clk, -- Clock input CE => '1', -- Clock enable input R => '0', -- Synchronous reset input D => Pr_outn -- Data input ); -- ACTIVE_LOW_PR_DFF : process (slowest_sync_clk) -- begin -- if (slowest_sync_clk'event and slowest_sync_clk = '1') then -- peripheral_aresetn(i) <= not(Pr_out); -- end if; -- end process; end generate ACTIVE_LOW_PR_OUT_DFF; ------------------------------------------------------------------------------- -- This process defines the RstcPPCreset and MB_Reset outputs ------------------------------------------------------------------------------- -- Rstc_output_PROCESS_0: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and -- core_cnt_0(1) and core_cnt_0(0)) -- or Core_out; -- RstcPPCresetchip_0 <= Chip_out; -- RstcPPCresetsys_0 <= Sys_out; -- end if; -- end process; -- Rstc_output_PROCESS_1: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and -- core_cnt_1(1) and core_cnt_1(0)) -- or Core_out; -- RstcPPCresetchip_1 <= Chip_out; -- RstcPPCresetsys_1 <= Sys_out; -- end if; -- end process; ------------------------------------------------------------------------------- --------------------------------------------------------------------------------- ---- This process delays signals so the the edge can be detected and used ---- Double register to sync up with slowest_sync_clk --------------------------------------------------------------------------------- -- DELAY_PROCESS_0: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- core_reset_req_0_d1 <= Core_Reset_Req_0; -- core_reset_req_0_d2 <= core_reset_req_0_d1; -- core_reset_req_0_d3 <= core_reset_req_0_d2; -- end if; -- end process; -- -- DELAY_PROCESS_1: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- core_reset_req_1_d1 <= Core_Reset_Req_1; -- core_reset_req_1_d2 <= core_reset_req_1_d1; -- core_reset_req_1_d3 <= core_reset_req_1_d2; -- end if; -- end process; -- ** -- ------------------------------------------------------------------------------- -- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a -- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks -- ** -- ------------------------------------------------------------------------------- -- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_12.UPCNT_N -- ** -- generic map (C_SIZE => 4) -- ** -- port map( -- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); -- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC; -- ** -- Load => '0', -- in STD_LOGIC; -- ** -- Clr => core_req_edge_0, -- in STD_LOGIC; -- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; -- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) -- ** -- ); -- ** -- -- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_12.UPCNT_N -- ** -- generic map (C_SIZE => 4) -- ** -- port map( -- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); -- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC; -- ** -- Load => '0', -- in STD_LOGIC; -- ** -- Clr => core_req_edge_1, -- in STD_LOGIC; -- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; -- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) -- ** -- ); -- ** -- -- ** -- ------------------------------------------------------------------------------- -- ** -- -- CORE_RESET_PROCESS -- ** -- ------------------------------------------------------------------------------- -- ** -- -- This generates the reset pulse and the count enable to core reset counter -- ** -- -- -- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk) -- ** -- begin -- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1)); -- ** -- --or not core_req_edge_0; -- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3); -- ** -- end if; -- ** -- end process; -- ** -- -- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk) -- ** -- begin -- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1)); -- ** -- --or not core_req_edge_1; -- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3); -- ** -- end if; -- ** -- end process; ------------------------------------------------------------------------------- -- This instantiates a low pass filter to filter both External and Auxiliary -- Reset Inputs. ------------------------------------------------------------------------------- EXT_LPF : entity proc_sys_reset_v5_0_12.LPF generic map ( C_EXT_RST_WIDTH => C_EXT_RST_WIDTH, C_AUX_RST_WIDTH => C_AUX_RST_WIDTH, C_EXT_RESET_HIGH => C_EXT_RESET_HIGH, C_AUX_RESET_HIGH => C_AUX_RESET_HIGH ) port map( MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic Dcm_locked => dcm_locked, -- in std_logic External_System_Reset => ext_reset_in, -- in std_logic Auxiliary_System_Reset => aux_reset_in, -- in std_logic Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic Lpf_reset => lpf_reset -- out std_logic ); ------------------------------------------------------------------------------- -- This instantiates the sequencer -- This controls the time between resets becoming inactive ------------------------------------------------------------------------------- -- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1; -- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1; SEQ : entity proc_sys_reset_v5_0_12.SEQUENCE_PSR --generic map ( -- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH --) port map( Lpf_reset => lpf_reset, -- in std_logic --System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic --Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic Bsr_out => Bsr_out, -- out std_logic Pr_out => Pr_out, -- out std_logic --Core_out => open, -- Core_out, -- out std_logic --Chip_out => open, -- Chip_out, -- out std_logic --Sys_out => open, -- Sys_out, -- out std_logic MB_out => MB_out); -- out std_logic end imp; --END_SINGLE_FILE_TAG
mit
8938bee68c866863df7a7608f3f13136
0.436164
4.291709
false
false
false
false
MartinCura/SistDig-TP4
old/UART/data_adq/uart_comps.vhd
1
1,886
--component uart is -- generic ( -- F : natural := 50000; -- Device clock frequency [KHz]. -- min_baud : natural := 1200; -- num_data_bits : natural := 8 -- ); -- port ( -- Rx : in std_logic; -- Tx : out std_logic; -- Din : in std_logic_vector(7 downto 0); -- StartTx : in std_logic; -- TxBusy : out std_logic; -- Dout : out std_logic_vector(7 downto 0); -- RxRdy : out std_logic; -- RxErr : out std_logic; -- Divisor : in std_logic_vector; -- clk : in std_logic; -- rst : in std_logic -- ); -- end component uart; ----- library IEEE; use IEEE.std_logic_1164.all; package uart_comps is -- Componentes de la UART ----- component timing is generic ( F : natural:=8; baud_rate : natural:=9600 ); port ( CLK : in std_logic; RST : in std_logic; ClrDiv : in std_logic; Top16 : buffer std_logic; TopTx : out std_logic; TopRx : out std_logic ); end component; ----- component transmit is generic ( NDBits : natural := 8 ); port ( CLK : in std_logic; RST : in std_logic; Tx : out std_logic; Din : in std_logic_vector (NDBits-1 downto 0); TxBusy : out std_logic; TopTx : in std_logic; StartTx : in std_logic ); end component; ----- component receive is generic ( NDBits : natural := 8 ); port ( CLK : in std_logic; RST : in std_logic; Rx : in std_logic; Dout : out std_logic_vector (NDBits-1 downto 0); RxErr : out std_logic; RxRdy : out std_logic; Top16 : in std_logic; ClrDiv : out std_logic; TopRx : in std_logic ); end component; end package uart_comps;
gpl-3.0
487753a47532eebc89a37727f19a2192
0.50106
3.57197
false
false
false
false